2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
50 * Copyright (c) 2018 The FreeBSD Foundation
51 * All rights reserved.
53 * This software was developed for the FreeBSD Project by Jake Burkholder,
54 * Safeport Network Services, and Network Associates Laboratories, the
55 * Security Research Division of Network Associates, Inc. under
56 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
57 * CHATS research program.
59 * Portions of this software were developed by
60 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
61 * the FreeBSD Foundation.
63 * Redistribution and use in source and binary forms, with or without
64 * modification, are permitted provided that the following conditions
66 * 1. Redistributions of source code must retain the above copyright
67 * notice, this list of conditions and the following disclaimer.
68 * 2. Redistributions in binary form must reproduce the above copyright
69 * notice, this list of conditions and the following disclaimer in the
70 * documentation and/or other materials provided with the distribution.
72 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
73 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
75 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
78 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
79 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
80 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
81 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
85 #include <sys/cdefs.h>
86 __FBSDID("$FreeBSD$");
89 * Manages physical address maps.
91 * Since the information managed by this module is
92 * also stored by the logical address mapping module,
93 * this module may throw away valid virtual-to-physical
94 * mappings at almost any time. However, invalidations
95 * of virtual-to-physical mappings must be done as
98 * In order to cope with hardware architectures which
99 * make virtual-to-physical map invalidates expensive,
100 * this module may delay invalidate or reduced protection
101 * operations until such time as they are actually
102 * necessary. This module is given full information as
103 * to which processors are currently using which maps,
104 * and to when physical maps must be made correct.
107 #include "opt_apic.h"
109 #include "opt_pmap.h"
113 #include <sys/param.h>
114 #include <sys/systm.h>
115 #include <sys/kernel.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/proc.h>
123 #include <sys/rwlock.h>
124 #include <sys/sf_buf.h>
126 #include <sys/vmmeter.h>
127 #include <sys/sched.h>
128 #include <sys/sysctl.h>
130 #include <sys/vmem.h>
133 #include <vm/vm_param.h>
134 #include <vm/vm_kern.h>
135 #include <vm/vm_page.h>
136 #include <vm/vm_map.h>
137 #include <vm/vm_object.h>
138 #include <vm/vm_extern.h>
139 #include <vm/vm_pageout.h>
140 #include <vm/vm_pager.h>
141 #include <vm/vm_phys.h>
142 #include <vm/vm_radix.h>
143 #include <vm/vm_reserv.h>
148 #include <machine/intr_machdep.h>
149 #include <x86/apicvar.h>
151 #include <machine/bootinfo.h>
152 #include <machine/cpu.h>
153 #include <machine/cputypes.h>
154 #include <machine/md_var.h>
155 #include <machine/pcb.h>
156 #include <machine/specialreg.h>
158 #include <machine/smp.h>
161 #ifndef PMAP_SHPGPERPROC
162 #define PMAP_SHPGPERPROC 200
165 #if !defined(DIAGNOSTIC)
166 #ifdef __GNUC_GNU_INLINE__
167 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
169 #define PMAP_INLINE extern inline
176 #define PV_STAT(x) do { x ; } while (0)
178 #define PV_STAT(x) do { } while (0)
181 #define pa_index(pa) ((pa) >> PDRSHIFT)
182 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
185 * Get PDEs and PTEs for user/kernel address space
187 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
188 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
190 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
191 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
192 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
193 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
194 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
196 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
197 atomic_clear_int((u_int *)(pte), PG_W))
198 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
200 struct pmap kernel_pmap_store;
202 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
203 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
204 static int pgeflag = 0; /* PG_G or-in */
205 static int pseflag = 0; /* PG_PS or-in */
207 static int nkpt = NKPT;
208 vm_offset_t kernel_vm_end = /* 0 + */ NKPT * NBPDR;
210 #if defined(PAE) || defined(PAE_TABLES)
212 static uma_zone_t pdptzone;
215 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
217 static int pat_works = 1;
218 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
219 "Is page attribute table fully functional?");
221 static int pg_ps_enabled = 1;
222 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
223 &pg_ps_enabled, 0, "Are large page mappings enabled?");
225 #define PAT_INDEX_SIZE 8
226 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
229 * pmap_mapdev support pre initialization (i.e. console)
231 #define PMAP_PREINIT_MAPPING_COUNT 8
232 static struct pmap_preinit_mapping {
237 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
238 static int pmap_initialized;
240 static struct rwlock_padalign pvh_global_lock;
243 * Data for the pv entry allocation mechanism
245 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
246 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
247 static struct md_page *pv_table;
248 static int shpgperproc = PMAP_SHPGPERPROC;
250 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
251 int pv_maxchunks; /* How many chunks we have KVA for */
252 vm_offset_t pv_vafree; /* freelist stored in the PTE */
255 * All those kernel PT submaps that BSD is so fond of
258 static pd_entry_t *KPTD;
265 static caddr_t crashdumpmap;
267 static pt_entry_t *PMAP1 = NULL, *PMAP2, *PMAP3;
268 static pt_entry_t *PADDR1 = NULL, *PADDR2, *PADDR3;
270 static int PMAP1cpu, PMAP3cpu;
271 static int PMAP1changedcpu;
272 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
274 "Number of times pmap_pte_quick changed CPU with same PMAP1");
276 static int PMAP1changed;
277 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
279 "Number of times pmap_pte_quick changed PMAP1");
280 static int PMAP1unchanged;
281 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
283 "Number of times pmap_pte_quick didn't change PMAP1");
284 static struct mtx PMAP2mutex;
289 * Internal flags for pmap_enter()'s helper functions.
291 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
292 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
294 static void free_pv_chunk(struct pv_chunk *pc);
295 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
296 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
297 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
298 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
300 #if VM_NRESERVLEVEL > 0
301 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
303 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
304 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
306 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
308 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
309 static bool pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
311 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
312 u_int flags, vm_page_t m);
313 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
314 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
315 static void pmap_flush_page(vm_page_t m);
316 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
317 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
319 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
320 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
321 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
322 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
323 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
324 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
325 #if VM_NRESERVLEVEL > 0
326 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
328 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
330 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
331 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
332 struct spglist *free);
333 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
334 struct spglist *free);
335 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
336 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
337 struct spglist *free);
338 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
339 struct spglist *free);
340 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
342 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
343 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
345 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
347 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
349 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
351 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
352 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
353 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
354 static void pmap_pte_release(pt_entry_t *pte);
355 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
356 #if defined(PAE) || defined(PAE_TABLES)
357 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain,
358 uint8_t *flags, int wait);
360 static void pmap_init_trm(void);
362 static __inline void pagezero(void *page);
364 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
365 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
367 void pmap_cold(void);
369 u_long physfree; /* phys addr of next free page */
370 u_long vm86phystk; /* PA of vm86/bios stack */
371 u_long vm86paddr; /* address of vm86 region */
372 int vm86pa; /* phys addr of vm86 region */
373 u_long KERNend; /* phys addr end of kernel (just after bss) */
374 pd_entry_t *IdlePTD; /* phys addr of kernel PTD */
375 #if defined(PAE) || defined(PAE_TABLES)
376 pdpt_entry_t *IdlePDPT; /* phys addr of kernel PDPT */
378 pt_entry_t *KPTmap; /* address of kernel page tables */
379 u_long KPTphys; /* phys addr of kernel page tables */
380 extern u_long tramp_idleptd;
383 allocpages(u_int cnt, u_long *physfree)
388 *physfree += PAGE_SIZE * cnt;
389 bzero((void *)res, PAGE_SIZE * cnt);
394 pmap_cold_map(u_long pa, u_long va, u_long cnt)
398 for (pt = (pt_entry_t *)KPTphys + atop(va); cnt > 0;
399 cnt--, pt++, va += PAGE_SIZE, pa += PAGE_SIZE)
400 *pt = pa | PG_V | PG_RW | PG_A | PG_M;
404 pmap_cold_mapident(u_long pa, u_long cnt)
407 pmap_cold_map(pa, pa, cnt);
410 _Static_assert(2 * NBPDR == KERNBASE, "Broken double-map of zero PTD");
413 * Called from locore.s before paging is enabled. Sets up the first
414 * kernel page table. Since kernel is mapped with PA == VA, this code
415 * does not require relocations.
424 physfree = (u_long)&_end;
425 if (bootinfo.bi_esymtab != 0)
426 physfree = bootinfo.bi_esymtab;
427 if (bootinfo.bi_kernend != 0)
428 physfree = bootinfo.bi_kernend;
429 physfree = roundup2(physfree, NBPDR);
432 /* Allocate Kernel Page Tables */
433 KPTphys = allocpages(NKPT, &physfree);
434 KPTmap = (pt_entry_t *)KPTphys;
436 /* Allocate Page Table Directory */
437 #if defined(PAE) || defined(PAE_TABLES)
438 /* XXX only need 32 bytes (easier for now) */
439 IdlePDPT = (pdpt_entry_t *)allocpages(1, &physfree);
441 IdlePTD = (pd_entry_t *)allocpages(NPGPTD, &physfree);
444 * Allocate KSTACK. Leave a guard page between IdlePTD and
445 * proc0kstack, to control stack overflow for thread0 and
446 * prevent corruption of the page table. We leak the guard
447 * physical memory due to 1:1 mappings.
449 allocpages(1, &physfree);
450 proc0kstack = allocpages(TD0_KSTACK_PAGES, &physfree);
452 /* vm86/bios stack */
453 vm86phystk = allocpages(1, &physfree);
455 /* pgtable + ext + IOPAGES */
456 vm86paddr = vm86pa = allocpages(3, &physfree);
458 /* Install page tables into PTD. Page table page 1 is wasted. */
459 for (a = 0; a < NKPT; a++)
460 IdlePTD[a] = (KPTphys + ptoa(a)) | PG_V | PG_RW | PG_A | PG_M;
462 #if defined(PAE) || defined(PAE_TABLES)
463 /* PAE install PTD pointers into PDPT */
464 for (a = 0; a < NPGPTD; a++)
465 IdlePDPT[a] = ((u_int)IdlePTD + ptoa(a)) | PG_V;
469 * Install recursive mapping for kernel page tables into
472 for (a = 0; a < NPGPTD; a++)
473 IdlePTD[PTDPTDI + a] = ((u_int)IdlePTD + ptoa(a)) | PG_V |
477 * Initialize page table pages mapping physical address zero
478 * through the (physical) end of the kernel. Many of these
479 * pages must be reserved, and we reserve them all and map
480 * them linearly for convenience. We do this even if we've
481 * enabled PSE above; we'll just switch the corresponding
482 * kernel PDEs before we turn on paging.
484 * This and all other page table entries allow read and write
485 * access for various reasons. Kernel mappings never have any
486 * access restrictions.
488 pmap_cold_mapident(0, atop(NBPDR));
489 pmap_cold_map(0, NBPDR, atop(NBPDR));
490 pmap_cold_mapident(KERNBASE, atop(KERNend - KERNBASE));
492 /* Map page table directory */
493 #if defined(PAE) || defined(PAE_TABLES)
494 pmap_cold_mapident((u_long)IdlePDPT, 1);
496 pmap_cold_mapident((u_long)IdlePTD, NPGPTD);
498 /* Map early KPTmap. It is really pmap_cold_mapident. */
499 pmap_cold_map(KPTphys, (u_long)KPTmap, NKPT);
501 /* Map proc0kstack */
502 pmap_cold_mapident(proc0kstack, TD0_KSTACK_PAGES);
503 /* ISA hole already mapped */
505 pmap_cold_mapident(vm86phystk, 1);
506 pmap_cold_mapident(vm86pa, 3);
508 /* Map page 0 into the vm86 page table */
509 *(pt_entry_t *)vm86pa = 0 | PG_RW | PG_U | PG_A | PG_M | PG_V;
511 /* ...likewise for the ISA hole for vm86 */
512 for (pt = (pt_entry_t *)vm86pa + atop(ISA_HOLE_START), a = 0;
513 a < atop(ISA_HOLE_LENGTH); a++, pt++)
514 *pt = (ISA_HOLE_START + ptoa(a)) | PG_RW | PG_U | PG_A |
517 /* Enable PSE, PGE, VME, and PAE if configured. */
519 if ((cpu_feature & CPUID_PSE) != 0) {
523 * Superpage mapping of the kernel text. Existing 4k
524 * page table pages are wasted.
526 for (a = KERNBASE; a < KERNend; a += NBPDR)
527 IdlePTD[a >> PDRSHIFT] = a | PG_PS | PG_A | PG_M |
530 if ((cpu_feature & CPUID_PGE) != 0) {
534 ncr4 |= (cpu_feature & CPUID_VME) != 0 ? CR4_VME : 0;
535 #if defined(PAE) || defined(PAE_TABLES)
539 load_cr4(rcr4() | ncr4);
541 /* Now enable paging */
542 #if defined(PAE) || defined(PAE_TABLES)
543 cr3 = (u_int)IdlePDPT;
545 cr3 = (u_int)IdlePTD;
549 load_cr0(rcr0() | CR0_PG);
552 * Now running relocated at KERNBASE where the system is
557 * Remove the lowest part of the double mapping of low memory
558 * to get some null pointer checks.
561 load_cr3(cr3); /* invalidate TLB */
565 * Bootstrap the system enough to run with virtual memory.
567 * On the i386 this is called after mapping has already been enabled
568 * in locore.s with the page table created in pmap_cold(),
569 * and just syncs the pmap module with what has already been done.
572 pmap_bootstrap(vm_paddr_t firstaddr)
575 pt_entry_t *pte, *unused;
580 * Add a physical memory segment (vm_phys_seg) corresponding to the
581 * preallocated kernel page table pages so that vm_page structures
582 * representing these pages will be created. The vm_page structures
583 * are required for promotion of the corresponding kernel virtual
584 * addresses to superpage mappings.
586 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
589 * Initialize the first available kernel virtual address. However,
590 * using "firstaddr" may waste a few pages of the kernel virtual
591 * address space, because locore may not have mapped every physical
592 * page that it allocated. Preferably, locore would provide a first
593 * unused virtual address in addition to "firstaddr".
595 virtual_avail = (vm_offset_t)firstaddr;
597 virtual_end = VM_MAX_KERNEL_ADDRESS;
600 * Initialize the kernel pmap (which is statically allocated).
602 PMAP_LOCK_INIT(kernel_pmap);
603 kernel_pmap->pm_pdir = IdlePTD;
604 #if defined(PAE) || defined(PAE_TABLES)
605 kernel_pmap->pm_pdpt = IdlePDPT;
607 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
608 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
611 * Initialize the global pv list lock.
613 rw_init(&pvh_global_lock, "pmap pv global");
616 * Reserve some special page table entries/VA space for temporary
619 #define SYSMAP(c, p, v, n) \
620 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
627 * Initialize temporary map objects on the current CPU for use
629 * CMAP1/CMAP2 are used for zeroing and copying pages.
630 * CMAP3 is used for the boot-time memory test.
633 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
634 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1)
635 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1)
636 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1)
638 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
643 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
646 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
648 SYSMAP(caddr_t, unused, ptvmmap, 1)
651 * msgbufp is used to map the system message buffer.
653 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
656 * KPTmap is used by pmap_kextract().
658 * KPTmap is first initialized by locore. However, that initial
659 * KPTmap can only support NKPT page table pages. Here, a larger
660 * KPTmap is created that can support KVA_PAGES page table pages.
662 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
664 for (i = 0; i < NKPT; i++)
665 KPTD[i] = (KPTphys + ptoa(i)) | PG_RW | PG_V;
668 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
671 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
672 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
673 SYSMAP(pt_entry_t *, PMAP3, PADDR3, 1)
675 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
680 * Initialize the PAT MSR if present.
681 * pmap_init_pat() clears and sets CR4_PGE, which, as a
682 * side-effect, invalidates stale PG_G TLB entries that might
683 * have been created in our pre-boot environment. We assume
684 * that PAT support implies PGE and in reverse, PGE presence
685 * comes with PAT. Both features were added for Pentium Pro.
691 pmap_init_reserved_pages(void)
699 mtx_init(&pc->pc_copyout_mlock, "cpmlk", NULL, MTX_DEF |
701 pc->pc_copyout_maddr = kva_alloc(ptoa(2));
702 if (pc->pc_copyout_maddr == 0)
703 panic("unable to allocate non-sleepable copyout KVA");
704 sx_init(&pc->pc_copyout_slock, "cpslk");
705 pc->pc_copyout_saddr = kva_alloc(ptoa(2));
706 if (pc->pc_copyout_saddr == 0)
707 panic("unable to allocate sleepable copyout KVA");
708 pc->pc_pmap_eh_va = kva_alloc(ptoa(1));
709 if (pc->pc_pmap_eh_va == 0)
710 panic("unable to allocate pmap_extract_and_hold KVA");
711 pc->pc_pmap_eh_ptep = (char *)vtopte(pc->pc_pmap_eh_va);
714 * Skip if the mappings have already been initialized,
715 * i.e. this is the BSP.
717 if (pc->pc_cmap_addr1 != 0)
720 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
721 pages = kva_alloc(PAGE_SIZE * 3);
723 panic("unable to allocate CMAP KVA");
724 pc->pc_cmap_pte1 = vtopte(pages);
725 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE);
726 pc->pc_cmap_addr1 = (caddr_t)pages;
727 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE);
728 pc->pc_qmap_addr = pages + atop(2);
732 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
740 int pat_table[PAT_INDEX_SIZE];
745 /* Set default PAT index table. */
746 for (i = 0; i < PAT_INDEX_SIZE; i++)
748 pat_table[PAT_WRITE_BACK] = 0;
749 pat_table[PAT_WRITE_THROUGH] = 1;
750 pat_table[PAT_UNCACHEABLE] = 3;
751 pat_table[PAT_WRITE_COMBINING] = 3;
752 pat_table[PAT_WRITE_PROTECTED] = 3;
753 pat_table[PAT_UNCACHED] = 3;
756 * Bail if this CPU doesn't implement PAT.
757 * We assume that PAT support implies PGE.
759 if ((cpu_feature & CPUID_PAT) == 0) {
760 for (i = 0; i < PAT_INDEX_SIZE; i++)
761 pat_index[i] = pat_table[i];
767 * Due to some Intel errata, we can only safely use the lower 4
770 * Intel Pentium III Processor Specification Update
771 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
774 * Intel Pentium IV Processor Specification Update
775 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
777 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
778 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
781 /* Initialize default PAT entries. */
782 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
783 PAT_VALUE(1, PAT_WRITE_THROUGH) |
784 PAT_VALUE(2, PAT_UNCACHED) |
785 PAT_VALUE(3, PAT_UNCACHEABLE) |
786 PAT_VALUE(4, PAT_WRITE_BACK) |
787 PAT_VALUE(5, PAT_WRITE_THROUGH) |
788 PAT_VALUE(6, PAT_UNCACHED) |
789 PAT_VALUE(7, PAT_UNCACHEABLE);
793 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
794 * Program 5 and 6 as WP and WC.
795 * Leave 4 and 7 as WB and UC.
797 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
798 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
799 PAT_VALUE(6, PAT_WRITE_COMBINING);
800 pat_table[PAT_UNCACHED] = 2;
801 pat_table[PAT_WRITE_PROTECTED] = 5;
802 pat_table[PAT_WRITE_COMBINING] = 6;
805 * Just replace PAT Index 2 with WC instead of UC-.
807 pat_msr &= ~PAT_MASK(2);
808 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
809 pat_table[PAT_WRITE_COMBINING] = 2;
814 load_cr4(cr4 & ~CR4_PGE);
816 /* Disable caches (CD = 1, NW = 0). */
818 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
820 /* Flushes caches and TLBs. */
824 /* Update PAT and index table. */
825 wrmsr(MSR_PAT, pat_msr);
826 for (i = 0; i < PAT_INDEX_SIZE; i++)
827 pat_index[i] = pat_table[i];
829 /* Flush caches and TLBs again. */
833 /* Restore caches and PGE. */
839 * Initialize a vm_page's machine-dependent fields.
842 pmap_page_init(vm_page_t m)
845 TAILQ_INIT(&m->md.pv_list);
846 m->md.pat_mode = PAT_WRITE_BACK;
849 #if defined(PAE) || defined(PAE_TABLES)
851 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain, uint8_t *flags,
855 /* Inform UMA that this allocator uses kernel_map/object. */
856 *flags = UMA_SLAB_KERNEL;
857 return ((void *)kmem_alloc_contig_domain(domain, bytes, wait, 0x0ULL,
858 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
863 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
865 * - Must deal with pages in order to ensure that none of the PG_* bits
866 * are ever set, PG_V in particular.
867 * - Assumes we can write to ptes without pte_store() atomic ops, even
868 * on PAE systems. This should be ok.
869 * - Assumes nothing will ever test these addresses for 0 to indicate
870 * no mapping instead of correctly checking PG_V.
871 * - Assumes a vm_offset_t will fit in a pte (true for i386).
872 * Because PG_V is never set, there can be no mappings to invalidate.
875 pmap_ptelist_alloc(vm_offset_t *head)
882 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
886 panic("pmap_ptelist_alloc: va with PG_V set!");
892 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
897 panic("pmap_ptelist_free: freeing va with PG_V set!");
899 *pte = *head; /* virtual! PG_V is 0 though */
904 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
910 for (i = npages - 1; i >= 0; i--) {
911 va = (vm_offset_t)base + i * PAGE_SIZE;
912 pmap_ptelist_free(head, va);
918 * Initialize the pmap module.
919 * Called by vm_init, to initialize any structures that the pmap
920 * system needs to map virtual memory.
925 struct pmap_preinit_mapping *ppim;
931 * Initialize the vm page array entries for the kernel pmap's
934 PMAP_LOCK(kernel_pmap);
935 for (i = 0; i < NKPT; i++) {
936 mpte = PHYS_TO_VM_PAGE(KPTphys + ptoa(i));
937 KASSERT(mpte >= vm_page_array &&
938 mpte < &vm_page_array[vm_page_array_size],
939 ("pmap_init: page table page is out of range"));
940 mpte->pindex = i + KPTDI;
941 mpte->phys_addr = KPTphys + ptoa(i);
942 mpte->wire_count = 1;
944 KERNBASE <= i << PDRSHIFT && i << PDRSHIFT < KERNend &&
945 pmap_insert_pt_page(kernel_pmap, mpte))
946 panic("pmap_init: pmap_insert_pt_page failed");
948 PMAP_UNLOCK(kernel_pmap);
952 * Initialize the address space (zone) for the pv entries. Set a
953 * high water mark so that the system can recover from excessive
954 * numbers of pv entries.
956 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
957 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
958 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
959 pv_entry_max = roundup(pv_entry_max, _NPCPV);
960 pv_entry_high_water = 9 * (pv_entry_max / 10);
963 * If the kernel is running on a virtual machine, then it must assume
964 * that MCA is enabled by the hypervisor. Moreover, the kernel must
965 * be prepared for the hypervisor changing the vendor and family that
966 * are reported by CPUID. Consequently, the workaround for AMD Family
967 * 10h Erratum 383 is enabled if the processor's feature set does not
968 * include at least one feature that is only supported by older Intel
969 * or newer AMD processors.
971 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
972 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
973 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
975 workaround_erratum383 = 1;
978 * Are large page mappings supported and enabled?
980 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
983 else if (pg_ps_enabled) {
984 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
985 ("pmap_init: can't assign to pagesizes[1]"));
986 pagesizes[1] = NBPDR;
990 * Calculate the size of the pv head table for superpages.
991 * Handle the possibility that "vm_phys_segs[...].end" is zero.
993 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
994 PAGE_SIZE) / NBPDR + 1;
997 * Allocate memory for the pv head table for superpages.
999 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1001 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1002 for (i = 0; i < pv_npg; i++)
1003 TAILQ_INIT(&pv_table[i].pv_list);
1005 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
1006 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
1007 if (pv_chunkbase == NULL)
1008 panic("pmap_init: not enough kvm for pv chunks");
1009 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
1010 #if defined(PAE) || defined(PAE_TABLES)
1011 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
1012 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
1013 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1014 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
1017 pmap_initialized = 1;
1022 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1023 ppim = pmap_preinit_mapping + i;
1026 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
1027 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
1033 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
1034 "Max number of PV entries");
1035 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
1036 "Page share factor per proc");
1038 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1039 "2/4MB page mapping counters");
1041 static u_long pmap_pde_demotions;
1042 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1043 &pmap_pde_demotions, 0, "2/4MB page demotions");
1045 static u_long pmap_pde_mappings;
1046 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1047 &pmap_pde_mappings, 0, "2/4MB page mappings");
1049 static u_long pmap_pde_p_failures;
1050 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1051 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
1053 static u_long pmap_pde_promotions;
1054 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1055 &pmap_pde_promotions, 0, "2/4MB page promotions");
1057 /***************************************************
1058 * Low level helper routines.....
1059 ***************************************************/
1062 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
1065 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
1066 pat_index[(int)mode] >= 0);
1070 * Determine the appropriate bits to set in a PTE or PDE for a specified
1074 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
1076 int cache_bits, pat_flag, pat_idx;
1078 if (!pmap_is_valid_memattr(pmap, mode))
1079 panic("Unknown caching mode %d\n", mode);
1081 /* The PAT bit is different for PTE's and PDE's. */
1082 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
1084 /* Map the caching mode to a PAT index. */
1085 pat_idx = pat_index[mode];
1087 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1090 cache_bits |= pat_flag;
1092 cache_bits |= PG_NC_PCD;
1094 cache_bits |= PG_NC_PWT;
1095 return (cache_bits);
1099 pmap_ps_enabled(pmap_t pmap __unused)
1102 return (pg_ps_enabled);
1106 * The caller is responsible for maintaining TLB consistency.
1109 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
1113 pde = pmap_pde(kernel_pmap, va);
1114 pde_store(pde, newpde);
1118 * After changing the page size for the specified virtual address in the page
1119 * table, flush the corresponding entries from the processor's TLB. Only the
1120 * calling processor's TLB is affected.
1122 * The calling thread must be pinned to a processor.
1125 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
1128 if ((newpde & PG_PS) == 0)
1129 /* Demotion: flush a specific 2MB page mapping. */
1131 else /* if ((newpde & PG_G) == 0) */
1133 * Promotion: flush every 4KB page mapping from the TLB
1134 * because there are too many to flush individually.
1149 * For SMP, these functions have to use the IPI mechanism for coherence.
1151 * N.B.: Before calling any of the following TLB invalidation functions,
1152 * the calling processor must ensure that all stores updating a non-
1153 * kernel page table are globally performed. Otherwise, another
1154 * processor could cache an old, pre-update entry without being
1155 * invalidated. This can happen one of two ways: (1) The pmap becomes
1156 * active on another processor after its pm_active field is checked by
1157 * one of the following functions but before a store updating the page
1158 * table is globally performed. (2) The pmap becomes active on another
1159 * processor before its pm_active field is checked but due to
1160 * speculative loads one of the following functions stills reads the
1161 * pmap as inactive on the other processor.
1163 * The kernel page table is exempt because its pm_active field is
1164 * immutable. The kernel page table is always active on every
1168 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1170 cpuset_t *mask, other_cpus;
1174 if (pmap == kernel_pmap) {
1177 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1180 cpuid = PCPU_GET(cpuid);
1181 other_cpus = all_cpus;
1182 CPU_CLR(cpuid, &other_cpus);
1183 CPU_AND(&other_cpus, &pmap->pm_active);
1186 smp_masked_invlpg(*mask, va, pmap);
1190 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1191 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1194 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1196 cpuset_t *mask, other_cpus;
1200 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1201 pmap_invalidate_all(pmap);
1206 if (pmap == kernel_pmap) {
1207 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1210 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1213 cpuid = PCPU_GET(cpuid);
1214 other_cpus = all_cpus;
1215 CPU_CLR(cpuid, &other_cpus);
1216 CPU_AND(&other_cpus, &pmap->pm_active);
1219 smp_masked_invlpg_range(*mask, sva, eva, pmap);
1224 pmap_invalidate_all(pmap_t pmap)
1226 cpuset_t *mask, other_cpus;
1230 if (pmap == kernel_pmap) {
1233 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1236 cpuid = PCPU_GET(cpuid);
1237 other_cpus = all_cpus;
1238 CPU_CLR(cpuid, &other_cpus);
1239 CPU_AND(&other_cpus, &pmap->pm_active);
1242 smp_masked_invltlb(*mask, pmap);
1247 pmap_invalidate_cache(void)
1257 cpuset_t invalidate; /* processors that invalidate their TLB */
1261 u_int store; /* processor that updates the PDE */
1265 pmap_update_pde_kernel(void *arg)
1267 struct pde_action *act = arg;
1270 if (act->store == PCPU_GET(cpuid)) {
1271 pde = pmap_pde(kernel_pmap, act->va);
1272 pde_store(pde, act->newpde);
1277 pmap_update_pde_user(void *arg)
1279 struct pde_action *act = arg;
1281 if (act->store == PCPU_GET(cpuid))
1282 pde_store(act->pde, act->newpde);
1286 pmap_update_pde_teardown(void *arg)
1288 struct pde_action *act = arg;
1290 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1291 pmap_update_pde_invalidate(act->va, act->newpde);
1295 * Change the page size for the specified virtual address in a way that
1296 * prevents any possibility of the TLB ever having two entries that map the
1297 * same virtual address using different page sizes. This is the recommended
1298 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1299 * machine check exception for a TLB state that is improperly diagnosed as a
1303 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1305 struct pde_action act;
1306 cpuset_t active, other_cpus;
1310 cpuid = PCPU_GET(cpuid);
1311 other_cpus = all_cpus;
1312 CPU_CLR(cpuid, &other_cpus);
1313 if (pmap == kernel_pmap)
1316 active = pmap->pm_active;
1317 if (CPU_OVERLAP(&active, &other_cpus)) {
1319 act.invalidate = active;
1322 act.newpde = newpde;
1323 CPU_SET(cpuid, &active);
1324 smp_rendezvous_cpus(active,
1325 smp_no_rendezvous_barrier, pmap == kernel_pmap ?
1326 pmap_update_pde_kernel : pmap_update_pde_user,
1327 pmap_update_pde_teardown, &act);
1329 if (pmap == kernel_pmap)
1330 pmap_kenter_pde(va, newpde);
1332 pde_store(pde, newpde);
1333 if (CPU_ISSET(cpuid, &active))
1334 pmap_update_pde_invalidate(va, newpde);
1340 * Normal, non-SMP, 486+ invalidation functions.
1341 * We inline these within pmap.c for speed.
1344 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1347 if (pmap == kernel_pmap)
1352 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1356 if (pmap == kernel_pmap)
1357 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1362 pmap_invalidate_all(pmap_t pmap)
1365 if (pmap == kernel_pmap)
1370 pmap_invalidate_cache(void)
1377 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1380 if (pmap == kernel_pmap)
1381 pmap_kenter_pde(va, newpde);
1383 pde_store(pde, newpde);
1384 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1385 pmap_update_pde_invalidate(va, newpde);
1390 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1394 * When the PDE has PG_PROMOTED set, the 2- or 4MB page mapping was
1395 * created by a promotion that did not invalidate the 512 or 1024 4KB
1396 * page mappings that might exist in the TLB. Consequently, at this
1397 * point, the TLB may hold both 4KB and 2- or 4MB page mappings for
1398 * the address range [va, va + NBPDR). Therefore, the entire range
1399 * must be invalidated here. In contrast, when PG_PROMOTED is clear,
1400 * the TLB will not hold any 4KB page mappings for the address range
1401 * [va, va + NBPDR), and so a single INVLPG suffices to invalidate the
1402 * 2- or 4MB page mapping from the TLB.
1404 if ((pde & PG_PROMOTED) != 0)
1405 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
1407 pmap_invalidate_page(pmap, va);
1410 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1413 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1417 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
1419 KASSERT((sva & PAGE_MASK) == 0,
1420 ("pmap_invalidate_cache_range: sva not page-aligned"));
1421 KASSERT((eva & PAGE_MASK) == 0,
1422 ("pmap_invalidate_cache_range: eva not page-aligned"));
1425 if ((cpu_feature & CPUID_SS) != 0 && !force)
1426 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1427 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
1428 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1431 * XXX: Some CPUs fault, hang, or trash the local APIC
1432 * registers if we use CLFLUSH on the local APIC
1433 * range. The local APIC is always uncached, so we
1434 * don't need to flush for that range anyway.
1436 if (pmap_kextract(sva) == lapic_paddr)
1440 * Otherwise, do per-cache line flush. Use the sfence
1441 * instruction to insure that previous stores are
1442 * included in the write-back. The processor
1443 * propagates flush to other processors in the cache
1447 for (; sva < eva; sva += cpu_clflush_line_size)
1450 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1451 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1453 if (pmap_kextract(sva) == lapic_paddr)
1457 * Writes are ordered by CLFLUSH on Intel CPUs.
1459 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1461 for (; sva < eva; sva += cpu_clflush_line_size)
1463 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1468 * No targeted cache flush methods are supported by CPU,
1469 * or the supplied range is bigger than 2MB.
1470 * Globally invalidate cache.
1472 pmap_invalidate_cache();
1477 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1481 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1482 (cpu_feature & CPUID_CLFSH) == 0) {
1483 pmap_invalidate_cache();
1485 for (i = 0; i < count; i++)
1486 pmap_flush_page(pages[i]);
1491 * Are we current address space or kernel?
1494 pmap_is_current(pmap_t pmap)
1497 return (pmap == kernel_pmap);
1501 * If the given pmap is not the current or kernel pmap, the returned pte must
1502 * be released by passing it to pmap_pte_release().
1505 pmap_pte(pmap_t pmap, vm_offset_t va)
1510 pde = pmap_pde(pmap, va);
1514 /* are we current address space or kernel? */
1515 if (pmap_is_current(pmap))
1516 return (vtopte(va));
1517 mtx_lock(&PMAP2mutex);
1518 newpf = *pde & PG_FRAME;
1519 if ((*PMAP2 & PG_FRAME) != newpf) {
1520 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1521 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1523 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1529 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1532 static __inline void
1533 pmap_pte_release(pt_entry_t *pte)
1536 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1537 mtx_unlock(&PMAP2mutex);
1541 * NB: The sequence of updating a page table followed by accesses to the
1542 * corresponding pages is subject to the situation described in the "AMD64
1543 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1544 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1545 * right after modifying the PTE bits is crucial.
1547 static __inline void
1548 invlcaddr(void *caddr)
1551 invlpg((u_int)caddr);
1555 * Super fast pmap_pte routine best used when scanning
1556 * the pv lists. This eliminates many coarse-grained
1557 * invltlb calls. Note that many of the pv list
1558 * scans are across different pmaps. It is very wasteful
1559 * to do an entire invltlb for checking a single mapping.
1561 * If the given pmap is not the current pmap, pvh_global_lock
1562 * must be held and curthread pinned to a CPU.
1565 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1570 pde = pmap_pde(pmap, va);
1574 /* are we current address space or kernel? */
1575 if (pmap_is_current(pmap))
1576 return (vtopte(va));
1577 rw_assert(&pvh_global_lock, RA_WLOCKED);
1578 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1579 newpf = *pde & PG_FRAME;
1580 if ((*PMAP1 & PG_FRAME) != newpf) {
1581 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1583 PMAP1cpu = PCPU_GET(cpuid);
1589 if (PMAP1cpu != PCPU_GET(cpuid)) {
1590 PMAP1cpu = PCPU_GET(cpuid);
1596 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1602 pmap_pte_quick3(pmap_t pmap, vm_offset_t va)
1607 pde = pmap_pde(pmap, va);
1611 rw_assert(&pvh_global_lock, RA_WLOCKED);
1612 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1613 newpf = *pde & PG_FRAME;
1614 if ((*PMAP3 & PG_FRAME) != newpf) {
1615 *PMAP3 = newpf | PG_RW | PG_V | PG_A | PG_M;
1617 PMAP3cpu = PCPU_GET(cpuid);
1623 if (PMAP3cpu != PCPU_GET(cpuid)) {
1624 PMAP3cpu = PCPU_GET(cpuid);
1630 return (PADDR3 + (i386_btop(va) & (NPTEPG - 1)));
1636 pmap_pte_ufast(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1638 pt_entry_t *eh_ptep, pte, *ptep;
1640 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1643 eh_ptep = (pt_entry_t *)PCPU_GET(pmap_eh_ptep);
1644 if ((*eh_ptep & PG_FRAME) != pde) {
1645 *eh_ptep = pde | PG_RW | PG_V | PG_A | PG_M;
1646 invlcaddr((void *)PCPU_GET(pmap_eh_va));
1648 ptep = (pt_entry_t *)PCPU_GET(pmap_eh_va) + (i386_btop(va) &
1656 * Routine: pmap_extract
1658 * Extract the physical page address associated
1659 * with the given map/virtual_address pair.
1662 pmap_extract(pmap_t pmap, vm_offset_t va)
1670 pde = pmap->pm_pdir[va >> PDRSHIFT];
1672 if ((pde & PG_PS) != 0)
1673 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1675 pte = pmap_pte_ufast(pmap, va, pde);
1676 rtval = (pte & PG_FRAME) | (va & PAGE_MASK);
1684 * Routine: pmap_extract_and_hold
1686 * Atomically extract and hold the physical page
1687 * with the given pmap and virtual address pair
1688 * if that mapping permits the given protection.
1691 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1702 pde = *pmap_pde(pmap, va);
1705 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1706 if (vm_page_pa_tryrelock(pmap, (pde &
1707 PG_PS_FRAME) | (va & PDRMASK), &pa))
1709 m = PHYS_TO_VM_PAGE(pa);
1712 pte = pmap_pte_ufast(pmap, va, pde);
1714 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1715 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1718 m = PHYS_TO_VM_PAGE(pa);
1729 /***************************************************
1730 * Low level mapping routines.....
1731 ***************************************************/
1734 * Add a wired page to the kva.
1735 * Note: not SMP coherent.
1737 * This function may be used before pmap_bootstrap() is called.
1740 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1745 pte_store(pte, pa | PG_RW | PG_V);
1748 static __inline void
1749 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1754 pte_store(pte, pa | PG_RW | PG_V | pmap_cache_bits(kernel_pmap,
1759 * Remove a page from the kernel pagetables.
1760 * Note: not SMP coherent.
1762 * This function may be used before pmap_bootstrap() is called.
1765 pmap_kremove(vm_offset_t va)
1774 * Used to map a range of physical addresses into kernel
1775 * virtual address space.
1777 * The value passed in '*virt' is a suggested virtual address for
1778 * the mapping. Architectures which can support a direct-mapped
1779 * physical to virtual region can return the appropriate address
1780 * within that region, leaving '*virt' unchanged. Other
1781 * architectures should map the pages starting at '*virt' and
1782 * update '*virt' with the first usable address after the mapped
1786 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1788 vm_offset_t va, sva;
1789 vm_paddr_t superpage_offset;
1794 * Does the physical address range's size and alignment permit at
1795 * least one superpage mapping to be created?
1797 superpage_offset = start & PDRMASK;
1798 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1800 * Increase the starting virtual address so that its alignment
1801 * does not preclude the use of superpage mappings.
1803 if ((va & PDRMASK) < superpage_offset)
1804 va = (va & ~PDRMASK) + superpage_offset;
1805 else if ((va & PDRMASK) > superpage_offset)
1806 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1809 while (start < end) {
1810 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1812 KASSERT((va & PDRMASK) == 0,
1813 ("pmap_map: misaligned va %#x", va));
1814 newpde = start | PG_PS | PG_RW | PG_V;
1815 pmap_kenter_pde(va, newpde);
1819 pmap_kenter(va, start);
1824 pmap_invalidate_range(kernel_pmap, sva, va);
1831 * Add a list of wired pages to the kva
1832 * this routine is only used for temporary
1833 * kernel mappings that do not need to have
1834 * page modification or references recorded.
1835 * Note that old mappings are simply written
1836 * over. The page *must* be wired.
1837 * Note: SMP coherent. Uses a ranged shootdown IPI.
1840 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1842 pt_entry_t *endpte, oldpte, pa, *pte;
1847 endpte = pte + count;
1848 while (pte < endpte) {
1850 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(kernel_pmap,
1852 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1854 #if defined(PAE) || defined(PAE_TABLES)
1855 pte_store(pte, pa | pg_nx | PG_RW | PG_V);
1857 pte_store(pte, pa | PG_RW | PG_V);
1862 if (__predict_false((oldpte & PG_V) != 0))
1863 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1868 * This routine tears out page mappings from the
1869 * kernel -- it is meant only for temporary mappings.
1870 * Note: SMP coherent. Uses a ranged shootdown IPI.
1873 pmap_qremove(vm_offset_t sva, int count)
1878 while (count-- > 0) {
1882 pmap_invalidate_range(kernel_pmap, sva, va);
1885 /***************************************************
1886 * Page table page management routines.....
1887 ***************************************************/
1889 * Schedule the specified unused page table page to be freed. Specifically,
1890 * add the page to the specified list of pages that will be released to the
1891 * physical memory manager after the TLB has been updated.
1893 static __inline void
1894 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1895 boolean_t set_PG_ZERO)
1899 m->flags |= PG_ZERO;
1901 m->flags &= ~PG_ZERO;
1902 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1906 * Inserts the specified page table page into the specified pmap's collection
1907 * of idle page table pages. Each of a pmap's page table pages is responsible
1908 * for mapping a distinct range of virtual addresses. The pmap's collection is
1909 * ordered by this virtual address range.
1912 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1915 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1916 return (vm_radix_insert(&pmap->pm_root, mpte));
1920 * Removes the page table page mapping the specified virtual address from the
1921 * specified pmap's collection of idle page table pages, and returns it.
1922 * Otherwise, returns NULL if there is no page table page corresponding to the
1923 * specified virtual address.
1925 static __inline vm_page_t
1926 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
1929 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1930 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT));
1934 * Decrements a page table page's wire count, which is used to record the
1935 * number of valid page table entries within the page. If the wire count
1936 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1937 * page table page was unmapped and FALSE otherwise.
1939 static inline boolean_t
1940 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1944 if (m->wire_count == 0) {
1945 _pmap_unwire_ptp(pmap, m, free);
1952 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1956 * unmap the page table page
1958 pmap->pm_pdir[m->pindex] = 0;
1959 --pmap->pm_stats.resident_count;
1962 * There is not need to invalidate the recursive mapping since
1963 * we never instantiate such mapping for the usermode pmaps,
1964 * and never remove page table pages from the kernel pmap.
1965 * Put page on a list so that it is released since all TLB
1966 * shootdown is done.
1968 MPASS(pmap != kernel_pmap);
1969 pmap_add_delayed_free_list(m, free, TRUE);
1973 * After removing a page table entry, this routine is used to
1974 * conditionally free the page, and manage the hold/wire counts.
1977 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1982 if (pmap == kernel_pmap)
1984 ptepde = *pmap_pde(pmap, va);
1985 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1986 return (pmap_unwire_ptp(pmap, mpte, free));
1990 * Initialize the pmap for the swapper process.
1993 pmap_pinit0(pmap_t pmap)
1996 PMAP_LOCK_INIT(pmap);
1997 pmap->pm_pdir = IdlePTD;
1998 #if defined(PAE) || defined(PAE_TABLES)
1999 pmap->pm_pdpt = IdlePDPT;
2001 pmap->pm_root.rt_root = 0;
2002 CPU_ZERO(&pmap->pm_active);
2003 TAILQ_INIT(&pmap->pm_pvchunk);
2004 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2005 pmap_activate_boot(pmap);
2009 * Initialize a preallocated and zeroed pmap structure,
2010 * such as one in a vmspace structure.
2013 pmap_pinit(pmap_t pmap)
2019 * No need to allocate page table space yet but we do need a valid
2020 * page directory table.
2022 if (pmap->pm_pdir == NULL) {
2023 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
2024 if (pmap->pm_pdir == NULL)
2026 #if defined(PAE) || defined(PAE_TABLES)
2027 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
2028 KASSERT(((vm_offset_t)pmap->pm_pdpt &
2029 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
2030 ("pmap_pinit: pdpt misaligned"));
2031 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
2032 ("pmap_pinit: pdpt above 4g"));
2034 pmap->pm_root.rt_root = 0;
2036 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2037 ("pmap_pinit: pmap has reserved page table page(s)"));
2040 * allocate the page directory page(s)
2042 for (i = 0; i < NPGPTD;) {
2043 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2044 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2048 pmap->pm_ptdpg[i] = m;
2049 #if defined(PAE) || defined(PAE_TABLES)
2050 pmap->pm_pdpt[i] = VM_PAGE_TO_PHYS(m) | PG_V;
2056 pmap_qenter((vm_offset_t)pmap->pm_pdir, pmap->pm_ptdpg, NPGPTD);
2058 for (i = 0; i < NPGPTD; i++)
2059 if ((pmap->pm_ptdpg[i]->flags & PG_ZERO) == 0)
2060 pagezero(pmap->pm_pdir + (i * NPDEPG));
2062 /* Install the trampoline mapping. */
2063 pmap->pm_pdir[TRPTDI] = PTD[TRPTDI];
2065 CPU_ZERO(&pmap->pm_active);
2066 TAILQ_INIT(&pmap->pm_pvchunk);
2067 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2073 * this routine is called if the page table page is not
2077 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
2083 * Allocate a page table page.
2085 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2086 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2087 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2089 rw_wunlock(&pvh_global_lock);
2091 rw_wlock(&pvh_global_lock);
2096 * Indicate the need to retry. While waiting, the page table
2097 * page may have been allocated.
2101 if ((m->flags & PG_ZERO) == 0)
2105 * Map the pagetable page into the process address space, if
2106 * it isn't already there.
2109 pmap->pm_stats.resident_count++;
2111 ptepa = VM_PAGE_TO_PHYS(m);
2112 pmap->pm_pdir[ptepindex] =
2113 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
2119 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
2126 * Calculate pagetable page index
2128 ptepindex = va >> PDRSHIFT;
2131 * Get the page directory entry
2133 ptepa = pmap->pm_pdir[ptepindex];
2136 * This supports switching from a 4MB page to a
2139 if (ptepa & PG_PS) {
2140 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
2141 ptepa = pmap->pm_pdir[ptepindex];
2145 * If the page table page is mapped, we just increment the
2146 * hold count, and activate it.
2149 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
2153 * Here if the pte page isn't mapped, or if it has
2156 m = _pmap_allocpte(pmap, ptepindex, flags);
2157 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2164 /***************************************************
2165 * Pmap allocation/deallocation routines.
2166 ***************************************************/
2169 * Release any resources held by the given physical map.
2170 * Called when a pmap initialized by pmap_pinit is being released.
2171 * Should only be called if the map contains no valid mappings.
2174 pmap_release(pmap_t pmap)
2179 KASSERT(pmap->pm_stats.resident_count == 0,
2180 ("pmap_release: pmap resident count %ld != 0",
2181 pmap->pm_stats.resident_count));
2182 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2183 ("pmap_release: pmap has reserved page table page(s)"));
2184 KASSERT(CPU_EMPTY(&pmap->pm_active),
2185 ("releasing active pmap %p", pmap));
2187 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2189 for (i = 0; i < NPGPTD; i++) {
2190 m = pmap->pm_ptdpg[i];
2191 #if defined(PAE) || defined(PAE_TABLES)
2192 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2193 ("pmap_release: got wrong ptd page"));
2195 vm_page_unwire_noq(m);
2201 kvm_size(SYSCTL_HANDLER_ARGS)
2203 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2205 return (sysctl_handle_long(oidp, &ksize, 0, req));
2207 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2208 0, 0, kvm_size, "IU", "Size of KVM");
2211 kvm_free(SYSCTL_HANDLER_ARGS)
2213 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2215 return (sysctl_handle_long(oidp, &kfree, 0, req));
2217 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2218 0, 0, kvm_free, "IU", "Amount of KVM free");
2221 * grow the number of kernel page table entries, if needed
2224 pmap_growkernel(vm_offset_t addr)
2226 vm_paddr_t ptppaddr;
2230 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2231 addr = roundup2(addr, NBPDR);
2232 if (addr - 1 >= vm_map_max(kernel_map))
2233 addr = vm_map_max(kernel_map);
2234 while (kernel_vm_end < addr) {
2235 if (pdir_pde(PTD, kernel_vm_end)) {
2236 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2237 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2238 kernel_vm_end = vm_map_max(kernel_map);
2244 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2245 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2248 panic("pmap_growkernel: no memory to grow kernel");
2252 if ((nkpg->flags & PG_ZERO) == 0)
2253 pmap_zero_page(nkpg);
2254 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2255 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2256 pdir_pde(KPTD, kernel_vm_end) = newpdir;
2258 pmap_kenter_pde(kernel_vm_end, newpdir);
2259 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2260 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2261 kernel_vm_end = vm_map_max(kernel_map);
2268 /***************************************************
2269 * page management routines.
2270 ***************************************************/
2272 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2273 CTASSERT(_NPCM == 11);
2274 CTASSERT(_NPCPV == 336);
2276 static __inline struct pv_chunk *
2277 pv_to_chunk(pv_entry_t pv)
2280 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2283 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2285 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2286 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2288 static const uint32_t pc_freemask[_NPCM] = {
2289 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2290 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2291 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2292 PC_FREE0_9, PC_FREE10
2295 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2296 "Current number of pv entries");
2299 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2301 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2302 "Current number of pv entry chunks");
2303 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2304 "Current number of pv entry chunks allocated");
2305 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2306 "Current number of pv entry chunks frees");
2307 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2308 "Number of times tried to get a chunk page but failed.");
2310 static long pv_entry_frees, pv_entry_allocs;
2311 static int pv_entry_spare;
2313 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2314 "Current number of pv entry frees");
2315 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2316 "Current number of pv entry allocs");
2317 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2318 "Current number of spare pv entries");
2322 * We are in a serious low memory condition. Resort to
2323 * drastic measures to free some pages so we can allocate
2324 * another pv entry chunk.
2327 pmap_pv_reclaim(pmap_t locked_pmap)
2330 struct pv_chunk *pc;
2331 struct md_page *pvh;
2334 pt_entry_t *pte, tpte;
2338 struct spglist free;
2340 int bit, field, freed;
2342 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2346 TAILQ_INIT(&newtail);
2347 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2348 SLIST_EMPTY(&free))) {
2349 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2350 if (pmap != pc->pc_pmap) {
2352 pmap_invalidate_all(pmap);
2353 if (pmap != locked_pmap)
2357 /* Avoid deadlock and lock recursion. */
2358 if (pmap > locked_pmap)
2360 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2362 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2368 * Destroy every non-wired, 4 KB page mapping in the chunk.
2371 for (field = 0; field < _NPCM; field++) {
2372 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2373 inuse != 0; inuse &= ~(1UL << bit)) {
2375 pv = &pc->pc_pventry[field * 32 + bit];
2377 pde = pmap_pde(pmap, va);
2378 if ((*pde & PG_PS) != 0)
2380 pte = pmap_pte(pmap, va);
2382 if ((tpte & PG_W) == 0)
2383 tpte = pte_load_clear(pte);
2384 pmap_pte_release(pte);
2385 if ((tpte & PG_W) != 0)
2388 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2390 if ((tpte & PG_G) != 0)
2391 pmap_invalidate_page(pmap, va);
2392 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2393 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2395 if ((tpte & PG_A) != 0)
2396 vm_page_aflag_set(m, PGA_REFERENCED);
2397 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2398 if (TAILQ_EMPTY(&m->md.pv_list) &&
2399 (m->flags & PG_FICTITIOUS) == 0) {
2400 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2401 if (TAILQ_EMPTY(&pvh->pv_list)) {
2402 vm_page_aflag_clear(m,
2406 pc->pc_map[field] |= 1UL << bit;
2407 pmap_unuse_pt(pmap, va, &free);
2412 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2415 /* Every freed mapping is for a 4 KB page. */
2416 pmap->pm_stats.resident_count -= freed;
2417 PV_STAT(pv_entry_frees += freed);
2418 PV_STAT(pv_entry_spare += freed);
2419 pv_entry_count -= freed;
2420 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2421 for (field = 0; field < _NPCM; field++)
2422 if (pc->pc_map[field] != pc_freemask[field]) {
2423 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2425 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2428 * One freed pv entry in locked_pmap is
2431 if (pmap == locked_pmap)
2435 if (field == _NPCM) {
2436 PV_STAT(pv_entry_spare -= _NPCPV);
2437 PV_STAT(pc_chunk_count--);
2438 PV_STAT(pc_chunk_frees++);
2439 /* Entire chunk is free; return it. */
2440 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2441 pmap_qremove((vm_offset_t)pc, 1);
2442 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2447 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2449 pmap_invalidate_all(pmap);
2450 if (pmap != locked_pmap)
2453 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2454 m_pc = SLIST_FIRST(&free);
2455 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2456 /* Recycle a freed page table page. */
2457 m_pc->wire_count = 1;
2459 vm_page_free_pages_toq(&free, true);
2464 * free the pv_entry back to the free list
2467 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2469 struct pv_chunk *pc;
2470 int idx, field, bit;
2472 rw_assert(&pvh_global_lock, RA_WLOCKED);
2473 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2474 PV_STAT(pv_entry_frees++);
2475 PV_STAT(pv_entry_spare++);
2477 pc = pv_to_chunk(pv);
2478 idx = pv - &pc->pc_pventry[0];
2481 pc->pc_map[field] |= 1ul << bit;
2482 for (idx = 0; idx < _NPCM; idx++)
2483 if (pc->pc_map[idx] != pc_freemask[idx]) {
2485 * 98% of the time, pc is already at the head of the
2486 * list. If it isn't already, move it to the head.
2488 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2490 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2491 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2496 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2501 free_pv_chunk(struct pv_chunk *pc)
2505 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2506 PV_STAT(pv_entry_spare -= _NPCPV);
2507 PV_STAT(pc_chunk_count--);
2508 PV_STAT(pc_chunk_frees++);
2509 /* entire chunk is free, return it */
2510 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2511 pmap_qremove((vm_offset_t)pc, 1);
2512 vm_page_unwire(m, PQ_NONE);
2514 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2518 * get a new pv_entry, allocating a block from the system
2522 get_pv_entry(pmap_t pmap, boolean_t try)
2524 static const struct timeval printinterval = { 60, 0 };
2525 static struct timeval lastprint;
2528 struct pv_chunk *pc;
2531 rw_assert(&pvh_global_lock, RA_WLOCKED);
2532 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2533 PV_STAT(pv_entry_allocs++);
2535 if (pv_entry_count > pv_entry_high_water)
2536 if (ratecheck(&lastprint, &printinterval))
2537 printf("Approaching the limit on PV entries, consider "
2538 "increasing either the vm.pmap.shpgperproc or the "
2539 "vm.pmap.pv_entry_max tunable.\n");
2541 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2543 for (field = 0; field < _NPCM; field++) {
2544 if (pc->pc_map[field]) {
2545 bit = bsfl(pc->pc_map[field]);
2549 if (field < _NPCM) {
2550 pv = &pc->pc_pventry[field * 32 + bit];
2551 pc->pc_map[field] &= ~(1ul << bit);
2552 /* If this was the last item, move it to tail */
2553 for (field = 0; field < _NPCM; field++)
2554 if (pc->pc_map[field] != 0) {
2555 PV_STAT(pv_entry_spare--);
2556 return (pv); /* not full, return */
2558 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2559 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2560 PV_STAT(pv_entry_spare--);
2565 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2566 * global lock. If "pv_vafree" is currently non-empty, it will
2567 * remain non-empty until pmap_ptelist_alloc() completes.
2569 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2570 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2573 PV_STAT(pc_chunk_tryfail++);
2576 m = pmap_pv_reclaim(pmap);
2580 PV_STAT(pc_chunk_count++);
2581 PV_STAT(pc_chunk_allocs++);
2582 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2583 pmap_qenter((vm_offset_t)pc, &m, 1);
2585 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2586 for (field = 1; field < _NPCM; field++)
2587 pc->pc_map[field] = pc_freemask[field];
2588 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2589 pv = &pc->pc_pventry[0];
2590 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2591 PV_STAT(pv_entry_spare += _NPCPV - 1);
2595 static __inline pv_entry_t
2596 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2600 rw_assert(&pvh_global_lock, RA_WLOCKED);
2601 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2602 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2603 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2611 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2613 struct md_page *pvh;
2615 vm_offset_t va_last;
2618 rw_assert(&pvh_global_lock, RA_WLOCKED);
2619 KASSERT((pa & PDRMASK) == 0,
2620 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2623 * Transfer the 4mpage's pv entry for this mapping to the first
2626 pvh = pa_to_pvh(pa);
2627 va = trunc_4mpage(va);
2628 pv = pmap_pvh_remove(pvh, pmap, va);
2629 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2630 m = PHYS_TO_VM_PAGE(pa);
2631 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2632 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2633 va_last = va + NBPDR - PAGE_SIZE;
2636 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2637 ("pmap_pv_demote_pde: page %p is not managed", m));
2639 pmap_insert_entry(pmap, va, m);
2640 } while (va < va_last);
2643 #if VM_NRESERVLEVEL > 0
2645 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2647 struct md_page *pvh;
2649 vm_offset_t va_last;
2652 rw_assert(&pvh_global_lock, RA_WLOCKED);
2653 KASSERT((pa & PDRMASK) == 0,
2654 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2657 * Transfer the first page's pv entry for this mapping to the
2658 * 4mpage's pv list. Aside from avoiding the cost of a call
2659 * to get_pv_entry(), a transfer avoids the possibility that
2660 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2661 * removes one of the mappings that is being promoted.
2663 m = PHYS_TO_VM_PAGE(pa);
2664 va = trunc_4mpage(va);
2665 pv = pmap_pvh_remove(&m->md, pmap, va);
2666 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2667 pvh = pa_to_pvh(pa);
2668 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2669 /* Free the remaining NPTEPG - 1 pv entries. */
2670 va_last = va + NBPDR - PAGE_SIZE;
2674 pmap_pvh_free(&m->md, pmap, va);
2675 } while (va < va_last);
2677 #endif /* VM_NRESERVLEVEL > 0 */
2680 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2684 pv = pmap_pvh_remove(pvh, pmap, va);
2685 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2686 free_pv_entry(pmap, pv);
2690 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2692 struct md_page *pvh;
2694 rw_assert(&pvh_global_lock, RA_WLOCKED);
2695 pmap_pvh_free(&m->md, pmap, va);
2696 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2697 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2698 if (TAILQ_EMPTY(&pvh->pv_list))
2699 vm_page_aflag_clear(m, PGA_WRITEABLE);
2704 * Create a pv entry for page at pa for
2708 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2712 rw_assert(&pvh_global_lock, RA_WLOCKED);
2713 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2714 pv = get_pv_entry(pmap, FALSE);
2716 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2720 * Conditionally create a pv entry.
2723 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2727 rw_assert(&pvh_global_lock, RA_WLOCKED);
2728 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2729 if (pv_entry_count < pv_entry_high_water &&
2730 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2732 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2739 * Create the pv entries for each of the pages within a superpage.
2742 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags)
2744 struct md_page *pvh;
2748 rw_assert(&pvh_global_lock, RA_WLOCKED);
2749 noreclaim = (flags & PMAP_ENTER_NORECLAIM) != 0;
2750 if ((noreclaim && pv_entry_count >= pv_entry_high_water) ||
2751 (pv = get_pv_entry(pmap, noreclaim)) == NULL)
2754 pvh = pa_to_pvh(pde & PG_PS_FRAME);
2755 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2760 * Fills a page table page with mappings to consecutive physical pages.
2763 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2767 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2769 newpte += PAGE_SIZE;
2774 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2775 * 2- or 4MB page mapping is invalidated.
2778 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2780 pd_entry_t newpde, oldpde;
2781 pt_entry_t *firstpte, newpte;
2784 struct spglist free;
2787 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2789 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2790 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2791 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
2793 KASSERT((oldpde & PG_W) == 0,
2794 ("pmap_demote_pde: page table page for a wired mapping"
2798 * Invalidate the 2- or 4MB page mapping and return
2799 * "failure" if the mapping was never accessed or the
2800 * allocation of the new page table page fails.
2802 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2803 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2804 VM_ALLOC_WIRED)) == NULL) {
2806 sva = trunc_4mpage(va);
2807 pmap_remove_pde(pmap, pde, sva, &free);
2808 if ((oldpde & PG_G) == 0)
2809 pmap_invalidate_pde_page(pmap, sva, oldpde);
2810 vm_page_free_pages_toq(&free, true);
2811 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2812 " in pmap %p", va, pmap);
2815 if (pmap != kernel_pmap)
2816 pmap->pm_stats.resident_count++;
2818 mptepa = VM_PAGE_TO_PHYS(mpte);
2821 * If the page mapping is in the kernel's address space, then the
2822 * KPTmap can provide access to the page table page. Otherwise,
2823 * temporarily map the page table page (mpte) into the kernel's
2824 * address space at either PADDR1 or PADDR2.
2826 if (pmap == kernel_pmap)
2827 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2828 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2829 if ((*PMAP1 & PG_FRAME) != mptepa) {
2830 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2832 PMAP1cpu = PCPU_GET(cpuid);
2838 if (PMAP1cpu != PCPU_GET(cpuid)) {
2839 PMAP1cpu = PCPU_GET(cpuid);
2847 mtx_lock(&PMAP2mutex);
2848 if ((*PMAP2 & PG_FRAME) != mptepa) {
2849 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2850 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2854 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2855 KASSERT((oldpde & PG_A) != 0,
2856 ("pmap_demote_pde: oldpde is missing PG_A"));
2857 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2858 ("pmap_demote_pde: oldpde is missing PG_M"));
2859 newpte = oldpde & ~PG_PS;
2860 if ((newpte & PG_PDE_PAT) != 0)
2861 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2864 * If the page table page is new, initialize it.
2866 if (mpte->wire_count == 1) {
2867 mpte->wire_count = NPTEPG;
2868 pmap_fill_ptp(firstpte, newpte);
2870 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2871 ("pmap_demote_pde: firstpte and newpte map different physical"
2875 * If the mapping has changed attributes, update the page table
2878 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2879 pmap_fill_ptp(firstpte, newpte);
2882 * Demote the mapping. This pmap is locked. The old PDE has
2883 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2884 * set. Thus, there is no danger of a race with another
2885 * processor changing the setting of PG_A and/or PG_M between
2886 * the read above and the store below.
2888 if (workaround_erratum383)
2889 pmap_update_pde(pmap, va, pde, newpde);
2890 else if (pmap == kernel_pmap)
2891 pmap_kenter_pde(va, newpde);
2893 pde_store(pde, newpde);
2894 if (firstpte == PADDR2)
2895 mtx_unlock(&PMAP2mutex);
2898 * Invalidate the recursive mapping of the page table page.
2900 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2903 * Demote the pv entry. This depends on the earlier demotion
2904 * of the mapping. Specifically, the (re)creation of a per-
2905 * page pv entry might trigger the execution of pmap_collect(),
2906 * which might reclaim a newly (re)created per-page pv entry
2907 * and destroy the associated mapping. In order to destroy
2908 * the mapping, the PDE must have already changed from mapping
2909 * the 2mpage to referencing the page table page.
2911 if ((oldpde & PG_MANAGED) != 0)
2912 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2914 pmap_pde_demotions++;
2915 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2916 " in pmap %p", va, pmap);
2921 * Removes a 2- or 4MB page mapping from the kernel pmap.
2924 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2930 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2931 mpte = pmap_remove_pt_page(pmap, va);
2933 panic("pmap_remove_kernel_pde: Missing pt page.");
2935 mptepa = VM_PAGE_TO_PHYS(mpte);
2936 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2939 * Initialize the page table page.
2941 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2944 * Remove the mapping.
2946 if (workaround_erratum383)
2947 pmap_update_pde(pmap, va, pde, newpde);
2949 pmap_kenter_pde(va, newpde);
2952 * Invalidate the recursive mapping of the page table page.
2954 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2958 * pmap_remove_pde: do the things to unmap a superpage in a process
2961 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2962 struct spglist *free)
2964 struct md_page *pvh;
2966 vm_offset_t eva, va;
2969 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2970 KASSERT((sva & PDRMASK) == 0,
2971 ("pmap_remove_pde: sva is not 4mpage aligned"));
2972 oldpde = pte_load_clear(pdq);
2974 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2977 * Machines that don't support invlpg, also don't support
2980 if ((oldpde & PG_G) != 0)
2981 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
2983 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2984 if (oldpde & PG_MANAGED) {
2985 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2986 pmap_pvh_free(pvh, pmap, sva);
2988 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2989 va < eva; va += PAGE_SIZE, m++) {
2990 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2993 vm_page_aflag_set(m, PGA_REFERENCED);
2994 if (TAILQ_EMPTY(&m->md.pv_list) &&
2995 TAILQ_EMPTY(&pvh->pv_list))
2996 vm_page_aflag_clear(m, PGA_WRITEABLE);
2999 if (pmap == kernel_pmap) {
3000 pmap_remove_kernel_pde(pmap, pdq, sva);
3002 mpte = pmap_remove_pt_page(pmap, sva);
3004 pmap->pm_stats.resident_count--;
3005 KASSERT(mpte->wire_count == NPTEPG,
3006 ("pmap_remove_pde: pte page wire count error"));
3007 mpte->wire_count = 0;
3008 pmap_add_delayed_free_list(mpte, free, FALSE);
3014 * pmap_remove_pte: do the things to unmap a page in a process
3017 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
3018 struct spglist *free)
3023 rw_assert(&pvh_global_lock, RA_WLOCKED);
3024 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3025 oldpte = pte_load_clear(ptq);
3026 KASSERT(oldpte != 0,
3027 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
3029 pmap->pm_stats.wired_count -= 1;
3031 * Machines that don't support invlpg, also don't support
3035 pmap_invalidate_page(kernel_pmap, va);
3036 pmap->pm_stats.resident_count -= 1;
3037 if (oldpte & PG_MANAGED) {
3038 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
3039 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3042 vm_page_aflag_set(m, PGA_REFERENCED);
3043 pmap_remove_entry(pmap, m, va);
3045 return (pmap_unuse_pt(pmap, va, free));
3049 * Remove a single page from a process address space
3052 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
3056 rw_assert(&pvh_global_lock, RA_WLOCKED);
3057 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3058 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3059 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
3061 pmap_remove_pte(pmap, pte, va, free);
3062 pmap_invalidate_page(pmap, va);
3066 * Removes the specified range of addresses from the page table page.
3069 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
3070 struct spglist *free)
3075 rw_assert(&pvh_global_lock, RA_WLOCKED);
3076 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3077 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3079 for (pte = pmap_pte_quick(pmap, sva); sva != eva; pte++,
3085 * The TLB entry for a PG_G mapping is invalidated by
3086 * pmap_remove_pte().
3088 if ((*pte & PG_G) == 0)
3091 if (pmap_remove_pte(pmap, pte, sva, free))
3098 * Remove the given range of addresses from the specified map.
3100 * It is assumed that the start and end are properly
3101 * rounded to the page size.
3104 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3108 struct spglist free;
3112 * Perform an unsynchronized read. This is, however, safe.
3114 if (pmap->pm_stats.resident_count == 0)
3120 rw_wlock(&pvh_global_lock);
3125 * special handling of removing one page. a very
3126 * common operation and easy to short circuit some
3129 if ((sva + PAGE_SIZE == eva) &&
3130 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
3131 pmap_remove_page(pmap, sva, &free);
3135 for (; sva < eva; sva = pdnxt) {
3139 * Calculate index for next page table.
3141 pdnxt = (sva + NBPDR) & ~PDRMASK;
3144 if (pmap->pm_stats.resident_count == 0)
3147 pdirindex = sva >> PDRSHIFT;
3148 ptpaddr = pmap->pm_pdir[pdirindex];
3151 * Weed out invalid mappings. Note: we assume that the page
3152 * directory table is always allocated, and in kernel virtual.
3158 * Check for large page.
3160 if ((ptpaddr & PG_PS) != 0) {
3162 * Are we removing the entire large page? If not,
3163 * demote the mapping and fall through.
3165 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3167 * The TLB entry for a PG_G mapping is
3168 * invalidated by pmap_remove_pde().
3170 if ((ptpaddr & PG_G) == 0)
3172 pmap_remove_pde(pmap,
3173 &pmap->pm_pdir[pdirindex], sva, &free);
3175 } else if (!pmap_demote_pde(pmap,
3176 &pmap->pm_pdir[pdirindex], sva)) {
3177 /* The large page mapping was destroyed. */
3183 * Limit our scan to either the end of the va represented
3184 * by the current page table page, or to the end of the
3185 * range being removed.
3190 if (pmap_remove_ptes(pmap, sva, pdnxt, &free))
3196 pmap_invalidate_all(pmap);
3197 rw_wunlock(&pvh_global_lock);
3199 vm_page_free_pages_toq(&free, true);
3203 * Routine: pmap_remove_all
3205 * Removes this physical page from
3206 * all physical maps in which it resides.
3207 * Reflects back modify bits to the pager.
3210 * Original versions of this routine were very
3211 * inefficient because they iteratively called
3212 * pmap_remove (slow...)
3216 pmap_remove_all(vm_page_t m)
3218 struct md_page *pvh;
3221 pt_entry_t *pte, tpte;
3224 struct spglist free;
3226 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3227 ("pmap_remove_all: page %p is not managed", m));
3229 rw_wlock(&pvh_global_lock);
3231 if ((m->flags & PG_FICTITIOUS) != 0)
3232 goto small_mappings;
3233 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3234 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3238 pde = pmap_pde(pmap, va);
3239 (void)pmap_demote_pde(pmap, pde, va);
3243 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3246 pmap->pm_stats.resident_count--;
3247 pde = pmap_pde(pmap, pv->pv_va);
3248 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3249 " a 4mpage in page %p's pv list", m));
3250 pte = pmap_pte_quick(pmap, pv->pv_va);
3251 tpte = pte_load_clear(pte);
3252 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3255 pmap->pm_stats.wired_count--;
3257 vm_page_aflag_set(m, PGA_REFERENCED);
3260 * Update the vm_page_t clean and reference bits.
3262 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3264 pmap_unuse_pt(pmap, pv->pv_va, &free);
3265 pmap_invalidate_page(pmap, pv->pv_va);
3266 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3267 free_pv_entry(pmap, pv);
3270 vm_page_aflag_clear(m, PGA_WRITEABLE);
3272 rw_wunlock(&pvh_global_lock);
3273 vm_page_free_pages_toq(&free, true);
3277 * pmap_protect_pde: do the things to protect a 4mpage in a process
3280 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3282 pd_entry_t newpde, oldpde;
3283 vm_offset_t eva, va;
3285 boolean_t anychanged;
3287 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3288 KASSERT((sva & PDRMASK) == 0,
3289 ("pmap_protect_pde: sva is not 4mpage aligned"));
3292 oldpde = newpde = *pde;
3293 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
3294 (PG_MANAGED | PG_M | PG_RW)) {
3296 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3297 va < eva; va += PAGE_SIZE, m++)
3300 if ((prot & VM_PROT_WRITE) == 0)
3301 newpde &= ~(PG_RW | PG_M);
3302 #if defined(PAE) || defined(PAE_TABLES)
3303 if ((prot & VM_PROT_EXECUTE) == 0)
3306 if (newpde != oldpde) {
3308 * As an optimization to future operations on this PDE, clear
3309 * PG_PROMOTED. The impending invalidation will remove any
3310 * lingering 4KB page mappings from the TLB.
3312 if (!pde_cmpset(pde, oldpde, newpde & ~PG_PROMOTED))
3314 if ((oldpde & PG_G) != 0)
3315 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
3319 return (anychanged);
3323 * Set the physical protection on the
3324 * specified range of this map as requested.
3327 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3332 boolean_t anychanged, pv_lists_locked;
3334 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3335 if (prot == VM_PROT_NONE) {
3336 pmap_remove(pmap, sva, eva);
3340 #if defined(PAE) || defined(PAE_TABLES)
3341 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3342 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3345 if (prot & VM_PROT_WRITE)
3349 if (pmap_is_current(pmap))
3350 pv_lists_locked = FALSE;
3352 pv_lists_locked = TRUE;
3354 rw_wlock(&pvh_global_lock);
3360 for (; sva < eva; sva = pdnxt) {
3361 pt_entry_t obits, pbits;
3364 pdnxt = (sva + NBPDR) & ~PDRMASK;
3368 pdirindex = sva >> PDRSHIFT;
3369 ptpaddr = pmap->pm_pdir[pdirindex];
3372 * Weed out invalid mappings. Note: we assume that the page
3373 * directory table is always allocated, and in kernel virtual.
3379 * Check for large page.
3381 if ((ptpaddr & PG_PS) != 0) {
3383 * Are we protecting the entire large page? If not,
3384 * demote the mapping and fall through.
3386 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3388 * The TLB entry for a PG_G mapping is
3389 * invalidated by pmap_protect_pde().
3391 if (pmap_protect_pde(pmap,
3392 &pmap->pm_pdir[pdirindex], sva, prot))
3396 if (!pv_lists_locked) {
3397 pv_lists_locked = TRUE;
3398 if (!rw_try_wlock(&pvh_global_lock)) {
3400 pmap_invalidate_all(
3407 if (!pmap_demote_pde(pmap,
3408 &pmap->pm_pdir[pdirindex], sva)) {
3410 * The large page mapping was
3421 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3427 * Regardless of whether a pte is 32 or 64 bits in
3428 * size, PG_RW, PG_A, and PG_M are among the least
3429 * significant 32 bits.
3431 obits = pbits = *pte;
3432 if ((pbits & PG_V) == 0)
3435 if ((prot & VM_PROT_WRITE) == 0) {
3436 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3437 (PG_MANAGED | PG_M | PG_RW)) {
3438 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3441 pbits &= ~(PG_RW | PG_M);
3443 #if defined(PAE) || defined(PAE_TABLES)
3444 if ((prot & VM_PROT_EXECUTE) == 0)
3448 if (pbits != obits) {
3449 #if defined(PAE) || defined(PAE_TABLES)
3450 if (!atomic_cmpset_64(pte, obits, pbits))
3453 if (!atomic_cmpset_int((u_int *)pte, obits,
3458 pmap_invalidate_page(pmap, sva);
3465 pmap_invalidate_all(pmap);
3466 if (pv_lists_locked) {
3468 rw_wunlock(&pvh_global_lock);
3473 #if VM_NRESERVLEVEL > 0
3475 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3476 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3477 * For promotion to occur, two conditions must be met: (1) the 4KB page
3478 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3479 * mappings must have identical characteristics.
3481 * Managed (PG_MANAGED) mappings within the kernel address space are not
3482 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3483 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3487 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3490 pt_entry_t *firstpte, oldpte, pa, *pte;
3491 vm_offset_t oldpteva;
3494 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3497 * Examine the first PTE in the specified PTP. Abort if this PTE is
3498 * either invalid, unused, or does not map the first 4KB physical page
3499 * within a 2- or 4MB page.
3501 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3504 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3505 pmap_pde_p_failures++;
3506 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3507 " in pmap %p", va, pmap);
3510 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3511 pmap_pde_p_failures++;
3512 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3513 " in pmap %p", va, pmap);
3516 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3518 * When PG_M is already clear, PG_RW can be cleared without
3519 * a TLB invalidation.
3521 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3528 * Examine each of the other PTEs in the specified PTP. Abort if this
3529 * PTE maps an unexpected 4KB physical page or does not have identical
3530 * characteristics to the first PTE.
3532 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3533 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3536 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3537 pmap_pde_p_failures++;
3538 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3539 " in pmap %p", va, pmap);
3542 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3544 * When PG_M is already clear, PG_RW can be cleared
3545 * without a TLB invalidation.
3547 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3551 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3553 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3554 " in pmap %p", oldpteva, pmap);
3556 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3557 pmap_pde_p_failures++;
3558 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3559 " in pmap %p", va, pmap);
3566 * Save the page table page in its current state until the PDE
3567 * mapping the superpage is demoted by pmap_demote_pde() or
3568 * destroyed by pmap_remove_pde().
3570 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3571 KASSERT(mpte >= vm_page_array &&
3572 mpte < &vm_page_array[vm_page_array_size],
3573 ("pmap_promote_pde: page table page is out of range"));
3574 KASSERT(mpte->pindex == va >> PDRSHIFT,
3575 ("pmap_promote_pde: page table page's pindex is wrong"));
3576 if (pmap_insert_pt_page(pmap, mpte)) {
3577 pmap_pde_p_failures++;
3579 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3585 * Promote the pv entries.
3587 if ((newpde & PG_MANAGED) != 0)
3588 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3591 * Propagate the PAT index to its proper position.
3593 if ((newpde & PG_PTE_PAT) != 0)
3594 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3597 * Map the superpage.
3599 if (workaround_erratum383)
3600 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3601 else if (pmap == kernel_pmap)
3602 pmap_kenter_pde(va, PG_PROMOTED | PG_PS | newpde);
3604 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
3606 pmap_pde_promotions++;
3607 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3608 " in pmap %p", va, pmap);
3610 #endif /* VM_NRESERVLEVEL > 0 */
3613 * Insert the given physical page (p) at
3614 * the specified virtual address (v) in the
3615 * target physical map with the protection requested.
3617 * If specified, the page will be wired down, meaning
3618 * that the related pte can not be reclaimed.
3620 * NB: This is the only routine which MAY NOT lazy-evaluate
3621 * or lose information. That is, this routine must actually
3622 * insert this page into the given map NOW.
3625 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3626 u_int flags, int8_t psind)
3630 pt_entry_t newpte, origpte;
3636 va = trunc_page(va);
3637 KASSERT((pmap == kernel_pmap && va < VM_MAX_KERNEL_ADDRESS) ||
3638 (pmap != kernel_pmap && va < VM_MAXUSER_ADDRESS),
3639 ("pmap_enter: toobig k%d %#x", pmap == kernel_pmap, va));
3640 KASSERT(va < PMAP_TRM_MIN_ADDRESS,
3641 ("pmap_enter: invalid to pmap_enter into trampoline (va: 0x%x)",
3643 KASSERT(pmap != kernel_pmap || (m->oflags & VPO_UNMANAGED) != 0 ||
3644 va < kmi.clean_sva || va >= kmi.clean_eva,
3645 ("pmap_enter: managed mapping within the clean submap"));
3646 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3647 VM_OBJECT_ASSERT_LOCKED(m->object);
3648 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
3649 ("pmap_enter: flags %u has reserved bits set", flags));
3650 pa = VM_PAGE_TO_PHYS(m);
3651 newpte = (pt_entry_t)(pa | PG_A | PG_V);
3652 if ((flags & VM_PROT_WRITE) != 0)
3654 if ((prot & VM_PROT_WRITE) != 0)
3656 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
3657 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
3658 #if defined(PAE) || defined(PAE_TABLES)
3659 if ((prot & VM_PROT_EXECUTE) == 0)
3662 if ((flags & PMAP_ENTER_WIRED) != 0)
3664 if (pmap != kernel_pmap)
3666 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
3667 if ((m->oflags & VPO_UNMANAGED) == 0)
3668 newpte |= PG_MANAGED;
3670 rw_wlock(&pvh_global_lock);
3674 /* Assert the required virtual and physical alignment. */
3675 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
3676 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3677 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m);
3681 pde = pmap_pde(pmap, va);
3682 if (pmap != kernel_pmap) {
3685 * In the case that a page table page is not resident,
3686 * we are creating it here. pmap_allocpte() handles
3689 mpte = pmap_allocpte(pmap, va, flags);
3691 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3692 ("pmap_allocpte failed with sleep allowed"));
3693 rv = KERN_RESOURCE_SHORTAGE;
3698 * va is for KVA, so pmap_demote_pde() will never fail
3699 * to install a page table page. PG_V is also
3700 * asserted by pmap_demote_pde().
3703 KASSERT(pde != NULL && (*pde & PG_V) != 0,
3704 ("KVA %#x invalid pde pdir %#jx", va,
3705 (uintmax_t)pmap->pm_pdir[PTDPTDI]));
3706 if ((*pde & PG_PS) != 0)
3707 pmap_demote_pde(pmap, pde, va);
3709 pte = pmap_pte_quick(pmap, va);
3712 * Page Directory table entry is not valid, which should not
3713 * happen. We should have either allocated the page table
3714 * page or demoted the existing mapping above.
3717 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3718 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3725 * Is the specified virtual address already mapped?
3727 if ((origpte & PG_V) != 0) {
3729 * Wiring change, just update stats. We don't worry about
3730 * wiring PT pages as they remain resident as long as there
3731 * are valid mappings in them. Hence, if a user page is wired,
3732 * the PT page will be also.
3734 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
3735 pmap->pm_stats.wired_count++;
3736 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
3737 pmap->pm_stats.wired_count--;
3740 * Remove the extra PT page reference.
3744 KASSERT(mpte->wire_count > 0,
3745 ("pmap_enter: missing reference to page table page,"
3750 * Has the physical page changed?
3752 opa = origpte & PG_FRAME;
3755 * No, might be a protection or wiring change.
3757 if ((origpte & PG_MANAGED) != 0 &&
3758 (newpte & PG_RW) != 0)
3759 vm_page_aflag_set(m, PGA_WRITEABLE);
3760 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
3766 * The physical page has changed. Temporarily invalidate
3767 * the mapping. This ensures that all threads sharing the
3768 * pmap keep a consistent view of the mapping, which is
3769 * necessary for the correct handling of COW faults. It
3770 * also permits reuse of the old mapping's PV entry,
3771 * avoiding an allocation.
3773 * For consistency, handle unmanaged mappings the same way.
3775 origpte = pte_load_clear(pte);
3776 KASSERT((origpte & PG_FRAME) == opa,
3777 ("pmap_enter: unexpected pa update for %#x", va));
3778 if ((origpte & PG_MANAGED) != 0) {
3779 om = PHYS_TO_VM_PAGE(opa);
3782 * The pmap lock is sufficient to synchronize with
3783 * concurrent calls to pmap_page_test_mappings() and
3784 * pmap_ts_referenced().
3786 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3788 if ((origpte & PG_A) != 0)
3789 vm_page_aflag_set(om, PGA_REFERENCED);
3790 pv = pmap_pvh_remove(&om->md, pmap, va);
3791 if ((newpte & PG_MANAGED) == 0)
3792 free_pv_entry(pmap, pv);
3793 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3794 TAILQ_EMPTY(&om->md.pv_list) &&
3795 ((om->flags & PG_FICTITIOUS) != 0 ||
3796 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3797 vm_page_aflag_clear(om, PGA_WRITEABLE);
3799 if ((origpte & PG_A) != 0)
3800 pmap_invalidate_page(pmap, va);
3804 * Increment the counters.
3806 if ((newpte & PG_W) != 0)
3807 pmap->pm_stats.wired_count++;
3808 pmap->pm_stats.resident_count++;
3812 * Enter on the PV list if part of our managed memory.
3814 if ((newpte & PG_MANAGED) != 0) {
3816 pv = get_pv_entry(pmap, FALSE);
3819 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3820 if ((newpte & PG_RW) != 0)
3821 vm_page_aflag_set(m, PGA_WRITEABLE);
3827 if ((origpte & PG_V) != 0) {
3829 origpte = pte_load_store(pte, newpte);
3830 KASSERT((origpte & PG_FRAME) == pa,
3831 ("pmap_enter: unexpected pa update for %#x", va));
3832 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
3834 if ((origpte & PG_MANAGED) != 0)
3838 * Although the PTE may still have PG_RW set, TLB
3839 * invalidation may nonetheless be required because
3840 * the PTE no longer has PG_M set.
3843 #if defined(PAE) || defined(PAE_TABLES)
3844 else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
3846 * This PTE change does not require TLB invalidation.
3851 if ((origpte & PG_A) != 0)
3852 pmap_invalidate_page(pmap, va);
3854 pte_store(pte, newpte);
3858 #if VM_NRESERVLEVEL > 0
3860 * If both the page table page and the reservation are fully
3861 * populated, then attempt promotion.
3863 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3864 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3865 vm_reserv_level_iffullpop(m) == 0)
3866 pmap_promote_pde(pmap, pde, va);
3872 rw_wunlock(&pvh_global_lock);
3878 * Tries to create a read- and/or execute-only 2 or 4 MB page mapping. Returns
3879 * true if successful. Returns false if (1) a mapping already exists at the
3880 * specified virtual address or (2) a PV entry cannot be allocated without
3881 * reclaiming another PV entry.
3884 pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3888 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3889 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
3891 if ((m->oflags & VPO_UNMANAGED) == 0)
3892 newpde |= PG_MANAGED;
3893 #if defined(PAE) || defined(PAE_TABLES)
3894 if ((prot & VM_PROT_EXECUTE) == 0)
3897 if (pmap != kernel_pmap)
3899 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
3900 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL) ==
3905 * Tries to create the specified 2 or 4 MB page mapping. Returns KERN_SUCCESS
3906 * if the mapping was created, and either KERN_FAILURE or
3907 * KERN_RESOURCE_SHORTAGE otherwise. Returns KERN_FAILURE if
3908 * PMAP_ENTER_NOREPLACE was specified and a mapping already exists at the
3909 * specified virtual address. Returns KERN_RESOURCE_SHORTAGE if
3910 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3912 * The parameter "m" is only used when creating a managed, writeable mapping.
3915 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
3918 struct spglist free;
3919 pd_entry_t oldpde, *pde;
3922 rw_assert(&pvh_global_lock, RA_WLOCKED);
3923 KASSERT((newpde & (PG_M | PG_RW)) != PG_RW,
3924 ("pmap_enter_pde: newpde is missing PG_M"));
3925 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3926 pde = pmap_pde(pmap, va);
3928 if ((oldpde & PG_V) != 0) {
3929 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
3930 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3931 " in pmap %p", va, pmap);
3932 return (KERN_FAILURE);
3934 /* Break the existing mapping(s). */
3936 if ((oldpde & PG_PS) != 0) {
3938 * If the PDE resulted from a promotion, then a
3939 * reserved PT page could be freed.
3941 (void)pmap_remove_pde(pmap, pde, va, &free);
3942 if ((oldpde & PG_G) == 0)
3943 pmap_invalidate_pde_page(pmap, va, oldpde);
3945 if (pmap_remove_ptes(pmap, va, va + NBPDR, &free))
3946 pmap_invalidate_all(pmap);
3948 vm_page_free_pages_toq(&free, true);
3949 if (pmap == kernel_pmap) {
3950 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3951 if (pmap_insert_pt_page(pmap, mt)) {
3953 * XXX Currently, this can't happen because
3954 * we do not perform pmap_enter(psind == 1)
3955 * on the kernel pmap.
3957 panic("pmap_enter_pde: trie insert failed");
3960 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
3963 if ((newpde & PG_MANAGED) != 0) {
3965 * Abort this mapping if its PV entry could not be created.
3967 if (!pmap_pv_insert_pde(pmap, va, newpde, flags)) {
3968 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3969 " in pmap %p", va, pmap);
3970 return (KERN_RESOURCE_SHORTAGE);
3972 if ((newpde & PG_RW) != 0) {
3973 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
3974 vm_page_aflag_set(mt, PGA_WRITEABLE);
3979 * Increment counters.
3981 if ((newpde & PG_W) != 0)
3982 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
3983 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3986 * Map the superpage. (This is not a promoted mapping; there will not
3987 * be any lingering 4KB page mappings in the TLB.)
3989 pde_store(pde, newpde);
3991 pmap_pde_mappings++;
3992 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3993 " in pmap %p", va, pmap);
3994 return (KERN_SUCCESS);
3998 * Maps a sequence of resident pages belonging to the same object.
3999 * The sequence begins with the given page m_start. This page is
4000 * mapped at the given virtual address start. Each subsequent page is
4001 * mapped at a virtual address that is offset from start by the same
4002 * amount as the page is offset from m_start within the object. The
4003 * last page in the sequence is the page with the largest offset from
4004 * m_start that can be mapped at a virtual address less than the given
4005 * virtual address end. Not every virtual page between start and end
4006 * is mapped; only those for which a resident page exists with the
4007 * corresponding offset from m_start are mapped.
4010 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4011 vm_page_t m_start, vm_prot_t prot)
4015 vm_pindex_t diff, psize;
4017 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4019 psize = atop(end - start);
4022 rw_wlock(&pvh_global_lock);
4024 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4025 va = start + ptoa(diff);
4026 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
4027 m->psind == 1 && pg_ps_enabled &&
4028 pmap_enter_4mpage(pmap, va, m, prot))
4029 m = &m[NBPDR / PAGE_SIZE - 1];
4031 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
4033 m = TAILQ_NEXT(m, listq);
4035 rw_wunlock(&pvh_global_lock);
4040 * this code makes some *MAJOR* assumptions:
4041 * 1. Current pmap & pmap exists.
4044 * 4. No page table pages.
4045 * but is *MUCH* faster than pmap_enter...
4049 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4052 rw_wlock(&pvh_global_lock);
4054 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
4055 rw_wunlock(&pvh_global_lock);
4060 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4061 vm_prot_t prot, vm_page_t mpte)
4065 struct spglist free;
4067 KASSERT(pmap != kernel_pmap || va < kmi.clean_sva ||
4068 va >= kmi.clean_eva || (m->oflags & VPO_UNMANAGED) != 0,
4069 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4070 rw_assert(&pvh_global_lock, RA_WLOCKED);
4071 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4074 * In the case that a page table page is not
4075 * resident, we are creating it here.
4077 if (pmap != kernel_pmap) {
4082 * Calculate pagetable page index
4084 ptepindex = va >> PDRSHIFT;
4085 if (mpte && (mpte->pindex == ptepindex)) {
4089 * Get the page directory entry
4091 ptepa = pmap->pm_pdir[ptepindex];
4094 * If the page table page is mapped, we just increment
4095 * the hold count, and activate it.
4100 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
4103 mpte = _pmap_allocpte(pmap, ptepindex,
4104 PMAP_ENTER_NOSLEEP);
4114 pte = pmap_pte_quick(pmap, va);
4125 * Enter on the PV list if part of our managed memory.
4127 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4128 !pmap_try_insert_pv_entry(pmap, va, m)) {
4131 if (pmap_unwire_ptp(pmap, mpte, &free)) {
4132 pmap_invalidate_page(pmap, va);
4133 vm_page_free_pages_toq(&free, true);
4143 * Increment counters
4145 pmap->pm_stats.resident_count++;
4147 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 0);
4148 #if defined(PAE) || defined(PAE_TABLES)
4149 if ((prot & VM_PROT_EXECUTE) == 0)
4154 * Now validate mapping with RO protection
4156 if ((m->oflags & VPO_UNMANAGED) != 0)
4157 pte_store(pte, pa | PG_V | PG_U);
4159 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
4165 * Make a temporary mapping for a physical address. This is only intended
4166 * to be used for panic dumps.
4169 pmap_kenter_temporary(vm_paddr_t pa, int i)
4173 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
4174 pmap_kenter(va, pa);
4176 return ((void *)crashdumpmap);
4180 * This code maps large physical mmap regions into the
4181 * processor address space. Note that some shortcuts
4182 * are taken, but the code works.
4185 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4186 vm_pindex_t pindex, vm_size_t size)
4189 vm_paddr_t pa, ptepa;
4193 VM_OBJECT_ASSERT_WLOCKED(object);
4194 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4195 ("pmap_object_init_pt: non-device object"));
4196 if (pg_ps_enabled &&
4197 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
4198 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4200 p = vm_page_lookup(object, pindex);
4201 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4202 ("pmap_object_init_pt: invalid page %p", p));
4203 pat_mode = p->md.pat_mode;
4206 * Abort the mapping if the first page is not physically
4207 * aligned to a 2/4MB page boundary.
4209 ptepa = VM_PAGE_TO_PHYS(p);
4210 if (ptepa & (NBPDR - 1))
4214 * Skip the first page. Abort the mapping if the rest of
4215 * the pages are not physically contiguous or have differing
4216 * memory attributes.
4218 p = TAILQ_NEXT(p, listq);
4219 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4221 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4222 ("pmap_object_init_pt: invalid page %p", p));
4223 if (pa != VM_PAGE_TO_PHYS(p) ||
4224 pat_mode != p->md.pat_mode)
4226 p = TAILQ_NEXT(p, listq);
4230 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
4231 * "size" is a multiple of 2/4M, adding the PAT setting to
4232 * "pa" will not affect the termination of this loop.
4235 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
4236 pa < ptepa + size; pa += NBPDR) {
4237 pde = pmap_pde(pmap, addr);
4239 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4240 PG_U | PG_RW | PG_V);
4241 pmap->pm_stats.resident_count += NBPDR /
4243 pmap_pde_mappings++;
4245 /* Else continue on if the PDE is already valid. */
4253 * Clear the wired attribute from the mappings for the specified range of
4254 * addresses in the given pmap. Every valid mapping within that range
4255 * must have the wired attribute set. In contrast, invalid mappings
4256 * cannot have the wired attribute set, so they are ignored.
4258 * The wired attribute of the page table entry is not a hardware feature,
4259 * so there is no need to invalidate any TLB entries.
4262 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4267 boolean_t pv_lists_locked;
4269 if (pmap_is_current(pmap))
4270 pv_lists_locked = FALSE;
4272 pv_lists_locked = TRUE;
4274 rw_wlock(&pvh_global_lock);
4278 for (; sva < eva; sva = pdnxt) {
4279 pdnxt = (sva + NBPDR) & ~PDRMASK;
4282 pde = pmap_pde(pmap, sva);
4283 if ((*pde & PG_V) == 0)
4285 if ((*pde & PG_PS) != 0) {
4286 if ((*pde & PG_W) == 0)
4287 panic("pmap_unwire: pde %#jx is missing PG_W",
4291 * Are we unwiring the entire large page? If not,
4292 * demote the mapping and fall through.
4294 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4296 * Regardless of whether a pde (or pte) is 32
4297 * or 64 bits in size, PG_W is among the least
4298 * significant 32 bits.
4300 atomic_clear_int((u_int *)pde, PG_W);
4301 pmap->pm_stats.wired_count -= NBPDR /
4305 if (!pv_lists_locked) {
4306 pv_lists_locked = TRUE;
4307 if (!rw_try_wlock(&pvh_global_lock)) {
4314 if (!pmap_demote_pde(pmap, pde, sva))
4315 panic("pmap_unwire: demotion failed");
4320 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4322 if ((*pte & PG_V) == 0)
4324 if ((*pte & PG_W) == 0)
4325 panic("pmap_unwire: pte %#jx is missing PG_W",
4329 * PG_W must be cleared atomically. Although the pmap
4330 * lock synchronizes access to PG_W, another processor
4331 * could be setting PG_M and/or PG_A concurrently.
4333 * PG_W is among the least significant 32 bits.
4335 atomic_clear_int((u_int *)pte, PG_W);
4336 pmap->pm_stats.wired_count--;
4339 if (pv_lists_locked) {
4341 rw_wunlock(&pvh_global_lock);
4348 * Copy the range specified by src_addr/len
4349 * from the source map to the range dst_addr/len
4350 * in the destination map.
4352 * This routine is only advisory and need not do anything. Since
4353 * current pmap is always the kernel pmap when executing in
4354 * kernel, and we do not copy from the kernel pmap to a user
4355 * pmap, this optimization is not usable in 4/4G full split i386
4360 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4361 vm_offset_t src_addr)
4363 struct spglist free;
4364 pt_entry_t *src_pte, *dst_pte, ptetemp;
4365 pd_entry_t srcptepaddr;
4366 vm_page_t dstmpte, srcmpte;
4367 vm_offset_t addr, end_addr, pdnxt;
4370 if (dst_addr != src_addr)
4373 end_addr = src_addr + len;
4375 rw_wlock(&pvh_global_lock);
4376 if (dst_pmap < src_pmap) {
4377 PMAP_LOCK(dst_pmap);
4378 PMAP_LOCK(src_pmap);
4380 PMAP_LOCK(src_pmap);
4381 PMAP_LOCK(dst_pmap);
4384 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4385 KASSERT(addr < PMAP_TRM_MIN_ADDRESS,
4386 ("pmap_copy: invalid to pmap_copy the trampoline"));
4388 pdnxt = (addr + NBPDR) & ~PDRMASK;
4391 ptepindex = addr >> PDRSHIFT;
4393 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4394 if (srcptepaddr == 0)
4397 if (srcptepaddr & PG_PS) {
4398 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4400 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4401 ((srcptepaddr & PG_MANAGED) == 0 ||
4402 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
4403 PMAP_ENTER_NORECLAIM))) {
4404 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4406 dst_pmap->pm_stats.resident_count +=
4408 pmap_pde_mappings++;
4413 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4414 KASSERT(srcmpte->wire_count > 0,
4415 ("pmap_copy: source page table page is unused"));
4417 if (pdnxt > end_addr)
4420 src_pte = pmap_pte_quick3(src_pmap, addr);
4421 while (addr < pdnxt) {
4424 * we only virtual copy managed pages
4426 if ((ptetemp & PG_MANAGED) != 0) {
4427 dstmpte = pmap_allocpte(dst_pmap, addr,
4428 PMAP_ENTER_NOSLEEP);
4429 if (dstmpte == NULL)
4431 dst_pte = pmap_pte_quick(dst_pmap, addr);
4432 if (*dst_pte == 0 &&
4433 pmap_try_insert_pv_entry(dst_pmap, addr,
4434 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4436 * Clear the wired, modified, and
4437 * accessed (referenced) bits
4440 *dst_pte = ptetemp & ~(PG_W | PG_M |
4442 dst_pmap->pm_stats.resident_count++;
4445 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4447 pmap_invalidate_page(dst_pmap,
4449 vm_page_free_pages_toq(&free,
4454 if (dstmpte->wire_count >= srcmpte->wire_count)
4463 rw_wunlock(&pvh_global_lock);
4464 PMAP_UNLOCK(src_pmap);
4465 PMAP_UNLOCK(dst_pmap);
4469 * Zero 1 page of virtual memory mapped from a hardware page by the caller.
4471 static __inline void
4472 pagezero(void *page)
4474 #if defined(I686_CPU)
4475 if (cpu_class == CPUCLASS_686) {
4476 if (cpu_feature & CPUID_SSE2)
4477 sse2_pagezero(page);
4479 i686_pagezero(page);
4482 bzero(page, PAGE_SIZE);
4486 * Zero the specified hardware page.
4489 pmap_zero_page(vm_page_t m)
4491 pt_entry_t *cmap_pte2;
4496 cmap_pte2 = pc->pc_cmap_pte2;
4497 mtx_lock(&pc->pc_cmap_lock);
4499 panic("pmap_zero_page: CMAP2 busy");
4500 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4501 pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
4502 invlcaddr(pc->pc_cmap_addr2);
4503 pagezero(pc->pc_cmap_addr2);
4507 * Unpin the thread before releasing the lock. Otherwise the thread
4508 * could be rescheduled while still bound to the current CPU, only
4509 * to unpin itself immediately upon resuming execution.
4512 mtx_unlock(&pc->pc_cmap_lock);
4516 * Zero an an area within a single hardware page. off and size must not
4517 * cover an area beyond a single hardware page.
4520 pmap_zero_page_area(vm_page_t m, int off, int size)
4522 pt_entry_t *cmap_pte2;
4527 cmap_pte2 = pc->pc_cmap_pte2;
4528 mtx_lock(&pc->pc_cmap_lock);
4530 panic("pmap_zero_page_area: CMAP2 busy");
4531 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4532 pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
4533 invlcaddr(pc->pc_cmap_addr2);
4534 if (off == 0 && size == PAGE_SIZE)
4535 pagezero(pc->pc_cmap_addr2);
4537 bzero(pc->pc_cmap_addr2 + off, size);
4540 mtx_unlock(&pc->pc_cmap_lock);
4544 * Copy 1 specified hardware page to another.
4547 pmap_copy_page(vm_page_t src, vm_page_t dst)
4549 pt_entry_t *cmap_pte1, *cmap_pte2;
4554 cmap_pte1 = pc->pc_cmap_pte1;
4555 cmap_pte2 = pc->pc_cmap_pte2;
4556 mtx_lock(&pc->pc_cmap_lock);
4558 panic("pmap_copy_page: CMAP1 busy");
4560 panic("pmap_copy_page: CMAP2 busy");
4561 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4562 pmap_cache_bits(kernel_pmap, src->md.pat_mode, 0);
4563 invlcaddr(pc->pc_cmap_addr1);
4564 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4565 pmap_cache_bits(kernel_pmap, dst->md.pat_mode, 0);
4566 invlcaddr(pc->pc_cmap_addr2);
4567 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE);
4571 mtx_unlock(&pc->pc_cmap_lock);
4574 int unmapped_buf_allowed = 1;
4577 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4578 vm_offset_t b_offset, int xfersize)
4580 vm_page_t a_pg, b_pg;
4582 vm_offset_t a_pg_offset, b_pg_offset;
4583 pt_entry_t *cmap_pte1, *cmap_pte2;
4589 cmap_pte1 = pc->pc_cmap_pte1;
4590 cmap_pte2 = pc->pc_cmap_pte2;
4591 mtx_lock(&pc->pc_cmap_lock);
4592 if (*cmap_pte1 != 0)
4593 panic("pmap_copy_pages: CMAP1 busy");
4594 if (*cmap_pte2 != 0)
4595 panic("pmap_copy_pages: CMAP2 busy");
4596 while (xfersize > 0) {
4597 a_pg = ma[a_offset >> PAGE_SHIFT];
4598 a_pg_offset = a_offset & PAGE_MASK;
4599 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4600 b_pg = mb[b_offset >> PAGE_SHIFT];
4601 b_pg_offset = b_offset & PAGE_MASK;
4602 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4603 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4604 pmap_cache_bits(kernel_pmap, a_pg->md.pat_mode, 0);
4605 invlcaddr(pc->pc_cmap_addr1);
4606 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4607 PG_M | pmap_cache_bits(kernel_pmap, b_pg->md.pat_mode, 0);
4608 invlcaddr(pc->pc_cmap_addr2);
4609 a_cp = pc->pc_cmap_addr1 + a_pg_offset;
4610 b_cp = pc->pc_cmap_addr2 + b_pg_offset;
4611 bcopy(a_cp, b_cp, cnt);
4619 mtx_unlock(&pc->pc_cmap_lock);
4623 * Returns true if the pmap's pv is one of the first
4624 * 16 pvs linked to from this page. This count may
4625 * be changed upwards or downwards in the future; it
4626 * is only necessary that true be returned for a small
4627 * subset of pmaps for proper page aging.
4630 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4632 struct md_page *pvh;
4637 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4638 ("pmap_page_exists_quick: page %p is not managed", m));
4640 rw_wlock(&pvh_global_lock);
4641 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4642 if (PV_PMAP(pv) == pmap) {
4650 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4651 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4652 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4653 if (PV_PMAP(pv) == pmap) {
4662 rw_wunlock(&pvh_global_lock);
4667 * pmap_page_wired_mappings:
4669 * Return the number of managed mappings to the given physical page
4673 pmap_page_wired_mappings(vm_page_t m)
4678 if ((m->oflags & VPO_UNMANAGED) != 0)
4680 rw_wlock(&pvh_global_lock);
4681 count = pmap_pvh_wired_mappings(&m->md, count);
4682 if ((m->flags & PG_FICTITIOUS) == 0) {
4683 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4686 rw_wunlock(&pvh_global_lock);
4691 * pmap_pvh_wired_mappings:
4693 * Return the updated number "count" of managed mappings that are wired.
4696 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4702 rw_assert(&pvh_global_lock, RA_WLOCKED);
4704 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4707 pte = pmap_pte_quick(pmap, pv->pv_va);
4708 if ((*pte & PG_W) != 0)
4717 * Returns TRUE if the given page is mapped individually or as part of
4718 * a 4mpage. Otherwise, returns FALSE.
4721 pmap_page_is_mapped(vm_page_t m)
4725 if ((m->oflags & VPO_UNMANAGED) != 0)
4727 rw_wlock(&pvh_global_lock);
4728 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4729 ((m->flags & PG_FICTITIOUS) == 0 &&
4730 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4731 rw_wunlock(&pvh_global_lock);
4736 * Remove all pages from specified address space
4737 * this aids process exit speeds. Also, this code
4738 * is special cased for current process only, but
4739 * can have the more generic (and slightly slower)
4740 * mode enabled. This is much faster than pmap_remove
4741 * in the case of running down an entire address space.
4744 pmap_remove_pages(pmap_t pmap)
4746 pt_entry_t *pte, tpte;
4747 vm_page_t m, mpte, mt;
4749 struct md_page *pvh;
4750 struct pv_chunk *pc, *npc;
4751 struct spglist free;
4754 uint32_t inuse, bitmask;
4757 if (pmap != PCPU_GET(curpmap)) {
4758 printf("warning: pmap_remove_pages called with non-current pmap\n");
4762 rw_wlock(&pvh_global_lock);
4765 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4766 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4769 for (field = 0; field < _NPCM; field++) {
4770 inuse = ~pc->pc_map[field] & pc_freemask[field];
4771 while (inuse != 0) {
4773 bitmask = 1UL << bit;
4774 idx = field * 32 + bit;
4775 pv = &pc->pc_pventry[idx];
4778 pte = pmap_pde(pmap, pv->pv_va);
4780 if ((tpte & PG_PS) == 0) {
4781 pte = pmap_pte_quick(pmap, pv->pv_va);
4782 tpte = *pte & ~PG_PTE_PAT;
4787 "TPTE at %p IS ZERO @ VA %08x\n",
4793 * We cannot remove wired pages from a process' mapping at this time
4800 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4801 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4802 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4803 m, (uintmax_t)m->phys_addr,
4806 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4807 m < &vm_page_array[vm_page_array_size],
4808 ("pmap_remove_pages: bad tpte %#jx",
4814 * Update the vm_page_t clean/reference bits.
4816 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4817 if ((tpte & PG_PS) != 0) {
4818 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4825 PV_STAT(pv_entry_frees++);
4826 PV_STAT(pv_entry_spare++);
4828 pc->pc_map[field] |= bitmask;
4829 if ((tpte & PG_PS) != 0) {
4830 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4831 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4832 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4833 if (TAILQ_EMPTY(&pvh->pv_list)) {
4834 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4835 if (TAILQ_EMPTY(&mt->md.pv_list))
4836 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4838 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
4840 pmap->pm_stats.resident_count--;
4841 KASSERT(mpte->wire_count == NPTEPG,
4842 ("pmap_remove_pages: pte page wire count error"));
4843 mpte->wire_count = 0;
4844 pmap_add_delayed_free_list(mpte, &free, FALSE);
4847 pmap->pm_stats.resident_count--;
4848 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4849 if (TAILQ_EMPTY(&m->md.pv_list) &&
4850 (m->flags & PG_FICTITIOUS) == 0) {
4851 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4852 if (TAILQ_EMPTY(&pvh->pv_list))
4853 vm_page_aflag_clear(m, PGA_WRITEABLE);
4855 pmap_unuse_pt(pmap, pv->pv_va, &free);
4860 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4865 pmap_invalidate_all(pmap);
4866 rw_wunlock(&pvh_global_lock);
4868 vm_page_free_pages_toq(&free, true);
4874 * Return whether or not the specified physical page was modified
4875 * in any physical maps.
4878 pmap_is_modified(vm_page_t m)
4882 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4883 ("pmap_is_modified: page %p is not managed", m));
4886 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4887 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4888 * is clear, no PTEs can have PG_M set.
4890 VM_OBJECT_ASSERT_WLOCKED(m->object);
4891 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4893 rw_wlock(&pvh_global_lock);
4894 rv = pmap_is_modified_pvh(&m->md) ||
4895 ((m->flags & PG_FICTITIOUS) == 0 &&
4896 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4897 rw_wunlock(&pvh_global_lock);
4902 * Returns TRUE if any of the given mappings were used to modify
4903 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4904 * mappings are supported.
4907 pmap_is_modified_pvh(struct md_page *pvh)
4914 rw_assert(&pvh_global_lock, RA_WLOCKED);
4917 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4920 pte = pmap_pte_quick(pmap, pv->pv_va);
4921 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4931 * pmap_is_prefaultable:
4933 * Return whether or not the specified virtual address is elgible
4937 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4944 pde = *pmap_pde(pmap, addr);
4945 if (pde != 0 && (pde & PG_PS) == 0)
4946 rv = pmap_pte_ufast(pmap, addr, pde) == 0;
4952 * pmap_is_referenced:
4954 * Return whether or not the specified physical page was referenced
4955 * in any physical maps.
4958 pmap_is_referenced(vm_page_t m)
4962 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4963 ("pmap_is_referenced: page %p is not managed", m));
4964 rw_wlock(&pvh_global_lock);
4965 rv = pmap_is_referenced_pvh(&m->md) ||
4966 ((m->flags & PG_FICTITIOUS) == 0 &&
4967 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4968 rw_wunlock(&pvh_global_lock);
4973 * Returns TRUE if any of the given mappings were referenced and FALSE
4974 * otherwise. Both page and 4mpage mappings are supported.
4977 pmap_is_referenced_pvh(struct md_page *pvh)
4984 rw_assert(&pvh_global_lock, RA_WLOCKED);
4987 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4990 pte = pmap_pte_quick(pmap, pv->pv_va);
4991 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
5001 * Clear the write and modified bits in each of the given page's mappings.
5004 pmap_remove_write(vm_page_t m)
5006 struct md_page *pvh;
5007 pv_entry_t next_pv, pv;
5010 pt_entry_t oldpte, *pte;
5013 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5014 ("pmap_remove_write: page %p is not managed", m));
5017 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5018 * set by another thread while the object is locked. Thus,
5019 * if PGA_WRITEABLE is clear, no page table entries need updating.
5021 VM_OBJECT_ASSERT_WLOCKED(m->object);
5022 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5024 rw_wlock(&pvh_global_lock);
5026 if ((m->flags & PG_FICTITIOUS) != 0)
5027 goto small_mappings;
5028 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5029 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5033 pde = pmap_pde(pmap, va);
5034 if ((*pde & PG_RW) != 0)
5035 (void)pmap_demote_pde(pmap, pde, va);
5039 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5042 pde = pmap_pde(pmap, pv->pv_va);
5043 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
5044 " a 4mpage in page %p's pv list", m));
5045 pte = pmap_pte_quick(pmap, pv->pv_va);
5048 if ((oldpte & PG_RW) != 0) {
5050 * Regardless of whether a pte is 32 or 64 bits
5051 * in size, PG_RW and PG_M are among the least
5052 * significant 32 bits.
5054 if (!atomic_cmpset_int((u_int *)pte, oldpte,
5055 oldpte & ~(PG_RW | PG_M)))
5057 if ((oldpte & PG_M) != 0)
5059 pmap_invalidate_page(pmap, pv->pv_va);
5063 vm_page_aflag_clear(m, PGA_WRITEABLE);
5065 rw_wunlock(&pvh_global_lock);
5069 * pmap_ts_referenced:
5071 * Return a count of reference bits for a page, clearing those bits.
5072 * It is not necessary for every reference bit to be cleared, but it
5073 * is necessary that 0 only be returned when there are truly no
5074 * reference bits set.
5076 * As an optimization, update the page's dirty field if a modified bit is
5077 * found while counting reference bits. This opportunistic update can be
5078 * performed at low cost and can eliminate the need for some future calls
5079 * to pmap_is_modified(). However, since this function stops after
5080 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5081 * dirty pages. Those dirty pages will only be detected by a future call
5082 * to pmap_is_modified().
5085 pmap_ts_referenced(vm_page_t m)
5087 struct md_page *pvh;
5095 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5096 ("pmap_ts_referenced: page %p is not managed", m));
5097 pa = VM_PAGE_TO_PHYS(m);
5098 pvh = pa_to_pvh(pa);
5099 rw_wlock(&pvh_global_lock);
5101 if ((m->flags & PG_FICTITIOUS) != 0 ||
5102 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5103 goto small_mappings;
5108 pde = pmap_pde(pmap, pv->pv_va);
5109 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5111 * Although "*pde" is mapping a 2/4MB page, because
5112 * this function is called at a 4KB page granularity,
5113 * we only update the 4KB page under test.
5117 if ((*pde & PG_A) != 0) {
5119 * Since this reference bit is shared by either 1024
5120 * or 512 4KB pages, it should not be cleared every
5121 * time it is tested. Apply a simple "hash" function
5122 * on the physical page number, the virtual superpage
5123 * number, and the pmap address to select one 4KB page
5124 * out of the 1024 or 512 on which testing the
5125 * reference bit will result in clearing that bit.
5126 * This function is designed to avoid the selection of
5127 * the same 4KB page for every 2- or 4MB page mapping.
5129 * On demotion, a mapping that hasn't been referenced
5130 * is simply destroyed. To avoid the possibility of a
5131 * subsequent page fault on a demoted wired mapping,
5132 * always leave its reference bit set. Moreover,
5133 * since the superpage is wired, the current state of
5134 * its reference bit won't affect page replacement.
5136 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
5137 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
5138 (*pde & PG_W) == 0) {
5139 atomic_clear_int((u_int *)pde, PG_A);
5140 pmap_invalidate_page(pmap, pv->pv_va);
5145 /* Rotate the PV list if it has more than one entry. */
5146 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5147 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5148 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5150 if (rtval >= PMAP_TS_REFERENCED_MAX)
5152 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5154 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5160 pde = pmap_pde(pmap, pv->pv_va);
5161 KASSERT((*pde & PG_PS) == 0,
5162 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
5164 pte = pmap_pte_quick(pmap, pv->pv_va);
5165 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5167 if ((*pte & PG_A) != 0) {
5168 atomic_clear_int((u_int *)pte, PG_A);
5169 pmap_invalidate_page(pmap, pv->pv_va);
5173 /* Rotate the PV list if it has more than one entry. */
5174 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5175 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5176 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5178 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
5179 PMAP_TS_REFERENCED_MAX);
5182 rw_wunlock(&pvh_global_lock);
5187 * Apply the given advice to the specified range of addresses within the
5188 * given pmap. Depending on the advice, clear the referenced and/or
5189 * modified flags in each mapping and set the mapped page's dirty field.
5192 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5194 pd_entry_t oldpde, *pde;
5196 vm_offset_t va, pdnxt;
5198 boolean_t anychanged, pv_lists_locked;
5200 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5202 if (pmap_is_current(pmap))
5203 pv_lists_locked = FALSE;
5205 pv_lists_locked = TRUE;
5207 rw_wlock(&pvh_global_lock);
5212 for (; sva < eva; sva = pdnxt) {
5213 pdnxt = (sva + NBPDR) & ~PDRMASK;
5216 pde = pmap_pde(pmap, sva);
5218 if ((oldpde & PG_V) == 0)
5220 else if ((oldpde & PG_PS) != 0) {
5221 if ((oldpde & PG_MANAGED) == 0)
5223 if (!pv_lists_locked) {
5224 pv_lists_locked = TRUE;
5225 if (!rw_try_wlock(&pvh_global_lock)) {
5227 pmap_invalidate_all(pmap);
5233 if (!pmap_demote_pde(pmap, pde, sva)) {
5235 * The large page mapping was destroyed.
5241 * Unless the page mappings are wired, remove the
5242 * mapping to a single page so that a subsequent
5243 * access may repromote. Since the underlying page
5244 * table page is fully populated, this removal never
5245 * frees a page table page.
5247 if ((oldpde & PG_W) == 0) {
5248 pte = pmap_pte_quick(pmap, sva);
5249 KASSERT((*pte & PG_V) != 0,
5250 ("pmap_advise: invalid PTE"));
5251 pmap_remove_pte(pmap, pte, sva, NULL);
5258 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
5260 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
5262 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5263 if (advice == MADV_DONTNEED) {
5265 * Future calls to pmap_is_modified()
5266 * can be avoided by making the page
5269 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
5272 atomic_clear_int((u_int *)pte, PG_M | PG_A);
5273 } else if ((*pte & PG_A) != 0)
5274 atomic_clear_int((u_int *)pte, PG_A);
5277 if ((*pte & PG_G) != 0) {
5285 pmap_invalidate_range(pmap, va, sva);
5290 pmap_invalidate_range(pmap, va, sva);
5293 pmap_invalidate_all(pmap);
5294 if (pv_lists_locked) {
5296 rw_wunlock(&pvh_global_lock);
5302 * Clear the modify bits on the specified physical page.
5305 pmap_clear_modify(vm_page_t m)
5307 struct md_page *pvh;
5308 pv_entry_t next_pv, pv;
5310 pd_entry_t oldpde, *pde;
5311 pt_entry_t oldpte, *pte;
5314 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5315 ("pmap_clear_modify: page %p is not managed", m));
5316 VM_OBJECT_ASSERT_WLOCKED(m->object);
5317 KASSERT(!vm_page_xbusied(m),
5318 ("pmap_clear_modify: page %p is exclusive busied", m));
5321 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5322 * If the object containing the page is locked and the page is not
5323 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5325 if ((m->aflags & PGA_WRITEABLE) == 0)
5327 rw_wlock(&pvh_global_lock);
5329 if ((m->flags & PG_FICTITIOUS) != 0)
5330 goto small_mappings;
5331 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5332 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5336 pde = pmap_pde(pmap, va);
5338 if ((oldpde & PG_RW) != 0) {
5339 if (pmap_demote_pde(pmap, pde, va)) {
5340 if ((oldpde & PG_W) == 0) {
5342 * Write protect the mapping to a
5343 * single page so that a subsequent
5344 * write access may repromote.
5346 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5348 pte = pmap_pte_quick(pmap, va);
5350 if ((oldpte & PG_V) != 0) {
5352 * Regardless of whether a pte is 32 or 64 bits
5353 * in size, PG_RW and PG_M are among the least
5354 * significant 32 bits.
5356 while (!atomic_cmpset_int((u_int *)pte,
5358 oldpte & ~(PG_M | PG_RW)))
5361 pmap_invalidate_page(pmap, va);
5369 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5372 pde = pmap_pde(pmap, pv->pv_va);
5373 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5374 " a 4mpage in page %p's pv list", m));
5375 pte = pmap_pte_quick(pmap, pv->pv_va);
5376 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5378 * Regardless of whether a pte is 32 or 64 bits
5379 * in size, PG_M is among the least significant
5382 atomic_clear_int((u_int *)pte, PG_M);
5383 pmap_invalidate_page(pmap, pv->pv_va);
5388 rw_wunlock(&pvh_global_lock);
5392 * Miscellaneous support routines follow
5395 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5396 static __inline void
5397 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5402 * The cache mode bits are all in the low 32-bits of the
5403 * PTE, so we can just spin on updating the low 32-bits.
5406 opte = *(u_int *)pte;
5407 npte = opte & ~PG_PTE_CACHE;
5409 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5412 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5413 static __inline void
5414 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5419 * The cache mode bits are all in the low 32-bits of the
5420 * PDE, so we can just spin on updating the low 32-bits.
5423 opde = *(u_int *)pde;
5424 npde = opde & ~PG_PDE_CACHE;
5426 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5430 * Map a set of physical memory pages into the kernel virtual
5431 * address space. Return a pointer to where it is mapped. This
5432 * routine is intended to be used for mapping device memory,
5436 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5438 struct pmap_preinit_mapping *ppim;
5439 vm_offset_t va, offset;
5443 offset = pa & PAGE_MASK;
5444 size = round_page(offset + size);
5447 if (pa < PMAP_MAP_LOW && pa + size <= PMAP_MAP_LOW)
5448 va = pa + PMAP_MAP_LOW;
5449 else if (!pmap_initialized) {
5451 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5452 ppim = pmap_preinit_mapping + i;
5453 if (ppim->va == 0) {
5457 ppim->va = virtual_avail;
5458 virtual_avail += size;
5464 panic("%s: too many preinit mappings", __func__);
5467 * If we have a preinit mapping, re-use it.
5469 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5470 ppim = pmap_preinit_mapping + i;
5471 if (ppim->pa == pa && ppim->sz == size &&
5473 return ((void *)(ppim->va + offset));
5475 va = kva_alloc(size);
5477 panic("%s: Couldn't allocate KVA", __func__);
5479 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5480 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5481 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5482 pmap_invalidate_cache_range(va, va + size, FALSE);
5483 return ((void *)(va + offset));
5487 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5490 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5494 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5497 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5501 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5503 struct pmap_preinit_mapping *ppim;
5507 if (va >= PMAP_MAP_LOW && va <= KERNBASE && va + size <= KERNBASE)
5509 offset = va & PAGE_MASK;
5510 size = round_page(offset + size);
5511 va = trunc_page(va);
5512 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5513 ppim = pmap_preinit_mapping + i;
5514 if (ppim->va == va && ppim->sz == size) {
5515 if (pmap_initialized)
5521 if (va + size == virtual_avail)
5526 if (pmap_initialized)
5531 * Sets the memory attribute for the specified page.
5534 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5537 m->md.pat_mode = ma;
5538 if ((m->flags & PG_FICTITIOUS) != 0)
5542 * If "m" is a normal page, flush it from the cache.
5543 * See pmap_invalidate_cache_range().
5545 * First, try to find an existing mapping of the page by sf
5546 * buffer. sf_buf_invalidate_cache() modifies mapping and
5547 * flushes the cache.
5549 if (sf_buf_invalidate_cache(m))
5553 * If page is not mapped by sf buffer, but CPU does not
5554 * support self snoop, map the page transient and do
5555 * invalidation. In the worst case, whole cache is flushed by
5556 * pmap_invalidate_cache_range().
5558 if ((cpu_feature & CPUID_SS) == 0)
5563 pmap_flush_page(vm_page_t m)
5565 pt_entry_t *cmap_pte2;
5567 vm_offset_t sva, eva;
5570 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5571 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5574 cmap_pte2 = pc->pc_cmap_pte2;
5575 mtx_lock(&pc->pc_cmap_lock);
5577 panic("pmap_flush_page: CMAP2 busy");
5578 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5579 PG_A | PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode,
5581 invlcaddr(pc->pc_cmap_addr2);
5582 sva = (vm_offset_t)pc->pc_cmap_addr2;
5583 eva = sva + PAGE_SIZE;
5586 * Use mfence or sfence despite the ordering implied by
5587 * mtx_{un,}lock() because clflush on non-Intel CPUs
5588 * and clflushopt are not guaranteed to be ordered by
5589 * any other instruction.
5593 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5595 for (; sva < eva; sva += cpu_clflush_line_size) {
5603 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5607 mtx_unlock(&pc->pc_cmap_lock);
5609 pmap_invalidate_cache();
5613 * Changes the specified virtual address range's memory type to that given by
5614 * the parameter "mode". The specified virtual address range must be
5615 * completely contained within either the kernel map.
5617 * Returns zero if the change completed successfully, and either EINVAL or
5618 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5619 * of the virtual address range was not mapped, and ENOMEM is returned if
5620 * there was insufficient memory available to complete the change.
5623 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5625 vm_offset_t base, offset, tmpva;
5628 int cache_bits_pte, cache_bits_pde;
5631 base = trunc_page(va);
5632 offset = va & PAGE_MASK;
5633 size = round_page(offset + size);
5636 * Only supported on kernel virtual addresses above the recursive map.
5638 if (base < VM_MIN_KERNEL_ADDRESS)
5641 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
5642 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
5646 * Pages that aren't mapped aren't supported. Also break down
5647 * 2/4MB pages into 4KB pages if required.
5649 PMAP_LOCK(kernel_pmap);
5650 for (tmpva = base; tmpva < base + size; ) {
5651 pde = pmap_pde(kernel_pmap, tmpva);
5653 PMAP_UNLOCK(kernel_pmap);
5658 * If the current 2/4MB page already has
5659 * the required memory type, then we need not
5660 * demote this page. Just increment tmpva to
5661 * the next 2/4MB page frame.
5663 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5664 tmpva = trunc_4mpage(tmpva) + NBPDR;
5669 * If the current offset aligns with a 2/4MB
5670 * page frame and there is at least 2/4MB left
5671 * within the range, then we need not break
5672 * down this page into 4KB pages.
5674 if ((tmpva & PDRMASK) == 0 &&
5675 tmpva + PDRMASK < base + size) {
5679 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5680 PMAP_UNLOCK(kernel_pmap);
5684 pte = vtopte(tmpva);
5686 PMAP_UNLOCK(kernel_pmap);
5691 PMAP_UNLOCK(kernel_pmap);
5694 * Ok, all the pages exist, so run through them updating their
5695 * cache mode if required.
5697 for (tmpva = base; tmpva < base + size; ) {
5698 pde = pmap_pde(kernel_pmap, tmpva);
5700 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5701 pmap_pde_attr(pde, cache_bits_pde);
5704 tmpva = trunc_4mpage(tmpva) + NBPDR;
5706 pte = vtopte(tmpva);
5707 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5708 pmap_pte_attr(pte, cache_bits_pte);
5716 * Flush CPU caches to make sure any data isn't cached that
5717 * shouldn't be, etc.
5720 pmap_invalidate_range(kernel_pmap, base, tmpva);
5721 pmap_invalidate_cache_range(base, tmpva, FALSE);
5727 * perform the pmap work for mincore
5730 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5739 pde = *pmap_pde(pmap, addr);
5741 if ((pde & PG_PS) != 0) {
5743 /* Compute the physical address of the 4KB page. */
5744 pa = ((pde & PG_PS_FRAME) | (addr & PDRMASK)) &
5746 val = MINCORE_SUPER;
5748 pte = pmap_pte_ufast(pmap, addr, pde);
5749 pa = pte & PG_FRAME;
5757 if ((pte & PG_V) != 0) {
5758 val |= MINCORE_INCORE;
5759 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5760 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5761 if ((pte & PG_A) != 0)
5762 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5764 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5765 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5766 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5767 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5768 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5771 PA_UNLOCK_COND(*locked_pa);
5777 pmap_activate(struct thread *td)
5779 pmap_t pmap, oldpmap;
5784 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5785 oldpmap = PCPU_GET(curpmap);
5786 cpuid = PCPU_GET(cpuid);
5788 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5789 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5791 CPU_CLR(cpuid, &oldpmap->pm_active);
5792 CPU_SET(cpuid, &pmap->pm_active);
5794 #if defined(PAE) || defined(PAE_TABLES)
5795 cr3 = vtophys(pmap->pm_pdpt);
5797 cr3 = vtophys(pmap->pm_pdir);
5800 * pmap_activate is for the current thread on the current cpu
5802 td->td_pcb->pcb_cr3 = cr3;
5803 PCPU_SET(curpmap, pmap);
5808 pmap_activate_boot(pmap_t pmap)
5812 cpuid = PCPU_GET(cpuid);
5814 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5816 CPU_SET(cpuid, &pmap->pm_active);
5818 PCPU_SET(curpmap, pmap);
5822 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5827 * Increase the starting virtual address of the given mapping if a
5828 * different alignment might result in more superpage mappings.
5831 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5832 vm_offset_t *addr, vm_size_t size)
5834 vm_offset_t superpage_offset;
5838 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5839 offset += ptoa(object->pg_color);
5840 superpage_offset = offset & PDRMASK;
5841 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5842 (*addr & PDRMASK) == superpage_offset)
5844 if ((*addr & PDRMASK) < superpage_offset)
5845 *addr = (*addr & ~PDRMASK) + superpage_offset;
5847 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5851 pmap_quick_enter_page(vm_page_t m)
5857 qaddr = PCPU_GET(qmap_addr);
5858 pte = vtopte(qaddr);
5860 KASSERT(*pte == 0, ("pmap_quick_enter_page: PTE busy"));
5861 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5862 pmap_cache_bits(kernel_pmap, pmap_page_get_memattr(m), 0);
5869 pmap_quick_remove_page(vm_offset_t addr)
5874 qaddr = PCPU_GET(qmap_addr);
5875 pte = vtopte(qaddr);
5877 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5878 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5884 static vmem_t *pmap_trm_arena;
5885 static vmem_addr_t pmap_trm_arena_last = PMAP_TRM_MIN_ADDRESS;
5886 static int trm_guard = PAGE_SIZE;
5889 pmap_trm_import(void *unused __unused, vmem_size_t size, int flags,
5893 vmem_addr_t af, addr, prev_addr;
5894 pt_entry_t *trm_pte;
5896 prev_addr = atomic_load_long(&pmap_trm_arena_last);
5897 size = round_page(size) + trm_guard;
5899 if (prev_addr + size < prev_addr || prev_addr + size < size ||
5900 prev_addr + size > PMAP_TRM_MAX_ADDRESS)
5902 addr = prev_addr + size;
5903 if (atomic_fcmpset_int(&pmap_trm_arena_last, &prev_addr, addr))
5906 prev_addr += trm_guard;
5907 trm_pte = PTmap + atop(prev_addr);
5908 for (af = prev_addr; af < addr; af += PAGE_SIZE) {
5909 m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5910 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
5911 pte_store(&trm_pte[atop(af - prev_addr)], VM_PAGE_TO_PHYS(m) |
5912 PG_M | PG_A | PG_RW | PG_V | pgeflag |
5913 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE));
5920 void pmap_init_trm(void)
5924 TUNABLE_INT_FETCH("machdep.trm_guard", &trm_guard);
5925 if ((trm_guard & PAGE_MASK) != 0)
5927 pmap_trm_arena = vmem_create("i386trampoline", 0, 0, 1, 0, M_WAITOK);
5928 vmem_set_import(pmap_trm_arena, pmap_trm_import, NULL, NULL, PAGE_SIZE);
5929 pd_m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5930 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK | VM_ALLOC_ZERO);
5931 if ((pd_m->flags & PG_ZERO) == 0)
5932 pmap_zero_page(pd_m);
5933 PTD[TRPTDI] = VM_PAGE_TO_PHYS(pd_m) | PG_M | PG_A | PG_RW | PG_V |
5934 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, TRUE);
5938 pmap_trm_alloc(size_t size, int flags)
5943 MPASS((flags & ~(M_WAITOK | M_NOWAIT | M_ZERO)) == 0);
5944 error = vmem_xalloc(pmap_trm_arena, roundup2(size, 4), sizeof(int),
5945 0, 0, VMEM_ADDR_MIN, VMEM_ADDR_MAX, flags | M_FIRSTFIT, &res);
5948 if ((flags & M_ZERO) != 0)
5949 bzero((void *)res, size);
5950 return ((void *)res);
5954 pmap_trm_free(void *addr, size_t size)
5957 vmem_free(pmap_trm_arena, (uintptr_t)addr, roundup2(size, 4));
5960 #if defined(PMAP_DEBUG)
5961 pmap_pid_dump(int pid)
5968 sx_slock(&allproc_lock);
5969 FOREACH_PROC_IN_SYSTEM(p) {
5970 if (p->p_pid != pid)
5976 pmap = vmspace_pmap(p->p_vmspace);
5977 for (i = 0; i < NPDEPTD; i++) {
5980 vm_offset_t base = i << PDRSHIFT;
5982 pde = &pmap->pm_pdir[i];
5983 if (pde && pmap_pde_v(pde)) {
5984 for (j = 0; j < NPTEPG; j++) {
5985 vm_offset_t va = base + (j << PAGE_SHIFT);
5986 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5991 sx_sunlock(&allproc_lock);
5994 pte = pmap_pte(pmap, va);
5995 if (pte && pmap_pte_v(pte)) {
5999 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
6000 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
6001 va, pa, m->hold_count, m->wire_count, m->flags);
6016 sx_sunlock(&allproc_lock);