2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * This code is derived from software contributed to Berkeley by
12 * the Systems Programming Group of the University of Utah Computer
13 * Science Department and William Jolitz of UUNET Technologies Inc.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 * must display the following acknowledgement:
25 * This product includes software developed by the University of
26 * California, Berkeley and its contributors.
27 * 4. Neither the name of the University nor the names of its contributors
28 * may be used to endorse or promote products derived from this software
29 * without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
46 * Copyright (c) 2003 Networks Associates Technology, Inc.
47 * All rights reserved.
49 * This software was developed for the FreeBSD Project by Jake Burkholder,
50 * Safeport Network Services, and Network Associates Laboratories, the
51 * Security Research Division of Network Associates, Inc. under
52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
53 * CHATS research program.
55 * Redistribution and use in source and binary forms, with or without
56 * modification, are permitted provided that the following conditions
58 * 1. Redistributions of source code must retain the above copyright
59 * notice, this list of conditions and the following disclaimer.
60 * 2. Redistributions in binary form must reproduce the above copyright
61 * notice, this list of conditions and the following disclaimer in the
62 * documentation and/or other materials provided with the distribution.
64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
77 #include <sys/cdefs.h>
78 __FBSDID("$FreeBSD$");
81 * Manages physical address maps.
83 * Since the information managed by this module is
84 * also stored by the logical address mapping module,
85 * this module may throw away valid virtual-to-physical
86 * mappings at almost any time. However, invalidations
87 * of virtual-to-physical mappings must be done as
90 * In order to cope with hardware architectures which
91 * make virtual-to-physical map invalidates expensive,
92 * this module may delay invalidate or reduced protection
93 * operations until such time as they are actually
94 * necessary. This module is given full information as
95 * to which processors are currently using which maps,
96 * and to when physical maps must be made correct.
101 #include "opt_pmap.h"
103 #include "opt_xbox.h"
105 #include <sys/param.h>
106 #include <sys/systm.h>
107 #include <sys/kernel.h>
109 #include <sys/lock.h>
110 #include <sys/malloc.h>
111 #include <sys/mman.h>
112 #include <sys/msgbuf.h>
113 #include <sys/mutex.h>
114 #include <sys/proc.h>
115 #include <sys/rwlock.h>
116 #include <sys/sf_buf.h>
118 #include <sys/vmmeter.h>
119 #include <sys/sched.h>
120 #include <sys/sysctl.h>
124 #include <vm/vm_param.h>
125 #include <vm/vm_kern.h>
126 #include <vm/vm_page.h>
127 #include <vm/vm_map.h>
128 #include <vm/vm_object.h>
129 #include <vm/vm_extern.h>
130 #include <vm/vm_pageout.h>
131 #include <vm/vm_pager.h>
132 #include <vm/vm_phys.h>
133 #include <vm/vm_radix.h>
134 #include <vm/vm_reserv.h>
139 #include <machine/intr_machdep.h>
140 #include <x86/apicvar.h>
142 #include <machine/cpu.h>
143 #include <machine/cputypes.h>
144 #include <machine/md_var.h>
145 #include <machine/pcb.h>
146 #include <machine/specialreg.h>
148 #include <machine/smp.h>
152 #include <machine/xbox.h>
155 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
156 #define CPU_ENABLE_SSE
159 #ifndef PMAP_SHPGPERPROC
160 #define PMAP_SHPGPERPROC 200
163 #if !defined(DIAGNOSTIC)
164 #ifdef __GNUC_GNU_INLINE__
165 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
167 #define PMAP_INLINE extern inline
174 #define PV_STAT(x) do { x ; } while (0)
176 #define PV_STAT(x) do { } while (0)
179 #define pa_index(pa) ((pa) >> PDRSHIFT)
180 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
183 * Get PDEs and PTEs for user/kernel address space
185 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
186 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
188 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
189 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
190 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
191 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
192 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
194 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
195 atomic_clear_int((u_int *)(pte), PG_W))
196 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
198 struct pmap kernel_pmap_store;
199 LIST_HEAD(pmaplist, pmap);
200 static struct pmaplist allpmaps;
201 static struct mtx allpmaps_lock;
203 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
204 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
205 int pgeflag = 0; /* PG_G or-in */
206 int pseflag = 0; /* PG_PS or-in */
208 static int nkpt = NKPT;
209 vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR;
210 extern u_int32_t KERNend;
211 extern u_int32_t KPTphys;
213 #if defined(PAE) || defined(PAE_TABLES)
215 static uma_zone_t pdptzone;
218 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
220 static int pat_works = 1;
221 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
222 "Is page attribute table fully functional?");
224 static int pg_ps_enabled = 1;
225 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
226 &pg_ps_enabled, 0, "Are large page mappings enabled?");
228 #define PAT_INDEX_SIZE 8
229 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
232 * pmap_mapdev support pre initialization (i.e. console)
234 #define PMAP_PREINIT_MAPPING_COUNT 8
235 static struct pmap_preinit_mapping {
240 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
241 static int pmap_initialized;
243 static struct rwlock_padalign pvh_global_lock;
246 * Data for the pv entry allocation mechanism
248 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
249 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
250 static struct md_page *pv_table;
251 static int shpgperproc = PMAP_SHPGPERPROC;
253 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
254 int pv_maxchunks; /* How many chunks we have KVA for */
255 vm_offset_t pv_vafree; /* freelist stored in the PTE */
258 * All those kernel PT submaps that BSD is so fond of
267 static struct sysmaps sysmaps_pcpu[MAXCPU];
269 static pd_entry_t *KPTD;
272 struct msgbuf *msgbufp = NULL;
277 static caddr_t crashdumpmap;
279 static pt_entry_t *PMAP1 = NULL, *PMAP2;
280 static pt_entry_t *PADDR1 = NULL, *PADDR2;
283 static int PMAP1changedcpu;
284 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
286 "Number of times pmap_pte_quick changed CPU with same PMAP1");
288 static int PMAP1changed;
289 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
291 "Number of times pmap_pte_quick changed PMAP1");
292 static int PMAP1unchanged;
293 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
295 "Number of times pmap_pte_quick didn't change PMAP1");
296 static struct mtx PMAP2mutex;
298 static void free_pv_chunk(struct pv_chunk *pc);
299 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
300 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
301 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
302 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
303 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
304 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
305 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
307 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
309 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
310 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
312 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
313 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
314 static void pmap_flush_page(vm_page_t m);
315 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
316 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
317 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
318 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
319 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
320 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
321 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
322 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
323 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
325 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
326 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
327 struct spglist *free);
328 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
329 struct spglist *free);
330 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
331 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
332 struct spglist *free);
333 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
335 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
336 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
338 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
340 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
342 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
344 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
345 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
346 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
347 static void pmap_pte_release(pt_entry_t *pte);
348 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
349 #if defined(PAE) || defined(PAE_TABLES)
350 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, uint8_t *flags,
353 static void pmap_set_pg(void);
355 static __inline void pagezero(void *page);
357 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
358 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
361 * If you get an error here, then you set KVA_PAGES wrong! See the
362 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be
363 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE.
365 CTASSERT(KERNBASE % (1 << 24) == 0);
368 * Bootstrap the system enough to run with virtual memory.
370 * On the i386 this is called after mapping has already been enabled
371 * and just syncs the pmap module with what has already been done.
372 * [We can't call it easily with mapping off since the kernel is not
373 * mapped with PA == VA, hence we would have to relocate every address
374 * from the linked base (virtual) address "KERNBASE" to the actual
375 * (physical) address starting relative to 0]
378 pmap_bootstrap(vm_paddr_t firstaddr)
381 pt_entry_t *pte, *unused;
382 struct sysmaps *sysmaps;
386 * Add a physical memory segment (vm_phys_seg) corresponding to the
387 * preallocated kernel page table pages so that vm_page structures
388 * representing these pages will be created. The vm_page structures
389 * are required for promotion of the corresponding kernel virtual
390 * addresses to superpage mappings.
392 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
395 * Initialize the first available kernel virtual address. However,
396 * using "firstaddr" may waste a few pages of the kernel virtual
397 * address space, because locore may not have mapped every physical
398 * page that it allocated. Preferably, locore would provide a first
399 * unused virtual address in addition to "firstaddr".
401 virtual_avail = (vm_offset_t) KERNBASE + firstaddr;
403 virtual_end = VM_MAX_KERNEL_ADDRESS;
406 * Initialize the kernel pmap (which is statically allocated).
408 PMAP_LOCK_INIT(kernel_pmap);
409 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD);
410 #if defined(PAE) || defined(PAE_TABLES)
411 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT);
413 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
414 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
417 * Initialize the global pv list lock.
419 rw_init(&pvh_global_lock, "pmap pv global");
421 LIST_INIT(&allpmaps);
424 * Request a spin mutex so that changes to allpmaps cannot be
425 * preempted by smp_rendezvous_cpus(). Otherwise,
426 * pmap_update_pde_kernel() could access allpmaps while it is
429 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
430 mtx_lock_spin(&allpmaps_lock);
431 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
432 mtx_unlock_spin(&allpmaps_lock);
435 * Reserve some special page table entries/VA space for temporary
438 #define SYSMAP(c, p, v, n) \
439 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
445 * CMAP1/CMAP2 are used for zeroing and copying pages.
446 * CMAP3 is used for the boot-time memory test.
448 for (i = 0; i < MAXCPU; i++) {
449 sysmaps = &sysmaps_pcpu[i];
450 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF);
451 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1)
452 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1)
454 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
459 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
462 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
464 SYSMAP(caddr_t, unused, ptvmmap, 1)
467 * msgbufp is used to map the system message buffer.
469 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
472 * KPTmap is used by pmap_kextract().
474 * KPTmap is first initialized by locore. However, that initial
475 * KPTmap can only support NKPT page table pages. Here, a larger
476 * KPTmap is created that can support KVA_PAGES page table pages.
478 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
480 for (i = 0; i < NKPT; i++)
481 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V;
484 * Adjust the start of the KPTD and KPTmap so that the implementation
485 * of pmap_kextract() and pmap_growkernel() can be made simpler.
488 KPTmap -= i386_btop(KPTDI << PDRSHIFT);
491 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
494 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
495 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
497 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
502 * Leave in place an identity mapping (virt == phys) for the low 1 MB
503 * physical memory region that is used by the ACPI wakeup code. This
504 * mapping must not have PG_G set.
507 /* FIXME: This is gross, but needed for the XBOX. Since we are in such
508 * an early stadium, we cannot yet neatly map video memory ... :-(
509 * Better fixes are very welcome! */
510 if (!arch_i386_is_xbox)
512 for (i = 1; i < NKPT; i++)
515 /* Initialize the PAT MSR if present. */
518 /* Turn on PG_G on kernel page(s) */
523 pmap_init_qpages(void)
530 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE);
531 if (pc->pc_qmap_addr == 0)
532 panic("pmap_init_qpages: unable to allocate KVA");
536 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_qpages, NULL);
544 int pat_table[PAT_INDEX_SIZE];
549 /* Set default PAT index table. */
550 for (i = 0; i < PAT_INDEX_SIZE; i++)
552 pat_table[PAT_WRITE_BACK] = 0;
553 pat_table[PAT_WRITE_THROUGH] = 1;
554 pat_table[PAT_UNCACHEABLE] = 3;
555 pat_table[PAT_WRITE_COMBINING] = 3;
556 pat_table[PAT_WRITE_PROTECTED] = 3;
557 pat_table[PAT_UNCACHED] = 3;
559 /* Bail if this CPU doesn't implement PAT. */
560 if ((cpu_feature & CPUID_PAT) == 0) {
561 for (i = 0; i < PAT_INDEX_SIZE; i++)
562 pat_index[i] = pat_table[i];
568 * Due to some Intel errata, we can only safely use the lower 4
571 * Intel Pentium III Processor Specification Update
572 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
575 * Intel Pentium IV Processor Specification Update
576 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
578 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
579 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
582 /* Initialize default PAT entries. */
583 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
584 PAT_VALUE(1, PAT_WRITE_THROUGH) |
585 PAT_VALUE(2, PAT_UNCACHED) |
586 PAT_VALUE(3, PAT_UNCACHEABLE) |
587 PAT_VALUE(4, PAT_WRITE_BACK) |
588 PAT_VALUE(5, PAT_WRITE_THROUGH) |
589 PAT_VALUE(6, PAT_UNCACHED) |
590 PAT_VALUE(7, PAT_UNCACHEABLE);
594 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
595 * Program 5 and 6 as WP and WC.
596 * Leave 4 and 7 as WB and UC.
598 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
599 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
600 PAT_VALUE(6, PAT_WRITE_COMBINING);
601 pat_table[PAT_UNCACHED] = 2;
602 pat_table[PAT_WRITE_PROTECTED] = 5;
603 pat_table[PAT_WRITE_COMBINING] = 6;
606 * Just replace PAT Index 2 with WC instead of UC-.
608 pat_msr &= ~PAT_MASK(2);
609 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
610 pat_table[PAT_WRITE_COMBINING] = 2;
615 load_cr4(cr4 & ~CR4_PGE);
617 /* Disable caches (CD = 1, NW = 0). */
619 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
621 /* Flushes caches and TLBs. */
625 /* Update PAT and index table. */
626 wrmsr(MSR_PAT, pat_msr);
627 for (i = 0; i < PAT_INDEX_SIZE; i++)
628 pat_index[i] = pat_table[i];
630 /* Flush caches and TLBs again. */
634 /* Restore caches and PGE. */
640 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on.
646 vm_offset_t va, endva;
651 endva = KERNBASE + KERNend;
654 va = KERNBASE + KERNLOAD;
656 pdir_pde(PTD, va) |= pgeflag;
657 invltlb(); /* Flush non-PG_G entries. */
661 va = (vm_offset_t)btext;
666 invltlb(); /* Flush non-PG_G entries. */
673 * Initialize a vm_page's machine-dependent fields.
676 pmap_page_init(vm_page_t m)
679 TAILQ_INIT(&m->md.pv_list);
680 m->md.pat_mode = PAT_WRITE_BACK;
683 #if defined(PAE) || defined(PAE_TABLES)
685 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, uint8_t *flags, int wait)
688 /* Inform UMA that this allocator uses kernel_map/object. */
689 *flags = UMA_SLAB_KERNEL;
690 return ((void *)kmem_alloc_contig(kernel_arena, bytes, wait, 0x0ULL,
691 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
696 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
698 * - Must deal with pages in order to ensure that none of the PG_* bits
699 * are ever set, PG_V in particular.
700 * - Assumes we can write to ptes without pte_store() atomic ops, even
701 * on PAE systems. This should be ok.
702 * - Assumes nothing will ever test these addresses for 0 to indicate
703 * no mapping instead of correctly checking PG_V.
704 * - Assumes a vm_offset_t will fit in a pte (true for i386).
705 * Because PG_V is never set, there can be no mappings to invalidate.
708 pmap_ptelist_alloc(vm_offset_t *head)
715 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
719 panic("pmap_ptelist_alloc: va with PG_V set!");
725 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
730 panic("pmap_ptelist_free: freeing va with PG_V set!");
732 *pte = *head; /* virtual! PG_V is 0 though */
737 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
743 for (i = npages - 1; i >= 0; i--) {
744 va = (vm_offset_t)base + i * PAGE_SIZE;
745 pmap_ptelist_free(head, va);
751 * Initialize the pmap module.
752 * Called by vm_init, to initialize any structures that the pmap
753 * system needs to map virtual memory.
758 struct pmap_preinit_mapping *ppim;
764 * Initialize the vm page array entries for the kernel pmap's
767 for (i = 0; i < NKPT; i++) {
768 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
769 KASSERT(mpte >= vm_page_array &&
770 mpte < &vm_page_array[vm_page_array_size],
771 ("pmap_init: page table page is out of range"));
772 mpte->pindex = i + KPTDI;
773 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
777 * Initialize the address space (zone) for the pv entries. Set a
778 * high water mark so that the system can recover from excessive
779 * numbers of pv entries.
781 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
782 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
783 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
784 pv_entry_max = roundup(pv_entry_max, _NPCPV);
785 pv_entry_high_water = 9 * (pv_entry_max / 10);
788 * If the kernel is running on a virtual machine, then it must assume
789 * that MCA is enabled by the hypervisor. Moreover, the kernel must
790 * be prepared for the hypervisor changing the vendor and family that
791 * are reported by CPUID. Consequently, the workaround for AMD Family
792 * 10h Erratum 383 is enabled if the processor's feature set does not
793 * include at least one feature that is only supported by older Intel
794 * or newer AMD processors.
796 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
797 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
798 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
800 workaround_erratum383 = 1;
803 * Are large page mappings supported and enabled?
805 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
808 else if (pg_ps_enabled) {
809 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
810 ("pmap_init: can't assign to pagesizes[1]"));
811 pagesizes[1] = NBPDR;
815 * Calculate the size of the pv head table for superpages.
816 * Handle the possibility that "vm_phys_segs[...].end" is zero.
818 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
819 PAGE_SIZE) / NBPDR + 1;
822 * Allocate memory for the pv head table for superpages.
824 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
826 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
828 for (i = 0; i < pv_npg; i++)
829 TAILQ_INIT(&pv_table[i].pv_list);
831 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
832 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
833 if (pv_chunkbase == NULL)
834 panic("pmap_init: not enough kvm for pv chunks");
835 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
836 #if defined(PAE) || defined(PAE_TABLES)
837 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
838 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
839 UMA_ZONE_VM | UMA_ZONE_NOFREE);
840 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
843 pmap_initialized = 1;
846 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
847 ppim = pmap_preinit_mapping + i;
850 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
851 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
856 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
857 "Max number of PV entries");
858 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
859 "Page share factor per proc");
861 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
862 "2/4MB page mapping counters");
864 static u_long pmap_pde_demotions;
865 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
866 &pmap_pde_demotions, 0, "2/4MB page demotions");
868 static u_long pmap_pde_mappings;
869 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
870 &pmap_pde_mappings, 0, "2/4MB page mappings");
872 static u_long pmap_pde_p_failures;
873 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
874 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
876 static u_long pmap_pde_promotions;
877 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
878 &pmap_pde_promotions, 0, "2/4MB page promotions");
880 /***************************************************
881 * Low level helper routines.....
882 ***************************************************/
885 * Determine the appropriate bits to set in a PTE or PDE for a specified
889 pmap_cache_bits(int mode, boolean_t is_pde)
891 int cache_bits, pat_flag, pat_idx;
893 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
894 panic("Unknown caching mode %d\n", mode);
896 /* The PAT bit is different for PTE's and PDE's. */
897 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
899 /* Map the caching mode to a PAT index. */
900 pat_idx = pat_index[mode];
902 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
905 cache_bits |= pat_flag;
907 cache_bits |= PG_NC_PCD;
909 cache_bits |= PG_NC_PWT;
914 * The caller is responsible for maintaining TLB consistency.
917 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
921 boolean_t PTD_updated;
924 mtx_lock_spin(&allpmaps_lock);
925 LIST_FOREACH(pmap, &allpmaps, pm_list) {
926 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] &
929 pde = pmap_pde(pmap, va);
930 pde_store(pde, newpde);
932 mtx_unlock_spin(&allpmaps_lock);
934 ("pmap_kenter_pde: current page table is not in allpmaps"));
938 * After changing the page size for the specified virtual address in the page
939 * table, flush the corresponding entries from the processor's TLB. Only the
940 * calling processor's TLB is affected.
942 * The calling thread must be pinned to a processor.
945 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
949 if ((newpde & PG_PS) == 0)
950 /* Demotion: flush a specific 2MB page mapping. */
952 else if ((newpde & PG_G) == 0)
954 * Promotion: flush every 4KB page mapping from the TLB
955 * because there are too many to flush individually.
960 * Promotion: flush every 4KB page mapping from the TLB,
961 * including any global (PG_G) mappings.
964 load_cr4(cr4 & ~CR4_PGE);
966 * Although preemption at this point could be detrimental to
967 * performance, it would not lead to an error. PG_G is simply
968 * ignored if CR4.PGE is clear. Moreover, in case this block
969 * is re-entered, the load_cr4() either above or below will
970 * modify CR4.PGE flushing the TLB.
972 load_cr4(cr4 | CR4_PGE);
985 load_cr4(cr4 & ~CR4_PGE);
986 load_cr4(cr4 | CR4_PGE);
993 * For SMP, these functions have to use the IPI mechanism for coherence.
995 * N.B.: Before calling any of the following TLB invalidation functions,
996 * the calling processor must ensure that all stores updating a non-
997 * kernel page table are globally performed. Otherwise, another
998 * processor could cache an old, pre-update entry without being
999 * invalidated. This can happen one of two ways: (1) The pmap becomes
1000 * active on another processor after its pm_active field is checked by
1001 * one of the following functions but before a store updating the page
1002 * table is globally performed. (2) The pmap becomes active on another
1003 * processor before its pm_active field is checked but due to
1004 * speculative loads one of the following functions stills reads the
1005 * pmap as inactive on the other processor.
1007 * The kernel page table is exempt because its pm_active field is
1008 * immutable. The kernel page table is always active on every
1012 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1014 cpuset_t *mask, other_cpus;
1018 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1022 cpuid = PCPU_GET(cpuid);
1023 other_cpus = all_cpus;
1024 CPU_CLR(cpuid, &other_cpus);
1025 if (CPU_ISSET(cpuid, &pmap->pm_active))
1027 CPU_AND(&other_cpus, &pmap->pm_active);
1030 smp_masked_invlpg(*mask, va);
1034 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1035 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1038 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1040 cpuset_t *mask, other_cpus;
1044 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1045 pmap_invalidate_all(pmap);
1050 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1051 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1055 cpuid = PCPU_GET(cpuid);
1056 other_cpus = all_cpus;
1057 CPU_CLR(cpuid, &other_cpus);
1058 if (CPU_ISSET(cpuid, &pmap->pm_active))
1059 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1061 CPU_AND(&other_cpus, &pmap->pm_active);
1064 smp_masked_invlpg_range(*mask, sva, eva);
1069 pmap_invalidate_all(pmap_t pmap)
1071 cpuset_t *mask, other_cpus;
1075 if (pmap == kernel_pmap) {
1078 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1082 cpuid = PCPU_GET(cpuid);
1083 other_cpus = all_cpus;
1084 CPU_CLR(cpuid, &other_cpus);
1085 if (CPU_ISSET(cpuid, &pmap->pm_active))
1087 CPU_AND(&other_cpus, &pmap->pm_active);
1090 smp_masked_invltlb(*mask, pmap);
1095 pmap_invalidate_cache(void)
1105 cpuset_t invalidate; /* processors that invalidate their TLB */
1109 u_int store; /* processor that updates the PDE */
1113 pmap_update_pde_kernel(void *arg)
1115 struct pde_action *act = arg;
1119 if (act->store == PCPU_GET(cpuid)) {
1122 * Elsewhere, this operation requires allpmaps_lock for
1123 * synchronization. Here, it does not because it is being
1124 * performed in the context of an all_cpus rendezvous.
1126 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1127 pde = pmap_pde(pmap, act->va);
1128 pde_store(pde, act->newpde);
1134 pmap_update_pde_user(void *arg)
1136 struct pde_action *act = arg;
1138 if (act->store == PCPU_GET(cpuid))
1139 pde_store(act->pde, act->newpde);
1143 pmap_update_pde_teardown(void *arg)
1145 struct pde_action *act = arg;
1147 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1148 pmap_update_pde_invalidate(act->va, act->newpde);
1152 * Change the page size for the specified virtual address in a way that
1153 * prevents any possibility of the TLB ever having two entries that map the
1154 * same virtual address using different page sizes. This is the recommended
1155 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1156 * machine check exception for a TLB state that is improperly diagnosed as a
1160 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1162 struct pde_action act;
1163 cpuset_t active, other_cpus;
1167 cpuid = PCPU_GET(cpuid);
1168 other_cpus = all_cpus;
1169 CPU_CLR(cpuid, &other_cpus);
1170 if (pmap == kernel_pmap)
1173 active = pmap->pm_active;
1174 if (CPU_OVERLAP(&active, &other_cpus)) {
1176 act.invalidate = active;
1179 act.newpde = newpde;
1180 CPU_SET(cpuid, &active);
1181 smp_rendezvous_cpus(active,
1182 smp_no_rendevous_barrier, pmap == kernel_pmap ?
1183 pmap_update_pde_kernel : pmap_update_pde_user,
1184 pmap_update_pde_teardown, &act);
1186 if (pmap == kernel_pmap)
1187 pmap_kenter_pde(va, newpde);
1189 pde_store(pde, newpde);
1190 if (CPU_ISSET(cpuid, &active))
1191 pmap_update_pde_invalidate(va, newpde);
1197 * Normal, non-SMP, 486+ invalidation functions.
1198 * We inline these within pmap.c for speed.
1201 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1204 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1209 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1213 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1214 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1219 pmap_invalidate_all(pmap_t pmap)
1222 if (pmap == kernel_pmap)
1224 else if (!CPU_EMPTY(&pmap->pm_active))
1229 pmap_invalidate_cache(void)
1236 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1239 if (pmap == kernel_pmap)
1240 pmap_kenter_pde(va, newpde);
1242 pde_store(pde, newpde);
1243 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1244 pmap_update_pde_invalidate(va, newpde);
1248 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1251 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1255 sva &= ~(vm_offset_t)cpu_clflush_line_size;
1257 KASSERT((sva & PAGE_MASK) == 0,
1258 ("pmap_invalidate_cache_range: sva not page-aligned"));
1259 KASSERT((eva & PAGE_MASK) == 0,
1260 ("pmap_invalidate_cache_range: eva not page-aligned"));
1263 if ((cpu_feature & CPUID_SS) != 0 && !force)
1264 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1265 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
1266 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1269 * XXX: Some CPUs fault, hang, or trash the local APIC
1270 * registers if we use CLFLUSH on the local APIC
1271 * range. The local APIC is always uncached, so we
1272 * don't need to flush for that range anyway.
1274 if (pmap_kextract(sva) == lapic_paddr)
1278 * Otherwise, do per-cache line flush. Use the mfence
1279 * instruction to insure that previous stores are
1280 * included in the write-back. The processor
1281 * propagates flush to other processors in the cache
1285 for (; sva < eva; sva += cpu_clflush_line_size)
1288 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1289 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1291 if (pmap_kextract(sva) == lapic_paddr)
1295 * Writes are ordered by CLFLUSH on Intel CPUs.
1297 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1299 for (; sva < eva; sva += cpu_clflush_line_size)
1301 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1306 * No targeted cache flush methods are supported by CPU,
1307 * or the supplied range is bigger than 2MB.
1308 * Globally invalidate cache.
1310 pmap_invalidate_cache();
1315 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1319 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1320 (cpu_feature & CPUID_CLFSH) == 0) {
1321 pmap_invalidate_cache();
1323 for (i = 0; i < count; i++)
1324 pmap_flush_page(pages[i]);
1329 * Are we current address space or kernel?
1332 pmap_is_current(pmap_t pmap)
1335 return (pmap == kernel_pmap || pmap ==
1336 vmspace_pmap(curthread->td_proc->p_vmspace));
1340 * If the given pmap is not the current or kernel pmap, the returned pte must
1341 * be released by passing it to pmap_pte_release().
1344 pmap_pte(pmap_t pmap, vm_offset_t va)
1349 pde = pmap_pde(pmap, va);
1353 /* are we current address space or kernel? */
1354 if (pmap_is_current(pmap))
1355 return (vtopte(va));
1356 mtx_lock(&PMAP2mutex);
1357 newpf = *pde & PG_FRAME;
1358 if ((*PMAP2 & PG_FRAME) != newpf) {
1359 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1360 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1362 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1368 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1371 static __inline void
1372 pmap_pte_release(pt_entry_t *pte)
1375 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1376 mtx_unlock(&PMAP2mutex);
1380 * NB: The sequence of updating a page table followed by accesses to the
1381 * corresponding pages is subject to the situation described in the "AMD64
1382 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1383 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1384 * right after modifying the PTE bits is crucial.
1386 static __inline void
1387 invlcaddr(void *caddr)
1390 invlpg((u_int)caddr);
1394 * Super fast pmap_pte routine best used when scanning
1395 * the pv lists. This eliminates many coarse-grained
1396 * invltlb calls. Note that many of the pv list
1397 * scans are across different pmaps. It is very wasteful
1398 * to do an entire invltlb for checking a single mapping.
1400 * If the given pmap is not the current pmap, pvh_global_lock
1401 * must be held and curthread pinned to a CPU.
1404 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1409 pde = pmap_pde(pmap, va);
1413 /* are we current address space or kernel? */
1414 if (pmap_is_current(pmap))
1415 return (vtopte(va));
1416 rw_assert(&pvh_global_lock, RA_WLOCKED);
1417 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1418 newpf = *pde & PG_FRAME;
1419 if ((*PMAP1 & PG_FRAME) != newpf) {
1420 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1422 PMAP1cpu = PCPU_GET(cpuid);
1428 if (PMAP1cpu != PCPU_GET(cpuid)) {
1429 PMAP1cpu = PCPU_GET(cpuid);
1435 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1441 * Routine: pmap_extract
1443 * Extract the physical page address associated
1444 * with the given map/virtual_address pair.
1447 pmap_extract(pmap_t pmap, vm_offset_t va)
1455 pde = pmap->pm_pdir[va >> PDRSHIFT];
1457 if ((pde & PG_PS) != 0)
1458 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1460 pte = pmap_pte(pmap, va);
1461 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK);
1462 pmap_pte_release(pte);
1470 * Routine: pmap_extract_and_hold
1472 * Atomically extract and hold the physical page
1473 * with the given pmap and virtual address pair
1474 * if that mapping permits the given protection.
1477 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1480 pt_entry_t pte, *ptep;
1488 pde = *pmap_pde(pmap, va);
1491 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1492 if (vm_page_pa_tryrelock(pmap, (pde &
1493 PG_PS_FRAME) | (va & PDRMASK), &pa))
1495 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1500 ptep = pmap_pte(pmap, va);
1502 pmap_pte_release(ptep);
1504 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1505 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1508 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1518 /***************************************************
1519 * Low level mapping routines.....
1520 ***************************************************/
1523 * Add a wired page to the kva.
1524 * Note: not SMP coherent.
1526 * This function may be used before pmap_bootstrap() is called.
1529 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1534 pte_store(pte, pa | PG_RW | PG_V | pgeflag);
1537 static __inline void
1538 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1543 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0));
1547 * Remove a page from the kernel pagetables.
1548 * Note: not SMP coherent.
1550 * This function may be used before pmap_bootstrap() is called.
1553 pmap_kremove(vm_offset_t va)
1562 * Used to map a range of physical addresses into kernel
1563 * virtual address space.
1565 * The value passed in '*virt' is a suggested virtual address for
1566 * the mapping. Architectures which can support a direct-mapped
1567 * physical to virtual region can return the appropriate address
1568 * within that region, leaving '*virt' unchanged. Other
1569 * architectures should map the pages starting at '*virt' and
1570 * update '*virt' with the first usable address after the mapped
1574 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1576 vm_offset_t va, sva;
1577 vm_paddr_t superpage_offset;
1582 * Does the physical address range's size and alignment permit at
1583 * least one superpage mapping to be created?
1585 superpage_offset = start & PDRMASK;
1586 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1588 * Increase the starting virtual address so that its alignment
1589 * does not preclude the use of superpage mappings.
1591 if ((va & PDRMASK) < superpage_offset)
1592 va = (va & ~PDRMASK) + superpage_offset;
1593 else if ((va & PDRMASK) > superpage_offset)
1594 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1597 while (start < end) {
1598 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1600 KASSERT((va & PDRMASK) == 0,
1601 ("pmap_map: misaligned va %#x", va));
1602 newpde = start | PG_PS | pgeflag | PG_RW | PG_V;
1603 pmap_kenter_pde(va, newpde);
1607 pmap_kenter(va, start);
1612 pmap_invalidate_range(kernel_pmap, sva, va);
1619 * Add a list of wired pages to the kva
1620 * this routine is only used for temporary
1621 * kernel mappings that do not need to have
1622 * page modification or references recorded.
1623 * Note that old mappings are simply written
1624 * over. The page *must* be wired.
1625 * Note: SMP coherent. Uses a ranged shootdown IPI.
1628 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1630 pt_entry_t *endpte, oldpte, pa, *pte;
1635 endpte = pte + count;
1636 while (pte < endpte) {
1638 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1639 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1641 pte_store(pte, pa | pgeflag | PG_RW | PG_V);
1645 if (__predict_false((oldpte & PG_V) != 0))
1646 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1651 * This routine tears out page mappings from the
1652 * kernel -- it is meant only for temporary mappings.
1653 * Note: SMP coherent. Uses a ranged shootdown IPI.
1656 pmap_qremove(vm_offset_t sva, int count)
1661 while (count-- > 0) {
1665 pmap_invalidate_range(kernel_pmap, sva, va);
1668 /***************************************************
1669 * Page table page management routines.....
1670 ***************************************************/
1671 static __inline void
1672 pmap_free_zero_pages(struct spglist *free)
1676 while ((m = SLIST_FIRST(free)) != NULL) {
1677 SLIST_REMOVE_HEAD(free, plinks.s.ss);
1678 /* Preserve the page's PG_ZERO setting. */
1679 vm_page_free_toq(m);
1684 * Schedule the specified unused page table page to be freed. Specifically,
1685 * add the page to the specified list of pages that will be released to the
1686 * physical memory manager after the TLB has been updated.
1688 static __inline void
1689 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1690 boolean_t set_PG_ZERO)
1694 m->flags |= PG_ZERO;
1696 m->flags &= ~PG_ZERO;
1697 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1701 * Inserts the specified page table page into the specified pmap's collection
1702 * of idle page table pages. Each of a pmap's page table pages is responsible
1703 * for mapping a distinct range of virtual addresses. The pmap's collection is
1704 * ordered by this virtual address range.
1707 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1710 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1711 return (vm_radix_insert(&pmap->pm_root, mpte));
1715 * Removes the page table page mapping the specified virtual address from the
1716 * specified pmap's collection of idle page table pages, and returns it.
1717 * Otherwise, returns NULL if there is no page table page corresponding to the
1718 * specified virtual address.
1720 static __inline vm_page_t
1721 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
1724 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1725 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT));
1729 * Decrements a page table page's wire count, which is used to record the
1730 * number of valid page table entries within the page. If the wire count
1731 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1732 * page table page was unmapped and FALSE otherwise.
1734 static inline boolean_t
1735 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1739 if (m->wire_count == 0) {
1740 _pmap_unwire_ptp(pmap, m, free);
1747 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1752 * unmap the page table page
1754 pmap->pm_pdir[m->pindex] = 0;
1755 --pmap->pm_stats.resident_count;
1758 * This is a release store so that the ordinary store unmapping
1759 * the page table page is globally performed before TLB shoot-
1762 atomic_subtract_rel_int(&vm_cnt.v_wire_count, 1);
1765 * Do an invltlb to make the invalidated mapping
1766 * take effect immediately.
1768 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex);
1769 pmap_invalidate_page(pmap, pteva);
1772 * Put page on a list so that it is released after
1773 * *ALL* TLB shootdown is done
1775 pmap_add_delayed_free_list(m, free, TRUE);
1779 * After removing a page table entry, this routine is used to
1780 * conditionally free the page, and manage the hold/wire counts.
1783 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1788 if (va >= VM_MAXUSER_ADDRESS)
1790 ptepde = *pmap_pde(pmap, va);
1791 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1792 return (pmap_unwire_ptp(pmap, mpte, free));
1796 * Initialize the pmap for the swapper process.
1799 pmap_pinit0(pmap_t pmap)
1802 PMAP_LOCK_INIT(pmap);
1804 * Since the page table directory is shared with the kernel pmap,
1805 * which is already included in the list "allpmaps", this pmap does
1806 * not need to be inserted into that list.
1808 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD);
1809 #if defined(PAE) || defined(PAE_TABLES)
1810 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT);
1812 pmap->pm_root.rt_root = 0;
1813 CPU_ZERO(&pmap->pm_active);
1814 PCPU_SET(curpmap, pmap);
1815 TAILQ_INIT(&pmap->pm_pvchunk);
1816 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1820 * Initialize a preallocated and zeroed pmap structure,
1821 * such as one in a vmspace structure.
1824 pmap_pinit(pmap_t pmap)
1826 vm_page_t m, ptdpg[NPGPTD];
1831 * No need to allocate page table space yet but we do need a valid
1832 * page directory table.
1834 if (pmap->pm_pdir == NULL) {
1835 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
1836 if (pmap->pm_pdir == NULL)
1838 #if defined(PAE) || defined(PAE_TABLES)
1839 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
1840 KASSERT(((vm_offset_t)pmap->pm_pdpt &
1841 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
1842 ("pmap_pinit: pdpt misaligned"));
1843 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
1844 ("pmap_pinit: pdpt above 4g"));
1846 pmap->pm_root.rt_root = 0;
1848 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1849 ("pmap_pinit: pmap has reserved page table page(s)"));
1852 * allocate the page directory page(s)
1854 for (i = 0; i < NPGPTD;) {
1855 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1856 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1864 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD);
1866 for (i = 0; i < NPGPTD; i++)
1867 if ((ptdpg[i]->flags & PG_ZERO) == 0)
1868 pagezero(pmap->pm_pdir + (i * NPDEPG));
1870 mtx_lock_spin(&allpmaps_lock);
1871 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1872 /* Copy the kernel page table directory entries. */
1873 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t));
1874 mtx_unlock_spin(&allpmaps_lock);
1876 /* install self-referential address mapping entry(s) */
1877 for (i = 0; i < NPGPTD; i++) {
1878 pa = VM_PAGE_TO_PHYS(ptdpg[i]);
1879 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M;
1880 #if defined(PAE) || defined(PAE_TABLES)
1881 pmap->pm_pdpt[i] = pa | PG_V;
1885 CPU_ZERO(&pmap->pm_active);
1886 TAILQ_INIT(&pmap->pm_pvchunk);
1887 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1893 * this routine is called if the page table page is not
1897 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
1903 * Allocate a page table page.
1905 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1906 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1907 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
1909 rw_wunlock(&pvh_global_lock);
1911 rw_wlock(&pvh_global_lock);
1916 * Indicate the need to retry. While waiting, the page table
1917 * page may have been allocated.
1921 if ((m->flags & PG_ZERO) == 0)
1925 * Map the pagetable page into the process address space, if
1926 * it isn't already there.
1929 pmap->pm_stats.resident_count++;
1931 ptepa = VM_PAGE_TO_PHYS(m);
1932 pmap->pm_pdir[ptepindex] =
1933 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
1939 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
1946 * Calculate pagetable page index
1948 ptepindex = va >> PDRSHIFT;
1951 * Get the page directory entry
1953 ptepa = pmap->pm_pdir[ptepindex];
1956 * This supports switching from a 4MB page to a
1959 if (ptepa & PG_PS) {
1960 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
1961 ptepa = pmap->pm_pdir[ptepindex];
1965 * If the page table page is mapped, we just increment the
1966 * hold count, and activate it.
1969 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
1973 * Here if the pte page isn't mapped, or if it has
1976 m = _pmap_allocpte(pmap, ptepindex, flags);
1977 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
1984 /***************************************************
1985 * Pmap allocation/deallocation routines.
1986 ***************************************************/
1989 * Release any resources held by the given physical map.
1990 * Called when a pmap initialized by pmap_pinit is being released.
1991 * Should only be called if the map contains no valid mappings.
1994 pmap_release(pmap_t pmap)
1996 vm_page_t m, ptdpg[NPGPTD];
1999 KASSERT(pmap->pm_stats.resident_count == 0,
2000 ("pmap_release: pmap resident count %ld != 0",
2001 pmap->pm_stats.resident_count));
2002 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2003 ("pmap_release: pmap has reserved page table page(s)"));
2004 KASSERT(CPU_EMPTY(&pmap->pm_active),
2005 ("releasing active pmap %p", pmap));
2007 mtx_lock_spin(&allpmaps_lock);
2008 LIST_REMOVE(pmap, pm_list);
2009 mtx_unlock_spin(&allpmaps_lock);
2011 for (i = 0; i < NPGPTD; i++)
2012 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] &
2015 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) *
2016 sizeof(*pmap->pm_pdir));
2018 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2020 for (i = 0; i < NPGPTD; i++) {
2022 #if defined(PAE) || defined(PAE_TABLES)
2023 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2024 ("pmap_release: got wrong ptd page"));
2027 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2028 vm_page_free_zero(m);
2033 kvm_size(SYSCTL_HANDLER_ARGS)
2035 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2037 return (sysctl_handle_long(oidp, &ksize, 0, req));
2039 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2040 0, 0, kvm_size, "IU", "Size of KVM");
2043 kvm_free(SYSCTL_HANDLER_ARGS)
2045 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2047 return (sysctl_handle_long(oidp, &kfree, 0, req));
2049 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2050 0, 0, kvm_free, "IU", "Amount of KVM free");
2053 * grow the number of kernel page table entries, if needed
2056 pmap_growkernel(vm_offset_t addr)
2058 vm_paddr_t ptppaddr;
2062 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2063 addr = roundup2(addr, NBPDR);
2064 if (addr - 1 >= kernel_map->max_offset)
2065 addr = kernel_map->max_offset;
2066 while (kernel_vm_end < addr) {
2067 if (pdir_pde(PTD, kernel_vm_end)) {
2068 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2069 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2070 kernel_vm_end = kernel_map->max_offset;
2076 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2077 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2080 panic("pmap_growkernel: no memory to grow kernel");
2084 if ((nkpg->flags & PG_ZERO) == 0)
2085 pmap_zero_page(nkpg);
2086 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2087 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2088 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir;
2090 pmap_kenter_pde(kernel_vm_end, newpdir);
2091 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2092 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2093 kernel_vm_end = kernel_map->max_offset;
2100 /***************************************************
2101 * page management routines.
2102 ***************************************************/
2104 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2105 CTASSERT(_NPCM == 11);
2106 CTASSERT(_NPCPV == 336);
2108 static __inline struct pv_chunk *
2109 pv_to_chunk(pv_entry_t pv)
2112 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2115 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2117 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2118 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2120 static const uint32_t pc_freemask[_NPCM] = {
2121 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2122 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2123 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2124 PC_FREE0_9, PC_FREE10
2127 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2128 "Current number of pv entries");
2131 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2133 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2134 "Current number of pv entry chunks");
2135 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2136 "Current number of pv entry chunks allocated");
2137 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2138 "Current number of pv entry chunks frees");
2139 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2140 "Number of times tried to get a chunk page but failed.");
2142 static long pv_entry_frees, pv_entry_allocs;
2143 static int pv_entry_spare;
2145 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2146 "Current number of pv entry frees");
2147 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2148 "Current number of pv entry allocs");
2149 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2150 "Current number of spare pv entries");
2154 * We are in a serious low memory condition. Resort to
2155 * drastic measures to free some pages so we can allocate
2156 * another pv entry chunk.
2159 pmap_pv_reclaim(pmap_t locked_pmap)
2162 struct pv_chunk *pc;
2163 struct md_page *pvh;
2166 pt_entry_t *pte, tpte;
2170 struct spglist free;
2172 int bit, field, freed;
2174 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2178 TAILQ_INIT(&newtail);
2179 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2180 SLIST_EMPTY(&free))) {
2181 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2182 if (pmap != pc->pc_pmap) {
2184 pmap_invalidate_all(pmap);
2185 if (pmap != locked_pmap)
2189 /* Avoid deadlock and lock recursion. */
2190 if (pmap > locked_pmap)
2192 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2194 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2200 * Destroy every non-wired, 4 KB page mapping in the chunk.
2203 for (field = 0; field < _NPCM; field++) {
2204 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2205 inuse != 0; inuse &= ~(1UL << bit)) {
2207 pv = &pc->pc_pventry[field * 32 + bit];
2209 pde = pmap_pde(pmap, va);
2210 if ((*pde & PG_PS) != 0)
2212 pte = pmap_pte(pmap, va);
2214 if ((tpte & PG_W) == 0)
2215 tpte = pte_load_clear(pte);
2216 pmap_pte_release(pte);
2217 if ((tpte & PG_W) != 0)
2220 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2222 if ((tpte & PG_G) != 0)
2223 pmap_invalidate_page(pmap, va);
2224 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2225 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2227 if ((tpte & PG_A) != 0)
2228 vm_page_aflag_set(m, PGA_REFERENCED);
2229 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2230 if (TAILQ_EMPTY(&m->md.pv_list) &&
2231 (m->flags & PG_FICTITIOUS) == 0) {
2232 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2233 if (TAILQ_EMPTY(&pvh->pv_list)) {
2234 vm_page_aflag_clear(m,
2238 pc->pc_map[field] |= 1UL << bit;
2239 pmap_unuse_pt(pmap, va, &free);
2244 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2247 /* Every freed mapping is for a 4 KB page. */
2248 pmap->pm_stats.resident_count -= freed;
2249 PV_STAT(pv_entry_frees += freed);
2250 PV_STAT(pv_entry_spare += freed);
2251 pv_entry_count -= freed;
2252 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2253 for (field = 0; field < _NPCM; field++)
2254 if (pc->pc_map[field] != pc_freemask[field]) {
2255 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2257 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2260 * One freed pv entry in locked_pmap is
2263 if (pmap == locked_pmap)
2267 if (field == _NPCM) {
2268 PV_STAT(pv_entry_spare -= _NPCPV);
2269 PV_STAT(pc_chunk_count--);
2270 PV_STAT(pc_chunk_frees++);
2271 /* Entire chunk is free; return it. */
2272 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2273 pmap_qremove((vm_offset_t)pc, 1);
2274 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2279 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2281 pmap_invalidate_all(pmap);
2282 if (pmap != locked_pmap)
2285 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2286 m_pc = SLIST_FIRST(&free);
2287 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2288 /* Recycle a freed page table page. */
2289 m_pc->wire_count = 1;
2290 atomic_add_int(&vm_cnt.v_wire_count, 1);
2292 pmap_free_zero_pages(&free);
2297 * free the pv_entry back to the free list
2300 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2302 struct pv_chunk *pc;
2303 int idx, field, bit;
2305 rw_assert(&pvh_global_lock, RA_WLOCKED);
2306 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2307 PV_STAT(pv_entry_frees++);
2308 PV_STAT(pv_entry_spare++);
2310 pc = pv_to_chunk(pv);
2311 idx = pv - &pc->pc_pventry[0];
2314 pc->pc_map[field] |= 1ul << bit;
2315 for (idx = 0; idx < _NPCM; idx++)
2316 if (pc->pc_map[idx] != pc_freemask[idx]) {
2318 * 98% of the time, pc is already at the head of the
2319 * list. If it isn't already, move it to the head.
2321 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2323 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2324 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2329 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2334 free_pv_chunk(struct pv_chunk *pc)
2338 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2339 PV_STAT(pv_entry_spare -= _NPCPV);
2340 PV_STAT(pc_chunk_count--);
2341 PV_STAT(pc_chunk_frees++);
2342 /* entire chunk is free, return it */
2343 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2344 pmap_qremove((vm_offset_t)pc, 1);
2345 vm_page_unwire(m, PQ_NONE);
2347 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2351 * get a new pv_entry, allocating a block from the system
2355 get_pv_entry(pmap_t pmap, boolean_t try)
2357 static const struct timeval printinterval = { 60, 0 };
2358 static struct timeval lastprint;
2361 struct pv_chunk *pc;
2364 rw_assert(&pvh_global_lock, RA_WLOCKED);
2365 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2366 PV_STAT(pv_entry_allocs++);
2368 if (pv_entry_count > pv_entry_high_water)
2369 if (ratecheck(&lastprint, &printinterval))
2370 printf("Approaching the limit on PV entries, consider "
2371 "increasing either the vm.pmap.shpgperproc or the "
2372 "vm.pmap.pv_entry_max tunable.\n");
2374 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2376 for (field = 0; field < _NPCM; field++) {
2377 if (pc->pc_map[field]) {
2378 bit = bsfl(pc->pc_map[field]);
2382 if (field < _NPCM) {
2383 pv = &pc->pc_pventry[field * 32 + bit];
2384 pc->pc_map[field] &= ~(1ul << bit);
2385 /* If this was the last item, move it to tail */
2386 for (field = 0; field < _NPCM; field++)
2387 if (pc->pc_map[field] != 0) {
2388 PV_STAT(pv_entry_spare--);
2389 return (pv); /* not full, return */
2391 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2392 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2393 PV_STAT(pv_entry_spare--);
2398 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2399 * global lock. If "pv_vafree" is currently non-empty, it will
2400 * remain non-empty until pmap_ptelist_alloc() completes.
2402 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2403 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2406 PV_STAT(pc_chunk_tryfail++);
2409 m = pmap_pv_reclaim(pmap);
2413 PV_STAT(pc_chunk_count++);
2414 PV_STAT(pc_chunk_allocs++);
2415 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2416 pmap_qenter((vm_offset_t)pc, &m, 1);
2418 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2419 for (field = 1; field < _NPCM; field++)
2420 pc->pc_map[field] = pc_freemask[field];
2421 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2422 pv = &pc->pc_pventry[0];
2423 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2424 PV_STAT(pv_entry_spare += _NPCPV - 1);
2428 static __inline pv_entry_t
2429 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2433 rw_assert(&pvh_global_lock, RA_WLOCKED);
2434 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2435 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2436 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2444 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2446 struct md_page *pvh;
2448 vm_offset_t va_last;
2451 rw_assert(&pvh_global_lock, RA_WLOCKED);
2452 KASSERT((pa & PDRMASK) == 0,
2453 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2456 * Transfer the 4mpage's pv entry for this mapping to the first
2459 pvh = pa_to_pvh(pa);
2460 va = trunc_4mpage(va);
2461 pv = pmap_pvh_remove(pvh, pmap, va);
2462 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2463 m = PHYS_TO_VM_PAGE(pa);
2464 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2465 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2466 va_last = va + NBPDR - PAGE_SIZE;
2469 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2470 ("pmap_pv_demote_pde: page %p is not managed", m));
2472 pmap_insert_entry(pmap, va, m);
2473 } while (va < va_last);
2477 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2479 struct md_page *pvh;
2481 vm_offset_t va_last;
2484 rw_assert(&pvh_global_lock, RA_WLOCKED);
2485 KASSERT((pa & PDRMASK) == 0,
2486 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2489 * Transfer the first page's pv entry for this mapping to the
2490 * 4mpage's pv list. Aside from avoiding the cost of a call
2491 * to get_pv_entry(), a transfer avoids the possibility that
2492 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2493 * removes one of the mappings that is being promoted.
2495 m = PHYS_TO_VM_PAGE(pa);
2496 va = trunc_4mpage(va);
2497 pv = pmap_pvh_remove(&m->md, pmap, va);
2498 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2499 pvh = pa_to_pvh(pa);
2500 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2501 /* Free the remaining NPTEPG - 1 pv entries. */
2502 va_last = va + NBPDR - PAGE_SIZE;
2506 pmap_pvh_free(&m->md, pmap, va);
2507 } while (va < va_last);
2511 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2515 pv = pmap_pvh_remove(pvh, pmap, va);
2516 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2517 free_pv_entry(pmap, pv);
2521 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2523 struct md_page *pvh;
2525 rw_assert(&pvh_global_lock, RA_WLOCKED);
2526 pmap_pvh_free(&m->md, pmap, va);
2527 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2528 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2529 if (TAILQ_EMPTY(&pvh->pv_list))
2530 vm_page_aflag_clear(m, PGA_WRITEABLE);
2535 * Create a pv entry for page at pa for
2539 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2543 rw_assert(&pvh_global_lock, RA_WLOCKED);
2544 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2545 pv = get_pv_entry(pmap, FALSE);
2547 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2551 * Conditionally create a pv entry.
2554 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2558 rw_assert(&pvh_global_lock, RA_WLOCKED);
2559 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2560 if (pv_entry_count < pv_entry_high_water &&
2561 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2563 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2570 * Create the pv entries for each of the pages within a superpage.
2573 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2575 struct md_page *pvh;
2578 rw_assert(&pvh_global_lock, RA_WLOCKED);
2579 if (pv_entry_count < pv_entry_high_water &&
2580 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2582 pvh = pa_to_pvh(pa);
2583 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2590 * Fills a page table page with mappings to consecutive physical pages.
2593 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2597 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2599 newpte += PAGE_SIZE;
2604 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2605 * 2- or 4MB page mapping is invalidated.
2608 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2610 pd_entry_t newpde, oldpde;
2611 pt_entry_t *firstpte, newpte;
2614 struct spglist free;
2616 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2618 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2619 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2620 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
2622 KASSERT((oldpde & PG_W) == 0,
2623 ("pmap_demote_pde: page table page for a wired mapping"
2627 * Invalidate the 2- or 4MB page mapping and return
2628 * "failure" if the mapping was never accessed or the
2629 * allocation of the new page table page fails.
2631 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2632 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2633 VM_ALLOC_WIRED)) == NULL) {
2635 pmap_remove_pde(pmap, pde, trunc_4mpage(va), &free);
2636 pmap_invalidate_page(pmap, trunc_4mpage(va));
2637 pmap_free_zero_pages(&free);
2638 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2639 " in pmap %p", va, pmap);
2642 if (va < VM_MAXUSER_ADDRESS)
2643 pmap->pm_stats.resident_count++;
2645 mptepa = VM_PAGE_TO_PHYS(mpte);
2648 * If the page mapping is in the kernel's address space, then the
2649 * KPTmap can provide access to the page table page. Otherwise,
2650 * temporarily map the page table page (mpte) into the kernel's
2651 * address space at either PADDR1 or PADDR2.
2654 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2655 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2656 if ((*PMAP1 & PG_FRAME) != mptepa) {
2657 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2659 PMAP1cpu = PCPU_GET(cpuid);
2665 if (PMAP1cpu != PCPU_GET(cpuid)) {
2666 PMAP1cpu = PCPU_GET(cpuid);
2674 mtx_lock(&PMAP2mutex);
2675 if ((*PMAP2 & PG_FRAME) != mptepa) {
2676 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2677 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2681 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2682 KASSERT((oldpde & PG_A) != 0,
2683 ("pmap_demote_pde: oldpde is missing PG_A"));
2684 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2685 ("pmap_demote_pde: oldpde is missing PG_M"));
2686 newpte = oldpde & ~PG_PS;
2687 if ((newpte & PG_PDE_PAT) != 0)
2688 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2691 * If the page table page is new, initialize it.
2693 if (mpte->wire_count == 1) {
2694 mpte->wire_count = NPTEPG;
2695 pmap_fill_ptp(firstpte, newpte);
2697 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2698 ("pmap_demote_pde: firstpte and newpte map different physical"
2702 * If the mapping has changed attributes, update the page table
2705 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2706 pmap_fill_ptp(firstpte, newpte);
2709 * Demote the mapping. This pmap is locked. The old PDE has
2710 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2711 * set. Thus, there is no danger of a race with another
2712 * processor changing the setting of PG_A and/or PG_M between
2713 * the read above and the store below.
2715 if (workaround_erratum383)
2716 pmap_update_pde(pmap, va, pde, newpde);
2717 else if (pmap == kernel_pmap)
2718 pmap_kenter_pde(va, newpde);
2720 pde_store(pde, newpde);
2721 if (firstpte == PADDR2)
2722 mtx_unlock(&PMAP2mutex);
2725 * Invalidate the recursive mapping of the page table page.
2727 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2730 * Demote the pv entry. This depends on the earlier demotion
2731 * of the mapping. Specifically, the (re)creation of a per-
2732 * page pv entry might trigger the execution of pmap_collect(),
2733 * which might reclaim a newly (re)created per-page pv entry
2734 * and destroy the associated mapping. In order to destroy
2735 * the mapping, the PDE must have already changed from mapping
2736 * the 2mpage to referencing the page table page.
2738 if ((oldpde & PG_MANAGED) != 0)
2739 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2741 pmap_pde_demotions++;
2742 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2743 " in pmap %p", va, pmap);
2748 * Removes a 2- or 4MB page mapping from the kernel pmap.
2751 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2757 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2758 mpte = pmap_remove_pt_page(pmap, va);
2760 panic("pmap_remove_kernel_pde: Missing pt page.");
2762 mptepa = VM_PAGE_TO_PHYS(mpte);
2763 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2766 * Initialize the page table page.
2768 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2771 * Remove the mapping.
2773 if (workaround_erratum383)
2774 pmap_update_pde(pmap, va, pde, newpde);
2776 pmap_kenter_pde(va, newpde);
2779 * Invalidate the recursive mapping of the page table page.
2781 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2785 * pmap_remove_pde: do the things to unmap a superpage in a process
2788 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2789 struct spglist *free)
2791 struct md_page *pvh;
2793 vm_offset_t eva, va;
2796 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2797 KASSERT((sva & PDRMASK) == 0,
2798 ("pmap_remove_pde: sva is not 4mpage aligned"));
2799 oldpde = pte_load_clear(pdq);
2801 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2804 * Machines that don't support invlpg, also don't support
2808 pmap_invalidate_page(kernel_pmap, sva);
2809 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2810 if (oldpde & PG_MANAGED) {
2811 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2812 pmap_pvh_free(pvh, pmap, sva);
2814 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2815 va < eva; va += PAGE_SIZE, m++) {
2816 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2819 vm_page_aflag_set(m, PGA_REFERENCED);
2820 if (TAILQ_EMPTY(&m->md.pv_list) &&
2821 TAILQ_EMPTY(&pvh->pv_list))
2822 vm_page_aflag_clear(m, PGA_WRITEABLE);
2825 if (pmap == kernel_pmap) {
2826 pmap_remove_kernel_pde(pmap, pdq, sva);
2828 mpte = pmap_remove_pt_page(pmap, sva);
2830 pmap->pm_stats.resident_count--;
2831 KASSERT(mpte->wire_count == NPTEPG,
2832 ("pmap_remove_pde: pte page wire count error"));
2833 mpte->wire_count = 0;
2834 pmap_add_delayed_free_list(mpte, free, FALSE);
2835 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2841 * pmap_remove_pte: do the things to unmap a page in a process
2844 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
2845 struct spglist *free)
2850 rw_assert(&pvh_global_lock, RA_WLOCKED);
2851 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2852 oldpte = pte_load_clear(ptq);
2853 KASSERT(oldpte != 0,
2854 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
2856 pmap->pm_stats.wired_count -= 1;
2858 * Machines that don't support invlpg, also don't support
2862 pmap_invalidate_page(kernel_pmap, va);
2863 pmap->pm_stats.resident_count -= 1;
2864 if (oldpte & PG_MANAGED) {
2865 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2866 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2869 vm_page_aflag_set(m, PGA_REFERENCED);
2870 pmap_remove_entry(pmap, m, va);
2872 return (pmap_unuse_pt(pmap, va, free));
2876 * Remove a single page from a process address space
2879 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
2883 rw_assert(&pvh_global_lock, RA_WLOCKED);
2884 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
2885 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2886 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
2888 pmap_remove_pte(pmap, pte, va, free);
2889 pmap_invalidate_page(pmap, va);
2893 * Remove the given range of addresses from the specified map.
2895 * It is assumed that the start and end are properly
2896 * rounded to the page size.
2899 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2904 struct spglist free;
2908 * Perform an unsynchronized read. This is, however, safe.
2910 if (pmap->pm_stats.resident_count == 0)
2916 rw_wlock(&pvh_global_lock);
2921 * special handling of removing one page. a very
2922 * common operation and easy to short circuit some
2925 if ((sva + PAGE_SIZE == eva) &&
2926 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
2927 pmap_remove_page(pmap, sva, &free);
2931 for (; sva < eva; sva = pdnxt) {
2935 * Calculate index for next page table.
2937 pdnxt = (sva + NBPDR) & ~PDRMASK;
2940 if (pmap->pm_stats.resident_count == 0)
2943 pdirindex = sva >> PDRSHIFT;
2944 ptpaddr = pmap->pm_pdir[pdirindex];
2947 * Weed out invalid mappings. Note: we assume that the page
2948 * directory table is always allocated, and in kernel virtual.
2954 * Check for large page.
2956 if ((ptpaddr & PG_PS) != 0) {
2958 * Are we removing the entire large page? If not,
2959 * demote the mapping and fall through.
2961 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
2963 * The TLB entry for a PG_G mapping is
2964 * invalidated by pmap_remove_pde().
2966 if ((ptpaddr & PG_G) == 0)
2968 pmap_remove_pde(pmap,
2969 &pmap->pm_pdir[pdirindex], sva, &free);
2971 } else if (!pmap_demote_pde(pmap,
2972 &pmap->pm_pdir[pdirindex], sva)) {
2973 /* The large page mapping was destroyed. */
2979 * Limit our scan to either the end of the va represented
2980 * by the current page table page, or to the end of the
2981 * range being removed.
2986 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
2992 * The TLB entry for a PG_G mapping is invalidated
2993 * by pmap_remove_pte().
2995 if ((*pte & PG_G) == 0)
2997 if (pmap_remove_pte(pmap, pte, sva, &free))
3004 pmap_invalidate_all(pmap);
3005 rw_wunlock(&pvh_global_lock);
3007 pmap_free_zero_pages(&free);
3011 * Routine: pmap_remove_all
3013 * Removes this physical page from
3014 * all physical maps in which it resides.
3015 * Reflects back modify bits to the pager.
3018 * Original versions of this routine were very
3019 * inefficient because they iteratively called
3020 * pmap_remove (slow...)
3024 pmap_remove_all(vm_page_t m)
3026 struct md_page *pvh;
3029 pt_entry_t *pte, tpte;
3032 struct spglist free;
3034 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3035 ("pmap_remove_all: page %p is not managed", m));
3037 rw_wlock(&pvh_global_lock);
3039 if ((m->flags & PG_FICTITIOUS) != 0)
3040 goto small_mappings;
3041 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3042 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3046 pde = pmap_pde(pmap, va);
3047 (void)pmap_demote_pde(pmap, pde, va);
3051 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3054 pmap->pm_stats.resident_count--;
3055 pde = pmap_pde(pmap, pv->pv_va);
3056 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3057 " a 4mpage in page %p's pv list", m));
3058 pte = pmap_pte_quick(pmap, pv->pv_va);
3059 tpte = pte_load_clear(pte);
3060 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3063 pmap->pm_stats.wired_count--;
3065 vm_page_aflag_set(m, PGA_REFERENCED);
3068 * Update the vm_page_t clean and reference bits.
3070 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3072 pmap_unuse_pt(pmap, pv->pv_va, &free);
3073 pmap_invalidate_page(pmap, pv->pv_va);
3074 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3075 free_pv_entry(pmap, pv);
3078 vm_page_aflag_clear(m, PGA_WRITEABLE);
3080 rw_wunlock(&pvh_global_lock);
3081 pmap_free_zero_pages(&free);
3085 * pmap_protect_pde: do the things to protect a 4mpage in a process
3088 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3090 pd_entry_t newpde, oldpde;
3091 vm_offset_t eva, va;
3093 boolean_t anychanged;
3095 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3096 KASSERT((sva & PDRMASK) == 0,
3097 ("pmap_protect_pde: sva is not 4mpage aligned"));
3100 oldpde = newpde = *pde;
3101 if (oldpde & PG_MANAGED) {
3103 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3104 va < eva; va += PAGE_SIZE, m++)
3105 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3108 if ((prot & VM_PROT_WRITE) == 0)
3109 newpde &= ~(PG_RW | PG_M);
3110 #if defined(PAE) || defined(PAE_TABLES)
3111 if ((prot & VM_PROT_EXECUTE) == 0)
3114 if (newpde != oldpde) {
3115 if (!pde_cmpset(pde, oldpde, newpde))
3118 pmap_invalidate_page(pmap, sva);
3122 return (anychanged);
3126 * Set the physical protection on the
3127 * specified range of this map as requested.
3130 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3135 boolean_t anychanged, pv_lists_locked;
3137 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3138 if (prot == VM_PROT_NONE) {
3139 pmap_remove(pmap, sva, eva);
3143 #if defined(PAE) || defined(PAE_TABLES)
3144 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3145 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3148 if (prot & VM_PROT_WRITE)
3152 if (pmap_is_current(pmap))
3153 pv_lists_locked = FALSE;
3155 pv_lists_locked = TRUE;
3157 rw_wlock(&pvh_global_lock);
3163 for (; sva < eva; sva = pdnxt) {
3164 pt_entry_t obits, pbits;
3167 pdnxt = (sva + NBPDR) & ~PDRMASK;
3171 pdirindex = sva >> PDRSHIFT;
3172 ptpaddr = pmap->pm_pdir[pdirindex];
3175 * Weed out invalid mappings. Note: we assume that the page
3176 * directory table is always allocated, and in kernel virtual.
3182 * Check for large page.
3184 if ((ptpaddr & PG_PS) != 0) {
3186 * Are we protecting the entire large page? If not,
3187 * demote the mapping and fall through.
3189 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3191 * The TLB entry for a PG_G mapping is
3192 * invalidated by pmap_protect_pde().
3194 if (pmap_protect_pde(pmap,
3195 &pmap->pm_pdir[pdirindex], sva, prot))
3199 if (!pv_lists_locked) {
3200 pv_lists_locked = TRUE;
3201 if (!rw_try_wlock(&pvh_global_lock)) {
3203 pmap_invalidate_all(
3210 if (!pmap_demote_pde(pmap,
3211 &pmap->pm_pdir[pdirindex], sva)) {
3213 * The large page mapping was
3224 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3230 * Regardless of whether a pte is 32 or 64 bits in
3231 * size, PG_RW, PG_A, and PG_M are among the least
3232 * significant 32 bits.
3234 obits = pbits = *pte;
3235 if ((pbits & PG_V) == 0)
3238 if ((prot & VM_PROT_WRITE) == 0) {
3239 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3240 (PG_MANAGED | PG_M | PG_RW)) {
3241 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3244 pbits &= ~(PG_RW | PG_M);
3246 #if defined(PAE) || defined(PAE_TABLES)
3247 if ((prot & VM_PROT_EXECUTE) == 0)
3251 if (pbits != obits) {
3252 #if defined(PAE) || defined(PAE_TABLES)
3253 if (!atomic_cmpset_64(pte, obits, pbits))
3256 if (!atomic_cmpset_int((u_int *)pte, obits,
3261 pmap_invalidate_page(pmap, sva);
3268 pmap_invalidate_all(pmap);
3269 if (pv_lists_locked) {
3271 rw_wunlock(&pvh_global_lock);
3277 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3278 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3279 * For promotion to occur, two conditions must be met: (1) the 4KB page
3280 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3281 * mappings must have identical characteristics.
3283 * Managed (PG_MANAGED) mappings within the kernel address space are not
3284 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3285 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3289 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3292 pt_entry_t *firstpte, oldpte, pa, *pte;
3293 vm_offset_t oldpteva;
3296 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3299 * Examine the first PTE in the specified PTP. Abort if this PTE is
3300 * either invalid, unused, or does not map the first 4KB physical page
3301 * within a 2- or 4MB page.
3303 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3306 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3307 pmap_pde_p_failures++;
3308 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3309 " in pmap %p", va, pmap);
3312 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3313 pmap_pde_p_failures++;
3314 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3315 " in pmap %p", va, pmap);
3318 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3320 * When PG_M is already clear, PG_RW can be cleared without
3321 * a TLB invalidation.
3323 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3330 * Examine each of the other PTEs in the specified PTP. Abort if this
3331 * PTE maps an unexpected 4KB physical page or does not have identical
3332 * characteristics to the first PTE.
3334 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3335 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3338 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3339 pmap_pde_p_failures++;
3340 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3341 " in pmap %p", va, pmap);
3344 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3346 * When PG_M is already clear, PG_RW can be cleared
3347 * without a TLB invalidation.
3349 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3353 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3355 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3356 " in pmap %p", oldpteva, pmap);
3358 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3359 pmap_pde_p_failures++;
3360 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3361 " in pmap %p", va, pmap);
3368 * Save the page table page in its current state until the PDE
3369 * mapping the superpage is demoted by pmap_demote_pde() or
3370 * destroyed by pmap_remove_pde().
3372 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3373 KASSERT(mpte >= vm_page_array &&
3374 mpte < &vm_page_array[vm_page_array_size],
3375 ("pmap_promote_pde: page table page is out of range"));
3376 KASSERT(mpte->pindex == va >> PDRSHIFT,
3377 ("pmap_promote_pde: page table page's pindex is wrong"));
3378 if (pmap_insert_pt_page(pmap, mpte)) {
3379 pmap_pde_p_failures++;
3381 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3387 * Promote the pv entries.
3389 if ((newpde & PG_MANAGED) != 0)
3390 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3393 * Propagate the PAT index to its proper position.
3395 if ((newpde & PG_PTE_PAT) != 0)
3396 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3399 * Map the superpage.
3401 if (workaround_erratum383)
3402 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3403 else if (pmap == kernel_pmap)
3404 pmap_kenter_pde(va, PG_PS | newpde);
3406 pde_store(pde, PG_PS | newpde);
3408 pmap_pde_promotions++;
3409 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3410 " in pmap %p", va, pmap);
3414 * Insert the given physical page (p) at
3415 * the specified virtual address (v) in the
3416 * target physical map with the protection requested.
3418 * If specified, the page will be wired down, meaning
3419 * that the related pte can not be reclaimed.
3421 * NB: This is the only routine which MAY NOT lazy-evaluate
3422 * or lose information. That is, this routine must actually
3423 * insert this page into the given map NOW.
3426 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3427 u_int flags, int8_t psind)
3431 pt_entry_t newpte, origpte;
3435 boolean_t invlva, wired;
3437 va = trunc_page(va);
3439 wired = (flags & PMAP_ENTER_WIRED) != 0;
3441 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
3442 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
3443 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)",
3445 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3446 VM_OBJECT_ASSERT_LOCKED(m->object);
3448 rw_wlock(&pvh_global_lock);
3452 pde = pmap_pde(pmap, va);
3453 if (va < VM_MAXUSER_ADDRESS) {
3456 * In the case that a page table page is not resident,
3457 * we are creating it here. pmap_allocpte() handles
3460 mpte = pmap_allocpte(pmap, va, flags);
3462 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3463 ("pmap_allocpte failed with sleep allowed"));
3465 rw_wunlock(&pvh_global_lock);
3467 return (KERN_RESOURCE_SHORTAGE);
3471 * va is for KVA, so pmap_demote_pde() will never fail
3472 * to install a page table page. PG_V is also
3473 * asserted by pmap_demote_pde().
3475 KASSERT(pde != NULL && (*pde & PG_V) != 0,
3476 ("KVA %#x invalid pde pdir %#jx", va,
3477 (uintmax_t)pmap->pm_pdir[PTDPTDI]));
3478 if ((*pde & PG_PS) != 0)
3479 pmap_demote_pde(pmap, pde, va);
3481 pte = pmap_pte_quick(pmap, va);
3484 * Page Directory table entry is not valid, which should not
3485 * happen. We should have either allocated the page table
3486 * page or demoted the existing mapping above.
3489 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3490 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3493 pa = VM_PAGE_TO_PHYS(m);
3496 opa = origpte & PG_FRAME;
3499 * Mapping has not changed, must be protection or wiring change.
3501 if (origpte && (opa == pa)) {
3503 * Wiring change, just update stats. We don't worry about
3504 * wiring PT pages as they remain resident as long as there
3505 * are valid mappings in them. Hence, if a user page is wired,
3506 * the PT page will be also.
3508 if (wired && ((origpte & PG_W) == 0))
3509 pmap->pm_stats.wired_count++;
3510 else if (!wired && (origpte & PG_W))
3511 pmap->pm_stats.wired_count--;
3514 * Remove extra pte reference
3519 if (origpte & PG_MANAGED) {
3529 * Mapping has changed, invalidate old range and fall through to
3530 * handle validating new mapping.
3534 pmap->pm_stats.wired_count--;
3535 if (origpte & PG_MANAGED) {
3536 om = PHYS_TO_VM_PAGE(opa);
3537 pv = pmap_pvh_remove(&om->md, pmap, va);
3541 KASSERT(mpte->wire_count > 0,
3542 ("pmap_enter: missing reference to page table page,"
3546 pmap->pm_stats.resident_count++;
3549 * Enter on the PV list if part of our managed memory.
3551 if ((m->oflags & VPO_UNMANAGED) == 0) {
3552 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3553 ("pmap_enter: managed mapping within the clean submap"));
3555 pv = get_pv_entry(pmap, FALSE);
3557 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3559 } else if (pv != NULL)
3560 free_pv_entry(pmap, pv);
3563 * Increment counters
3566 pmap->pm_stats.wired_count++;
3570 * Now validate mapping with desired protection/wiring.
3572 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V);
3573 if ((prot & VM_PROT_WRITE) != 0) {
3575 if ((newpte & PG_MANAGED) != 0)
3576 vm_page_aflag_set(m, PGA_WRITEABLE);
3578 #if defined(PAE) || defined(PAE_TABLES)
3579 if ((prot & VM_PROT_EXECUTE) == 0)
3584 if (va < VM_MAXUSER_ADDRESS)
3586 if (pmap == kernel_pmap)
3590 * if the mapping or permission bits are different, we need
3591 * to update the pte.
3593 if ((origpte & ~(PG_M|PG_A)) != newpte) {
3595 if ((flags & VM_PROT_WRITE) != 0)
3597 if (origpte & PG_V) {
3599 origpte = pte_load_store(pte, newpte);
3600 if (origpte & PG_A) {
3601 if (origpte & PG_MANAGED)
3602 vm_page_aflag_set(om, PGA_REFERENCED);
3603 if (opa != VM_PAGE_TO_PHYS(m))
3605 #if defined(PAE) || defined(PAE_TABLES)
3606 if ((origpte & PG_NX) == 0 &&
3607 (newpte & PG_NX) != 0)
3611 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
3612 if ((origpte & PG_MANAGED) != 0)
3614 if ((prot & VM_PROT_WRITE) == 0)
3617 if ((origpte & PG_MANAGED) != 0 &&
3618 TAILQ_EMPTY(&om->md.pv_list) &&
3619 ((om->flags & PG_FICTITIOUS) != 0 ||
3620 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3621 vm_page_aflag_clear(om, PGA_WRITEABLE);
3623 pmap_invalidate_page(pmap, va);
3625 pte_store(pte, newpte);
3629 * If both the page table page and the reservation are fully
3630 * populated, then attempt promotion.
3632 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3633 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3634 vm_reserv_level_iffullpop(m) == 0)
3635 pmap_promote_pde(pmap, pde, va);
3638 rw_wunlock(&pvh_global_lock);
3640 return (KERN_SUCCESS);
3644 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and
3645 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
3646 * blocking, (2) a mapping already exists at the specified virtual address, or
3647 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3650 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3652 pd_entry_t *pde, newpde;
3654 rw_assert(&pvh_global_lock, RA_WLOCKED);
3655 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3656 pde = pmap_pde(pmap, va);
3658 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3659 " in pmap %p", va, pmap);
3662 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3664 if ((m->oflags & VPO_UNMANAGED) == 0) {
3665 newpde |= PG_MANAGED;
3668 * Abort this mapping if its PV entry could not be created.
3670 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) {
3671 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3672 " in pmap %p", va, pmap);
3676 #if defined(PAE) || defined(PAE_TABLES)
3677 if ((prot & VM_PROT_EXECUTE) == 0)
3680 if (va < VM_MAXUSER_ADDRESS)
3684 * Increment counters.
3686 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3689 * Map the superpage.
3691 pde_store(pde, newpde);
3693 pmap_pde_mappings++;
3694 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3695 " in pmap %p", va, pmap);
3700 * Maps a sequence of resident pages belonging to the same object.
3701 * The sequence begins with the given page m_start. This page is
3702 * mapped at the given virtual address start. Each subsequent page is
3703 * mapped at a virtual address that is offset from start by the same
3704 * amount as the page is offset from m_start within the object. The
3705 * last page in the sequence is the page with the largest offset from
3706 * m_start that can be mapped at a virtual address less than the given
3707 * virtual address end. Not every virtual page between start and end
3708 * is mapped; only those for which a resident page exists with the
3709 * corresponding offset from m_start are mapped.
3712 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3713 vm_page_t m_start, vm_prot_t prot)
3717 vm_pindex_t diff, psize;
3719 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3721 psize = atop(end - start);
3724 rw_wlock(&pvh_global_lock);
3726 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3727 va = start + ptoa(diff);
3728 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3729 m->psind == 1 && pg_ps_enabled &&
3730 pmap_enter_pde(pmap, va, m, prot))
3731 m = &m[NBPDR / PAGE_SIZE - 1];
3733 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3735 m = TAILQ_NEXT(m, listq);
3737 rw_wunlock(&pvh_global_lock);
3742 * this code makes some *MAJOR* assumptions:
3743 * 1. Current pmap & pmap exists.
3746 * 4. No page table pages.
3747 * but is *MUCH* faster than pmap_enter...
3751 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3754 rw_wlock(&pvh_global_lock);
3756 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
3757 rw_wunlock(&pvh_global_lock);
3762 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3763 vm_prot_t prot, vm_page_t mpte)
3767 struct spglist free;
3769 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3770 (m->oflags & VPO_UNMANAGED) != 0,
3771 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3772 rw_assert(&pvh_global_lock, RA_WLOCKED);
3773 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3776 * In the case that a page table page is not
3777 * resident, we are creating it here.
3779 if (va < VM_MAXUSER_ADDRESS) {
3784 * Calculate pagetable page index
3786 ptepindex = va >> PDRSHIFT;
3787 if (mpte && (mpte->pindex == ptepindex)) {
3791 * Get the page directory entry
3793 ptepa = pmap->pm_pdir[ptepindex];
3796 * If the page table page is mapped, we just increment
3797 * the hold count, and activate it.
3802 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
3805 mpte = _pmap_allocpte(pmap, ptepindex,
3806 PMAP_ENTER_NOSLEEP);
3816 * This call to vtopte makes the assumption that we are
3817 * entering the page into the current pmap. In order to support
3818 * quick entry into any pmap, one would likely use pmap_pte_quick.
3819 * But that isn't as quick as vtopte.
3831 * Enter on the PV list if part of our managed memory.
3833 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3834 !pmap_try_insert_pv_entry(pmap, va, m)) {
3837 if (pmap_unwire_ptp(pmap, mpte, &free)) {
3838 pmap_invalidate_page(pmap, va);
3839 pmap_free_zero_pages(&free);
3848 * Increment counters
3850 pmap->pm_stats.resident_count++;
3852 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3853 #if defined(PAE) || defined(PAE_TABLES)
3854 if ((prot & VM_PROT_EXECUTE) == 0)
3859 * Now validate mapping with RO protection
3861 if ((m->oflags & VPO_UNMANAGED) != 0)
3862 pte_store(pte, pa | PG_V | PG_U);
3864 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3869 * Make a temporary mapping for a physical address. This is only intended
3870 * to be used for panic dumps.
3873 pmap_kenter_temporary(vm_paddr_t pa, int i)
3877 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3878 pmap_kenter(va, pa);
3880 return ((void *)crashdumpmap);
3884 * This code maps large physical mmap regions into the
3885 * processor address space. Note that some shortcuts
3886 * are taken, but the code works.
3889 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3890 vm_pindex_t pindex, vm_size_t size)
3893 vm_paddr_t pa, ptepa;
3897 VM_OBJECT_ASSERT_WLOCKED(object);
3898 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3899 ("pmap_object_init_pt: non-device object"));
3901 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3902 if (!vm_object_populate(object, pindex, pindex + atop(size)))
3904 p = vm_page_lookup(object, pindex);
3905 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3906 ("pmap_object_init_pt: invalid page %p", p));
3907 pat_mode = p->md.pat_mode;
3910 * Abort the mapping if the first page is not physically
3911 * aligned to a 2/4MB page boundary.
3913 ptepa = VM_PAGE_TO_PHYS(p);
3914 if (ptepa & (NBPDR - 1))
3918 * Skip the first page. Abort the mapping if the rest of
3919 * the pages are not physically contiguous or have differing
3920 * memory attributes.
3922 p = TAILQ_NEXT(p, listq);
3923 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
3925 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3926 ("pmap_object_init_pt: invalid page %p", p));
3927 if (pa != VM_PAGE_TO_PHYS(p) ||
3928 pat_mode != p->md.pat_mode)
3930 p = TAILQ_NEXT(p, listq);
3934 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
3935 * "size" is a multiple of 2/4M, adding the PAT setting to
3936 * "pa" will not affect the termination of this loop.
3939 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
3940 size; pa += NBPDR) {
3941 pde = pmap_pde(pmap, addr);
3943 pde_store(pde, pa | PG_PS | PG_M | PG_A |
3944 PG_U | PG_RW | PG_V);
3945 pmap->pm_stats.resident_count += NBPDR /
3947 pmap_pde_mappings++;
3949 /* Else continue on if the PDE is already valid. */
3957 * Clear the wired attribute from the mappings for the specified range of
3958 * addresses in the given pmap. Every valid mapping within that range
3959 * must have the wired attribute set. In contrast, invalid mappings
3960 * cannot have the wired attribute set, so they are ignored.
3962 * The wired attribute of the page table entry is not a hardware feature,
3963 * so there is no need to invalidate any TLB entries.
3966 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3971 boolean_t pv_lists_locked;
3973 if (pmap_is_current(pmap))
3974 pv_lists_locked = FALSE;
3976 pv_lists_locked = TRUE;
3978 rw_wlock(&pvh_global_lock);
3982 for (; sva < eva; sva = pdnxt) {
3983 pdnxt = (sva + NBPDR) & ~PDRMASK;
3986 pde = pmap_pde(pmap, sva);
3987 if ((*pde & PG_V) == 0)
3989 if ((*pde & PG_PS) != 0) {
3990 if ((*pde & PG_W) == 0)
3991 panic("pmap_unwire: pde %#jx is missing PG_W",
3995 * Are we unwiring the entire large page? If not,
3996 * demote the mapping and fall through.
3998 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4000 * Regardless of whether a pde (or pte) is 32
4001 * or 64 bits in size, PG_W is among the least
4002 * significant 32 bits.
4004 atomic_clear_int((u_int *)pde, PG_W);
4005 pmap->pm_stats.wired_count -= NBPDR /
4009 if (!pv_lists_locked) {
4010 pv_lists_locked = TRUE;
4011 if (!rw_try_wlock(&pvh_global_lock)) {
4018 if (!pmap_demote_pde(pmap, pde, sva))
4019 panic("pmap_unwire: demotion failed");
4024 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4026 if ((*pte & PG_V) == 0)
4028 if ((*pte & PG_W) == 0)
4029 panic("pmap_unwire: pte %#jx is missing PG_W",
4033 * PG_W must be cleared atomically. Although the pmap
4034 * lock synchronizes access to PG_W, another processor
4035 * could be setting PG_M and/or PG_A concurrently.
4037 * PG_W is among the least significant 32 bits.
4039 atomic_clear_int((u_int *)pte, PG_W);
4040 pmap->pm_stats.wired_count--;
4043 if (pv_lists_locked) {
4045 rw_wunlock(&pvh_global_lock);
4052 * Copy the range specified by src_addr/len
4053 * from the source map to the range dst_addr/len
4054 * in the destination map.
4056 * This routine is only advisory and need not do anything.
4060 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4061 vm_offset_t src_addr)
4063 struct spglist free;
4065 vm_offset_t end_addr = src_addr + len;
4068 if (dst_addr != src_addr)
4071 if (!pmap_is_current(src_pmap))
4074 rw_wlock(&pvh_global_lock);
4075 if (dst_pmap < src_pmap) {
4076 PMAP_LOCK(dst_pmap);
4077 PMAP_LOCK(src_pmap);
4079 PMAP_LOCK(src_pmap);
4080 PMAP_LOCK(dst_pmap);
4083 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4084 pt_entry_t *src_pte, *dst_pte;
4085 vm_page_t dstmpte, srcmpte;
4086 pd_entry_t srcptepaddr;
4089 KASSERT(addr < UPT_MIN_ADDRESS,
4090 ("pmap_copy: invalid to pmap_copy page tables"));
4092 pdnxt = (addr + NBPDR) & ~PDRMASK;
4095 ptepindex = addr >> PDRSHIFT;
4097 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4098 if (srcptepaddr == 0)
4101 if (srcptepaddr & PG_PS) {
4102 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4104 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4105 ((srcptepaddr & PG_MANAGED) == 0 ||
4106 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4108 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4110 dst_pmap->pm_stats.resident_count +=
4112 pmap_pde_mappings++;
4117 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4118 KASSERT(srcmpte->wire_count > 0,
4119 ("pmap_copy: source page table page is unused"));
4121 if (pdnxt > end_addr)
4124 src_pte = vtopte(addr);
4125 while (addr < pdnxt) {
4129 * we only virtual copy managed pages
4131 if ((ptetemp & PG_MANAGED) != 0) {
4132 dstmpte = pmap_allocpte(dst_pmap, addr,
4133 PMAP_ENTER_NOSLEEP);
4134 if (dstmpte == NULL)
4136 dst_pte = pmap_pte_quick(dst_pmap, addr);
4137 if (*dst_pte == 0 &&
4138 pmap_try_insert_pv_entry(dst_pmap, addr,
4139 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4141 * Clear the wired, modified, and
4142 * accessed (referenced) bits
4145 *dst_pte = ptetemp & ~(PG_W | PG_M |
4147 dst_pmap->pm_stats.resident_count++;
4150 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4152 pmap_invalidate_page(dst_pmap,
4154 pmap_free_zero_pages(&free);
4158 if (dstmpte->wire_count >= srcmpte->wire_count)
4167 rw_wunlock(&pvh_global_lock);
4168 PMAP_UNLOCK(src_pmap);
4169 PMAP_UNLOCK(dst_pmap);
4173 * Zero 1 page of virtual memory mapped from a hardware page by the caller.
4175 static __inline void
4176 pagezero(void *page)
4178 #if defined(I686_CPU)
4179 if (cpu_class == CPUCLASS_686) {
4180 #if defined(CPU_ENABLE_SSE)
4181 if (cpu_feature & CPUID_SSE2)
4182 sse2_pagezero(page);
4185 i686_pagezero(page);
4188 bzero(page, PAGE_SIZE);
4192 * Zero the specified hardware page.
4195 pmap_zero_page(vm_page_t m)
4197 struct sysmaps *sysmaps;
4199 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4200 mtx_lock(&sysmaps->lock);
4201 if (*sysmaps->CMAP2)
4202 panic("pmap_zero_page: CMAP2 busy");
4204 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4205 pmap_cache_bits(m->md.pat_mode, 0);
4206 invlcaddr(sysmaps->CADDR2);
4207 pagezero(sysmaps->CADDR2);
4208 *sysmaps->CMAP2 = 0;
4210 mtx_unlock(&sysmaps->lock);
4214 * Zero an an area within a single hardware page. off and size must not
4215 * cover an area beyond a single hardware page.
4218 pmap_zero_page_area(vm_page_t m, int off, int size)
4220 struct sysmaps *sysmaps;
4222 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4223 mtx_lock(&sysmaps->lock);
4224 if (*sysmaps->CMAP2)
4225 panic("pmap_zero_page_area: CMAP2 busy");
4227 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4228 pmap_cache_bits(m->md.pat_mode, 0);
4229 invlcaddr(sysmaps->CADDR2);
4230 if (off == 0 && size == PAGE_SIZE)
4231 pagezero(sysmaps->CADDR2);
4233 bzero((char *)sysmaps->CADDR2 + off, size);
4234 *sysmaps->CMAP2 = 0;
4236 mtx_unlock(&sysmaps->lock);
4240 * Copy 1 specified hardware page to another.
4243 pmap_copy_page(vm_page_t src, vm_page_t dst)
4245 struct sysmaps *sysmaps;
4247 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4248 mtx_lock(&sysmaps->lock);
4249 if (*sysmaps->CMAP1)
4250 panic("pmap_copy_page: CMAP1 busy");
4251 if (*sysmaps->CMAP2)
4252 panic("pmap_copy_page: CMAP2 busy");
4254 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4255 pmap_cache_bits(src->md.pat_mode, 0);
4256 invlcaddr(sysmaps->CADDR1);
4257 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4258 pmap_cache_bits(dst->md.pat_mode, 0);
4259 invlcaddr(sysmaps->CADDR2);
4260 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE);
4261 *sysmaps->CMAP1 = 0;
4262 *sysmaps->CMAP2 = 0;
4264 mtx_unlock(&sysmaps->lock);
4267 int unmapped_buf_allowed = 1;
4270 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4271 vm_offset_t b_offset, int xfersize)
4273 struct sysmaps *sysmaps;
4274 vm_page_t a_pg, b_pg;
4276 vm_offset_t a_pg_offset, b_pg_offset;
4279 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4280 mtx_lock(&sysmaps->lock);
4281 if (*sysmaps->CMAP1 != 0)
4282 panic("pmap_copy_pages: CMAP1 busy");
4283 if (*sysmaps->CMAP2 != 0)
4284 panic("pmap_copy_pages: CMAP2 busy");
4286 while (xfersize > 0) {
4287 a_pg = ma[a_offset >> PAGE_SHIFT];
4288 a_pg_offset = a_offset & PAGE_MASK;
4289 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4290 b_pg = mb[b_offset >> PAGE_SHIFT];
4291 b_pg_offset = b_offset & PAGE_MASK;
4292 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4293 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4294 pmap_cache_bits(a_pg->md.pat_mode, 0);
4295 invlcaddr(sysmaps->CADDR1);
4296 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4297 PG_M | pmap_cache_bits(b_pg->md.pat_mode, 0);
4298 invlcaddr(sysmaps->CADDR2);
4299 a_cp = sysmaps->CADDR1 + a_pg_offset;
4300 b_cp = sysmaps->CADDR2 + b_pg_offset;
4301 bcopy(a_cp, b_cp, cnt);
4306 *sysmaps->CMAP1 = 0;
4307 *sysmaps->CMAP2 = 0;
4309 mtx_unlock(&sysmaps->lock);
4313 * Returns true if the pmap's pv is one of the first
4314 * 16 pvs linked to from this page. This count may
4315 * be changed upwards or downwards in the future; it
4316 * is only necessary that true be returned for a small
4317 * subset of pmaps for proper page aging.
4320 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4322 struct md_page *pvh;
4327 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4328 ("pmap_page_exists_quick: page %p is not managed", m));
4330 rw_wlock(&pvh_global_lock);
4331 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4332 if (PV_PMAP(pv) == pmap) {
4340 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4341 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4342 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4343 if (PV_PMAP(pv) == pmap) {
4352 rw_wunlock(&pvh_global_lock);
4357 * pmap_page_wired_mappings:
4359 * Return the number of managed mappings to the given physical page
4363 pmap_page_wired_mappings(vm_page_t m)
4368 if ((m->oflags & VPO_UNMANAGED) != 0)
4370 rw_wlock(&pvh_global_lock);
4371 count = pmap_pvh_wired_mappings(&m->md, count);
4372 if ((m->flags & PG_FICTITIOUS) == 0) {
4373 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4376 rw_wunlock(&pvh_global_lock);
4381 * pmap_pvh_wired_mappings:
4383 * Return the updated number "count" of managed mappings that are wired.
4386 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4392 rw_assert(&pvh_global_lock, RA_WLOCKED);
4394 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4397 pte = pmap_pte_quick(pmap, pv->pv_va);
4398 if ((*pte & PG_W) != 0)
4407 * Returns TRUE if the given page is mapped individually or as part of
4408 * a 4mpage. Otherwise, returns FALSE.
4411 pmap_page_is_mapped(vm_page_t m)
4415 if ((m->oflags & VPO_UNMANAGED) != 0)
4417 rw_wlock(&pvh_global_lock);
4418 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4419 ((m->flags & PG_FICTITIOUS) == 0 &&
4420 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4421 rw_wunlock(&pvh_global_lock);
4426 * Remove all pages from specified address space
4427 * this aids process exit speeds. Also, this code
4428 * is special cased for current process only, but
4429 * can have the more generic (and slightly slower)
4430 * mode enabled. This is much faster than pmap_remove
4431 * in the case of running down an entire address space.
4434 pmap_remove_pages(pmap_t pmap)
4436 pt_entry_t *pte, tpte;
4437 vm_page_t m, mpte, mt;
4439 struct md_page *pvh;
4440 struct pv_chunk *pc, *npc;
4441 struct spglist free;
4444 uint32_t inuse, bitmask;
4447 if (pmap != PCPU_GET(curpmap)) {
4448 printf("warning: pmap_remove_pages called with non-current pmap\n");
4452 rw_wlock(&pvh_global_lock);
4455 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4456 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4459 for (field = 0; field < _NPCM; field++) {
4460 inuse = ~pc->pc_map[field] & pc_freemask[field];
4461 while (inuse != 0) {
4463 bitmask = 1UL << bit;
4464 idx = field * 32 + bit;
4465 pv = &pc->pc_pventry[idx];
4468 pte = pmap_pde(pmap, pv->pv_va);
4470 if ((tpte & PG_PS) == 0) {
4471 pte = vtopte(pv->pv_va);
4472 tpte = *pte & ~PG_PTE_PAT;
4477 "TPTE at %p IS ZERO @ VA %08x\n",
4483 * We cannot remove wired pages from a process' mapping at this time
4490 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4491 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4492 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4493 m, (uintmax_t)m->phys_addr,
4496 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4497 m < &vm_page_array[vm_page_array_size],
4498 ("pmap_remove_pages: bad tpte %#jx",
4504 * Update the vm_page_t clean/reference bits.
4506 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4507 if ((tpte & PG_PS) != 0) {
4508 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4515 PV_STAT(pv_entry_frees++);
4516 PV_STAT(pv_entry_spare++);
4518 pc->pc_map[field] |= bitmask;
4519 if ((tpte & PG_PS) != 0) {
4520 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4521 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4522 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4523 if (TAILQ_EMPTY(&pvh->pv_list)) {
4524 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4525 if (TAILQ_EMPTY(&mt->md.pv_list))
4526 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4528 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
4530 pmap->pm_stats.resident_count--;
4531 KASSERT(mpte->wire_count == NPTEPG,
4532 ("pmap_remove_pages: pte page wire count error"));
4533 mpte->wire_count = 0;
4534 pmap_add_delayed_free_list(mpte, &free, FALSE);
4535 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
4538 pmap->pm_stats.resident_count--;
4539 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4540 if (TAILQ_EMPTY(&m->md.pv_list) &&
4541 (m->flags & PG_FICTITIOUS) == 0) {
4542 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4543 if (TAILQ_EMPTY(&pvh->pv_list))
4544 vm_page_aflag_clear(m, PGA_WRITEABLE);
4546 pmap_unuse_pt(pmap, pv->pv_va, &free);
4551 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4556 pmap_invalidate_all(pmap);
4557 rw_wunlock(&pvh_global_lock);
4559 pmap_free_zero_pages(&free);
4565 * Return whether or not the specified physical page was modified
4566 * in any physical maps.
4569 pmap_is_modified(vm_page_t m)
4573 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4574 ("pmap_is_modified: page %p is not managed", m));
4577 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4578 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4579 * is clear, no PTEs can have PG_M set.
4581 VM_OBJECT_ASSERT_WLOCKED(m->object);
4582 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4584 rw_wlock(&pvh_global_lock);
4585 rv = pmap_is_modified_pvh(&m->md) ||
4586 ((m->flags & PG_FICTITIOUS) == 0 &&
4587 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4588 rw_wunlock(&pvh_global_lock);
4593 * Returns TRUE if any of the given mappings were used to modify
4594 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4595 * mappings are supported.
4598 pmap_is_modified_pvh(struct md_page *pvh)
4605 rw_assert(&pvh_global_lock, RA_WLOCKED);
4608 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4611 pte = pmap_pte_quick(pmap, pv->pv_va);
4612 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4622 * pmap_is_prefaultable:
4624 * Return whether or not the specified virtual address is elgible
4628 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4636 pde = pmap_pde(pmap, addr);
4637 if (*pde != 0 && (*pde & PG_PS) == 0) {
4646 * pmap_is_referenced:
4648 * Return whether or not the specified physical page was referenced
4649 * in any physical maps.
4652 pmap_is_referenced(vm_page_t m)
4656 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4657 ("pmap_is_referenced: page %p is not managed", m));
4658 rw_wlock(&pvh_global_lock);
4659 rv = pmap_is_referenced_pvh(&m->md) ||
4660 ((m->flags & PG_FICTITIOUS) == 0 &&
4661 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4662 rw_wunlock(&pvh_global_lock);
4667 * Returns TRUE if any of the given mappings were referenced and FALSE
4668 * otherwise. Both page and 4mpage mappings are supported.
4671 pmap_is_referenced_pvh(struct md_page *pvh)
4678 rw_assert(&pvh_global_lock, RA_WLOCKED);
4681 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4684 pte = pmap_pte_quick(pmap, pv->pv_va);
4685 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4695 * Clear the write and modified bits in each of the given page's mappings.
4698 pmap_remove_write(vm_page_t m)
4700 struct md_page *pvh;
4701 pv_entry_t next_pv, pv;
4704 pt_entry_t oldpte, *pte;
4707 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4708 ("pmap_remove_write: page %p is not managed", m));
4711 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4712 * set by another thread while the object is locked. Thus,
4713 * if PGA_WRITEABLE is clear, no page table entries need updating.
4715 VM_OBJECT_ASSERT_WLOCKED(m->object);
4716 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4718 rw_wlock(&pvh_global_lock);
4720 if ((m->flags & PG_FICTITIOUS) != 0)
4721 goto small_mappings;
4722 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4723 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4727 pde = pmap_pde(pmap, va);
4728 if ((*pde & PG_RW) != 0)
4729 (void)pmap_demote_pde(pmap, pde, va);
4733 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4736 pde = pmap_pde(pmap, pv->pv_va);
4737 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
4738 " a 4mpage in page %p's pv list", m));
4739 pte = pmap_pte_quick(pmap, pv->pv_va);
4742 if ((oldpte & PG_RW) != 0) {
4744 * Regardless of whether a pte is 32 or 64 bits
4745 * in size, PG_RW and PG_M are among the least
4746 * significant 32 bits.
4748 if (!atomic_cmpset_int((u_int *)pte, oldpte,
4749 oldpte & ~(PG_RW | PG_M)))
4751 if ((oldpte & PG_M) != 0)
4753 pmap_invalidate_page(pmap, pv->pv_va);
4757 vm_page_aflag_clear(m, PGA_WRITEABLE);
4759 rw_wunlock(&pvh_global_lock);
4763 * pmap_ts_referenced:
4765 * Return a count of reference bits for a page, clearing those bits.
4766 * It is not necessary for every reference bit to be cleared, but it
4767 * is necessary that 0 only be returned when there are truly no
4768 * reference bits set.
4770 * As an optimization, update the page's dirty field if a modified bit is
4771 * found while counting reference bits. This opportunistic update can be
4772 * performed at low cost and can eliminate the need for some future calls
4773 * to pmap_is_modified(). However, since this function stops after
4774 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4775 * dirty pages. Those dirty pages will only be detected by a future call
4776 * to pmap_is_modified().
4779 pmap_ts_referenced(vm_page_t m)
4781 struct md_page *pvh;
4789 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4790 ("pmap_ts_referenced: page %p is not managed", m));
4791 pa = VM_PAGE_TO_PHYS(m);
4792 pvh = pa_to_pvh(pa);
4793 rw_wlock(&pvh_global_lock);
4795 if ((m->flags & PG_FICTITIOUS) != 0 ||
4796 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4797 goto small_mappings;
4802 pde = pmap_pde(pmap, pv->pv_va);
4803 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4805 * Although "*pde" is mapping a 2/4MB page, because
4806 * this function is called at a 4KB page granularity,
4807 * we only update the 4KB page under test.
4811 if ((*pde & PG_A) != 0) {
4813 * Since this reference bit is shared by either 1024
4814 * or 512 4KB pages, it should not be cleared every
4815 * time it is tested. Apply a simple "hash" function
4816 * on the physical page number, the virtual superpage
4817 * number, and the pmap address to select one 4KB page
4818 * out of the 1024 or 512 on which testing the
4819 * reference bit will result in clearing that bit.
4820 * This function is designed to avoid the selection of
4821 * the same 4KB page for every 2- or 4MB page mapping.
4823 * On demotion, a mapping that hasn't been referenced
4824 * is simply destroyed. To avoid the possibility of a
4825 * subsequent page fault on a demoted wired mapping,
4826 * always leave its reference bit set. Moreover,
4827 * since the superpage is wired, the current state of
4828 * its reference bit won't affect page replacement.
4830 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
4831 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
4832 (*pde & PG_W) == 0) {
4833 atomic_clear_int((u_int *)pde, PG_A);
4834 pmap_invalidate_page(pmap, pv->pv_va);
4839 /* Rotate the PV list if it has more than one entry. */
4840 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4841 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4842 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4844 if (rtval >= PMAP_TS_REFERENCED_MAX)
4846 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4848 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4854 pde = pmap_pde(pmap, pv->pv_va);
4855 KASSERT((*pde & PG_PS) == 0,
4856 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
4858 pte = pmap_pte_quick(pmap, pv->pv_va);
4859 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4861 if ((*pte & PG_A) != 0) {
4862 atomic_clear_int((u_int *)pte, PG_A);
4863 pmap_invalidate_page(pmap, pv->pv_va);
4867 /* Rotate the PV list if it has more than one entry. */
4868 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4869 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4870 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4872 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
4873 PMAP_TS_REFERENCED_MAX);
4876 rw_wunlock(&pvh_global_lock);
4881 * Apply the given advice to the specified range of addresses within the
4882 * given pmap. Depending on the advice, clear the referenced and/or
4883 * modified flags in each mapping and set the mapped page's dirty field.
4886 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4888 pd_entry_t oldpde, *pde;
4892 boolean_t anychanged, pv_lists_locked;
4894 if (advice != MADV_DONTNEED && advice != MADV_FREE)
4896 if (pmap_is_current(pmap))
4897 pv_lists_locked = FALSE;
4899 pv_lists_locked = TRUE;
4901 rw_wlock(&pvh_global_lock);
4906 for (; sva < eva; sva = pdnxt) {
4907 pdnxt = (sva + NBPDR) & ~PDRMASK;
4910 pde = pmap_pde(pmap, sva);
4912 if ((oldpde & PG_V) == 0)
4914 else if ((oldpde & PG_PS) != 0) {
4915 if ((oldpde & PG_MANAGED) == 0)
4917 if (!pv_lists_locked) {
4918 pv_lists_locked = TRUE;
4919 if (!rw_try_wlock(&pvh_global_lock)) {
4921 pmap_invalidate_all(pmap);
4927 if (!pmap_demote_pde(pmap, pde, sva)) {
4929 * The large page mapping was destroyed.
4935 * Unless the page mappings are wired, remove the
4936 * mapping to a single page so that a subsequent
4937 * access may repromote. Since the underlying page
4938 * table page is fully populated, this removal never
4939 * frees a page table page.
4941 if ((oldpde & PG_W) == 0) {
4942 pte = pmap_pte_quick(pmap, sva);
4943 KASSERT((*pte & PG_V) != 0,
4944 ("pmap_advise: invalid PTE"));
4945 pmap_remove_pte(pmap, pte, sva, NULL);
4951 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4953 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED |
4956 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4957 if (advice == MADV_DONTNEED) {
4959 * Future calls to pmap_is_modified()
4960 * can be avoided by making the page
4963 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
4966 atomic_clear_int((u_int *)pte, PG_M | PG_A);
4967 } else if ((*pte & PG_A) != 0)
4968 atomic_clear_int((u_int *)pte, PG_A);
4971 if ((*pte & PG_G) != 0)
4972 pmap_invalidate_page(pmap, sva);
4978 pmap_invalidate_all(pmap);
4979 if (pv_lists_locked) {
4981 rw_wunlock(&pvh_global_lock);
4987 * Clear the modify bits on the specified physical page.
4990 pmap_clear_modify(vm_page_t m)
4992 struct md_page *pvh;
4993 pv_entry_t next_pv, pv;
4995 pd_entry_t oldpde, *pde;
4996 pt_entry_t oldpte, *pte;
4999 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5000 ("pmap_clear_modify: page %p is not managed", m));
5001 VM_OBJECT_ASSERT_WLOCKED(m->object);
5002 KASSERT(!vm_page_xbusied(m),
5003 ("pmap_clear_modify: page %p is exclusive busied", m));
5006 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5007 * If the object containing the page is locked and the page is not
5008 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5010 if ((m->aflags & PGA_WRITEABLE) == 0)
5012 rw_wlock(&pvh_global_lock);
5014 if ((m->flags & PG_FICTITIOUS) != 0)
5015 goto small_mappings;
5016 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5017 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5021 pde = pmap_pde(pmap, va);
5023 if ((oldpde & PG_RW) != 0) {
5024 if (pmap_demote_pde(pmap, pde, va)) {
5025 if ((oldpde & PG_W) == 0) {
5027 * Write protect the mapping to a
5028 * single page so that a subsequent
5029 * write access may repromote.
5031 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5033 pte = pmap_pte_quick(pmap, va);
5035 if ((oldpte & PG_V) != 0) {
5037 * Regardless of whether a pte is 32 or 64 bits
5038 * in size, PG_RW and PG_M are among the least
5039 * significant 32 bits.
5041 while (!atomic_cmpset_int((u_int *)pte,
5043 oldpte & ~(PG_M | PG_RW)))
5046 pmap_invalidate_page(pmap, va);
5054 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5057 pde = pmap_pde(pmap, pv->pv_va);
5058 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5059 " a 4mpage in page %p's pv list", m));
5060 pte = pmap_pte_quick(pmap, pv->pv_va);
5061 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5063 * Regardless of whether a pte is 32 or 64 bits
5064 * in size, PG_M is among the least significant
5067 atomic_clear_int((u_int *)pte, PG_M);
5068 pmap_invalidate_page(pmap, pv->pv_va);
5073 rw_wunlock(&pvh_global_lock);
5077 * Miscellaneous support routines follow
5080 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5081 static __inline void
5082 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5087 * The cache mode bits are all in the low 32-bits of the
5088 * PTE, so we can just spin on updating the low 32-bits.
5091 opte = *(u_int *)pte;
5092 npte = opte & ~PG_PTE_CACHE;
5094 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5097 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5098 static __inline void
5099 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5104 * The cache mode bits are all in the low 32-bits of the
5105 * PDE, so we can just spin on updating the low 32-bits.
5108 opde = *(u_int *)pde;
5109 npde = opde & ~PG_PDE_CACHE;
5111 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5115 * Map a set of physical memory pages into the kernel virtual
5116 * address space. Return a pointer to where it is mapped. This
5117 * routine is intended to be used for mapping device memory,
5121 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5123 struct pmap_preinit_mapping *ppim;
5124 vm_offset_t va, offset;
5128 offset = pa & PAGE_MASK;
5129 size = round_page(offset + size);
5132 if (pa < KERNLOAD && pa + size <= KERNLOAD)
5134 else if (!pmap_initialized) {
5136 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5137 ppim = pmap_preinit_mapping + i;
5138 if (ppim->va == 0) {
5142 ppim->va = virtual_avail;
5143 virtual_avail += size;
5149 panic("%s: too many preinit mappings", __func__);
5152 * If we have a preinit mapping, re-use it.
5154 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5155 ppim = pmap_preinit_mapping + i;
5156 if (ppim->pa == pa && ppim->sz == size &&
5158 return ((void *)(ppim->va + offset));
5160 va = kva_alloc(size);
5162 panic("%s: Couldn't allocate KVA", __func__);
5164 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5165 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5166 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5167 pmap_invalidate_cache_range(va, va + size, FALSE);
5168 return ((void *)(va + offset));
5172 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5175 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5179 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5182 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5186 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5188 struct pmap_preinit_mapping *ppim;
5192 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD)
5194 offset = va & PAGE_MASK;
5195 size = round_page(offset + size);
5196 va = trunc_page(va);
5197 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5198 ppim = pmap_preinit_mapping + i;
5199 if (ppim->va == va && ppim->sz == size) {
5200 if (pmap_initialized)
5206 if (va + size == virtual_avail)
5211 if (pmap_initialized)
5216 * Sets the memory attribute for the specified page.
5219 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5222 m->md.pat_mode = ma;
5223 if ((m->flags & PG_FICTITIOUS) != 0)
5227 * If "m" is a normal page, flush it from the cache.
5228 * See pmap_invalidate_cache_range().
5230 * First, try to find an existing mapping of the page by sf
5231 * buffer. sf_buf_invalidate_cache() modifies mapping and
5232 * flushes the cache.
5234 if (sf_buf_invalidate_cache(m))
5238 * If page is not mapped by sf buffer, but CPU does not
5239 * support self snoop, map the page transient and do
5240 * invalidation. In the worst case, whole cache is flushed by
5241 * pmap_invalidate_cache_range().
5243 if ((cpu_feature & CPUID_SS) == 0)
5248 pmap_flush_page(vm_page_t m)
5250 struct sysmaps *sysmaps;
5251 vm_offset_t sva, eva;
5254 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5255 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5256 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
5257 mtx_lock(&sysmaps->lock);
5258 if (*sysmaps->CMAP2)
5259 panic("pmap_flush_page: CMAP2 busy");
5261 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5262 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0);
5263 invlcaddr(sysmaps->CADDR2);
5264 sva = (vm_offset_t)sysmaps->CADDR2;
5265 eva = sva + PAGE_SIZE;
5268 * Use mfence despite the ordering implied by
5269 * mtx_{un,}lock() because clflush on non-Intel CPUs
5270 * and clflushopt are not guaranteed to be ordered by
5271 * any other instruction.
5273 if (useclflushopt || cpu_vendor_id != CPU_VENDOR_INTEL)
5275 for (; sva < eva; sva += cpu_clflush_line_size) {
5281 if (useclflushopt || cpu_vendor_id != CPU_VENDOR_INTEL)
5283 *sysmaps->CMAP2 = 0;
5285 mtx_unlock(&sysmaps->lock);
5287 pmap_invalidate_cache();
5291 * Changes the specified virtual address range's memory type to that given by
5292 * the parameter "mode". The specified virtual address range must be
5293 * completely contained within either the kernel map.
5295 * Returns zero if the change completed successfully, and either EINVAL or
5296 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5297 * of the virtual address range was not mapped, and ENOMEM is returned if
5298 * there was insufficient memory available to complete the change.
5301 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5303 vm_offset_t base, offset, tmpva;
5306 int cache_bits_pte, cache_bits_pde;
5309 base = trunc_page(va);
5310 offset = va & PAGE_MASK;
5311 size = round_page(offset + size);
5314 * Only supported on kernel virtual addresses above the recursive map.
5316 if (base < VM_MIN_KERNEL_ADDRESS)
5319 cache_bits_pde = pmap_cache_bits(mode, 1);
5320 cache_bits_pte = pmap_cache_bits(mode, 0);
5324 * Pages that aren't mapped aren't supported. Also break down
5325 * 2/4MB pages into 4KB pages if required.
5327 PMAP_LOCK(kernel_pmap);
5328 for (tmpva = base; tmpva < base + size; ) {
5329 pde = pmap_pde(kernel_pmap, tmpva);
5331 PMAP_UNLOCK(kernel_pmap);
5336 * If the current 2/4MB page already has
5337 * the required memory type, then we need not
5338 * demote this page. Just increment tmpva to
5339 * the next 2/4MB page frame.
5341 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5342 tmpva = trunc_4mpage(tmpva) + NBPDR;
5347 * If the current offset aligns with a 2/4MB
5348 * page frame and there is at least 2/4MB left
5349 * within the range, then we need not break
5350 * down this page into 4KB pages.
5352 if ((tmpva & PDRMASK) == 0 &&
5353 tmpva + PDRMASK < base + size) {
5357 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5358 PMAP_UNLOCK(kernel_pmap);
5362 pte = vtopte(tmpva);
5364 PMAP_UNLOCK(kernel_pmap);
5369 PMAP_UNLOCK(kernel_pmap);
5372 * Ok, all the pages exist, so run through them updating their
5373 * cache mode if required.
5375 for (tmpva = base; tmpva < base + size; ) {
5376 pde = pmap_pde(kernel_pmap, tmpva);
5378 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5379 pmap_pde_attr(pde, cache_bits_pde);
5382 tmpva = trunc_4mpage(tmpva) + NBPDR;
5384 pte = vtopte(tmpva);
5385 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5386 pmap_pte_attr(pte, cache_bits_pte);
5394 * Flush CPU caches to make sure any data isn't cached that
5395 * shouldn't be, etc.
5398 pmap_invalidate_range(kernel_pmap, base, tmpva);
5399 pmap_invalidate_cache_range(base, tmpva, FALSE);
5405 * perform the pmap work for mincore
5408 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5411 pt_entry_t *ptep, pte;
5417 pdep = pmap_pde(pmap, addr);
5419 if (*pdep & PG_PS) {
5421 /* Compute the physical address of the 4KB page. */
5422 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5424 val = MINCORE_SUPER;
5426 ptep = pmap_pte(pmap, addr);
5428 pmap_pte_release(ptep);
5429 pa = pte & PG_FRAME;
5437 if ((pte & PG_V) != 0) {
5438 val |= MINCORE_INCORE;
5439 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5440 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5441 if ((pte & PG_A) != 0)
5442 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5444 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5445 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5446 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5447 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5448 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5451 PA_UNLOCK_COND(*locked_pa);
5457 pmap_activate(struct thread *td)
5459 pmap_t pmap, oldpmap;
5464 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5465 oldpmap = PCPU_GET(curpmap);
5466 cpuid = PCPU_GET(cpuid);
5468 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5469 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5471 CPU_CLR(cpuid, &oldpmap->pm_active);
5472 CPU_SET(cpuid, &pmap->pm_active);
5474 #if defined(PAE) || defined(PAE_TABLES)
5475 cr3 = vtophys(pmap->pm_pdpt);
5477 cr3 = vtophys(pmap->pm_pdir);
5480 * pmap_activate is for the current thread on the current cpu
5482 td->td_pcb->pcb_cr3 = cr3;
5484 PCPU_SET(curpmap, pmap);
5489 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5494 * Increase the starting virtual address of the given mapping if a
5495 * different alignment might result in more superpage mappings.
5498 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5499 vm_offset_t *addr, vm_size_t size)
5501 vm_offset_t superpage_offset;
5505 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5506 offset += ptoa(object->pg_color);
5507 superpage_offset = offset & PDRMASK;
5508 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5509 (*addr & PDRMASK) == superpage_offset)
5511 if ((*addr & PDRMASK) < superpage_offset)
5512 *addr = (*addr & ~PDRMASK) + superpage_offset;
5514 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5518 pmap_quick_enter_page(vm_page_t m)
5524 qaddr = PCPU_GET(qmap_addr);
5525 pte = vtopte(qaddr);
5527 KASSERT(*pte == 0, ("pmap_quick_enter_page: PTE busy"));
5528 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5529 pmap_cache_bits(pmap_page_get_memattr(m), 0);
5536 pmap_quick_remove_page(vm_offset_t addr)
5541 qaddr = PCPU_GET(qmap_addr);
5542 pte = vtopte(qaddr);
5544 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5545 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5551 #if defined(PMAP_DEBUG)
5552 pmap_pid_dump(int pid)
5559 sx_slock(&allproc_lock);
5560 FOREACH_PROC_IN_SYSTEM(p) {
5561 if (p->p_pid != pid)
5567 pmap = vmspace_pmap(p->p_vmspace);
5568 for (i = 0; i < NPDEPTD; i++) {
5571 vm_offset_t base = i << PDRSHIFT;
5573 pde = &pmap->pm_pdir[i];
5574 if (pde && pmap_pde_v(pde)) {
5575 for (j = 0; j < NPTEPG; j++) {
5576 vm_offset_t va = base + (j << PAGE_SHIFT);
5577 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5582 sx_sunlock(&allproc_lock);
5585 pte = pmap_pte(pmap, va);
5586 if (pte && pmap_pte_v(pte)) {
5590 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5591 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5592 va, pa, m->hold_count, m->wire_count, m->flags);
5607 sx_sunlock(&allproc_lock);