2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * This code is derived from software contributed to Berkeley by
12 * the Systems Programming Group of the University of Utah Computer
13 * Science Department and William Jolitz of UUNET Technologies Inc.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 * must display the following acknowledgement:
25 * This product includes software developed by the University of
26 * California, Berkeley and its contributors.
27 * 4. Neither the name of the University nor the names of its contributors
28 * may be used to endorse or promote products derived from this software
29 * without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
46 * Copyright (c) 2003 Networks Associates Technology, Inc.
47 * All rights reserved.
49 * This software was developed for the FreeBSD Project by Jake Burkholder,
50 * Safeport Network Services, and Network Associates Laboratories, the
51 * Security Research Division of Network Associates, Inc. under
52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
53 * CHATS research program.
55 * Redistribution and use in source and binary forms, with or without
56 * modification, are permitted provided that the following conditions
58 * 1. Redistributions of source code must retain the above copyright
59 * notice, this list of conditions and the following disclaimer.
60 * 2. Redistributions in binary form must reproduce the above copyright
61 * notice, this list of conditions and the following disclaimer in the
62 * documentation and/or other materials provided with the distribution.
64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
77 #include <sys/cdefs.h>
78 __FBSDID("$FreeBSD$");
81 * Manages physical address maps.
83 * Since the information managed by this module is
84 * also stored by the logical address mapping module,
85 * this module may throw away valid virtual-to-physical
86 * mappings at almost any time. However, invalidations
87 * of virtual-to-physical mappings must be done as
90 * In order to cope with hardware architectures which
91 * make virtual-to-physical map invalidates expensive,
92 * this module may delay invalidate or reduced protection
93 * operations until such time as they are actually
94 * necessary. This module is given full information as
95 * to which processors are currently using which maps,
96 * and to when physical maps must be made correct.
101 #include "opt_pmap.h"
103 #include "opt_xbox.h"
105 #include <sys/param.h>
106 #include <sys/systm.h>
107 #include <sys/kernel.h>
109 #include <sys/lock.h>
110 #include <sys/malloc.h>
111 #include <sys/mman.h>
112 #include <sys/msgbuf.h>
113 #include <sys/mutex.h>
114 #include <sys/proc.h>
115 #include <sys/rwlock.h>
116 #include <sys/sf_buf.h>
118 #include <sys/vmmeter.h>
119 #include <sys/sched.h>
120 #include <sys/sysctl.h>
124 #include <vm/vm_param.h>
125 #include <vm/vm_kern.h>
126 #include <vm/vm_page.h>
127 #include <vm/vm_map.h>
128 #include <vm/vm_object.h>
129 #include <vm/vm_extern.h>
130 #include <vm/vm_pageout.h>
131 #include <vm/vm_pager.h>
132 #include <vm/vm_phys.h>
133 #include <vm/vm_radix.h>
134 #include <vm/vm_reserv.h>
139 #include <machine/intr_machdep.h>
140 #include <x86/apicvar.h>
142 #include <machine/cpu.h>
143 #include <machine/cputypes.h>
144 #include <machine/md_var.h>
145 #include <machine/pcb.h>
146 #include <machine/specialreg.h>
148 #include <machine/smp.h>
152 #include <machine/xbox.h>
155 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
156 #define CPU_ENABLE_SSE
159 #ifndef PMAP_SHPGPERPROC
160 #define PMAP_SHPGPERPROC 200
163 #if !defined(DIAGNOSTIC)
164 #ifdef __GNUC_GNU_INLINE__
165 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
167 #define PMAP_INLINE extern inline
174 #define PV_STAT(x) do { x ; } while (0)
176 #define PV_STAT(x) do { } while (0)
179 #define pa_index(pa) ((pa) >> PDRSHIFT)
180 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
183 * Get PDEs and PTEs for user/kernel address space
185 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
186 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
188 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
189 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
190 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
191 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
192 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
194 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
195 atomic_clear_int((u_int *)(pte), PG_W))
196 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
198 struct pmap kernel_pmap_store;
199 LIST_HEAD(pmaplist, pmap);
200 static struct pmaplist allpmaps;
201 static struct mtx allpmaps_lock;
203 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
204 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
205 int pgeflag = 0; /* PG_G or-in */
206 int pseflag = 0; /* PG_PS or-in */
208 static int nkpt = NKPT;
209 vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR;
210 extern u_int32_t KERNend;
211 extern u_int32_t KPTphys;
213 #if defined(PAE) || defined(PAE_TABLES)
215 static uma_zone_t pdptzone;
218 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
220 static int pat_works = 1;
221 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
222 "Is page attribute table fully functional?");
224 static int pg_ps_enabled = 1;
225 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
226 &pg_ps_enabled, 0, "Are large page mappings enabled?");
228 #define PAT_INDEX_SIZE 8
229 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
232 * pmap_mapdev support pre initialization (i.e. console)
234 #define PMAP_PREINIT_MAPPING_COUNT 8
235 static struct pmap_preinit_mapping {
240 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
241 static int pmap_initialized;
243 static struct rwlock_padalign pvh_global_lock;
246 * Data for the pv entry allocation mechanism
248 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
249 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
250 static struct md_page *pv_table;
251 static int shpgperproc = PMAP_SHPGPERPROC;
253 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
254 int pv_maxchunks; /* How many chunks we have KVA for */
255 vm_offset_t pv_vafree; /* freelist stored in the PTE */
258 * All those kernel PT submaps that BSD is so fond of
261 static pd_entry_t *KPTD;
264 struct msgbuf *msgbufp = NULL;
269 static caddr_t crashdumpmap;
271 static pt_entry_t *PMAP1 = NULL, *PMAP2;
272 static pt_entry_t *PADDR1 = NULL, *PADDR2;
275 static int PMAP1changedcpu;
276 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
278 "Number of times pmap_pte_quick changed CPU with same PMAP1");
280 static int PMAP1changed;
281 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
283 "Number of times pmap_pte_quick changed PMAP1");
284 static int PMAP1unchanged;
285 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
287 "Number of times pmap_pte_quick didn't change PMAP1");
288 static struct mtx PMAP2mutex;
290 static void free_pv_chunk(struct pv_chunk *pc);
291 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
292 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
293 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
294 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
295 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
296 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
297 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
299 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
301 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
302 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
304 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
305 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
306 static void pmap_flush_page(vm_page_t m);
307 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
308 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
309 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
310 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
311 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
312 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
313 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
314 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
315 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
317 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
318 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
319 struct spglist *free);
320 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
321 struct spglist *free);
322 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
323 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
324 struct spglist *free);
325 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
327 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
328 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
330 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
332 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
334 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
336 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
337 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
338 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
339 static void pmap_pte_release(pt_entry_t *pte);
340 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
341 #if defined(PAE) || defined(PAE_TABLES)
342 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, uint8_t *flags,
345 static void pmap_set_pg(void);
347 static __inline void pagezero(void *page);
349 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
350 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
353 * If you get an error here, then you set KVA_PAGES wrong! See the
354 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be
355 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE.
357 CTASSERT(KERNBASE % (1 << 24) == 0);
360 * Bootstrap the system enough to run with virtual memory.
362 * On the i386 this is called after mapping has already been enabled
363 * and just syncs the pmap module with what has already been done.
364 * [We can't call it easily with mapping off since the kernel is not
365 * mapped with PA == VA, hence we would have to relocate every address
366 * from the linked base (virtual) address "KERNBASE" to the actual
367 * (physical) address starting relative to 0]
370 pmap_bootstrap(vm_paddr_t firstaddr)
373 pt_entry_t *pte, *unused;
378 * Add a physical memory segment (vm_phys_seg) corresponding to the
379 * preallocated kernel page table pages so that vm_page structures
380 * representing these pages will be created. The vm_page structures
381 * are required for promotion of the corresponding kernel virtual
382 * addresses to superpage mappings.
384 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
387 * Initialize the first available kernel virtual address. However,
388 * using "firstaddr" may waste a few pages of the kernel virtual
389 * address space, because locore may not have mapped every physical
390 * page that it allocated. Preferably, locore would provide a first
391 * unused virtual address in addition to "firstaddr".
393 virtual_avail = (vm_offset_t) KERNBASE + firstaddr;
395 virtual_end = VM_MAX_KERNEL_ADDRESS;
398 * Initialize the kernel pmap (which is statically allocated).
400 PMAP_LOCK_INIT(kernel_pmap);
401 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD);
402 #if defined(PAE) || defined(PAE_TABLES)
403 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT);
405 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
406 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
409 * Initialize the global pv list lock.
411 rw_init(&pvh_global_lock, "pmap pv global");
413 LIST_INIT(&allpmaps);
416 * Request a spin mutex so that changes to allpmaps cannot be
417 * preempted by smp_rendezvous_cpus(). Otherwise,
418 * pmap_update_pde_kernel() could access allpmaps while it is
421 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
422 mtx_lock_spin(&allpmaps_lock);
423 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
424 mtx_unlock_spin(&allpmaps_lock);
427 * Reserve some special page table entries/VA space for temporary
430 #define SYSMAP(c, p, v, n) \
431 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
438 * Initialize temporary map objects on the current CPU for use
440 * CMAP1/CMAP2 are used for zeroing and copying pages.
441 * CMAP3 is used for the boot-time memory test.
443 pc = pcpu_find(curcpu);
444 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
445 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1)
446 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1)
447 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1)
449 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
454 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
457 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
459 SYSMAP(caddr_t, unused, ptvmmap, 1)
462 * msgbufp is used to map the system message buffer.
464 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
467 * KPTmap is used by pmap_kextract().
469 * KPTmap is first initialized by locore. However, that initial
470 * KPTmap can only support NKPT page table pages. Here, a larger
471 * KPTmap is created that can support KVA_PAGES page table pages.
473 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
475 for (i = 0; i < NKPT; i++)
476 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V;
479 * Adjust the start of the KPTD and KPTmap so that the implementation
480 * of pmap_kextract() and pmap_growkernel() can be made simpler.
483 KPTmap -= i386_btop(KPTDI << PDRSHIFT);
486 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
489 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
490 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
492 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
497 * Leave in place an identity mapping (virt == phys) for the low 1 MB
498 * physical memory region that is used by the ACPI wakeup code. This
499 * mapping must not have PG_G set.
502 /* FIXME: This is gross, but needed for the XBOX. Since we are in such
503 * an early stadium, we cannot yet neatly map video memory ... :-(
504 * Better fixes are very welcome! */
505 if (!arch_i386_is_xbox)
507 for (i = 1; i < NKPT; i++)
510 /* Initialize the PAT MSR if present. */
513 /* Turn on PG_G on kernel page(s) */
518 pmap_init_reserved_pages(void)
527 * Skip if the mapping has already been initialized,
528 * i.e. this is the BSP.
530 if (pc->pc_cmap_addr1 != 0)
532 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
533 pages = kva_alloc(PAGE_SIZE * 3);
535 panic("%s: unable to allocate KVA", __func__);
536 pc->pc_cmap_pte1 = vtopte(pages);
537 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE);
538 pc->pc_cmap_addr1 = (caddr_t)pages;
539 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE);
540 pc->pc_qmap_addr = pages + (PAGE_SIZE * 2);
544 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
552 int pat_table[PAT_INDEX_SIZE];
557 /* Set default PAT index table. */
558 for (i = 0; i < PAT_INDEX_SIZE; i++)
560 pat_table[PAT_WRITE_BACK] = 0;
561 pat_table[PAT_WRITE_THROUGH] = 1;
562 pat_table[PAT_UNCACHEABLE] = 3;
563 pat_table[PAT_WRITE_COMBINING] = 3;
564 pat_table[PAT_WRITE_PROTECTED] = 3;
565 pat_table[PAT_UNCACHED] = 3;
567 /* Bail if this CPU doesn't implement PAT. */
568 if ((cpu_feature & CPUID_PAT) == 0) {
569 for (i = 0; i < PAT_INDEX_SIZE; i++)
570 pat_index[i] = pat_table[i];
576 * Due to some Intel errata, we can only safely use the lower 4
579 * Intel Pentium III Processor Specification Update
580 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
583 * Intel Pentium IV Processor Specification Update
584 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
586 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
587 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
590 /* Initialize default PAT entries. */
591 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
592 PAT_VALUE(1, PAT_WRITE_THROUGH) |
593 PAT_VALUE(2, PAT_UNCACHED) |
594 PAT_VALUE(3, PAT_UNCACHEABLE) |
595 PAT_VALUE(4, PAT_WRITE_BACK) |
596 PAT_VALUE(5, PAT_WRITE_THROUGH) |
597 PAT_VALUE(6, PAT_UNCACHED) |
598 PAT_VALUE(7, PAT_UNCACHEABLE);
602 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
603 * Program 5 and 6 as WP and WC.
604 * Leave 4 and 7 as WB and UC.
606 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
607 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
608 PAT_VALUE(6, PAT_WRITE_COMBINING);
609 pat_table[PAT_UNCACHED] = 2;
610 pat_table[PAT_WRITE_PROTECTED] = 5;
611 pat_table[PAT_WRITE_COMBINING] = 6;
614 * Just replace PAT Index 2 with WC instead of UC-.
616 pat_msr &= ~PAT_MASK(2);
617 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
618 pat_table[PAT_WRITE_COMBINING] = 2;
623 load_cr4(cr4 & ~CR4_PGE);
625 /* Disable caches (CD = 1, NW = 0). */
627 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
629 /* Flushes caches and TLBs. */
633 /* Update PAT and index table. */
634 wrmsr(MSR_PAT, pat_msr);
635 for (i = 0; i < PAT_INDEX_SIZE; i++)
636 pat_index[i] = pat_table[i];
638 /* Flush caches and TLBs again. */
642 /* Restore caches and PGE. */
648 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on.
654 vm_offset_t va, endva;
659 endva = KERNBASE + KERNend;
662 va = KERNBASE + KERNLOAD;
664 pdir_pde(PTD, va) |= pgeflag;
665 invltlb(); /* Flush non-PG_G entries. */
669 va = (vm_offset_t)btext;
674 invltlb(); /* Flush non-PG_G entries. */
681 * Initialize a vm_page's machine-dependent fields.
684 pmap_page_init(vm_page_t m)
687 TAILQ_INIT(&m->md.pv_list);
688 m->md.pat_mode = PAT_WRITE_BACK;
691 #if defined(PAE) || defined(PAE_TABLES)
693 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, uint8_t *flags, int wait)
696 /* Inform UMA that this allocator uses kernel_map/object. */
697 *flags = UMA_SLAB_KERNEL;
698 return ((void *)kmem_alloc_contig(kernel_arena, bytes, wait, 0x0ULL,
699 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
704 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
706 * - Must deal with pages in order to ensure that none of the PG_* bits
707 * are ever set, PG_V in particular.
708 * - Assumes we can write to ptes without pte_store() atomic ops, even
709 * on PAE systems. This should be ok.
710 * - Assumes nothing will ever test these addresses for 0 to indicate
711 * no mapping instead of correctly checking PG_V.
712 * - Assumes a vm_offset_t will fit in a pte (true for i386).
713 * Because PG_V is never set, there can be no mappings to invalidate.
716 pmap_ptelist_alloc(vm_offset_t *head)
723 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
727 panic("pmap_ptelist_alloc: va with PG_V set!");
733 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
738 panic("pmap_ptelist_free: freeing va with PG_V set!");
740 *pte = *head; /* virtual! PG_V is 0 though */
745 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
751 for (i = npages - 1; i >= 0; i--) {
752 va = (vm_offset_t)base + i * PAGE_SIZE;
753 pmap_ptelist_free(head, va);
759 * Initialize the pmap module.
760 * Called by vm_init, to initialize any structures that the pmap
761 * system needs to map virtual memory.
766 struct pmap_preinit_mapping *ppim;
772 * Initialize the vm page array entries for the kernel pmap's
775 for (i = 0; i < NKPT; i++) {
776 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
777 KASSERT(mpte >= vm_page_array &&
778 mpte < &vm_page_array[vm_page_array_size],
779 ("pmap_init: page table page is out of range"));
780 mpte->pindex = i + KPTDI;
781 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
785 * Initialize the address space (zone) for the pv entries. Set a
786 * high water mark so that the system can recover from excessive
787 * numbers of pv entries.
789 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
790 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
791 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
792 pv_entry_max = roundup(pv_entry_max, _NPCPV);
793 pv_entry_high_water = 9 * (pv_entry_max / 10);
796 * If the kernel is running on a virtual machine, then it must assume
797 * that MCA is enabled by the hypervisor. Moreover, the kernel must
798 * be prepared for the hypervisor changing the vendor and family that
799 * are reported by CPUID. Consequently, the workaround for AMD Family
800 * 10h Erratum 383 is enabled if the processor's feature set does not
801 * include at least one feature that is only supported by older Intel
802 * or newer AMD processors.
804 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
805 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
806 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
808 workaround_erratum383 = 1;
811 * Are large page mappings supported and enabled?
813 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
816 else if (pg_ps_enabled) {
817 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
818 ("pmap_init: can't assign to pagesizes[1]"));
819 pagesizes[1] = NBPDR;
823 * Calculate the size of the pv head table for superpages.
824 * Handle the possibility that "vm_phys_segs[...].end" is zero.
826 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
827 PAGE_SIZE) / NBPDR + 1;
830 * Allocate memory for the pv head table for superpages.
832 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
834 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
836 for (i = 0; i < pv_npg; i++)
837 TAILQ_INIT(&pv_table[i].pv_list);
839 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
840 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
841 if (pv_chunkbase == NULL)
842 panic("pmap_init: not enough kvm for pv chunks");
843 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
844 #if defined(PAE) || defined(PAE_TABLES)
845 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
846 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
847 UMA_ZONE_VM | UMA_ZONE_NOFREE);
848 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
851 pmap_initialized = 1;
854 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
855 ppim = pmap_preinit_mapping + i;
858 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
859 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
864 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
865 "Max number of PV entries");
866 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
867 "Page share factor per proc");
869 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
870 "2/4MB page mapping counters");
872 static u_long pmap_pde_demotions;
873 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
874 &pmap_pde_demotions, 0, "2/4MB page demotions");
876 static u_long pmap_pde_mappings;
877 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
878 &pmap_pde_mappings, 0, "2/4MB page mappings");
880 static u_long pmap_pde_p_failures;
881 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
882 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
884 static u_long pmap_pde_promotions;
885 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
886 &pmap_pde_promotions, 0, "2/4MB page promotions");
888 /***************************************************
889 * Low level helper routines.....
890 ***************************************************/
893 * Determine the appropriate bits to set in a PTE or PDE for a specified
897 pmap_cache_bits(int mode, boolean_t is_pde)
899 int cache_bits, pat_flag, pat_idx;
901 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
902 panic("Unknown caching mode %d\n", mode);
904 /* The PAT bit is different for PTE's and PDE's. */
905 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
907 /* Map the caching mode to a PAT index. */
908 pat_idx = pat_index[mode];
910 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
913 cache_bits |= pat_flag;
915 cache_bits |= PG_NC_PCD;
917 cache_bits |= PG_NC_PWT;
922 * The caller is responsible for maintaining TLB consistency.
925 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
929 boolean_t PTD_updated;
932 mtx_lock_spin(&allpmaps_lock);
933 LIST_FOREACH(pmap, &allpmaps, pm_list) {
934 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] &
937 pde = pmap_pde(pmap, va);
938 pde_store(pde, newpde);
940 mtx_unlock_spin(&allpmaps_lock);
942 ("pmap_kenter_pde: current page table is not in allpmaps"));
946 * After changing the page size for the specified virtual address in the page
947 * table, flush the corresponding entries from the processor's TLB. Only the
948 * calling processor's TLB is affected.
950 * The calling thread must be pinned to a processor.
953 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
957 if ((newpde & PG_PS) == 0)
958 /* Demotion: flush a specific 2MB page mapping. */
960 else if ((newpde & PG_G) == 0)
962 * Promotion: flush every 4KB page mapping from the TLB
963 * because there are too many to flush individually.
968 * Promotion: flush every 4KB page mapping from the TLB,
969 * including any global (PG_G) mappings.
972 load_cr4(cr4 & ~CR4_PGE);
974 * Although preemption at this point could be detrimental to
975 * performance, it would not lead to an error. PG_G is simply
976 * ignored if CR4.PGE is clear. Moreover, in case this block
977 * is re-entered, the load_cr4() either above or below will
978 * modify CR4.PGE flushing the TLB.
980 load_cr4(cr4 | CR4_PGE);
993 load_cr4(cr4 & ~CR4_PGE);
994 load_cr4(cr4 | CR4_PGE);
1001 * For SMP, these functions have to use the IPI mechanism for coherence.
1003 * N.B.: Before calling any of the following TLB invalidation functions,
1004 * the calling processor must ensure that all stores updating a non-
1005 * kernel page table are globally performed. Otherwise, another
1006 * processor could cache an old, pre-update entry without being
1007 * invalidated. This can happen one of two ways: (1) The pmap becomes
1008 * active on another processor after its pm_active field is checked by
1009 * one of the following functions but before a store updating the page
1010 * table is globally performed. (2) The pmap becomes active on another
1011 * processor before its pm_active field is checked but due to
1012 * speculative loads one of the following functions stills reads the
1013 * pmap as inactive on the other processor.
1015 * The kernel page table is exempt because its pm_active field is
1016 * immutable. The kernel page table is always active on every
1020 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1022 cpuset_t *mask, other_cpus;
1026 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1030 cpuid = PCPU_GET(cpuid);
1031 other_cpus = all_cpus;
1032 CPU_CLR(cpuid, &other_cpus);
1033 if (CPU_ISSET(cpuid, &pmap->pm_active))
1035 CPU_AND(&other_cpus, &pmap->pm_active);
1038 smp_masked_invlpg(*mask, va);
1042 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1043 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1046 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1048 cpuset_t *mask, other_cpus;
1052 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1053 pmap_invalidate_all(pmap);
1058 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1059 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1063 cpuid = PCPU_GET(cpuid);
1064 other_cpus = all_cpus;
1065 CPU_CLR(cpuid, &other_cpus);
1066 if (CPU_ISSET(cpuid, &pmap->pm_active))
1067 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1069 CPU_AND(&other_cpus, &pmap->pm_active);
1072 smp_masked_invlpg_range(*mask, sva, eva);
1077 pmap_invalidate_all(pmap_t pmap)
1079 cpuset_t *mask, other_cpus;
1083 if (pmap == kernel_pmap) {
1086 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1090 cpuid = PCPU_GET(cpuid);
1091 other_cpus = all_cpus;
1092 CPU_CLR(cpuid, &other_cpus);
1093 if (CPU_ISSET(cpuid, &pmap->pm_active))
1095 CPU_AND(&other_cpus, &pmap->pm_active);
1098 smp_masked_invltlb(*mask, pmap);
1103 pmap_invalidate_cache(void)
1113 cpuset_t invalidate; /* processors that invalidate their TLB */
1117 u_int store; /* processor that updates the PDE */
1121 pmap_update_pde_kernel(void *arg)
1123 struct pde_action *act = arg;
1127 if (act->store == PCPU_GET(cpuid)) {
1130 * Elsewhere, this operation requires allpmaps_lock for
1131 * synchronization. Here, it does not because it is being
1132 * performed in the context of an all_cpus rendezvous.
1134 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1135 pde = pmap_pde(pmap, act->va);
1136 pde_store(pde, act->newpde);
1142 pmap_update_pde_user(void *arg)
1144 struct pde_action *act = arg;
1146 if (act->store == PCPU_GET(cpuid))
1147 pde_store(act->pde, act->newpde);
1151 pmap_update_pde_teardown(void *arg)
1153 struct pde_action *act = arg;
1155 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1156 pmap_update_pde_invalidate(act->va, act->newpde);
1160 * Change the page size for the specified virtual address in a way that
1161 * prevents any possibility of the TLB ever having two entries that map the
1162 * same virtual address using different page sizes. This is the recommended
1163 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1164 * machine check exception for a TLB state that is improperly diagnosed as a
1168 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1170 struct pde_action act;
1171 cpuset_t active, other_cpus;
1175 cpuid = PCPU_GET(cpuid);
1176 other_cpus = all_cpus;
1177 CPU_CLR(cpuid, &other_cpus);
1178 if (pmap == kernel_pmap)
1181 active = pmap->pm_active;
1182 if (CPU_OVERLAP(&active, &other_cpus)) {
1184 act.invalidate = active;
1187 act.newpde = newpde;
1188 CPU_SET(cpuid, &active);
1189 smp_rendezvous_cpus(active,
1190 smp_no_rendevous_barrier, pmap == kernel_pmap ?
1191 pmap_update_pde_kernel : pmap_update_pde_user,
1192 pmap_update_pde_teardown, &act);
1194 if (pmap == kernel_pmap)
1195 pmap_kenter_pde(va, newpde);
1197 pde_store(pde, newpde);
1198 if (CPU_ISSET(cpuid, &active))
1199 pmap_update_pde_invalidate(va, newpde);
1205 * Normal, non-SMP, 486+ invalidation functions.
1206 * We inline these within pmap.c for speed.
1209 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1212 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1217 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1221 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1222 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1227 pmap_invalidate_all(pmap_t pmap)
1230 if (pmap == kernel_pmap)
1232 else if (!CPU_EMPTY(&pmap->pm_active))
1237 pmap_invalidate_cache(void)
1244 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1247 if (pmap == kernel_pmap)
1248 pmap_kenter_pde(va, newpde);
1250 pde_store(pde, newpde);
1251 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1252 pmap_update_pde_invalidate(va, newpde);
1256 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1259 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1263 sva &= ~(vm_offset_t)cpu_clflush_line_size;
1265 KASSERT((sva & PAGE_MASK) == 0,
1266 ("pmap_invalidate_cache_range: sva not page-aligned"));
1267 KASSERT((eva & PAGE_MASK) == 0,
1268 ("pmap_invalidate_cache_range: eva not page-aligned"));
1271 if ((cpu_feature & CPUID_SS) != 0 && !force)
1272 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1273 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
1274 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1277 * XXX: Some CPUs fault, hang, or trash the local APIC
1278 * registers if we use CLFLUSH on the local APIC
1279 * range. The local APIC is always uncached, so we
1280 * don't need to flush for that range anyway.
1282 if (pmap_kextract(sva) == lapic_paddr)
1286 * Otherwise, do per-cache line flush. Use the mfence
1287 * instruction to insure that previous stores are
1288 * included in the write-back. The processor
1289 * propagates flush to other processors in the cache
1293 for (; sva < eva; sva += cpu_clflush_line_size)
1296 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1297 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1299 if (pmap_kextract(sva) == lapic_paddr)
1303 * Writes are ordered by CLFLUSH on Intel CPUs.
1305 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1307 for (; sva < eva; sva += cpu_clflush_line_size)
1309 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1314 * No targeted cache flush methods are supported by CPU,
1315 * or the supplied range is bigger than 2MB.
1316 * Globally invalidate cache.
1318 pmap_invalidate_cache();
1323 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1327 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1328 (cpu_feature & CPUID_CLFSH) == 0) {
1329 pmap_invalidate_cache();
1331 for (i = 0; i < count; i++)
1332 pmap_flush_page(pages[i]);
1337 * Are we current address space or kernel?
1340 pmap_is_current(pmap_t pmap)
1343 return (pmap == kernel_pmap || pmap ==
1344 vmspace_pmap(curthread->td_proc->p_vmspace));
1348 * If the given pmap is not the current or kernel pmap, the returned pte must
1349 * be released by passing it to pmap_pte_release().
1352 pmap_pte(pmap_t pmap, vm_offset_t va)
1357 pde = pmap_pde(pmap, va);
1361 /* are we current address space or kernel? */
1362 if (pmap_is_current(pmap))
1363 return (vtopte(va));
1364 mtx_lock(&PMAP2mutex);
1365 newpf = *pde & PG_FRAME;
1366 if ((*PMAP2 & PG_FRAME) != newpf) {
1367 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1368 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1370 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1376 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1379 static __inline void
1380 pmap_pte_release(pt_entry_t *pte)
1383 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1384 mtx_unlock(&PMAP2mutex);
1388 * NB: The sequence of updating a page table followed by accesses to the
1389 * corresponding pages is subject to the situation described in the "AMD64
1390 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1391 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1392 * right after modifying the PTE bits is crucial.
1394 static __inline void
1395 invlcaddr(void *caddr)
1398 invlpg((u_int)caddr);
1402 * Super fast pmap_pte routine best used when scanning
1403 * the pv lists. This eliminates many coarse-grained
1404 * invltlb calls. Note that many of the pv list
1405 * scans are across different pmaps. It is very wasteful
1406 * to do an entire invltlb for checking a single mapping.
1408 * If the given pmap is not the current pmap, pvh_global_lock
1409 * must be held and curthread pinned to a CPU.
1412 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1417 pde = pmap_pde(pmap, va);
1421 /* are we current address space or kernel? */
1422 if (pmap_is_current(pmap))
1423 return (vtopte(va));
1424 rw_assert(&pvh_global_lock, RA_WLOCKED);
1425 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1426 newpf = *pde & PG_FRAME;
1427 if ((*PMAP1 & PG_FRAME) != newpf) {
1428 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1430 PMAP1cpu = PCPU_GET(cpuid);
1436 if (PMAP1cpu != PCPU_GET(cpuid)) {
1437 PMAP1cpu = PCPU_GET(cpuid);
1443 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1449 * Routine: pmap_extract
1451 * Extract the physical page address associated
1452 * with the given map/virtual_address pair.
1455 pmap_extract(pmap_t pmap, vm_offset_t va)
1463 pde = pmap->pm_pdir[va >> PDRSHIFT];
1465 if ((pde & PG_PS) != 0)
1466 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1468 pte = pmap_pte(pmap, va);
1469 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK);
1470 pmap_pte_release(pte);
1478 * Routine: pmap_extract_and_hold
1480 * Atomically extract and hold the physical page
1481 * with the given pmap and virtual address pair
1482 * if that mapping permits the given protection.
1485 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1488 pt_entry_t pte, *ptep;
1496 pde = *pmap_pde(pmap, va);
1499 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1500 if (vm_page_pa_tryrelock(pmap, (pde &
1501 PG_PS_FRAME) | (va & PDRMASK), &pa))
1503 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1508 ptep = pmap_pte(pmap, va);
1510 pmap_pte_release(ptep);
1512 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1513 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1516 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1526 /***************************************************
1527 * Low level mapping routines.....
1528 ***************************************************/
1531 * Add a wired page to the kva.
1532 * Note: not SMP coherent.
1534 * This function may be used before pmap_bootstrap() is called.
1537 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1542 pte_store(pte, pa | PG_RW | PG_V | pgeflag);
1545 static __inline void
1546 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1551 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0));
1555 * Remove a page from the kernel pagetables.
1556 * Note: not SMP coherent.
1558 * This function may be used before pmap_bootstrap() is called.
1561 pmap_kremove(vm_offset_t va)
1570 * Used to map a range of physical addresses into kernel
1571 * virtual address space.
1573 * The value passed in '*virt' is a suggested virtual address for
1574 * the mapping. Architectures which can support a direct-mapped
1575 * physical to virtual region can return the appropriate address
1576 * within that region, leaving '*virt' unchanged. Other
1577 * architectures should map the pages starting at '*virt' and
1578 * update '*virt' with the first usable address after the mapped
1582 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1584 vm_offset_t va, sva;
1585 vm_paddr_t superpage_offset;
1590 * Does the physical address range's size and alignment permit at
1591 * least one superpage mapping to be created?
1593 superpage_offset = start & PDRMASK;
1594 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1596 * Increase the starting virtual address so that its alignment
1597 * does not preclude the use of superpage mappings.
1599 if ((va & PDRMASK) < superpage_offset)
1600 va = (va & ~PDRMASK) + superpage_offset;
1601 else if ((va & PDRMASK) > superpage_offset)
1602 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1605 while (start < end) {
1606 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1608 KASSERT((va & PDRMASK) == 0,
1609 ("pmap_map: misaligned va %#x", va));
1610 newpde = start | PG_PS | pgeflag | PG_RW | PG_V;
1611 pmap_kenter_pde(va, newpde);
1615 pmap_kenter(va, start);
1620 pmap_invalidate_range(kernel_pmap, sva, va);
1627 * Add a list of wired pages to the kva
1628 * this routine is only used for temporary
1629 * kernel mappings that do not need to have
1630 * page modification or references recorded.
1631 * Note that old mappings are simply written
1632 * over. The page *must* be wired.
1633 * Note: SMP coherent. Uses a ranged shootdown IPI.
1636 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1638 pt_entry_t *endpte, oldpte, pa, *pte;
1643 endpte = pte + count;
1644 while (pte < endpte) {
1646 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1647 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1649 pte_store(pte, pa | pgeflag | PG_RW | PG_V);
1653 if (__predict_false((oldpte & PG_V) != 0))
1654 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1659 * This routine tears out page mappings from the
1660 * kernel -- it is meant only for temporary mappings.
1661 * Note: SMP coherent. Uses a ranged shootdown IPI.
1664 pmap_qremove(vm_offset_t sva, int count)
1669 while (count-- > 0) {
1673 pmap_invalidate_range(kernel_pmap, sva, va);
1676 /***************************************************
1677 * Page table page management routines.....
1678 ***************************************************/
1679 static __inline void
1680 pmap_free_zero_pages(struct spglist *free)
1684 while ((m = SLIST_FIRST(free)) != NULL) {
1685 SLIST_REMOVE_HEAD(free, plinks.s.ss);
1686 /* Preserve the page's PG_ZERO setting. */
1687 vm_page_free_toq(m);
1692 * Schedule the specified unused page table page to be freed. Specifically,
1693 * add the page to the specified list of pages that will be released to the
1694 * physical memory manager after the TLB has been updated.
1696 static __inline void
1697 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1698 boolean_t set_PG_ZERO)
1702 m->flags |= PG_ZERO;
1704 m->flags &= ~PG_ZERO;
1705 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1709 * Inserts the specified page table page into the specified pmap's collection
1710 * of idle page table pages. Each of a pmap's page table pages is responsible
1711 * for mapping a distinct range of virtual addresses. The pmap's collection is
1712 * ordered by this virtual address range.
1715 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1718 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1719 return (vm_radix_insert(&pmap->pm_root, mpte));
1723 * Removes the page table page mapping the specified virtual address from the
1724 * specified pmap's collection of idle page table pages, and returns it.
1725 * Otherwise, returns NULL if there is no page table page corresponding to the
1726 * specified virtual address.
1728 static __inline vm_page_t
1729 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
1732 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1733 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT));
1737 * Decrements a page table page's wire count, which is used to record the
1738 * number of valid page table entries within the page. If the wire count
1739 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1740 * page table page was unmapped and FALSE otherwise.
1742 static inline boolean_t
1743 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1747 if (m->wire_count == 0) {
1748 _pmap_unwire_ptp(pmap, m, free);
1755 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1760 * unmap the page table page
1762 pmap->pm_pdir[m->pindex] = 0;
1763 --pmap->pm_stats.resident_count;
1766 * This is a release store so that the ordinary store unmapping
1767 * the page table page is globally performed before TLB shoot-
1770 atomic_subtract_rel_int(&vm_cnt.v_wire_count, 1);
1773 * Do an invltlb to make the invalidated mapping
1774 * take effect immediately.
1776 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex);
1777 pmap_invalidate_page(pmap, pteva);
1780 * Put page on a list so that it is released after
1781 * *ALL* TLB shootdown is done
1783 pmap_add_delayed_free_list(m, free, TRUE);
1787 * After removing a page table entry, this routine is used to
1788 * conditionally free the page, and manage the hold/wire counts.
1791 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1796 if (va >= VM_MAXUSER_ADDRESS)
1798 ptepde = *pmap_pde(pmap, va);
1799 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1800 return (pmap_unwire_ptp(pmap, mpte, free));
1804 * Initialize the pmap for the swapper process.
1807 pmap_pinit0(pmap_t pmap)
1810 PMAP_LOCK_INIT(pmap);
1812 * Since the page table directory is shared with the kernel pmap,
1813 * which is already included in the list "allpmaps", this pmap does
1814 * not need to be inserted into that list.
1816 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD);
1817 #if defined(PAE) || defined(PAE_TABLES)
1818 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT);
1820 pmap->pm_root.rt_root = 0;
1821 CPU_ZERO(&pmap->pm_active);
1822 PCPU_SET(curpmap, pmap);
1823 TAILQ_INIT(&pmap->pm_pvchunk);
1824 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1828 * Initialize a preallocated and zeroed pmap structure,
1829 * such as one in a vmspace structure.
1832 pmap_pinit(pmap_t pmap)
1834 vm_page_t m, ptdpg[NPGPTD];
1839 * No need to allocate page table space yet but we do need a valid
1840 * page directory table.
1842 if (pmap->pm_pdir == NULL) {
1843 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
1844 if (pmap->pm_pdir == NULL)
1846 #if defined(PAE) || defined(PAE_TABLES)
1847 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
1848 KASSERT(((vm_offset_t)pmap->pm_pdpt &
1849 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
1850 ("pmap_pinit: pdpt misaligned"));
1851 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
1852 ("pmap_pinit: pdpt above 4g"));
1854 pmap->pm_root.rt_root = 0;
1856 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1857 ("pmap_pinit: pmap has reserved page table page(s)"));
1860 * allocate the page directory page(s)
1862 for (i = 0; i < NPGPTD;) {
1863 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1864 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1872 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD);
1874 for (i = 0; i < NPGPTD; i++)
1875 if ((ptdpg[i]->flags & PG_ZERO) == 0)
1876 pagezero(pmap->pm_pdir + (i * NPDEPG));
1878 mtx_lock_spin(&allpmaps_lock);
1879 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1880 /* Copy the kernel page table directory entries. */
1881 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t));
1882 mtx_unlock_spin(&allpmaps_lock);
1884 /* install self-referential address mapping entry(s) */
1885 for (i = 0; i < NPGPTD; i++) {
1886 pa = VM_PAGE_TO_PHYS(ptdpg[i]);
1887 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M;
1888 #if defined(PAE) || defined(PAE_TABLES)
1889 pmap->pm_pdpt[i] = pa | PG_V;
1893 CPU_ZERO(&pmap->pm_active);
1894 TAILQ_INIT(&pmap->pm_pvchunk);
1895 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1901 * this routine is called if the page table page is not
1905 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
1911 * Allocate a page table page.
1913 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1914 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1915 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
1917 rw_wunlock(&pvh_global_lock);
1919 rw_wlock(&pvh_global_lock);
1924 * Indicate the need to retry. While waiting, the page table
1925 * page may have been allocated.
1929 if ((m->flags & PG_ZERO) == 0)
1933 * Map the pagetable page into the process address space, if
1934 * it isn't already there.
1937 pmap->pm_stats.resident_count++;
1939 ptepa = VM_PAGE_TO_PHYS(m);
1940 pmap->pm_pdir[ptepindex] =
1941 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
1947 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
1954 * Calculate pagetable page index
1956 ptepindex = va >> PDRSHIFT;
1959 * Get the page directory entry
1961 ptepa = pmap->pm_pdir[ptepindex];
1964 * This supports switching from a 4MB page to a
1967 if (ptepa & PG_PS) {
1968 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
1969 ptepa = pmap->pm_pdir[ptepindex];
1973 * If the page table page is mapped, we just increment the
1974 * hold count, and activate it.
1977 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
1981 * Here if the pte page isn't mapped, or if it has
1984 m = _pmap_allocpte(pmap, ptepindex, flags);
1985 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
1992 /***************************************************
1993 * Pmap allocation/deallocation routines.
1994 ***************************************************/
1997 * Release any resources held by the given physical map.
1998 * Called when a pmap initialized by pmap_pinit is being released.
1999 * Should only be called if the map contains no valid mappings.
2002 pmap_release(pmap_t pmap)
2004 vm_page_t m, ptdpg[NPGPTD];
2007 KASSERT(pmap->pm_stats.resident_count == 0,
2008 ("pmap_release: pmap resident count %ld != 0",
2009 pmap->pm_stats.resident_count));
2010 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2011 ("pmap_release: pmap has reserved page table page(s)"));
2012 KASSERT(CPU_EMPTY(&pmap->pm_active),
2013 ("releasing active pmap %p", pmap));
2015 mtx_lock_spin(&allpmaps_lock);
2016 LIST_REMOVE(pmap, pm_list);
2017 mtx_unlock_spin(&allpmaps_lock);
2019 for (i = 0; i < NPGPTD; i++)
2020 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] &
2023 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) *
2024 sizeof(*pmap->pm_pdir));
2026 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2028 for (i = 0; i < NPGPTD; i++) {
2030 #if defined(PAE) || defined(PAE_TABLES)
2031 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2032 ("pmap_release: got wrong ptd page"));
2035 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2036 vm_page_free_zero(m);
2041 kvm_size(SYSCTL_HANDLER_ARGS)
2043 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2045 return (sysctl_handle_long(oidp, &ksize, 0, req));
2047 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2048 0, 0, kvm_size, "IU", "Size of KVM");
2051 kvm_free(SYSCTL_HANDLER_ARGS)
2053 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2055 return (sysctl_handle_long(oidp, &kfree, 0, req));
2057 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2058 0, 0, kvm_free, "IU", "Amount of KVM free");
2061 * grow the number of kernel page table entries, if needed
2064 pmap_growkernel(vm_offset_t addr)
2066 vm_paddr_t ptppaddr;
2070 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2071 addr = roundup2(addr, NBPDR);
2072 if (addr - 1 >= kernel_map->max_offset)
2073 addr = kernel_map->max_offset;
2074 while (kernel_vm_end < addr) {
2075 if (pdir_pde(PTD, kernel_vm_end)) {
2076 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2077 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2078 kernel_vm_end = kernel_map->max_offset;
2084 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2085 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2088 panic("pmap_growkernel: no memory to grow kernel");
2092 if ((nkpg->flags & PG_ZERO) == 0)
2093 pmap_zero_page(nkpg);
2094 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2095 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2096 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir;
2098 pmap_kenter_pde(kernel_vm_end, newpdir);
2099 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2100 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2101 kernel_vm_end = kernel_map->max_offset;
2108 /***************************************************
2109 * page management routines.
2110 ***************************************************/
2112 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2113 CTASSERT(_NPCM == 11);
2114 CTASSERT(_NPCPV == 336);
2116 static __inline struct pv_chunk *
2117 pv_to_chunk(pv_entry_t pv)
2120 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2123 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2125 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2126 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2128 static const uint32_t pc_freemask[_NPCM] = {
2129 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2130 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2131 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2132 PC_FREE0_9, PC_FREE10
2135 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2136 "Current number of pv entries");
2139 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2141 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2142 "Current number of pv entry chunks");
2143 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2144 "Current number of pv entry chunks allocated");
2145 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2146 "Current number of pv entry chunks frees");
2147 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2148 "Number of times tried to get a chunk page but failed.");
2150 static long pv_entry_frees, pv_entry_allocs;
2151 static int pv_entry_spare;
2153 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2154 "Current number of pv entry frees");
2155 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2156 "Current number of pv entry allocs");
2157 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2158 "Current number of spare pv entries");
2162 * We are in a serious low memory condition. Resort to
2163 * drastic measures to free some pages so we can allocate
2164 * another pv entry chunk.
2167 pmap_pv_reclaim(pmap_t locked_pmap)
2170 struct pv_chunk *pc;
2171 struct md_page *pvh;
2174 pt_entry_t *pte, tpte;
2178 struct spglist free;
2180 int bit, field, freed;
2182 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2186 TAILQ_INIT(&newtail);
2187 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2188 SLIST_EMPTY(&free))) {
2189 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2190 if (pmap != pc->pc_pmap) {
2192 pmap_invalidate_all(pmap);
2193 if (pmap != locked_pmap)
2197 /* Avoid deadlock and lock recursion. */
2198 if (pmap > locked_pmap)
2200 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2202 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2208 * Destroy every non-wired, 4 KB page mapping in the chunk.
2211 for (field = 0; field < _NPCM; field++) {
2212 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2213 inuse != 0; inuse &= ~(1UL << bit)) {
2215 pv = &pc->pc_pventry[field * 32 + bit];
2217 pde = pmap_pde(pmap, va);
2218 if ((*pde & PG_PS) != 0)
2220 pte = pmap_pte(pmap, va);
2222 if ((tpte & PG_W) == 0)
2223 tpte = pte_load_clear(pte);
2224 pmap_pte_release(pte);
2225 if ((tpte & PG_W) != 0)
2228 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2230 if ((tpte & PG_G) != 0)
2231 pmap_invalidate_page(pmap, va);
2232 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2233 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2235 if ((tpte & PG_A) != 0)
2236 vm_page_aflag_set(m, PGA_REFERENCED);
2237 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2238 if (TAILQ_EMPTY(&m->md.pv_list) &&
2239 (m->flags & PG_FICTITIOUS) == 0) {
2240 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2241 if (TAILQ_EMPTY(&pvh->pv_list)) {
2242 vm_page_aflag_clear(m,
2246 pc->pc_map[field] |= 1UL << bit;
2247 pmap_unuse_pt(pmap, va, &free);
2252 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2255 /* Every freed mapping is for a 4 KB page. */
2256 pmap->pm_stats.resident_count -= freed;
2257 PV_STAT(pv_entry_frees += freed);
2258 PV_STAT(pv_entry_spare += freed);
2259 pv_entry_count -= freed;
2260 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2261 for (field = 0; field < _NPCM; field++)
2262 if (pc->pc_map[field] != pc_freemask[field]) {
2263 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2265 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2268 * One freed pv entry in locked_pmap is
2271 if (pmap == locked_pmap)
2275 if (field == _NPCM) {
2276 PV_STAT(pv_entry_spare -= _NPCPV);
2277 PV_STAT(pc_chunk_count--);
2278 PV_STAT(pc_chunk_frees++);
2279 /* Entire chunk is free; return it. */
2280 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2281 pmap_qremove((vm_offset_t)pc, 1);
2282 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2287 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2289 pmap_invalidate_all(pmap);
2290 if (pmap != locked_pmap)
2293 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2294 m_pc = SLIST_FIRST(&free);
2295 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2296 /* Recycle a freed page table page. */
2297 m_pc->wire_count = 1;
2298 atomic_add_int(&vm_cnt.v_wire_count, 1);
2300 pmap_free_zero_pages(&free);
2305 * free the pv_entry back to the free list
2308 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2310 struct pv_chunk *pc;
2311 int idx, field, bit;
2313 rw_assert(&pvh_global_lock, RA_WLOCKED);
2314 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2315 PV_STAT(pv_entry_frees++);
2316 PV_STAT(pv_entry_spare++);
2318 pc = pv_to_chunk(pv);
2319 idx = pv - &pc->pc_pventry[0];
2322 pc->pc_map[field] |= 1ul << bit;
2323 for (idx = 0; idx < _NPCM; idx++)
2324 if (pc->pc_map[idx] != pc_freemask[idx]) {
2326 * 98% of the time, pc is already at the head of the
2327 * list. If it isn't already, move it to the head.
2329 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2331 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2332 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2337 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2342 free_pv_chunk(struct pv_chunk *pc)
2346 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2347 PV_STAT(pv_entry_spare -= _NPCPV);
2348 PV_STAT(pc_chunk_count--);
2349 PV_STAT(pc_chunk_frees++);
2350 /* entire chunk is free, return it */
2351 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2352 pmap_qremove((vm_offset_t)pc, 1);
2353 vm_page_unwire(m, PQ_NONE);
2355 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2359 * get a new pv_entry, allocating a block from the system
2363 get_pv_entry(pmap_t pmap, boolean_t try)
2365 static const struct timeval printinterval = { 60, 0 };
2366 static struct timeval lastprint;
2369 struct pv_chunk *pc;
2372 rw_assert(&pvh_global_lock, RA_WLOCKED);
2373 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2374 PV_STAT(pv_entry_allocs++);
2376 if (pv_entry_count > pv_entry_high_water)
2377 if (ratecheck(&lastprint, &printinterval))
2378 printf("Approaching the limit on PV entries, consider "
2379 "increasing either the vm.pmap.shpgperproc or the "
2380 "vm.pmap.pv_entry_max tunable.\n");
2382 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2384 for (field = 0; field < _NPCM; field++) {
2385 if (pc->pc_map[field]) {
2386 bit = bsfl(pc->pc_map[field]);
2390 if (field < _NPCM) {
2391 pv = &pc->pc_pventry[field * 32 + bit];
2392 pc->pc_map[field] &= ~(1ul << bit);
2393 /* If this was the last item, move it to tail */
2394 for (field = 0; field < _NPCM; field++)
2395 if (pc->pc_map[field] != 0) {
2396 PV_STAT(pv_entry_spare--);
2397 return (pv); /* not full, return */
2399 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2400 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2401 PV_STAT(pv_entry_spare--);
2406 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2407 * global lock. If "pv_vafree" is currently non-empty, it will
2408 * remain non-empty until pmap_ptelist_alloc() completes.
2410 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2411 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2414 PV_STAT(pc_chunk_tryfail++);
2417 m = pmap_pv_reclaim(pmap);
2421 PV_STAT(pc_chunk_count++);
2422 PV_STAT(pc_chunk_allocs++);
2423 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2424 pmap_qenter((vm_offset_t)pc, &m, 1);
2426 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2427 for (field = 1; field < _NPCM; field++)
2428 pc->pc_map[field] = pc_freemask[field];
2429 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2430 pv = &pc->pc_pventry[0];
2431 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2432 PV_STAT(pv_entry_spare += _NPCPV - 1);
2436 static __inline pv_entry_t
2437 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2441 rw_assert(&pvh_global_lock, RA_WLOCKED);
2442 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2443 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2444 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2452 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2454 struct md_page *pvh;
2456 vm_offset_t va_last;
2459 rw_assert(&pvh_global_lock, RA_WLOCKED);
2460 KASSERT((pa & PDRMASK) == 0,
2461 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2464 * Transfer the 4mpage's pv entry for this mapping to the first
2467 pvh = pa_to_pvh(pa);
2468 va = trunc_4mpage(va);
2469 pv = pmap_pvh_remove(pvh, pmap, va);
2470 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2471 m = PHYS_TO_VM_PAGE(pa);
2472 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2473 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2474 va_last = va + NBPDR - PAGE_SIZE;
2477 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2478 ("pmap_pv_demote_pde: page %p is not managed", m));
2480 pmap_insert_entry(pmap, va, m);
2481 } while (va < va_last);
2485 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2487 struct md_page *pvh;
2489 vm_offset_t va_last;
2492 rw_assert(&pvh_global_lock, RA_WLOCKED);
2493 KASSERT((pa & PDRMASK) == 0,
2494 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2497 * Transfer the first page's pv entry for this mapping to the
2498 * 4mpage's pv list. Aside from avoiding the cost of a call
2499 * to get_pv_entry(), a transfer avoids the possibility that
2500 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2501 * removes one of the mappings that is being promoted.
2503 m = PHYS_TO_VM_PAGE(pa);
2504 va = trunc_4mpage(va);
2505 pv = pmap_pvh_remove(&m->md, pmap, va);
2506 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2507 pvh = pa_to_pvh(pa);
2508 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2509 /* Free the remaining NPTEPG - 1 pv entries. */
2510 va_last = va + NBPDR - PAGE_SIZE;
2514 pmap_pvh_free(&m->md, pmap, va);
2515 } while (va < va_last);
2519 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2523 pv = pmap_pvh_remove(pvh, pmap, va);
2524 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2525 free_pv_entry(pmap, pv);
2529 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2531 struct md_page *pvh;
2533 rw_assert(&pvh_global_lock, RA_WLOCKED);
2534 pmap_pvh_free(&m->md, pmap, va);
2535 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2536 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2537 if (TAILQ_EMPTY(&pvh->pv_list))
2538 vm_page_aflag_clear(m, PGA_WRITEABLE);
2543 * Create a pv entry for page at pa for
2547 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2551 rw_assert(&pvh_global_lock, RA_WLOCKED);
2552 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2553 pv = get_pv_entry(pmap, FALSE);
2555 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2559 * Conditionally create a pv entry.
2562 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2566 rw_assert(&pvh_global_lock, RA_WLOCKED);
2567 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2568 if (pv_entry_count < pv_entry_high_water &&
2569 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2571 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2578 * Create the pv entries for each of the pages within a superpage.
2581 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2583 struct md_page *pvh;
2586 rw_assert(&pvh_global_lock, RA_WLOCKED);
2587 if (pv_entry_count < pv_entry_high_water &&
2588 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2590 pvh = pa_to_pvh(pa);
2591 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2598 * Fills a page table page with mappings to consecutive physical pages.
2601 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2605 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2607 newpte += PAGE_SIZE;
2612 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2613 * 2- or 4MB page mapping is invalidated.
2616 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2618 pd_entry_t newpde, oldpde;
2619 pt_entry_t *firstpte, newpte;
2622 struct spglist free;
2624 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2626 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2627 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2628 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
2630 KASSERT((oldpde & PG_W) == 0,
2631 ("pmap_demote_pde: page table page for a wired mapping"
2635 * Invalidate the 2- or 4MB page mapping and return
2636 * "failure" if the mapping was never accessed or the
2637 * allocation of the new page table page fails.
2639 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2640 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2641 VM_ALLOC_WIRED)) == NULL) {
2643 pmap_remove_pde(pmap, pde, trunc_4mpage(va), &free);
2644 pmap_invalidate_page(pmap, trunc_4mpage(va));
2645 pmap_free_zero_pages(&free);
2646 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2647 " in pmap %p", va, pmap);
2650 if (va < VM_MAXUSER_ADDRESS)
2651 pmap->pm_stats.resident_count++;
2653 mptepa = VM_PAGE_TO_PHYS(mpte);
2656 * If the page mapping is in the kernel's address space, then the
2657 * KPTmap can provide access to the page table page. Otherwise,
2658 * temporarily map the page table page (mpte) into the kernel's
2659 * address space at either PADDR1 or PADDR2.
2662 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2663 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2664 if ((*PMAP1 & PG_FRAME) != mptepa) {
2665 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2667 PMAP1cpu = PCPU_GET(cpuid);
2673 if (PMAP1cpu != PCPU_GET(cpuid)) {
2674 PMAP1cpu = PCPU_GET(cpuid);
2682 mtx_lock(&PMAP2mutex);
2683 if ((*PMAP2 & PG_FRAME) != mptepa) {
2684 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2685 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2689 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2690 KASSERT((oldpde & PG_A) != 0,
2691 ("pmap_demote_pde: oldpde is missing PG_A"));
2692 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2693 ("pmap_demote_pde: oldpde is missing PG_M"));
2694 newpte = oldpde & ~PG_PS;
2695 if ((newpte & PG_PDE_PAT) != 0)
2696 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2699 * If the page table page is new, initialize it.
2701 if (mpte->wire_count == 1) {
2702 mpte->wire_count = NPTEPG;
2703 pmap_fill_ptp(firstpte, newpte);
2705 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2706 ("pmap_demote_pde: firstpte and newpte map different physical"
2710 * If the mapping has changed attributes, update the page table
2713 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2714 pmap_fill_ptp(firstpte, newpte);
2717 * Demote the mapping. This pmap is locked. The old PDE has
2718 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2719 * set. Thus, there is no danger of a race with another
2720 * processor changing the setting of PG_A and/or PG_M between
2721 * the read above and the store below.
2723 if (workaround_erratum383)
2724 pmap_update_pde(pmap, va, pde, newpde);
2725 else if (pmap == kernel_pmap)
2726 pmap_kenter_pde(va, newpde);
2728 pde_store(pde, newpde);
2729 if (firstpte == PADDR2)
2730 mtx_unlock(&PMAP2mutex);
2733 * Invalidate the recursive mapping of the page table page.
2735 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2738 * Demote the pv entry. This depends on the earlier demotion
2739 * of the mapping. Specifically, the (re)creation of a per-
2740 * page pv entry might trigger the execution of pmap_collect(),
2741 * which might reclaim a newly (re)created per-page pv entry
2742 * and destroy the associated mapping. In order to destroy
2743 * the mapping, the PDE must have already changed from mapping
2744 * the 2mpage to referencing the page table page.
2746 if ((oldpde & PG_MANAGED) != 0)
2747 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2749 pmap_pde_demotions++;
2750 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2751 " in pmap %p", va, pmap);
2756 * Removes a 2- or 4MB page mapping from the kernel pmap.
2759 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2765 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2766 mpte = pmap_remove_pt_page(pmap, va);
2768 panic("pmap_remove_kernel_pde: Missing pt page.");
2770 mptepa = VM_PAGE_TO_PHYS(mpte);
2771 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2774 * Initialize the page table page.
2776 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2779 * Remove the mapping.
2781 if (workaround_erratum383)
2782 pmap_update_pde(pmap, va, pde, newpde);
2784 pmap_kenter_pde(va, newpde);
2787 * Invalidate the recursive mapping of the page table page.
2789 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2793 * pmap_remove_pde: do the things to unmap a superpage in a process
2796 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2797 struct spglist *free)
2799 struct md_page *pvh;
2801 vm_offset_t eva, va;
2804 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2805 KASSERT((sva & PDRMASK) == 0,
2806 ("pmap_remove_pde: sva is not 4mpage aligned"));
2807 oldpde = pte_load_clear(pdq);
2809 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2812 * Machines that don't support invlpg, also don't support
2816 pmap_invalidate_page(kernel_pmap, sva);
2817 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2818 if (oldpde & PG_MANAGED) {
2819 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2820 pmap_pvh_free(pvh, pmap, sva);
2822 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2823 va < eva; va += PAGE_SIZE, m++) {
2824 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2827 vm_page_aflag_set(m, PGA_REFERENCED);
2828 if (TAILQ_EMPTY(&m->md.pv_list) &&
2829 TAILQ_EMPTY(&pvh->pv_list))
2830 vm_page_aflag_clear(m, PGA_WRITEABLE);
2833 if (pmap == kernel_pmap) {
2834 pmap_remove_kernel_pde(pmap, pdq, sva);
2836 mpte = pmap_remove_pt_page(pmap, sva);
2838 pmap->pm_stats.resident_count--;
2839 KASSERT(mpte->wire_count == NPTEPG,
2840 ("pmap_remove_pde: pte page wire count error"));
2841 mpte->wire_count = 0;
2842 pmap_add_delayed_free_list(mpte, free, FALSE);
2843 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2849 * pmap_remove_pte: do the things to unmap a page in a process
2852 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
2853 struct spglist *free)
2858 rw_assert(&pvh_global_lock, RA_WLOCKED);
2859 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2860 oldpte = pte_load_clear(ptq);
2861 KASSERT(oldpte != 0,
2862 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
2864 pmap->pm_stats.wired_count -= 1;
2866 * Machines that don't support invlpg, also don't support
2870 pmap_invalidate_page(kernel_pmap, va);
2871 pmap->pm_stats.resident_count -= 1;
2872 if (oldpte & PG_MANAGED) {
2873 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2874 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2877 vm_page_aflag_set(m, PGA_REFERENCED);
2878 pmap_remove_entry(pmap, m, va);
2880 return (pmap_unuse_pt(pmap, va, free));
2884 * Remove a single page from a process address space
2887 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
2891 rw_assert(&pvh_global_lock, RA_WLOCKED);
2892 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
2893 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2894 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
2896 pmap_remove_pte(pmap, pte, va, free);
2897 pmap_invalidate_page(pmap, va);
2901 * Remove the given range of addresses from the specified map.
2903 * It is assumed that the start and end are properly
2904 * rounded to the page size.
2907 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2912 struct spglist free;
2916 * Perform an unsynchronized read. This is, however, safe.
2918 if (pmap->pm_stats.resident_count == 0)
2924 rw_wlock(&pvh_global_lock);
2929 * special handling of removing one page. a very
2930 * common operation and easy to short circuit some
2933 if ((sva + PAGE_SIZE == eva) &&
2934 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
2935 pmap_remove_page(pmap, sva, &free);
2939 for (; sva < eva; sva = pdnxt) {
2943 * Calculate index for next page table.
2945 pdnxt = (sva + NBPDR) & ~PDRMASK;
2948 if (pmap->pm_stats.resident_count == 0)
2951 pdirindex = sva >> PDRSHIFT;
2952 ptpaddr = pmap->pm_pdir[pdirindex];
2955 * Weed out invalid mappings. Note: we assume that the page
2956 * directory table is always allocated, and in kernel virtual.
2962 * Check for large page.
2964 if ((ptpaddr & PG_PS) != 0) {
2966 * Are we removing the entire large page? If not,
2967 * demote the mapping and fall through.
2969 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
2971 * The TLB entry for a PG_G mapping is
2972 * invalidated by pmap_remove_pde().
2974 if ((ptpaddr & PG_G) == 0)
2976 pmap_remove_pde(pmap,
2977 &pmap->pm_pdir[pdirindex], sva, &free);
2979 } else if (!pmap_demote_pde(pmap,
2980 &pmap->pm_pdir[pdirindex], sva)) {
2981 /* The large page mapping was destroyed. */
2987 * Limit our scan to either the end of the va represented
2988 * by the current page table page, or to the end of the
2989 * range being removed.
2994 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3000 * The TLB entry for a PG_G mapping is invalidated
3001 * by pmap_remove_pte().
3003 if ((*pte & PG_G) == 0)
3005 if (pmap_remove_pte(pmap, pte, sva, &free))
3012 pmap_invalidate_all(pmap);
3013 rw_wunlock(&pvh_global_lock);
3015 pmap_free_zero_pages(&free);
3019 * Routine: pmap_remove_all
3021 * Removes this physical page from
3022 * all physical maps in which it resides.
3023 * Reflects back modify bits to the pager.
3026 * Original versions of this routine were very
3027 * inefficient because they iteratively called
3028 * pmap_remove (slow...)
3032 pmap_remove_all(vm_page_t m)
3034 struct md_page *pvh;
3037 pt_entry_t *pte, tpte;
3040 struct spglist free;
3042 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3043 ("pmap_remove_all: page %p is not managed", m));
3045 rw_wlock(&pvh_global_lock);
3047 if ((m->flags & PG_FICTITIOUS) != 0)
3048 goto small_mappings;
3049 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3050 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3054 pde = pmap_pde(pmap, va);
3055 (void)pmap_demote_pde(pmap, pde, va);
3059 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3062 pmap->pm_stats.resident_count--;
3063 pde = pmap_pde(pmap, pv->pv_va);
3064 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3065 " a 4mpage in page %p's pv list", m));
3066 pte = pmap_pte_quick(pmap, pv->pv_va);
3067 tpte = pte_load_clear(pte);
3068 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3071 pmap->pm_stats.wired_count--;
3073 vm_page_aflag_set(m, PGA_REFERENCED);
3076 * Update the vm_page_t clean and reference bits.
3078 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3080 pmap_unuse_pt(pmap, pv->pv_va, &free);
3081 pmap_invalidate_page(pmap, pv->pv_va);
3082 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3083 free_pv_entry(pmap, pv);
3086 vm_page_aflag_clear(m, PGA_WRITEABLE);
3088 rw_wunlock(&pvh_global_lock);
3089 pmap_free_zero_pages(&free);
3093 * pmap_protect_pde: do the things to protect a 4mpage in a process
3096 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3098 pd_entry_t newpde, oldpde;
3099 vm_offset_t eva, va;
3101 boolean_t anychanged;
3103 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3104 KASSERT((sva & PDRMASK) == 0,
3105 ("pmap_protect_pde: sva is not 4mpage aligned"));
3108 oldpde = newpde = *pde;
3109 if (oldpde & PG_MANAGED) {
3111 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3112 va < eva; va += PAGE_SIZE, m++)
3113 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3116 if ((prot & VM_PROT_WRITE) == 0)
3117 newpde &= ~(PG_RW | PG_M);
3118 #if defined(PAE) || defined(PAE_TABLES)
3119 if ((prot & VM_PROT_EXECUTE) == 0)
3122 if (newpde != oldpde) {
3123 if (!pde_cmpset(pde, oldpde, newpde))
3126 pmap_invalidate_page(pmap, sva);
3130 return (anychanged);
3134 * Set the physical protection on the
3135 * specified range of this map as requested.
3138 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3143 boolean_t anychanged, pv_lists_locked;
3145 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3146 if (prot == VM_PROT_NONE) {
3147 pmap_remove(pmap, sva, eva);
3151 #if defined(PAE) || defined(PAE_TABLES)
3152 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3153 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3156 if (prot & VM_PROT_WRITE)
3160 if (pmap_is_current(pmap))
3161 pv_lists_locked = FALSE;
3163 pv_lists_locked = TRUE;
3165 rw_wlock(&pvh_global_lock);
3171 for (; sva < eva; sva = pdnxt) {
3172 pt_entry_t obits, pbits;
3175 pdnxt = (sva + NBPDR) & ~PDRMASK;
3179 pdirindex = sva >> PDRSHIFT;
3180 ptpaddr = pmap->pm_pdir[pdirindex];
3183 * Weed out invalid mappings. Note: we assume that the page
3184 * directory table is always allocated, and in kernel virtual.
3190 * Check for large page.
3192 if ((ptpaddr & PG_PS) != 0) {
3194 * Are we protecting the entire large page? If not,
3195 * demote the mapping and fall through.
3197 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3199 * The TLB entry for a PG_G mapping is
3200 * invalidated by pmap_protect_pde().
3202 if (pmap_protect_pde(pmap,
3203 &pmap->pm_pdir[pdirindex], sva, prot))
3207 if (!pv_lists_locked) {
3208 pv_lists_locked = TRUE;
3209 if (!rw_try_wlock(&pvh_global_lock)) {
3211 pmap_invalidate_all(
3218 if (!pmap_demote_pde(pmap,
3219 &pmap->pm_pdir[pdirindex], sva)) {
3221 * The large page mapping was
3232 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3238 * Regardless of whether a pte is 32 or 64 bits in
3239 * size, PG_RW, PG_A, and PG_M are among the least
3240 * significant 32 bits.
3242 obits = pbits = *pte;
3243 if ((pbits & PG_V) == 0)
3246 if ((prot & VM_PROT_WRITE) == 0) {
3247 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3248 (PG_MANAGED | PG_M | PG_RW)) {
3249 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3252 pbits &= ~(PG_RW | PG_M);
3254 #if defined(PAE) || defined(PAE_TABLES)
3255 if ((prot & VM_PROT_EXECUTE) == 0)
3259 if (pbits != obits) {
3260 #if defined(PAE) || defined(PAE_TABLES)
3261 if (!atomic_cmpset_64(pte, obits, pbits))
3264 if (!atomic_cmpset_int((u_int *)pte, obits,
3269 pmap_invalidate_page(pmap, sva);
3276 pmap_invalidate_all(pmap);
3277 if (pv_lists_locked) {
3279 rw_wunlock(&pvh_global_lock);
3285 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3286 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3287 * For promotion to occur, two conditions must be met: (1) the 4KB page
3288 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3289 * mappings must have identical characteristics.
3291 * Managed (PG_MANAGED) mappings within the kernel address space are not
3292 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3293 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3297 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3300 pt_entry_t *firstpte, oldpte, pa, *pte;
3301 vm_offset_t oldpteva;
3304 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3307 * Examine the first PTE in the specified PTP. Abort if this PTE is
3308 * either invalid, unused, or does not map the first 4KB physical page
3309 * within a 2- or 4MB page.
3311 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3314 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3315 pmap_pde_p_failures++;
3316 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3317 " in pmap %p", va, pmap);
3320 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3321 pmap_pde_p_failures++;
3322 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3323 " in pmap %p", va, pmap);
3326 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3328 * When PG_M is already clear, PG_RW can be cleared without
3329 * a TLB invalidation.
3331 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3338 * Examine each of the other PTEs in the specified PTP. Abort if this
3339 * PTE maps an unexpected 4KB physical page or does not have identical
3340 * characteristics to the first PTE.
3342 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3343 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3346 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3347 pmap_pde_p_failures++;
3348 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3349 " in pmap %p", va, pmap);
3352 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3354 * When PG_M is already clear, PG_RW can be cleared
3355 * without a TLB invalidation.
3357 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3361 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3363 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3364 " in pmap %p", oldpteva, pmap);
3366 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3367 pmap_pde_p_failures++;
3368 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3369 " in pmap %p", va, pmap);
3376 * Save the page table page in its current state until the PDE
3377 * mapping the superpage is demoted by pmap_demote_pde() or
3378 * destroyed by pmap_remove_pde().
3380 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3381 KASSERT(mpte >= vm_page_array &&
3382 mpte < &vm_page_array[vm_page_array_size],
3383 ("pmap_promote_pde: page table page is out of range"));
3384 KASSERT(mpte->pindex == va >> PDRSHIFT,
3385 ("pmap_promote_pde: page table page's pindex is wrong"));
3386 if (pmap_insert_pt_page(pmap, mpte)) {
3387 pmap_pde_p_failures++;
3389 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3395 * Promote the pv entries.
3397 if ((newpde & PG_MANAGED) != 0)
3398 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3401 * Propagate the PAT index to its proper position.
3403 if ((newpde & PG_PTE_PAT) != 0)
3404 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3407 * Map the superpage.
3409 if (workaround_erratum383)
3410 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3411 else if (pmap == kernel_pmap)
3412 pmap_kenter_pde(va, PG_PS | newpde);
3414 pde_store(pde, PG_PS | newpde);
3416 pmap_pde_promotions++;
3417 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3418 " in pmap %p", va, pmap);
3422 * Insert the given physical page (p) at
3423 * the specified virtual address (v) in the
3424 * target physical map with the protection requested.
3426 * If specified, the page will be wired down, meaning
3427 * that the related pte can not be reclaimed.
3429 * NB: This is the only routine which MAY NOT lazy-evaluate
3430 * or lose information. That is, this routine must actually
3431 * insert this page into the given map NOW.
3434 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3435 u_int flags, int8_t psind)
3439 pt_entry_t newpte, origpte;
3443 boolean_t invlva, wired;
3445 va = trunc_page(va);
3447 wired = (flags & PMAP_ENTER_WIRED) != 0;
3449 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
3450 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
3451 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)",
3453 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3454 VM_OBJECT_ASSERT_LOCKED(m->object);
3456 rw_wlock(&pvh_global_lock);
3460 pde = pmap_pde(pmap, va);
3461 if (va < VM_MAXUSER_ADDRESS) {
3464 * In the case that a page table page is not resident,
3465 * we are creating it here. pmap_allocpte() handles
3468 mpte = pmap_allocpte(pmap, va, flags);
3470 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3471 ("pmap_allocpte failed with sleep allowed"));
3473 rw_wunlock(&pvh_global_lock);
3475 return (KERN_RESOURCE_SHORTAGE);
3479 * va is for KVA, so pmap_demote_pde() will never fail
3480 * to install a page table page. PG_V is also
3481 * asserted by pmap_demote_pde().
3483 KASSERT(pde != NULL && (*pde & PG_V) != 0,
3484 ("KVA %#x invalid pde pdir %#jx", va,
3485 (uintmax_t)pmap->pm_pdir[PTDPTDI]));
3486 if ((*pde & PG_PS) != 0)
3487 pmap_demote_pde(pmap, pde, va);
3489 pte = pmap_pte_quick(pmap, va);
3492 * Page Directory table entry is not valid, which should not
3493 * happen. We should have either allocated the page table
3494 * page or demoted the existing mapping above.
3497 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3498 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3501 pa = VM_PAGE_TO_PHYS(m);
3504 opa = origpte & PG_FRAME;
3507 * Mapping has not changed, must be protection or wiring change.
3509 if (origpte && (opa == pa)) {
3511 * Wiring change, just update stats. We don't worry about
3512 * wiring PT pages as they remain resident as long as there
3513 * are valid mappings in them. Hence, if a user page is wired,
3514 * the PT page will be also.
3516 if (wired && ((origpte & PG_W) == 0))
3517 pmap->pm_stats.wired_count++;
3518 else if (!wired && (origpte & PG_W))
3519 pmap->pm_stats.wired_count--;
3522 * Remove extra pte reference
3527 if (origpte & PG_MANAGED) {
3537 * Mapping has changed, invalidate old range and fall through to
3538 * handle validating new mapping.
3542 pmap->pm_stats.wired_count--;
3543 if (origpte & PG_MANAGED) {
3544 om = PHYS_TO_VM_PAGE(opa);
3545 pv = pmap_pvh_remove(&om->md, pmap, va);
3549 KASSERT(mpte->wire_count > 0,
3550 ("pmap_enter: missing reference to page table page,"
3554 pmap->pm_stats.resident_count++;
3557 * Enter on the PV list if part of our managed memory.
3559 if ((m->oflags & VPO_UNMANAGED) == 0) {
3560 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3561 ("pmap_enter: managed mapping within the clean submap"));
3563 pv = get_pv_entry(pmap, FALSE);
3565 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3567 } else if (pv != NULL)
3568 free_pv_entry(pmap, pv);
3571 * Increment counters
3574 pmap->pm_stats.wired_count++;
3578 * Now validate mapping with desired protection/wiring.
3580 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V);
3581 if ((prot & VM_PROT_WRITE) != 0) {
3583 if ((newpte & PG_MANAGED) != 0)
3584 vm_page_aflag_set(m, PGA_WRITEABLE);
3586 #if defined(PAE) || defined(PAE_TABLES)
3587 if ((prot & VM_PROT_EXECUTE) == 0)
3592 if (va < VM_MAXUSER_ADDRESS)
3594 if (pmap == kernel_pmap)
3598 * if the mapping or permission bits are different, we need
3599 * to update the pte.
3601 if ((origpte & ~(PG_M|PG_A)) != newpte) {
3603 if ((flags & VM_PROT_WRITE) != 0)
3605 if (origpte & PG_V) {
3607 origpte = pte_load_store(pte, newpte);
3608 if (origpte & PG_A) {
3609 if (origpte & PG_MANAGED)
3610 vm_page_aflag_set(om, PGA_REFERENCED);
3611 if (opa != VM_PAGE_TO_PHYS(m))
3613 #if defined(PAE) || defined(PAE_TABLES)
3614 if ((origpte & PG_NX) == 0 &&
3615 (newpte & PG_NX) != 0)
3619 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
3620 if ((origpte & PG_MANAGED) != 0)
3622 if ((prot & VM_PROT_WRITE) == 0)
3625 if ((origpte & PG_MANAGED) != 0 &&
3626 TAILQ_EMPTY(&om->md.pv_list) &&
3627 ((om->flags & PG_FICTITIOUS) != 0 ||
3628 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3629 vm_page_aflag_clear(om, PGA_WRITEABLE);
3631 pmap_invalidate_page(pmap, va);
3633 pte_store(pte, newpte);
3637 * If both the page table page and the reservation are fully
3638 * populated, then attempt promotion.
3640 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3641 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3642 vm_reserv_level_iffullpop(m) == 0)
3643 pmap_promote_pde(pmap, pde, va);
3646 rw_wunlock(&pvh_global_lock);
3648 return (KERN_SUCCESS);
3652 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and
3653 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
3654 * blocking, (2) a mapping already exists at the specified virtual address, or
3655 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3658 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3660 pd_entry_t *pde, newpde;
3662 rw_assert(&pvh_global_lock, RA_WLOCKED);
3663 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3664 pde = pmap_pde(pmap, va);
3666 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3667 " in pmap %p", va, pmap);
3670 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3672 if ((m->oflags & VPO_UNMANAGED) == 0) {
3673 newpde |= PG_MANAGED;
3676 * Abort this mapping if its PV entry could not be created.
3678 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) {
3679 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3680 " in pmap %p", va, pmap);
3684 #if defined(PAE) || defined(PAE_TABLES)
3685 if ((prot & VM_PROT_EXECUTE) == 0)
3688 if (va < VM_MAXUSER_ADDRESS)
3692 * Increment counters.
3694 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3697 * Map the superpage.
3699 pde_store(pde, newpde);
3701 pmap_pde_mappings++;
3702 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3703 " in pmap %p", va, pmap);
3708 * Maps a sequence of resident pages belonging to the same object.
3709 * The sequence begins with the given page m_start. This page is
3710 * mapped at the given virtual address start. Each subsequent page is
3711 * mapped at a virtual address that is offset from start by the same
3712 * amount as the page is offset from m_start within the object. The
3713 * last page in the sequence is the page with the largest offset from
3714 * m_start that can be mapped at a virtual address less than the given
3715 * virtual address end. Not every virtual page between start and end
3716 * is mapped; only those for which a resident page exists with the
3717 * corresponding offset from m_start are mapped.
3720 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3721 vm_page_t m_start, vm_prot_t prot)
3725 vm_pindex_t diff, psize;
3727 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3729 psize = atop(end - start);
3732 rw_wlock(&pvh_global_lock);
3734 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3735 va = start + ptoa(diff);
3736 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3737 m->psind == 1 && pg_ps_enabled &&
3738 pmap_enter_pde(pmap, va, m, prot))
3739 m = &m[NBPDR / PAGE_SIZE - 1];
3741 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3743 m = TAILQ_NEXT(m, listq);
3745 rw_wunlock(&pvh_global_lock);
3750 * this code makes some *MAJOR* assumptions:
3751 * 1. Current pmap & pmap exists.
3754 * 4. No page table pages.
3755 * but is *MUCH* faster than pmap_enter...
3759 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3762 rw_wlock(&pvh_global_lock);
3764 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
3765 rw_wunlock(&pvh_global_lock);
3770 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3771 vm_prot_t prot, vm_page_t mpte)
3775 struct spglist free;
3777 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3778 (m->oflags & VPO_UNMANAGED) != 0,
3779 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3780 rw_assert(&pvh_global_lock, RA_WLOCKED);
3781 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3784 * In the case that a page table page is not
3785 * resident, we are creating it here.
3787 if (va < VM_MAXUSER_ADDRESS) {
3792 * Calculate pagetable page index
3794 ptepindex = va >> PDRSHIFT;
3795 if (mpte && (mpte->pindex == ptepindex)) {
3799 * Get the page directory entry
3801 ptepa = pmap->pm_pdir[ptepindex];
3804 * If the page table page is mapped, we just increment
3805 * the hold count, and activate it.
3810 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
3813 mpte = _pmap_allocpte(pmap, ptepindex,
3814 PMAP_ENTER_NOSLEEP);
3824 * This call to vtopte makes the assumption that we are
3825 * entering the page into the current pmap. In order to support
3826 * quick entry into any pmap, one would likely use pmap_pte_quick.
3827 * But that isn't as quick as vtopte.
3839 * Enter on the PV list if part of our managed memory.
3841 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3842 !pmap_try_insert_pv_entry(pmap, va, m)) {
3845 if (pmap_unwire_ptp(pmap, mpte, &free)) {
3846 pmap_invalidate_page(pmap, va);
3847 pmap_free_zero_pages(&free);
3856 * Increment counters
3858 pmap->pm_stats.resident_count++;
3860 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3861 #if defined(PAE) || defined(PAE_TABLES)
3862 if ((prot & VM_PROT_EXECUTE) == 0)
3867 * Now validate mapping with RO protection
3869 if ((m->oflags & VPO_UNMANAGED) != 0)
3870 pte_store(pte, pa | PG_V | PG_U);
3872 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3877 * Make a temporary mapping for a physical address. This is only intended
3878 * to be used for panic dumps.
3881 pmap_kenter_temporary(vm_paddr_t pa, int i)
3885 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3886 pmap_kenter(va, pa);
3888 return ((void *)crashdumpmap);
3892 * This code maps large physical mmap regions into the
3893 * processor address space. Note that some shortcuts
3894 * are taken, but the code works.
3897 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3898 vm_pindex_t pindex, vm_size_t size)
3901 vm_paddr_t pa, ptepa;
3905 VM_OBJECT_ASSERT_WLOCKED(object);
3906 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3907 ("pmap_object_init_pt: non-device object"));
3909 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3910 if (!vm_object_populate(object, pindex, pindex + atop(size)))
3912 p = vm_page_lookup(object, pindex);
3913 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3914 ("pmap_object_init_pt: invalid page %p", p));
3915 pat_mode = p->md.pat_mode;
3918 * Abort the mapping if the first page is not physically
3919 * aligned to a 2/4MB page boundary.
3921 ptepa = VM_PAGE_TO_PHYS(p);
3922 if (ptepa & (NBPDR - 1))
3926 * Skip the first page. Abort the mapping if the rest of
3927 * the pages are not physically contiguous or have differing
3928 * memory attributes.
3930 p = TAILQ_NEXT(p, listq);
3931 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
3933 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3934 ("pmap_object_init_pt: invalid page %p", p));
3935 if (pa != VM_PAGE_TO_PHYS(p) ||
3936 pat_mode != p->md.pat_mode)
3938 p = TAILQ_NEXT(p, listq);
3942 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
3943 * "size" is a multiple of 2/4M, adding the PAT setting to
3944 * "pa" will not affect the termination of this loop.
3947 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
3948 size; pa += NBPDR) {
3949 pde = pmap_pde(pmap, addr);
3951 pde_store(pde, pa | PG_PS | PG_M | PG_A |
3952 PG_U | PG_RW | PG_V);
3953 pmap->pm_stats.resident_count += NBPDR /
3955 pmap_pde_mappings++;
3957 /* Else continue on if the PDE is already valid. */
3965 * Clear the wired attribute from the mappings for the specified range of
3966 * addresses in the given pmap. Every valid mapping within that range
3967 * must have the wired attribute set. In contrast, invalid mappings
3968 * cannot have the wired attribute set, so they are ignored.
3970 * The wired attribute of the page table entry is not a hardware feature,
3971 * so there is no need to invalidate any TLB entries.
3974 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3979 boolean_t pv_lists_locked;
3981 if (pmap_is_current(pmap))
3982 pv_lists_locked = FALSE;
3984 pv_lists_locked = TRUE;
3986 rw_wlock(&pvh_global_lock);
3990 for (; sva < eva; sva = pdnxt) {
3991 pdnxt = (sva + NBPDR) & ~PDRMASK;
3994 pde = pmap_pde(pmap, sva);
3995 if ((*pde & PG_V) == 0)
3997 if ((*pde & PG_PS) != 0) {
3998 if ((*pde & PG_W) == 0)
3999 panic("pmap_unwire: pde %#jx is missing PG_W",
4003 * Are we unwiring the entire large page? If not,
4004 * demote the mapping and fall through.
4006 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4008 * Regardless of whether a pde (or pte) is 32
4009 * or 64 bits in size, PG_W is among the least
4010 * significant 32 bits.
4012 atomic_clear_int((u_int *)pde, PG_W);
4013 pmap->pm_stats.wired_count -= NBPDR /
4017 if (!pv_lists_locked) {
4018 pv_lists_locked = TRUE;
4019 if (!rw_try_wlock(&pvh_global_lock)) {
4026 if (!pmap_demote_pde(pmap, pde, sva))
4027 panic("pmap_unwire: demotion failed");
4032 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4034 if ((*pte & PG_V) == 0)
4036 if ((*pte & PG_W) == 0)
4037 panic("pmap_unwire: pte %#jx is missing PG_W",
4041 * PG_W must be cleared atomically. Although the pmap
4042 * lock synchronizes access to PG_W, another processor
4043 * could be setting PG_M and/or PG_A concurrently.
4045 * PG_W is among the least significant 32 bits.
4047 atomic_clear_int((u_int *)pte, PG_W);
4048 pmap->pm_stats.wired_count--;
4051 if (pv_lists_locked) {
4053 rw_wunlock(&pvh_global_lock);
4060 * Copy the range specified by src_addr/len
4061 * from the source map to the range dst_addr/len
4062 * in the destination map.
4064 * This routine is only advisory and need not do anything.
4068 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4069 vm_offset_t src_addr)
4071 struct spglist free;
4073 vm_offset_t end_addr = src_addr + len;
4076 if (dst_addr != src_addr)
4079 if (!pmap_is_current(src_pmap))
4082 rw_wlock(&pvh_global_lock);
4083 if (dst_pmap < src_pmap) {
4084 PMAP_LOCK(dst_pmap);
4085 PMAP_LOCK(src_pmap);
4087 PMAP_LOCK(src_pmap);
4088 PMAP_LOCK(dst_pmap);
4091 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4092 pt_entry_t *src_pte, *dst_pte;
4093 vm_page_t dstmpte, srcmpte;
4094 pd_entry_t srcptepaddr;
4097 KASSERT(addr < UPT_MIN_ADDRESS,
4098 ("pmap_copy: invalid to pmap_copy page tables"));
4100 pdnxt = (addr + NBPDR) & ~PDRMASK;
4103 ptepindex = addr >> PDRSHIFT;
4105 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4106 if (srcptepaddr == 0)
4109 if (srcptepaddr & PG_PS) {
4110 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4112 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4113 ((srcptepaddr & PG_MANAGED) == 0 ||
4114 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4116 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4118 dst_pmap->pm_stats.resident_count +=
4120 pmap_pde_mappings++;
4125 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4126 KASSERT(srcmpte->wire_count > 0,
4127 ("pmap_copy: source page table page is unused"));
4129 if (pdnxt > end_addr)
4132 src_pte = vtopte(addr);
4133 while (addr < pdnxt) {
4137 * we only virtual copy managed pages
4139 if ((ptetemp & PG_MANAGED) != 0) {
4140 dstmpte = pmap_allocpte(dst_pmap, addr,
4141 PMAP_ENTER_NOSLEEP);
4142 if (dstmpte == NULL)
4144 dst_pte = pmap_pte_quick(dst_pmap, addr);
4145 if (*dst_pte == 0 &&
4146 pmap_try_insert_pv_entry(dst_pmap, addr,
4147 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4149 * Clear the wired, modified, and
4150 * accessed (referenced) bits
4153 *dst_pte = ptetemp & ~(PG_W | PG_M |
4155 dst_pmap->pm_stats.resident_count++;
4158 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4160 pmap_invalidate_page(dst_pmap,
4162 pmap_free_zero_pages(&free);
4166 if (dstmpte->wire_count >= srcmpte->wire_count)
4175 rw_wunlock(&pvh_global_lock);
4176 PMAP_UNLOCK(src_pmap);
4177 PMAP_UNLOCK(dst_pmap);
4181 * Zero 1 page of virtual memory mapped from a hardware page by the caller.
4183 static __inline void
4184 pagezero(void *page)
4186 #if defined(I686_CPU)
4187 if (cpu_class == CPUCLASS_686) {
4188 #if defined(CPU_ENABLE_SSE)
4189 if (cpu_feature & CPUID_SSE2)
4190 sse2_pagezero(page);
4193 i686_pagezero(page);
4196 bzero(page, PAGE_SIZE);
4200 * Zero the specified hardware page.
4203 pmap_zero_page(vm_page_t m)
4205 pt_entry_t *cmap_pte2;
4209 pc = pcpu_find(curcpu);
4210 cmap_pte2 = pc->pc_cmap_pte2;
4211 mtx_lock(&pc->pc_cmap_lock);
4213 panic("pmap_zero_page: CMAP2 busy");
4214 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4215 pmap_cache_bits(m->md.pat_mode, 0);
4216 invlcaddr(pc->pc_cmap_addr2);
4217 pagezero(pc->pc_cmap_addr2);
4219 mtx_unlock(&pc->pc_cmap_lock);
4224 * Zero an an area within a single hardware page. off and size must not
4225 * cover an area beyond a single hardware page.
4228 pmap_zero_page_area(vm_page_t m, int off, int size)
4230 pt_entry_t *cmap_pte2;
4234 pc = pcpu_find(curcpu);
4235 cmap_pte2 = pc->pc_cmap_pte2;
4236 mtx_lock(&pc->pc_cmap_lock);
4238 panic("pmap_zero_page_area: CMAP2 busy");
4239 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4240 pmap_cache_bits(m->md.pat_mode, 0);
4241 invlcaddr(pc->pc_cmap_addr2);
4242 if (off == 0 && size == PAGE_SIZE)
4243 pagezero(pc->pc_cmap_addr2);
4245 bzero(pc->pc_cmap_addr2 + off, size);
4247 mtx_unlock(&pc->pc_cmap_lock);
4252 * Copy 1 specified hardware page to another.
4255 pmap_copy_page(vm_page_t src, vm_page_t dst)
4257 pt_entry_t *cmap_pte1, *cmap_pte2;
4261 pc = pcpu_find(curcpu);
4262 cmap_pte1 = pc->pc_cmap_pte1;
4263 cmap_pte2 = pc->pc_cmap_pte2;
4264 mtx_lock(&pc->pc_cmap_lock);
4266 panic("pmap_copy_page: CMAP1 busy");
4268 panic("pmap_copy_page: CMAP2 busy");
4269 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4270 pmap_cache_bits(src->md.pat_mode, 0);
4271 invlcaddr(pc->pc_cmap_addr1);
4272 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4273 pmap_cache_bits(dst->md.pat_mode, 0);
4274 invlcaddr(pc->pc_cmap_addr2);
4275 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE);
4278 mtx_unlock(&pc->pc_cmap_lock);
4282 int unmapped_buf_allowed = 1;
4285 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4286 vm_offset_t b_offset, int xfersize)
4288 vm_page_t a_pg, b_pg;
4290 vm_offset_t a_pg_offset, b_pg_offset;
4291 pt_entry_t *cmap_pte1, *cmap_pte2;
4296 pc = pcpu_find(curcpu);
4297 cmap_pte1 = pc->pc_cmap_pte1;
4298 cmap_pte2 = pc->pc_cmap_pte2;
4299 mtx_lock(&pc->pc_cmap_lock);
4300 if (*cmap_pte1 != 0)
4301 panic("pmap_copy_pages: CMAP1 busy");
4302 if (*cmap_pte2 != 0)
4303 panic("pmap_copy_pages: CMAP2 busy");
4304 while (xfersize > 0) {
4305 a_pg = ma[a_offset >> PAGE_SHIFT];
4306 a_pg_offset = a_offset & PAGE_MASK;
4307 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4308 b_pg = mb[b_offset >> PAGE_SHIFT];
4309 b_pg_offset = b_offset & PAGE_MASK;
4310 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4311 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4312 pmap_cache_bits(a_pg->md.pat_mode, 0);
4313 invlcaddr(pc->pc_cmap_addr1);
4314 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4315 PG_M | pmap_cache_bits(b_pg->md.pat_mode, 0);
4316 invlcaddr(pc->pc_cmap_addr2);
4317 a_cp = pc->pc_cmap_addr1 + a_pg_offset;
4318 b_cp = pc->pc_cmap_addr2 + b_pg_offset;
4319 bcopy(a_cp, b_cp, cnt);
4326 mtx_unlock(&pc->pc_cmap_lock);
4331 * Returns true if the pmap's pv is one of the first
4332 * 16 pvs linked to from this page. This count may
4333 * be changed upwards or downwards in the future; it
4334 * is only necessary that true be returned for a small
4335 * subset of pmaps for proper page aging.
4338 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4340 struct md_page *pvh;
4345 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4346 ("pmap_page_exists_quick: page %p is not managed", m));
4348 rw_wlock(&pvh_global_lock);
4349 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4350 if (PV_PMAP(pv) == pmap) {
4358 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4359 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4360 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4361 if (PV_PMAP(pv) == pmap) {
4370 rw_wunlock(&pvh_global_lock);
4375 * pmap_page_wired_mappings:
4377 * Return the number of managed mappings to the given physical page
4381 pmap_page_wired_mappings(vm_page_t m)
4386 if ((m->oflags & VPO_UNMANAGED) != 0)
4388 rw_wlock(&pvh_global_lock);
4389 count = pmap_pvh_wired_mappings(&m->md, count);
4390 if ((m->flags & PG_FICTITIOUS) == 0) {
4391 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4394 rw_wunlock(&pvh_global_lock);
4399 * pmap_pvh_wired_mappings:
4401 * Return the updated number "count" of managed mappings that are wired.
4404 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4410 rw_assert(&pvh_global_lock, RA_WLOCKED);
4412 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4415 pte = pmap_pte_quick(pmap, pv->pv_va);
4416 if ((*pte & PG_W) != 0)
4425 * Returns TRUE if the given page is mapped individually or as part of
4426 * a 4mpage. Otherwise, returns FALSE.
4429 pmap_page_is_mapped(vm_page_t m)
4433 if ((m->oflags & VPO_UNMANAGED) != 0)
4435 rw_wlock(&pvh_global_lock);
4436 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4437 ((m->flags & PG_FICTITIOUS) == 0 &&
4438 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4439 rw_wunlock(&pvh_global_lock);
4444 * Remove all pages from specified address space
4445 * this aids process exit speeds. Also, this code
4446 * is special cased for current process only, but
4447 * can have the more generic (and slightly slower)
4448 * mode enabled. This is much faster than pmap_remove
4449 * in the case of running down an entire address space.
4452 pmap_remove_pages(pmap_t pmap)
4454 pt_entry_t *pte, tpte;
4455 vm_page_t m, mpte, mt;
4457 struct md_page *pvh;
4458 struct pv_chunk *pc, *npc;
4459 struct spglist free;
4462 uint32_t inuse, bitmask;
4465 if (pmap != PCPU_GET(curpmap)) {
4466 printf("warning: pmap_remove_pages called with non-current pmap\n");
4470 rw_wlock(&pvh_global_lock);
4473 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4474 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4477 for (field = 0; field < _NPCM; field++) {
4478 inuse = ~pc->pc_map[field] & pc_freemask[field];
4479 while (inuse != 0) {
4481 bitmask = 1UL << bit;
4482 idx = field * 32 + bit;
4483 pv = &pc->pc_pventry[idx];
4486 pte = pmap_pde(pmap, pv->pv_va);
4488 if ((tpte & PG_PS) == 0) {
4489 pte = vtopte(pv->pv_va);
4490 tpte = *pte & ~PG_PTE_PAT;
4495 "TPTE at %p IS ZERO @ VA %08x\n",
4501 * We cannot remove wired pages from a process' mapping at this time
4508 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4509 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4510 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4511 m, (uintmax_t)m->phys_addr,
4514 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4515 m < &vm_page_array[vm_page_array_size],
4516 ("pmap_remove_pages: bad tpte %#jx",
4522 * Update the vm_page_t clean/reference bits.
4524 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4525 if ((tpte & PG_PS) != 0) {
4526 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4533 PV_STAT(pv_entry_frees++);
4534 PV_STAT(pv_entry_spare++);
4536 pc->pc_map[field] |= bitmask;
4537 if ((tpte & PG_PS) != 0) {
4538 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4539 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4540 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4541 if (TAILQ_EMPTY(&pvh->pv_list)) {
4542 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4543 if (TAILQ_EMPTY(&mt->md.pv_list))
4544 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4546 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
4548 pmap->pm_stats.resident_count--;
4549 KASSERT(mpte->wire_count == NPTEPG,
4550 ("pmap_remove_pages: pte page wire count error"));
4551 mpte->wire_count = 0;
4552 pmap_add_delayed_free_list(mpte, &free, FALSE);
4553 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
4556 pmap->pm_stats.resident_count--;
4557 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4558 if (TAILQ_EMPTY(&m->md.pv_list) &&
4559 (m->flags & PG_FICTITIOUS) == 0) {
4560 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4561 if (TAILQ_EMPTY(&pvh->pv_list))
4562 vm_page_aflag_clear(m, PGA_WRITEABLE);
4564 pmap_unuse_pt(pmap, pv->pv_va, &free);
4569 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4574 pmap_invalidate_all(pmap);
4575 rw_wunlock(&pvh_global_lock);
4577 pmap_free_zero_pages(&free);
4583 * Return whether or not the specified physical page was modified
4584 * in any physical maps.
4587 pmap_is_modified(vm_page_t m)
4591 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4592 ("pmap_is_modified: page %p is not managed", m));
4595 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4596 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4597 * is clear, no PTEs can have PG_M set.
4599 VM_OBJECT_ASSERT_WLOCKED(m->object);
4600 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4602 rw_wlock(&pvh_global_lock);
4603 rv = pmap_is_modified_pvh(&m->md) ||
4604 ((m->flags & PG_FICTITIOUS) == 0 &&
4605 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4606 rw_wunlock(&pvh_global_lock);
4611 * Returns TRUE if any of the given mappings were used to modify
4612 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4613 * mappings are supported.
4616 pmap_is_modified_pvh(struct md_page *pvh)
4623 rw_assert(&pvh_global_lock, RA_WLOCKED);
4626 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4629 pte = pmap_pte_quick(pmap, pv->pv_va);
4630 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4640 * pmap_is_prefaultable:
4642 * Return whether or not the specified virtual address is elgible
4646 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4654 pde = pmap_pde(pmap, addr);
4655 if (*pde != 0 && (*pde & PG_PS) == 0) {
4664 * pmap_is_referenced:
4666 * Return whether or not the specified physical page was referenced
4667 * in any physical maps.
4670 pmap_is_referenced(vm_page_t m)
4674 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4675 ("pmap_is_referenced: page %p is not managed", m));
4676 rw_wlock(&pvh_global_lock);
4677 rv = pmap_is_referenced_pvh(&m->md) ||
4678 ((m->flags & PG_FICTITIOUS) == 0 &&
4679 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4680 rw_wunlock(&pvh_global_lock);
4685 * Returns TRUE if any of the given mappings were referenced and FALSE
4686 * otherwise. Both page and 4mpage mappings are supported.
4689 pmap_is_referenced_pvh(struct md_page *pvh)
4696 rw_assert(&pvh_global_lock, RA_WLOCKED);
4699 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4702 pte = pmap_pte_quick(pmap, pv->pv_va);
4703 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4713 * Clear the write and modified bits in each of the given page's mappings.
4716 pmap_remove_write(vm_page_t m)
4718 struct md_page *pvh;
4719 pv_entry_t next_pv, pv;
4722 pt_entry_t oldpte, *pte;
4725 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4726 ("pmap_remove_write: page %p is not managed", m));
4729 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4730 * set by another thread while the object is locked. Thus,
4731 * if PGA_WRITEABLE is clear, no page table entries need updating.
4733 VM_OBJECT_ASSERT_WLOCKED(m->object);
4734 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4736 rw_wlock(&pvh_global_lock);
4738 if ((m->flags & PG_FICTITIOUS) != 0)
4739 goto small_mappings;
4740 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4741 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4745 pde = pmap_pde(pmap, va);
4746 if ((*pde & PG_RW) != 0)
4747 (void)pmap_demote_pde(pmap, pde, va);
4751 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4754 pde = pmap_pde(pmap, pv->pv_va);
4755 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
4756 " a 4mpage in page %p's pv list", m));
4757 pte = pmap_pte_quick(pmap, pv->pv_va);
4760 if ((oldpte & PG_RW) != 0) {
4762 * Regardless of whether a pte is 32 or 64 bits
4763 * in size, PG_RW and PG_M are among the least
4764 * significant 32 bits.
4766 if (!atomic_cmpset_int((u_int *)pte, oldpte,
4767 oldpte & ~(PG_RW | PG_M)))
4769 if ((oldpte & PG_M) != 0)
4771 pmap_invalidate_page(pmap, pv->pv_va);
4775 vm_page_aflag_clear(m, PGA_WRITEABLE);
4777 rw_wunlock(&pvh_global_lock);
4781 * pmap_ts_referenced:
4783 * Return a count of reference bits for a page, clearing those bits.
4784 * It is not necessary for every reference bit to be cleared, but it
4785 * is necessary that 0 only be returned when there are truly no
4786 * reference bits set.
4788 * As an optimization, update the page's dirty field if a modified bit is
4789 * found while counting reference bits. This opportunistic update can be
4790 * performed at low cost and can eliminate the need for some future calls
4791 * to pmap_is_modified(). However, since this function stops after
4792 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4793 * dirty pages. Those dirty pages will only be detected by a future call
4794 * to pmap_is_modified().
4797 pmap_ts_referenced(vm_page_t m)
4799 struct md_page *pvh;
4807 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4808 ("pmap_ts_referenced: page %p is not managed", m));
4809 pa = VM_PAGE_TO_PHYS(m);
4810 pvh = pa_to_pvh(pa);
4811 rw_wlock(&pvh_global_lock);
4813 if ((m->flags & PG_FICTITIOUS) != 0 ||
4814 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4815 goto small_mappings;
4820 pde = pmap_pde(pmap, pv->pv_va);
4821 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4823 * Although "*pde" is mapping a 2/4MB page, because
4824 * this function is called at a 4KB page granularity,
4825 * we only update the 4KB page under test.
4829 if ((*pde & PG_A) != 0) {
4831 * Since this reference bit is shared by either 1024
4832 * or 512 4KB pages, it should not be cleared every
4833 * time it is tested. Apply a simple "hash" function
4834 * on the physical page number, the virtual superpage
4835 * number, and the pmap address to select one 4KB page
4836 * out of the 1024 or 512 on which testing the
4837 * reference bit will result in clearing that bit.
4838 * This function is designed to avoid the selection of
4839 * the same 4KB page for every 2- or 4MB page mapping.
4841 * On demotion, a mapping that hasn't been referenced
4842 * is simply destroyed. To avoid the possibility of a
4843 * subsequent page fault on a demoted wired mapping,
4844 * always leave its reference bit set. Moreover,
4845 * since the superpage is wired, the current state of
4846 * its reference bit won't affect page replacement.
4848 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
4849 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
4850 (*pde & PG_W) == 0) {
4851 atomic_clear_int((u_int *)pde, PG_A);
4852 pmap_invalidate_page(pmap, pv->pv_va);
4857 /* Rotate the PV list if it has more than one entry. */
4858 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4859 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4860 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4862 if (rtval >= PMAP_TS_REFERENCED_MAX)
4864 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4866 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4872 pde = pmap_pde(pmap, pv->pv_va);
4873 KASSERT((*pde & PG_PS) == 0,
4874 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
4876 pte = pmap_pte_quick(pmap, pv->pv_va);
4877 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4879 if ((*pte & PG_A) != 0) {
4880 atomic_clear_int((u_int *)pte, PG_A);
4881 pmap_invalidate_page(pmap, pv->pv_va);
4885 /* Rotate the PV list if it has more than one entry. */
4886 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4887 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4888 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4890 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
4891 PMAP_TS_REFERENCED_MAX);
4894 rw_wunlock(&pvh_global_lock);
4899 * Apply the given advice to the specified range of addresses within the
4900 * given pmap. Depending on the advice, clear the referenced and/or
4901 * modified flags in each mapping and set the mapped page's dirty field.
4904 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4906 pd_entry_t oldpde, *pde;
4908 vm_offset_t va, pdnxt;
4910 boolean_t anychanged, pv_lists_locked;
4912 if (advice != MADV_DONTNEED && advice != MADV_FREE)
4914 if (pmap_is_current(pmap))
4915 pv_lists_locked = FALSE;
4917 pv_lists_locked = TRUE;
4919 rw_wlock(&pvh_global_lock);
4924 for (; sva < eva; sva = pdnxt) {
4925 pdnxt = (sva + NBPDR) & ~PDRMASK;
4928 pde = pmap_pde(pmap, sva);
4930 if ((oldpde & PG_V) == 0)
4932 else if ((oldpde & PG_PS) != 0) {
4933 if ((oldpde & PG_MANAGED) == 0)
4935 if (!pv_lists_locked) {
4936 pv_lists_locked = TRUE;
4937 if (!rw_try_wlock(&pvh_global_lock)) {
4939 pmap_invalidate_all(pmap);
4945 if (!pmap_demote_pde(pmap, pde, sva)) {
4947 * The large page mapping was destroyed.
4953 * Unless the page mappings are wired, remove the
4954 * mapping to a single page so that a subsequent
4955 * access may repromote. Since the underlying page
4956 * table page is fully populated, this removal never
4957 * frees a page table page.
4959 if ((oldpde & PG_W) == 0) {
4960 pte = pmap_pte_quick(pmap, sva);
4961 KASSERT((*pte & PG_V) != 0,
4962 ("pmap_advise: invalid PTE"));
4963 pmap_remove_pte(pmap, pte, sva, NULL);
4970 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4972 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
4974 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4975 if (advice == MADV_DONTNEED) {
4977 * Future calls to pmap_is_modified()
4978 * can be avoided by making the page
4981 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
4984 atomic_clear_int((u_int *)pte, PG_M | PG_A);
4985 } else if ((*pte & PG_A) != 0)
4986 atomic_clear_int((u_int *)pte, PG_A);
4989 if ((*pte & PG_G) != 0) {
4997 pmap_invalidate_range(pmap, va, sva);
5002 pmap_invalidate_range(pmap, va, sva);
5005 pmap_invalidate_all(pmap);
5006 if (pv_lists_locked) {
5008 rw_wunlock(&pvh_global_lock);
5014 * Clear the modify bits on the specified physical page.
5017 pmap_clear_modify(vm_page_t m)
5019 struct md_page *pvh;
5020 pv_entry_t next_pv, pv;
5022 pd_entry_t oldpde, *pde;
5023 pt_entry_t oldpte, *pte;
5026 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5027 ("pmap_clear_modify: page %p is not managed", m));
5028 VM_OBJECT_ASSERT_WLOCKED(m->object);
5029 KASSERT(!vm_page_xbusied(m),
5030 ("pmap_clear_modify: page %p is exclusive busied", m));
5033 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5034 * If the object containing the page is locked and the page is not
5035 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5037 if ((m->aflags & PGA_WRITEABLE) == 0)
5039 rw_wlock(&pvh_global_lock);
5041 if ((m->flags & PG_FICTITIOUS) != 0)
5042 goto small_mappings;
5043 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5044 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5048 pde = pmap_pde(pmap, va);
5050 if ((oldpde & PG_RW) != 0) {
5051 if (pmap_demote_pde(pmap, pde, va)) {
5052 if ((oldpde & PG_W) == 0) {
5054 * Write protect the mapping to a
5055 * single page so that a subsequent
5056 * write access may repromote.
5058 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5060 pte = pmap_pte_quick(pmap, va);
5062 if ((oldpte & PG_V) != 0) {
5064 * Regardless of whether a pte is 32 or 64 bits
5065 * in size, PG_RW and PG_M are among the least
5066 * significant 32 bits.
5068 while (!atomic_cmpset_int((u_int *)pte,
5070 oldpte & ~(PG_M | PG_RW)))
5073 pmap_invalidate_page(pmap, va);
5081 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5084 pde = pmap_pde(pmap, pv->pv_va);
5085 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5086 " a 4mpage in page %p's pv list", m));
5087 pte = pmap_pte_quick(pmap, pv->pv_va);
5088 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5090 * Regardless of whether a pte is 32 or 64 bits
5091 * in size, PG_M is among the least significant
5094 atomic_clear_int((u_int *)pte, PG_M);
5095 pmap_invalidate_page(pmap, pv->pv_va);
5100 rw_wunlock(&pvh_global_lock);
5104 * Miscellaneous support routines follow
5107 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5108 static __inline void
5109 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5114 * The cache mode bits are all in the low 32-bits of the
5115 * PTE, so we can just spin on updating the low 32-bits.
5118 opte = *(u_int *)pte;
5119 npte = opte & ~PG_PTE_CACHE;
5121 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5124 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5125 static __inline void
5126 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5131 * The cache mode bits are all in the low 32-bits of the
5132 * PDE, so we can just spin on updating the low 32-bits.
5135 opde = *(u_int *)pde;
5136 npde = opde & ~PG_PDE_CACHE;
5138 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5142 * Map a set of physical memory pages into the kernel virtual
5143 * address space. Return a pointer to where it is mapped. This
5144 * routine is intended to be used for mapping device memory,
5148 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5150 struct pmap_preinit_mapping *ppim;
5151 vm_offset_t va, offset;
5155 offset = pa & PAGE_MASK;
5156 size = round_page(offset + size);
5159 if (pa < KERNLOAD && pa + size <= KERNLOAD)
5161 else if (!pmap_initialized) {
5163 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5164 ppim = pmap_preinit_mapping + i;
5165 if (ppim->va == 0) {
5169 ppim->va = virtual_avail;
5170 virtual_avail += size;
5176 panic("%s: too many preinit mappings", __func__);
5179 * If we have a preinit mapping, re-use it.
5181 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5182 ppim = pmap_preinit_mapping + i;
5183 if (ppim->pa == pa && ppim->sz == size &&
5185 return ((void *)(ppim->va + offset));
5187 va = kva_alloc(size);
5189 panic("%s: Couldn't allocate KVA", __func__);
5191 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5192 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5193 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5194 pmap_invalidate_cache_range(va, va + size, FALSE);
5195 return ((void *)(va + offset));
5199 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5202 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5206 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5209 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5213 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5215 struct pmap_preinit_mapping *ppim;
5219 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD)
5221 offset = va & PAGE_MASK;
5222 size = round_page(offset + size);
5223 va = trunc_page(va);
5224 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5225 ppim = pmap_preinit_mapping + i;
5226 if (ppim->va == va && ppim->sz == size) {
5227 if (pmap_initialized)
5233 if (va + size == virtual_avail)
5238 if (pmap_initialized)
5243 * Sets the memory attribute for the specified page.
5246 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5249 m->md.pat_mode = ma;
5250 if ((m->flags & PG_FICTITIOUS) != 0)
5254 * If "m" is a normal page, flush it from the cache.
5255 * See pmap_invalidate_cache_range().
5257 * First, try to find an existing mapping of the page by sf
5258 * buffer. sf_buf_invalidate_cache() modifies mapping and
5259 * flushes the cache.
5261 if (sf_buf_invalidate_cache(m))
5265 * If page is not mapped by sf buffer, but CPU does not
5266 * support self snoop, map the page transient and do
5267 * invalidation. In the worst case, whole cache is flushed by
5268 * pmap_invalidate_cache_range().
5270 if ((cpu_feature & CPUID_SS) == 0)
5275 pmap_flush_page(vm_page_t m)
5277 pt_entry_t *cmap_pte2;
5279 vm_offset_t sva, eva;
5282 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5283 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5285 pc = pcpu_find(curcpu);
5286 cmap_pte2 = pc->pc_cmap_pte2;
5287 mtx_lock(&pc->pc_cmap_lock);
5289 panic("pmap_flush_page: CMAP2 busy");
5290 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5291 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0);
5292 invlcaddr(pc->pc_cmap_addr2);
5293 sva = (vm_offset_t)pc->pc_cmap_addr2;
5294 eva = sva + PAGE_SIZE;
5297 * Use mfence despite the ordering implied by
5298 * mtx_{un,}lock() because clflush on non-Intel CPUs
5299 * and clflushopt are not guaranteed to be ordered by
5300 * any other instruction.
5302 if (useclflushopt || cpu_vendor_id != CPU_VENDOR_INTEL)
5304 for (; sva < eva; sva += cpu_clflush_line_size) {
5310 if (useclflushopt || cpu_vendor_id != CPU_VENDOR_INTEL)
5313 mtx_unlock(&pc->pc_cmap_lock);
5316 pmap_invalidate_cache();
5320 * Changes the specified virtual address range's memory type to that given by
5321 * the parameter "mode". The specified virtual address range must be
5322 * completely contained within either the kernel map.
5324 * Returns zero if the change completed successfully, and either EINVAL or
5325 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5326 * of the virtual address range was not mapped, and ENOMEM is returned if
5327 * there was insufficient memory available to complete the change.
5330 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5332 vm_offset_t base, offset, tmpva;
5335 int cache_bits_pte, cache_bits_pde;
5338 base = trunc_page(va);
5339 offset = va & PAGE_MASK;
5340 size = round_page(offset + size);
5343 * Only supported on kernel virtual addresses above the recursive map.
5345 if (base < VM_MIN_KERNEL_ADDRESS)
5348 cache_bits_pde = pmap_cache_bits(mode, 1);
5349 cache_bits_pte = pmap_cache_bits(mode, 0);
5353 * Pages that aren't mapped aren't supported. Also break down
5354 * 2/4MB pages into 4KB pages if required.
5356 PMAP_LOCK(kernel_pmap);
5357 for (tmpva = base; tmpva < base + size; ) {
5358 pde = pmap_pde(kernel_pmap, tmpva);
5360 PMAP_UNLOCK(kernel_pmap);
5365 * If the current 2/4MB page already has
5366 * the required memory type, then we need not
5367 * demote this page. Just increment tmpva to
5368 * the next 2/4MB page frame.
5370 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5371 tmpva = trunc_4mpage(tmpva) + NBPDR;
5376 * If the current offset aligns with a 2/4MB
5377 * page frame and there is at least 2/4MB left
5378 * within the range, then we need not break
5379 * down this page into 4KB pages.
5381 if ((tmpva & PDRMASK) == 0 &&
5382 tmpva + PDRMASK < base + size) {
5386 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5387 PMAP_UNLOCK(kernel_pmap);
5391 pte = vtopte(tmpva);
5393 PMAP_UNLOCK(kernel_pmap);
5398 PMAP_UNLOCK(kernel_pmap);
5401 * Ok, all the pages exist, so run through them updating their
5402 * cache mode if required.
5404 for (tmpva = base; tmpva < base + size; ) {
5405 pde = pmap_pde(kernel_pmap, tmpva);
5407 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5408 pmap_pde_attr(pde, cache_bits_pde);
5411 tmpva = trunc_4mpage(tmpva) + NBPDR;
5413 pte = vtopte(tmpva);
5414 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5415 pmap_pte_attr(pte, cache_bits_pte);
5423 * Flush CPU caches to make sure any data isn't cached that
5424 * shouldn't be, etc.
5427 pmap_invalidate_range(kernel_pmap, base, tmpva);
5428 pmap_invalidate_cache_range(base, tmpva, FALSE);
5434 * perform the pmap work for mincore
5437 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5440 pt_entry_t *ptep, pte;
5446 pdep = pmap_pde(pmap, addr);
5448 if (*pdep & PG_PS) {
5450 /* Compute the physical address of the 4KB page. */
5451 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5453 val = MINCORE_SUPER;
5455 ptep = pmap_pte(pmap, addr);
5457 pmap_pte_release(ptep);
5458 pa = pte & PG_FRAME;
5466 if ((pte & PG_V) != 0) {
5467 val |= MINCORE_INCORE;
5468 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5469 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5470 if ((pte & PG_A) != 0)
5471 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5473 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5474 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5475 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5476 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5477 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5480 PA_UNLOCK_COND(*locked_pa);
5486 pmap_activate(struct thread *td)
5488 pmap_t pmap, oldpmap;
5493 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5494 oldpmap = PCPU_GET(curpmap);
5495 cpuid = PCPU_GET(cpuid);
5497 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5498 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5500 CPU_CLR(cpuid, &oldpmap->pm_active);
5501 CPU_SET(cpuid, &pmap->pm_active);
5503 #if defined(PAE) || defined(PAE_TABLES)
5504 cr3 = vtophys(pmap->pm_pdpt);
5506 cr3 = vtophys(pmap->pm_pdir);
5509 * pmap_activate is for the current thread on the current cpu
5511 td->td_pcb->pcb_cr3 = cr3;
5513 PCPU_SET(curpmap, pmap);
5518 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5523 * Increase the starting virtual address of the given mapping if a
5524 * different alignment might result in more superpage mappings.
5527 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5528 vm_offset_t *addr, vm_size_t size)
5530 vm_offset_t superpage_offset;
5534 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5535 offset += ptoa(object->pg_color);
5536 superpage_offset = offset & PDRMASK;
5537 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5538 (*addr & PDRMASK) == superpage_offset)
5540 if ((*addr & PDRMASK) < superpage_offset)
5541 *addr = (*addr & ~PDRMASK) + superpage_offset;
5543 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5547 pmap_quick_enter_page(vm_page_t m)
5553 qaddr = PCPU_GET(qmap_addr);
5554 pte = vtopte(qaddr);
5556 KASSERT(*pte == 0, ("pmap_quick_enter_page: PTE busy"));
5557 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5558 pmap_cache_bits(pmap_page_get_memattr(m), 0);
5565 pmap_quick_remove_page(vm_offset_t addr)
5570 qaddr = PCPU_GET(qmap_addr);
5571 pte = vtopte(qaddr);
5573 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5574 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5580 #if defined(PMAP_DEBUG)
5581 pmap_pid_dump(int pid)
5588 sx_slock(&allproc_lock);
5589 FOREACH_PROC_IN_SYSTEM(p) {
5590 if (p->p_pid != pid)
5596 pmap = vmspace_pmap(p->p_vmspace);
5597 for (i = 0; i < NPDEPTD; i++) {
5600 vm_offset_t base = i << PDRSHIFT;
5602 pde = &pmap->pm_pdir[i];
5603 if (pde && pmap_pde_v(pde)) {
5604 for (j = 0; j < NPTEPG; j++) {
5605 vm_offset_t va = base + (j << PAGE_SHIFT);
5606 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5611 sx_sunlock(&allproc_lock);
5614 pte = pmap_pte(pmap, va);
5615 if (pte && pmap_pte_v(pte)) {
5619 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5620 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5621 va, pa, m->hold_count, m->wire_count, m->flags);
5636 sx_sunlock(&allproc_lock);