2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
51 * This software was developed for the FreeBSD Project by Jake Burkholder,
52 * Safeport Network Services, and Network Associates Laboratories, the
53 * Security Research Division of Network Associates, Inc. under
54 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
55 * CHATS research program.
57 * Redistribution and use in source and binary forms, with or without
58 * modification, are permitted provided that the following conditions
60 * 1. Redistributions of source code must retain the above copyright
61 * notice, this list of conditions and the following disclaimer.
62 * 2. Redistributions in binary form must reproduce the above copyright
63 * notice, this list of conditions and the following disclaimer in the
64 * documentation and/or other materials provided with the distribution.
66 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
67 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
69 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
72 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
73 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
74 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
75 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
79 #include <sys/cdefs.h>
80 __FBSDID("$FreeBSD$");
83 * Manages physical address maps.
85 * Since the information managed by this module is
86 * also stored by the logical address mapping module,
87 * this module may throw away valid virtual-to-physical
88 * mappings at almost any time. However, invalidations
89 * of virtual-to-physical mappings must be done as
92 * In order to cope with hardware architectures which
93 * make virtual-to-physical map invalidates expensive,
94 * this module may delay invalidate or reduced protection
95 * operations until such time as they are actually
96 * necessary. This module is given full information as
97 * to which processors are currently using which maps,
98 * and to when physical maps must be made correct.
101 #include "opt_apic.h"
103 #include "opt_pmap.h"
107 #include <sys/param.h>
108 #include <sys/systm.h>
109 #include <sys/kernel.h>
111 #include <sys/lock.h>
112 #include <sys/malloc.h>
113 #include <sys/mman.h>
114 #include <sys/msgbuf.h>
115 #include <sys/mutex.h>
116 #include <sys/proc.h>
117 #include <sys/rwlock.h>
118 #include <sys/sf_buf.h>
120 #include <sys/vmmeter.h>
121 #include <sys/sched.h>
122 #include <sys/sysctl.h>
126 #include <vm/vm_param.h>
127 #include <vm/vm_kern.h>
128 #include <vm/vm_page.h>
129 #include <vm/vm_map.h>
130 #include <vm/vm_object.h>
131 #include <vm/vm_extern.h>
132 #include <vm/vm_pageout.h>
133 #include <vm/vm_pager.h>
134 #include <vm/vm_phys.h>
135 #include <vm/vm_radix.h>
136 #include <vm/vm_reserv.h>
141 #include <machine/intr_machdep.h>
142 #include <x86/apicvar.h>
144 #include <machine/cpu.h>
145 #include <machine/cputypes.h>
146 #include <machine/md_var.h>
147 #include <machine/pcb.h>
148 #include <machine/specialreg.h>
150 #include <machine/smp.h>
153 #ifndef PMAP_SHPGPERPROC
154 #define PMAP_SHPGPERPROC 200
157 #if !defined(DIAGNOSTIC)
158 #ifdef __GNUC_GNU_INLINE__
159 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
161 #define PMAP_INLINE extern inline
168 #define PV_STAT(x) do { x ; } while (0)
170 #define PV_STAT(x) do { } while (0)
173 #define pa_index(pa) ((pa) >> PDRSHIFT)
174 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
177 * Get PDEs and PTEs for user/kernel address space
179 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
180 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
182 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
183 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
184 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
185 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
186 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
188 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
189 atomic_clear_int((u_int *)(pte), PG_W))
190 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
192 struct pmap kernel_pmap_store;
193 LIST_HEAD(pmaplist, pmap);
194 static struct pmaplist allpmaps;
195 static struct mtx allpmaps_lock;
197 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
198 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
199 int pgeflag = 0; /* PG_G or-in */
200 int pseflag = 0; /* PG_PS or-in */
202 static int nkpt = NKPT;
203 vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR;
204 extern u_int32_t KERNend;
205 extern u_int32_t KPTphys;
207 #if defined(PAE) || defined(PAE_TABLES)
209 static uma_zone_t pdptzone;
212 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
214 static int pat_works = 1;
215 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
216 "Is page attribute table fully functional?");
218 static int pg_ps_enabled = 1;
219 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
220 &pg_ps_enabled, 0, "Are large page mappings enabled?");
222 #define PAT_INDEX_SIZE 8
223 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
226 * pmap_mapdev support pre initialization (i.e. console)
228 #define PMAP_PREINIT_MAPPING_COUNT 8
229 static struct pmap_preinit_mapping {
234 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
235 static int pmap_initialized;
237 static struct rwlock_padalign pvh_global_lock;
240 * Data for the pv entry allocation mechanism
242 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
243 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
244 static struct md_page *pv_table;
245 static int shpgperproc = PMAP_SHPGPERPROC;
247 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
248 int pv_maxchunks; /* How many chunks we have KVA for */
249 vm_offset_t pv_vafree; /* freelist stored in the PTE */
252 * All those kernel PT submaps that BSD is so fond of
255 static pd_entry_t *KPTD;
262 static caddr_t crashdumpmap;
264 static pt_entry_t *PMAP1 = NULL, *PMAP2;
265 static pt_entry_t *PADDR1 = NULL, *PADDR2;
268 static int PMAP1changedcpu;
269 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
271 "Number of times pmap_pte_quick changed CPU with same PMAP1");
273 static int PMAP1changed;
274 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
276 "Number of times pmap_pte_quick changed PMAP1");
277 static int PMAP1unchanged;
278 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
280 "Number of times pmap_pte_quick didn't change PMAP1");
281 static struct mtx PMAP2mutex;
285 static void free_pv_chunk(struct pv_chunk *pc);
286 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
287 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
288 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
289 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
290 #if VM_NRESERVLEVEL > 0
291 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
293 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
294 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
296 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
298 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
299 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
301 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
302 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
303 static void pmap_flush_page(vm_page_t m);
304 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
305 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
307 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
308 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
309 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
310 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
311 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
312 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
313 #if VM_NRESERVLEVEL > 0
314 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
316 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
318 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
319 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
320 struct spglist *free);
321 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
322 struct spglist *free);
323 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
324 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
325 struct spglist *free);
326 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
328 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
329 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
331 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
333 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
335 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
337 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
338 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
339 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
340 static void pmap_pte_release(pt_entry_t *pte);
341 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
342 #if defined(PAE) || defined(PAE_TABLES)
343 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain,
344 uint8_t *flags, int wait);
346 static void pmap_set_pg(void);
348 static __inline void pagezero(void *page);
350 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
351 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
354 * If you get an error here, then you set KVA_PAGES wrong! See the
355 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be
356 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE.
358 CTASSERT(KERNBASE % (1 << 24) == 0);
361 * Bootstrap the system enough to run with virtual memory.
363 * On the i386 this is called after mapping has already been enabled
364 * and just syncs the pmap module with what has already been done.
365 * [We can't call it easily with mapping off since the kernel is not
366 * mapped with PA == VA, hence we would have to relocate every address
367 * from the linked base (virtual) address "KERNBASE" to the actual
368 * (physical) address starting relative to 0]
371 pmap_bootstrap(vm_paddr_t firstaddr)
374 pt_entry_t *pte, *unused;
379 * Add a physical memory segment (vm_phys_seg) corresponding to the
380 * preallocated kernel page table pages so that vm_page structures
381 * representing these pages will be created. The vm_page structures
382 * are required for promotion of the corresponding kernel virtual
383 * addresses to superpage mappings.
385 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
388 * Initialize the first available kernel virtual address. However,
389 * using "firstaddr" may waste a few pages of the kernel virtual
390 * address space, because locore may not have mapped every physical
391 * page that it allocated. Preferably, locore would provide a first
392 * unused virtual address in addition to "firstaddr".
394 virtual_avail = (vm_offset_t) KERNBASE + firstaddr;
396 virtual_end = VM_MAX_KERNEL_ADDRESS;
399 * Initialize the kernel pmap (which is statically allocated).
401 PMAP_LOCK_INIT(kernel_pmap);
402 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD);
403 #if defined(PAE) || defined(PAE_TABLES)
404 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT);
406 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
407 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
410 * Initialize the global pv list lock.
412 rw_init(&pvh_global_lock, "pmap pv global");
414 LIST_INIT(&allpmaps);
417 * Request a spin mutex so that changes to allpmaps cannot be
418 * preempted by smp_rendezvous_cpus(). Otherwise,
419 * pmap_update_pde_kernel() could access allpmaps while it is
422 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
423 mtx_lock_spin(&allpmaps_lock);
424 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
425 mtx_unlock_spin(&allpmaps_lock);
428 * Reserve some special page table entries/VA space for temporary
431 #define SYSMAP(c, p, v, n) \
432 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
439 * Initialize temporary map objects on the current CPU for use
441 * CMAP1/CMAP2 are used for zeroing and copying pages.
442 * CMAP3 is used for the boot-time memory test.
445 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
446 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1)
447 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1)
448 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1)
450 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
455 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
458 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
460 SYSMAP(caddr_t, unused, ptvmmap, 1)
463 * msgbufp is used to map the system message buffer.
465 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
468 * KPTmap is used by pmap_kextract().
470 * KPTmap is first initialized by locore. However, that initial
471 * KPTmap can only support NKPT page table pages. Here, a larger
472 * KPTmap is created that can support KVA_PAGES page table pages.
474 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
476 for (i = 0; i < NKPT; i++)
477 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V;
480 * Adjust the start of the KPTD and KPTmap so that the implementation
481 * of pmap_kextract() and pmap_growkernel() can be made simpler.
484 KPTmap -= i386_btop(KPTDI << PDRSHIFT);
487 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
490 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
491 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
493 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
498 * Finish removing the identity mapping (virt == phys) of low memory.
499 * It was only used for 2 instructions in locore. locore then
500 * unmapped the first PTD to get some null pointer checks. ACPI
501 * wakeup will map the first PTD transiently to use it for 1
502 * instruction. The double mapping for low memory is not usable in
503 * normal operation since it breaks trapping of null pointers and
504 * causes inconsistencies in page tables when combined with PG_G.
506 for (i = 1; i < NKPT; i++)
510 * Initialize the PAT MSR if present.
511 * pmap_init_pat() clears and sets CR4_PGE, which, as a
512 * side-effect, invalidates stale PG_G TLB entries that might
513 * have been created in our pre-boot environment. We assume
514 * that PAT support implies PGE and in reverse, PGE presence
515 * comes with PAT. Both features were added for Pentium Pro.
519 /* Turn on PG_G on kernel page(s) */
524 pmap_init_reserved_pages(void)
533 * Skip if the mapping has already been initialized,
534 * i.e. this is the BSP.
536 if (pc->pc_cmap_addr1 != 0)
538 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
539 pages = kva_alloc(PAGE_SIZE * 3);
541 panic("%s: unable to allocate KVA", __func__);
542 pc->pc_cmap_pte1 = vtopte(pages);
543 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE);
544 pc->pc_cmap_addr1 = (caddr_t)pages;
545 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE);
546 pc->pc_qmap_addr = pages + (PAGE_SIZE * 2);
550 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
558 int pat_table[PAT_INDEX_SIZE];
563 /* Set default PAT index table. */
564 for (i = 0; i < PAT_INDEX_SIZE; i++)
566 pat_table[PAT_WRITE_BACK] = 0;
567 pat_table[PAT_WRITE_THROUGH] = 1;
568 pat_table[PAT_UNCACHEABLE] = 3;
569 pat_table[PAT_WRITE_COMBINING] = 3;
570 pat_table[PAT_WRITE_PROTECTED] = 3;
571 pat_table[PAT_UNCACHED] = 3;
574 * Bail if this CPU doesn't implement PAT.
575 * We assume that PAT support implies PGE.
577 if ((cpu_feature & CPUID_PAT) == 0) {
578 for (i = 0; i < PAT_INDEX_SIZE; i++)
579 pat_index[i] = pat_table[i];
585 * Due to some Intel errata, we can only safely use the lower 4
588 * Intel Pentium III Processor Specification Update
589 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
592 * Intel Pentium IV Processor Specification Update
593 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
595 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
596 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
599 /* Initialize default PAT entries. */
600 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
601 PAT_VALUE(1, PAT_WRITE_THROUGH) |
602 PAT_VALUE(2, PAT_UNCACHED) |
603 PAT_VALUE(3, PAT_UNCACHEABLE) |
604 PAT_VALUE(4, PAT_WRITE_BACK) |
605 PAT_VALUE(5, PAT_WRITE_THROUGH) |
606 PAT_VALUE(6, PAT_UNCACHED) |
607 PAT_VALUE(7, PAT_UNCACHEABLE);
611 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
612 * Program 5 and 6 as WP and WC.
613 * Leave 4 and 7 as WB and UC.
615 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
616 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
617 PAT_VALUE(6, PAT_WRITE_COMBINING);
618 pat_table[PAT_UNCACHED] = 2;
619 pat_table[PAT_WRITE_PROTECTED] = 5;
620 pat_table[PAT_WRITE_COMBINING] = 6;
623 * Just replace PAT Index 2 with WC instead of UC-.
625 pat_msr &= ~PAT_MASK(2);
626 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
627 pat_table[PAT_WRITE_COMBINING] = 2;
632 load_cr4(cr4 & ~CR4_PGE);
634 /* Disable caches (CD = 1, NW = 0). */
636 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
638 /* Flushes caches and TLBs. */
642 /* Update PAT and index table. */
643 wrmsr(MSR_PAT, pat_msr);
644 for (i = 0; i < PAT_INDEX_SIZE; i++)
645 pat_index[i] = pat_table[i];
647 /* Flush caches and TLBs again. */
651 /* Restore caches and PGE. */
657 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on.
663 vm_offset_t va, endva;
668 endva = KERNBASE + KERNend;
671 va = KERNBASE + roundup2(KERNLOAD, NBPDR);
673 pdir_pde(PTD, va) |= pgeflag;
674 invltlb(); /* Flush non-PG_G entries. */
678 va = (vm_offset_t)btext;
683 invltlb(); /* Flush non-PG_G entries. */
690 * Initialize a vm_page's machine-dependent fields.
693 pmap_page_init(vm_page_t m)
696 TAILQ_INIT(&m->md.pv_list);
697 m->md.pat_mode = PAT_WRITE_BACK;
700 #if defined(PAE) || defined(PAE_TABLES)
702 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain, uint8_t *flags,
706 /* Inform UMA that this allocator uses kernel_map/object. */
707 *flags = UMA_SLAB_KERNEL;
708 return ((void *)kmem_alloc_contig_domain(domain, bytes, wait, 0x0ULL,
709 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
714 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
716 * - Must deal with pages in order to ensure that none of the PG_* bits
717 * are ever set, PG_V in particular.
718 * - Assumes we can write to ptes without pte_store() atomic ops, even
719 * on PAE systems. This should be ok.
720 * - Assumes nothing will ever test these addresses for 0 to indicate
721 * no mapping instead of correctly checking PG_V.
722 * - Assumes a vm_offset_t will fit in a pte (true for i386).
723 * Because PG_V is never set, there can be no mappings to invalidate.
726 pmap_ptelist_alloc(vm_offset_t *head)
733 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
737 panic("pmap_ptelist_alloc: va with PG_V set!");
743 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
748 panic("pmap_ptelist_free: freeing va with PG_V set!");
750 *pte = *head; /* virtual! PG_V is 0 though */
755 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
761 for (i = npages - 1; i >= 0; i--) {
762 va = (vm_offset_t)base + i * PAGE_SIZE;
763 pmap_ptelist_free(head, va);
769 * Initialize the pmap module.
770 * Called by vm_init, to initialize any structures that the pmap
771 * system needs to map virtual memory.
776 struct pmap_preinit_mapping *ppim;
782 * Initialize the vm page array entries for the kernel pmap's
785 for (i = 0; i < NKPT; i++) {
786 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
787 KASSERT(mpte >= vm_page_array &&
788 mpte < &vm_page_array[vm_page_array_size],
789 ("pmap_init: page table page is out of range"));
790 mpte->pindex = i + KPTDI;
791 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
795 * Initialize the address space (zone) for the pv entries. Set a
796 * high water mark so that the system can recover from excessive
797 * numbers of pv entries.
799 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
800 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
801 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
802 pv_entry_max = roundup(pv_entry_max, _NPCPV);
803 pv_entry_high_water = 9 * (pv_entry_max / 10);
806 * If the kernel is running on a virtual machine, then it must assume
807 * that MCA is enabled by the hypervisor. Moreover, the kernel must
808 * be prepared for the hypervisor changing the vendor and family that
809 * are reported by CPUID. Consequently, the workaround for AMD Family
810 * 10h Erratum 383 is enabled if the processor's feature set does not
811 * include at least one feature that is only supported by older Intel
812 * or newer AMD processors.
814 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
815 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
816 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
818 workaround_erratum383 = 1;
821 * Are large page mappings supported and enabled?
823 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
826 else if (pg_ps_enabled) {
827 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
828 ("pmap_init: can't assign to pagesizes[1]"));
829 pagesizes[1] = NBPDR;
833 * Calculate the size of the pv head table for superpages.
834 * Handle the possibility that "vm_phys_segs[...].end" is zero.
836 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
837 PAGE_SIZE) / NBPDR + 1;
840 * Allocate memory for the pv head table for superpages.
842 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
844 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
846 for (i = 0; i < pv_npg; i++)
847 TAILQ_INIT(&pv_table[i].pv_list);
849 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
850 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
851 if (pv_chunkbase == NULL)
852 panic("pmap_init: not enough kvm for pv chunks");
853 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
854 #if defined(PAE) || defined(PAE_TABLES)
855 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
856 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
857 UMA_ZONE_VM | UMA_ZONE_NOFREE);
858 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
861 pmap_initialized = 1;
864 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
865 ppim = pmap_preinit_mapping + i;
868 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
869 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
874 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
875 "Max number of PV entries");
876 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
877 "Page share factor per proc");
879 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
880 "2/4MB page mapping counters");
882 static u_long pmap_pde_demotions;
883 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
884 &pmap_pde_demotions, 0, "2/4MB page demotions");
886 static u_long pmap_pde_mappings;
887 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
888 &pmap_pde_mappings, 0, "2/4MB page mappings");
890 static u_long pmap_pde_p_failures;
891 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
892 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
894 static u_long pmap_pde_promotions;
895 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
896 &pmap_pde_promotions, 0, "2/4MB page promotions");
898 /***************************************************
899 * Low level helper routines.....
900 ***************************************************/
903 * Determine the appropriate bits to set in a PTE or PDE for a specified
907 pmap_cache_bits(int mode, boolean_t is_pde)
909 int cache_bits, pat_flag, pat_idx;
911 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
912 panic("Unknown caching mode %d\n", mode);
914 /* The PAT bit is different for PTE's and PDE's. */
915 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
917 /* Map the caching mode to a PAT index. */
918 pat_idx = pat_index[mode];
920 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
923 cache_bits |= pat_flag;
925 cache_bits |= PG_NC_PCD;
927 cache_bits |= PG_NC_PWT;
932 * The caller is responsible for maintaining TLB consistency.
935 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
939 boolean_t PTD_updated;
942 mtx_lock_spin(&allpmaps_lock);
943 LIST_FOREACH(pmap, &allpmaps, pm_list) {
944 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] &
947 pde = pmap_pde(pmap, va);
948 pde_store(pde, newpde);
950 mtx_unlock_spin(&allpmaps_lock);
952 ("pmap_kenter_pde: current page table is not in allpmaps"));
956 * After changing the page size for the specified virtual address in the page
957 * table, flush the corresponding entries from the processor's TLB. Only the
958 * calling processor's TLB is affected.
960 * The calling thread must be pinned to a processor.
963 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
967 if ((newpde & PG_PS) == 0)
968 /* Demotion: flush a specific 2MB page mapping. */
970 else if ((newpde & PG_G) == 0)
972 * Promotion: flush every 4KB page mapping from the TLB
973 * because there are too many to flush individually.
978 * Promotion: flush every 4KB page mapping from the TLB,
979 * including any global (PG_G) mappings.
982 load_cr4(cr4 & ~CR4_PGE);
984 * Although preemption at this point could be detrimental to
985 * performance, it would not lead to an error. PG_G is simply
986 * ignored if CR4.PGE is clear. Moreover, in case this block
987 * is re-entered, the load_cr4() either above or below will
988 * modify CR4.PGE flushing the TLB.
990 load_cr4(cr4 | CR4_PGE);
1003 load_cr4(cr4 & ~CR4_PGE);
1004 load_cr4(cr4 | CR4_PGE);
1011 * For SMP, these functions have to use the IPI mechanism for coherence.
1013 * N.B.: Before calling any of the following TLB invalidation functions,
1014 * the calling processor must ensure that all stores updating a non-
1015 * kernel page table are globally performed. Otherwise, another
1016 * processor could cache an old, pre-update entry without being
1017 * invalidated. This can happen one of two ways: (1) The pmap becomes
1018 * active on another processor after its pm_active field is checked by
1019 * one of the following functions but before a store updating the page
1020 * table is globally performed. (2) The pmap becomes active on another
1021 * processor before its pm_active field is checked but due to
1022 * speculative loads one of the following functions stills reads the
1023 * pmap as inactive on the other processor.
1025 * The kernel page table is exempt because its pm_active field is
1026 * immutable. The kernel page table is always active on every
1030 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1032 cpuset_t *mask, other_cpus;
1036 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1040 cpuid = PCPU_GET(cpuid);
1041 other_cpus = all_cpus;
1042 CPU_CLR(cpuid, &other_cpus);
1043 if (CPU_ISSET(cpuid, &pmap->pm_active))
1045 CPU_AND(&other_cpus, &pmap->pm_active);
1048 smp_masked_invlpg(*mask, va, pmap);
1052 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1053 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1056 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1058 cpuset_t *mask, other_cpus;
1062 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1063 pmap_invalidate_all(pmap);
1068 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1069 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1073 cpuid = PCPU_GET(cpuid);
1074 other_cpus = all_cpus;
1075 CPU_CLR(cpuid, &other_cpus);
1076 if (CPU_ISSET(cpuid, &pmap->pm_active))
1077 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1079 CPU_AND(&other_cpus, &pmap->pm_active);
1082 smp_masked_invlpg_range(*mask, sva, eva, pmap);
1087 pmap_invalidate_all(pmap_t pmap)
1089 cpuset_t *mask, other_cpus;
1093 if (pmap == kernel_pmap) {
1096 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1100 cpuid = PCPU_GET(cpuid);
1101 other_cpus = all_cpus;
1102 CPU_CLR(cpuid, &other_cpus);
1103 if (CPU_ISSET(cpuid, &pmap->pm_active))
1105 CPU_AND(&other_cpus, &pmap->pm_active);
1108 smp_masked_invltlb(*mask, pmap);
1113 pmap_invalidate_cache(void)
1123 cpuset_t invalidate; /* processors that invalidate their TLB */
1127 u_int store; /* processor that updates the PDE */
1131 pmap_update_pde_kernel(void *arg)
1133 struct pde_action *act = arg;
1137 if (act->store == PCPU_GET(cpuid)) {
1140 * Elsewhere, this operation requires allpmaps_lock for
1141 * synchronization. Here, it does not because it is being
1142 * performed in the context of an all_cpus rendezvous.
1144 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1145 pde = pmap_pde(pmap, act->va);
1146 pde_store(pde, act->newpde);
1152 pmap_update_pde_user(void *arg)
1154 struct pde_action *act = arg;
1156 if (act->store == PCPU_GET(cpuid))
1157 pde_store(act->pde, act->newpde);
1161 pmap_update_pde_teardown(void *arg)
1163 struct pde_action *act = arg;
1165 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1166 pmap_update_pde_invalidate(act->va, act->newpde);
1170 * Change the page size for the specified virtual address in a way that
1171 * prevents any possibility of the TLB ever having two entries that map the
1172 * same virtual address using different page sizes. This is the recommended
1173 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1174 * machine check exception for a TLB state that is improperly diagnosed as a
1178 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1180 struct pde_action act;
1181 cpuset_t active, other_cpus;
1185 cpuid = PCPU_GET(cpuid);
1186 other_cpus = all_cpus;
1187 CPU_CLR(cpuid, &other_cpus);
1188 if (pmap == kernel_pmap)
1191 active = pmap->pm_active;
1192 if (CPU_OVERLAP(&active, &other_cpus)) {
1194 act.invalidate = active;
1197 act.newpde = newpde;
1198 CPU_SET(cpuid, &active);
1199 smp_rendezvous_cpus(active,
1200 smp_no_rendezvous_barrier, pmap == kernel_pmap ?
1201 pmap_update_pde_kernel : pmap_update_pde_user,
1202 pmap_update_pde_teardown, &act);
1204 if (pmap == kernel_pmap)
1205 pmap_kenter_pde(va, newpde);
1207 pde_store(pde, newpde);
1208 if (CPU_ISSET(cpuid, &active))
1209 pmap_update_pde_invalidate(va, newpde);
1215 * Normal, non-SMP, 486+ invalidation functions.
1216 * We inline these within pmap.c for speed.
1219 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1222 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1227 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1231 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1232 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1237 pmap_invalidate_all(pmap_t pmap)
1240 if (pmap == kernel_pmap)
1242 else if (!CPU_EMPTY(&pmap->pm_active))
1247 pmap_invalidate_cache(void)
1254 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1257 if (pmap == kernel_pmap)
1258 pmap_kenter_pde(va, newpde);
1260 pde_store(pde, newpde);
1261 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1262 pmap_update_pde_invalidate(va, newpde);
1267 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1271 * When the PDE has PG_PROMOTED set, the 2- or 4MB page mapping was
1272 * created by a promotion that did not invalidate the 512 or 1024 4KB
1273 * page mappings that might exist in the TLB. Consequently, at this
1274 * point, the TLB may hold both 4KB and 2- or 4MB page mappings for
1275 * the address range [va, va + NBPDR). Therefore, the entire range
1276 * must be invalidated here. In contrast, when PG_PROMOTED is clear,
1277 * the TLB will not hold any 4KB page mappings for the address range
1278 * [va, va + NBPDR), and so a single INVLPG suffices to invalidate the
1279 * 2- or 4MB page mapping from the TLB.
1281 if ((pde & PG_PROMOTED) != 0)
1282 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
1284 pmap_invalidate_page(pmap, va);
1287 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1290 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1294 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
1296 KASSERT((sva & PAGE_MASK) == 0,
1297 ("pmap_invalidate_cache_range: sva not page-aligned"));
1298 KASSERT((eva & PAGE_MASK) == 0,
1299 ("pmap_invalidate_cache_range: eva not page-aligned"));
1302 if ((cpu_feature & CPUID_SS) != 0 && !force)
1303 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1304 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
1305 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1308 * XXX: Some CPUs fault, hang, or trash the local APIC
1309 * registers if we use CLFLUSH on the local APIC
1310 * range. The local APIC is always uncached, so we
1311 * don't need to flush for that range anyway.
1313 if (pmap_kextract(sva) == lapic_paddr)
1317 * Otherwise, do per-cache line flush. Use the sfence
1318 * instruction to insure that previous stores are
1319 * included in the write-back. The processor
1320 * propagates flush to other processors in the cache
1324 for (; sva < eva; sva += cpu_clflush_line_size)
1327 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1328 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1330 if (pmap_kextract(sva) == lapic_paddr)
1334 * Writes are ordered by CLFLUSH on Intel CPUs.
1336 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1338 for (; sva < eva; sva += cpu_clflush_line_size)
1340 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1345 * No targeted cache flush methods are supported by CPU,
1346 * or the supplied range is bigger than 2MB.
1347 * Globally invalidate cache.
1349 pmap_invalidate_cache();
1354 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1358 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1359 (cpu_feature & CPUID_CLFSH) == 0) {
1360 pmap_invalidate_cache();
1362 for (i = 0; i < count; i++)
1363 pmap_flush_page(pages[i]);
1368 * Are we current address space or kernel?
1371 pmap_is_current(pmap_t pmap)
1374 return (pmap == kernel_pmap || pmap ==
1375 vmspace_pmap(curthread->td_proc->p_vmspace));
1379 * If the given pmap is not the current or kernel pmap, the returned pte must
1380 * be released by passing it to pmap_pte_release().
1383 pmap_pte(pmap_t pmap, vm_offset_t va)
1388 pde = pmap_pde(pmap, va);
1392 /* are we current address space or kernel? */
1393 if (pmap_is_current(pmap))
1394 return (vtopte(va));
1395 mtx_lock(&PMAP2mutex);
1396 newpf = *pde & PG_FRAME;
1397 if ((*PMAP2 & PG_FRAME) != newpf) {
1398 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1399 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1401 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1407 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1410 static __inline void
1411 pmap_pte_release(pt_entry_t *pte)
1414 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1415 mtx_unlock(&PMAP2mutex);
1419 * NB: The sequence of updating a page table followed by accesses to the
1420 * corresponding pages is subject to the situation described in the "AMD64
1421 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1422 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1423 * right after modifying the PTE bits is crucial.
1425 static __inline void
1426 invlcaddr(void *caddr)
1429 invlpg((u_int)caddr);
1433 * Super fast pmap_pte routine best used when scanning
1434 * the pv lists. This eliminates many coarse-grained
1435 * invltlb calls. Note that many of the pv list
1436 * scans are across different pmaps. It is very wasteful
1437 * to do an entire invltlb for checking a single mapping.
1439 * If the given pmap is not the current pmap, pvh_global_lock
1440 * must be held and curthread pinned to a CPU.
1443 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1448 pde = pmap_pde(pmap, va);
1452 /* are we current address space or kernel? */
1453 if (pmap_is_current(pmap))
1454 return (vtopte(va));
1455 rw_assert(&pvh_global_lock, RA_WLOCKED);
1456 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1457 newpf = *pde & PG_FRAME;
1458 if ((*PMAP1 & PG_FRAME) != newpf) {
1459 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1461 PMAP1cpu = PCPU_GET(cpuid);
1467 if (PMAP1cpu != PCPU_GET(cpuid)) {
1468 PMAP1cpu = PCPU_GET(cpuid);
1474 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1480 * Routine: pmap_extract
1482 * Extract the physical page address associated
1483 * with the given map/virtual_address pair.
1486 pmap_extract(pmap_t pmap, vm_offset_t va)
1494 pde = pmap->pm_pdir[va >> PDRSHIFT];
1496 if ((pde & PG_PS) != 0)
1497 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1499 pte = pmap_pte(pmap, va);
1500 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK);
1501 pmap_pte_release(pte);
1509 * Routine: pmap_extract_and_hold
1511 * Atomically extract and hold the physical page
1512 * with the given pmap and virtual address pair
1513 * if that mapping permits the given protection.
1516 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1519 pt_entry_t pte, *ptep;
1527 pde = *pmap_pde(pmap, va);
1530 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1531 if (vm_page_pa_tryrelock(pmap, (pde &
1532 PG_PS_FRAME) | (va & PDRMASK), &pa))
1534 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1539 ptep = pmap_pte(pmap, va);
1541 pmap_pte_release(ptep);
1543 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1544 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1547 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1557 /***************************************************
1558 * Low level mapping routines.....
1559 ***************************************************/
1562 * Add a wired page to the kva.
1563 * Note: not SMP coherent.
1565 * This function may be used before pmap_bootstrap() is called.
1568 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1573 pte_store(pte, pa | PG_RW | PG_V | pgeflag);
1576 static __inline void
1577 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1582 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0));
1586 * Remove a page from the kernel pagetables.
1587 * Note: not SMP coherent.
1589 * This function may be used before pmap_bootstrap() is called.
1592 pmap_kremove(vm_offset_t va)
1601 * Used to map a range of physical addresses into kernel
1602 * virtual address space.
1604 * The value passed in '*virt' is a suggested virtual address for
1605 * the mapping. Architectures which can support a direct-mapped
1606 * physical to virtual region can return the appropriate address
1607 * within that region, leaving '*virt' unchanged. Other
1608 * architectures should map the pages starting at '*virt' and
1609 * update '*virt' with the first usable address after the mapped
1613 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1615 vm_offset_t va, sva;
1616 vm_paddr_t superpage_offset;
1621 * Does the physical address range's size and alignment permit at
1622 * least one superpage mapping to be created?
1624 superpage_offset = start & PDRMASK;
1625 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1627 * Increase the starting virtual address so that its alignment
1628 * does not preclude the use of superpage mappings.
1630 if ((va & PDRMASK) < superpage_offset)
1631 va = (va & ~PDRMASK) + superpage_offset;
1632 else if ((va & PDRMASK) > superpage_offset)
1633 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1636 while (start < end) {
1637 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1639 KASSERT((va & PDRMASK) == 0,
1640 ("pmap_map: misaligned va %#x", va));
1641 newpde = start | PG_PS | pgeflag | PG_RW | PG_V;
1642 pmap_kenter_pde(va, newpde);
1646 pmap_kenter(va, start);
1651 pmap_invalidate_range(kernel_pmap, sva, va);
1658 * Add a list of wired pages to the kva
1659 * this routine is only used for temporary
1660 * kernel mappings that do not need to have
1661 * page modification or references recorded.
1662 * Note that old mappings are simply written
1663 * over. The page *must* be wired.
1664 * Note: SMP coherent. Uses a ranged shootdown IPI.
1667 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1669 pt_entry_t *endpte, oldpte, pa, *pte;
1674 endpte = pte + count;
1675 while (pte < endpte) {
1677 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1678 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1680 #if defined(PAE) || defined(PAE_TABLES)
1681 pte_store(pte, pa | pgeflag | pg_nx | PG_RW | PG_V);
1683 pte_store(pte, pa | pgeflag | PG_RW | PG_V);
1688 if (__predict_false((oldpte & PG_V) != 0))
1689 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1694 * This routine tears out page mappings from the
1695 * kernel -- it is meant only for temporary mappings.
1696 * Note: SMP coherent. Uses a ranged shootdown IPI.
1699 pmap_qremove(vm_offset_t sva, int count)
1704 while (count-- > 0) {
1708 pmap_invalidate_range(kernel_pmap, sva, va);
1711 /***************************************************
1712 * Page table page management routines.....
1713 ***************************************************/
1714 static __inline void
1715 pmap_free_zero_pages(struct spglist *free)
1720 for (count = 0; (m = SLIST_FIRST(free)) != NULL; count++) {
1721 SLIST_REMOVE_HEAD(free, plinks.s.ss);
1722 /* Preserve the page's PG_ZERO setting. */
1723 vm_page_free_toq(m);
1729 * Schedule the specified unused page table page to be freed. Specifically,
1730 * add the page to the specified list of pages that will be released to the
1731 * physical memory manager after the TLB has been updated.
1733 static __inline void
1734 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1735 boolean_t set_PG_ZERO)
1739 m->flags |= PG_ZERO;
1741 m->flags &= ~PG_ZERO;
1742 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1746 * Inserts the specified page table page into the specified pmap's collection
1747 * of idle page table pages. Each of a pmap's page table pages is responsible
1748 * for mapping a distinct range of virtual addresses. The pmap's collection is
1749 * ordered by this virtual address range.
1752 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1755 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1756 return (vm_radix_insert(&pmap->pm_root, mpte));
1760 * Removes the page table page mapping the specified virtual address from the
1761 * specified pmap's collection of idle page table pages, and returns it.
1762 * Otherwise, returns NULL if there is no page table page corresponding to the
1763 * specified virtual address.
1765 static __inline vm_page_t
1766 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
1769 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1770 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT));
1774 * Decrements a page table page's wire count, which is used to record the
1775 * number of valid page table entries within the page. If the wire count
1776 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1777 * page table page was unmapped and FALSE otherwise.
1779 static inline boolean_t
1780 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1784 if (m->wire_count == 0) {
1785 _pmap_unwire_ptp(pmap, m, free);
1792 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1797 * unmap the page table page
1799 pmap->pm_pdir[m->pindex] = 0;
1800 --pmap->pm_stats.resident_count;
1803 * Do an invltlb to make the invalidated mapping
1804 * take effect immediately.
1806 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex);
1807 pmap_invalidate_page(pmap, pteva);
1810 * Put page on a list so that it is released after
1811 * *ALL* TLB shootdown is done
1813 pmap_add_delayed_free_list(m, free, TRUE);
1817 * After removing a page table entry, this routine is used to
1818 * conditionally free the page, and manage the hold/wire counts.
1821 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1826 if (va >= VM_MAXUSER_ADDRESS)
1828 ptepde = *pmap_pde(pmap, va);
1829 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1830 return (pmap_unwire_ptp(pmap, mpte, free));
1834 * Initialize the pmap for the swapper process.
1837 pmap_pinit0(pmap_t pmap)
1840 PMAP_LOCK_INIT(pmap);
1842 * Since the page table directory is shared with the kernel pmap,
1843 * which is already included in the list "allpmaps", this pmap does
1844 * not need to be inserted into that list.
1846 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD);
1847 #if defined(PAE) || defined(PAE_TABLES)
1848 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT);
1850 pmap->pm_root.rt_root = 0;
1851 CPU_ZERO(&pmap->pm_active);
1852 PCPU_SET(curpmap, pmap);
1853 TAILQ_INIT(&pmap->pm_pvchunk);
1854 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1858 * Initialize a preallocated and zeroed pmap structure,
1859 * such as one in a vmspace structure.
1862 pmap_pinit(pmap_t pmap)
1864 vm_page_t m, ptdpg[NPGPTD];
1869 * No need to allocate page table space yet but we do need a valid
1870 * page directory table.
1872 if (pmap->pm_pdir == NULL) {
1873 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
1874 if (pmap->pm_pdir == NULL)
1876 #if defined(PAE) || defined(PAE_TABLES)
1877 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
1878 KASSERT(((vm_offset_t)pmap->pm_pdpt &
1879 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
1880 ("pmap_pinit: pdpt misaligned"));
1881 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
1882 ("pmap_pinit: pdpt above 4g"));
1884 pmap->pm_root.rt_root = 0;
1886 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1887 ("pmap_pinit: pmap has reserved page table page(s)"));
1890 * allocate the page directory page(s)
1892 for (i = 0; i < NPGPTD;) {
1893 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1894 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1902 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD);
1904 for (i = 0; i < NPGPTD; i++)
1905 if ((ptdpg[i]->flags & PG_ZERO) == 0)
1906 pagezero(pmap->pm_pdir + (i * NPDEPG));
1908 mtx_lock_spin(&allpmaps_lock);
1909 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1910 /* Copy the kernel page table directory entries. */
1911 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t));
1912 mtx_unlock_spin(&allpmaps_lock);
1914 /* install self-referential address mapping entry(s) */
1915 for (i = 0; i < NPGPTD; i++) {
1916 pa = VM_PAGE_TO_PHYS(ptdpg[i]);
1917 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M;
1918 #if defined(PAE) || defined(PAE_TABLES)
1919 pmap->pm_pdpt[i] = pa | PG_V;
1923 CPU_ZERO(&pmap->pm_active);
1924 TAILQ_INIT(&pmap->pm_pvchunk);
1925 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1931 * this routine is called if the page table page is not
1935 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
1941 * Allocate a page table page.
1943 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1944 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1945 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
1947 rw_wunlock(&pvh_global_lock);
1949 rw_wlock(&pvh_global_lock);
1954 * Indicate the need to retry. While waiting, the page table
1955 * page may have been allocated.
1959 if ((m->flags & PG_ZERO) == 0)
1963 * Map the pagetable page into the process address space, if
1964 * it isn't already there.
1967 pmap->pm_stats.resident_count++;
1969 ptepa = VM_PAGE_TO_PHYS(m);
1970 pmap->pm_pdir[ptepindex] =
1971 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
1977 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
1984 * Calculate pagetable page index
1986 ptepindex = va >> PDRSHIFT;
1989 * Get the page directory entry
1991 ptepa = pmap->pm_pdir[ptepindex];
1994 * This supports switching from a 4MB page to a
1997 if (ptepa & PG_PS) {
1998 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
1999 ptepa = pmap->pm_pdir[ptepindex];
2003 * If the page table page is mapped, we just increment the
2004 * hold count, and activate it.
2007 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
2011 * Here if the pte page isn't mapped, or if it has
2014 m = _pmap_allocpte(pmap, ptepindex, flags);
2015 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2022 /***************************************************
2023 * Pmap allocation/deallocation routines.
2024 ***************************************************/
2027 * Release any resources held by the given physical map.
2028 * Called when a pmap initialized by pmap_pinit is being released.
2029 * Should only be called if the map contains no valid mappings.
2032 pmap_release(pmap_t pmap)
2034 vm_page_t m, ptdpg[NPGPTD];
2037 KASSERT(pmap->pm_stats.resident_count == 0,
2038 ("pmap_release: pmap resident count %ld != 0",
2039 pmap->pm_stats.resident_count));
2040 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2041 ("pmap_release: pmap has reserved page table page(s)"));
2042 KASSERT(CPU_EMPTY(&pmap->pm_active),
2043 ("releasing active pmap %p", pmap));
2045 mtx_lock_spin(&allpmaps_lock);
2046 LIST_REMOVE(pmap, pm_list);
2047 mtx_unlock_spin(&allpmaps_lock);
2049 for (i = 0; i < NPGPTD; i++)
2050 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] &
2053 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) *
2054 sizeof(*pmap->pm_pdir));
2056 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2058 for (i = 0; i < NPGPTD; i++) {
2060 #if defined(PAE) || defined(PAE_TABLES)
2061 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2062 ("pmap_release: got wrong ptd page"));
2064 vm_page_unwire_noq(m);
2065 vm_page_free_zero(m);
2070 kvm_size(SYSCTL_HANDLER_ARGS)
2072 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2074 return (sysctl_handle_long(oidp, &ksize, 0, req));
2076 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2077 0, 0, kvm_size, "IU", "Size of KVM");
2080 kvm_free(SYSCTL_HANDLER_ARGS)
2082 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2084 return (sysctl_handle_long(oidp, &kfree, 0, req));
2086 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2087 0, 0, kvm_free, "IU", "Amount of KVM free");
2090 * grow the number of kernel page table entries, if needed
2093 pmap_growkernel(vm_offset_t addr)
2095 vm_paddr_t ptppaddr;
2099 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2100 addr = roundup2(addr, NBPDR);
2101 if (addr - 1 >= kernel_map->max_offset)
2102 addr = kernel_map->max_offset;
2103 while (kernel_vm_end < addr) {
2104 if (pdir_pde(PTD, kernel_vm_end)) {
2105 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2106 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2107 kernel_vm_end = kernel_map->max_offset;
2113 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2114 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2117 panic("pmap_growkernel: no memory to grow kernel");
2121 if ((nkpg->flags & PG_ZERO) == 0)
2122 pmap_zero_page(nkpg);
2123 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2124 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2125 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir;
2127 pmap_kenter_pde(kernel_vm_end, newpdir);
2128 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2129 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2130 kernel_vm_end = kernel_map->max_offset;
2137 /***************************************************
2138 * page management routines.
2139 ***************************************************/
2141 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2142 CTASSERT(_NPCM == 11);
2143 CTASSERT(_NPCPV == 336);
2145 static __inline struct pv_chunk *
2146 pv_to_chunk(pv_entry_t pv)
2149 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2152 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2154 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2155 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2157 static const uint32_t pc_freemask[_NPCM] = {
2158 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2159 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2160 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2161 PC_FREE0_9, PC_FREE10
2164 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2165 "Current number of pv entries");
2168 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2170 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2171 "Current number of pv entry chunks");
2172 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2173 "Current number of pv entry chunks allocated");
2174 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2175 "Current number of pv entry chunks frees");
2176 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2177 "Number of times tried to get a chunk page but failed.");
2179 static long pv_entry_frees, pv_entry_allocs;
2180 static int pv_entry_spare;
2182 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2183 "Current number of pv entry frees");
2184 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2185 "Current number of pv entry allocs");
2186 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2187 "Current number of spare pv entries");
2191 * We are in a serious low memory condition. Resort to
2192 * drastic measures to free some pages so we can allocate
2193 * another pv entry chunk.
2196 pmap_pv_reclaim(pmap_t locked_pmap)
2199 struct pv_chunk *pc;
2200 struct md_page *pvh;
2203 pt_entry_t *pte, tpte;
2207 struct spglist free;
2209 int bit, field, freed;
2211 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2215 TAILQ_INIT(&newtail);
2216 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2217 SLIST_EMPTY(&free))) {
2218 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2219 if (pmap != pc->pc_pmap) {
2221 pmap_invalidate_all(pmap);
2222 if (pmap != locked_pmap)
2226 /* Avoid deadlock and lock recursion. */
2227 if (pmap > locked_pmap)
2229 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2231 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2237 * Destroy every non-wired, 4 KB page mapping in the chunk.
2240 for (field = 0; field < _NPCM; field++) {
2241 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2242 inuse != 0; inuse &= ~(1UL << bit)) {
2244 pv = &pc->pc_pventry[field * 32 + bit];
2246 pde = pmap_pde(pmap, va);
2247 if ((*pde & PG_PS) != 0)
2249 pte = pmap_pte(pmap, va);
2251 if ((tpte & PG_W) == 0)
2252 tpte = pte_load_clear(pte);
2253 pmap_pte_release(pte);
2254 if ((tpte & PG_W) != 0)
2257 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2259 if ((tpte & PG_G) != 0)
2260 pmap_invalidate_page(pmap, va);
2261 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2262 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2264 if ((tpte & PG_A) != 0)
2265 vm_page_aflag_set(m, PGA_REFERENCED);
2266 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2267 if (TAILQ_EMPTY(&m->md.pv_list) &&
2268 (m->flags & PG_FICTITIOUS) == 0) {
2269 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2270 if (TAILQ_EMPTY(&pvh->pv_list)) {
2271 vm_page_aflag_clear(m,
2275 pc->pc_map[field] |= 1UL << bit;
2276 pmap_unuse_pt(pmap, va, &free);
2281 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2284 /* Every freed mapping is for a 4 KB page. */
2285 pmap->pm_stats.resident_count -= freed;
2286 PV_STAT(pv_entry_frees += freed);
2287 PV_STAT(pv_entry_spare += freed);
2288 pv_entry_count -= freed;
2289 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2290 for (field = 0; field < _NPCM; field++)
2291 if (pc->pc_map[field] != pc_freemask[field]) {
2292 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2294 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2297 * One freed pv entry in locked_pmap is
2300 if (pmap == locked_pmap)
2304 if (field == _NPCM) {
2305 PV_STAT(pv_entry_spare -= _NPCPV);
2306 PV_STAT(pc_chunk_count--);
2307 PV_STAT(pc_chunk_frees++);
2308 /* Entire chunk is free; return it. */
2309 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2310 pmap_qremove((vm_offset_t)pc, 1);
2311 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2316 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2318 pmap_invalidate_all(pmap);
2319 if (pmap != locked_pmap)
2322 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2323 m_pc = SLIST_FIRST(&free);
2324 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2325 /* Recycle a freed page table page. */
2326 m_pc->wire_count = 1;
2328 pmap_free_zero_pages(&free);
2333 * free the pv_entry back to the free list
2336 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2338 struct pv_chunk *pc;
2339 int idx, field, bit;
2341 rw_assert(&pvh_global_lock, RA_WLOCKED);
2342 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2343 PV_STAT(pv_entry_frees++);
2344 PV_STAT(pv_entry_spare++);
2346 pc = pv_to_chunk(pv);
2347 idx = pv - &pc->pc_pventry[0];
2350 pc->pc_map[field] |= 1ul << bit;
2351 for (idx = 0; idx < _NPCM; idx++)
2352 if (pc->pc_map[idx] != pc_freemask[idx]) {
2354 * 98% of the time, pc is already at the head of the
2355 * list. If it isn't already, move it to the head.
2357 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2359 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2360 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2365 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2370 free_pv_chunk(struct pv_chunk *pc)
2374 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2375 PV_STAT(pv_entry_spare -= _NPCPV);
2376 PV_STAT(pc_chunk_count--);
2377 PV_STAT(pc_chunk_frees++);
2378 /* entire chunk is free, return it */
2379 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2380 pmap_qremove((vm_offset_t)pc, 1);
2381 vm_page_unwire(m, PQ_NONE);
2383 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2387 * get a new pv_entry, allocating a block from the system
2391 get_pv_entry(pmap_t pmap, boolean_t try)
2393 static const struct timeval printinterval = { 60, 0 };
2394 static struct timeval lastprint;
2397 struct pv_chunk *pc;
2400 rw_assert(&pvh_global_lock, RA_WLOCKED);
2401 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2402 PV_STAT(pv_entry_allocs++);
2404 if (pv_entry_count > pv_entry_high_water)
2405 if (ratecheck(&lastprint, &printinterval))
2406 printf("Approaching the limit on PV entries, consider "
2407 "increasing either the vm.pmap.shpgperproc or the "
2408 "vm.pmap.pv_entry_max tunable.\n");
2410 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2412 for (field = 0; field < _NPCM; field++) {
2413 if (pc->pc_map[field]) {
2414 bit = bsfl(pc->pc_map[field]);
2418 if (field < _NPCM) {
2419 pv = &pc->pc_pventry[field * 32 + bit];
2420 pc->pc_map[field] &= ~(1ul << bit);
2421 /* If this was the last item, move it to tail */
2422 for (field = 0; field < _NPCM; field++)
2423 if (pc->pc_map[field] != 0) {
2424 PV_STAT(pv_entry_spare--);
2425 return (pv); /* not full, return */
2427 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2428 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2429 PV_STAT(pv_entry_spare--);
2434 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2435 * global lock. If "pv_vafree" is currently non-empty, it will
2436 * remain non-empty until pmap_ptelist_alloc() completes.
2438 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2439 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2442 PV_STAT(pc_chunk_tryfail++);
2445 m = pmap_pv_reclaim(pmap);
2449 PV_STAT(pc_chunk_count++);
2450 PV_STAT(pc_chunk_allocs++);
2451 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2452 pmap_qenter((vm_offset_t)pc, &m, 1);
2454 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2455 for (field = 1; field < _NPCM; field++)
2456 pc->pc_map[field] = pc_freemask[field];
2457 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2458 pv = &pc->pc_pventry[0];
2459 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2460 PV_STAT(pv_entry_spare += _NPCPV - 1);
2464 static __inline pv_entry_t
2465 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2469 rw_assert(&pvh_global_lock, RA_WLOCKED);
2470 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2471 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2472 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2480 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2482 struct md_page *pvh;
2484 vm_offset_t va_last;
2487 rw_assert(&pvh_global_lock, RA_WLOCKED);
2488 KASSERT((pa & PDRMASK) == 0,
2489 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2492 * Transfer the 4mpage's pv entry for this mapping to the first
2495 pvh = pa_to_pvh(pa);
2496 va = trunc_4mpage(va);
2497 pv = pmap_pvh_remove(pvh, pmap, va);
2498 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2499 m = PHYS_TO_VM_PAGE(pa);
2500 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2501 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2502 va_last = va + NBPDR - PAGE_SIZE;
2505 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2506 ("pmap_pv_demote_pde: page %p is not managed", m));
2508 pmap_insert_entry(pmap, va, m);
2509 } while (va < va_last);
2512 #if VM_NRESERVLEVEL > 0
2514 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2516 struct md_page *pvh;
2518 vm_offset_t va_last;
2521 rw_assert(&pvh_global_lock, RA_WLOCKED);
2522 KASSERT((pa & PDRMASK) == 0,
2523 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2526 * Transfer the first page's pv entry for this mapping to the
2527 * 4mpage's pv list. Aside from avoiding the cost of a call
2528 * to get_pv_entry(), a transfer avoids the possibility that
2529 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2530 * removes one of the mappings that is being promoted.
2532 m = PHYS_TO_VM_PAGE(pa);
2533 va = trunc_4mpage(va);
2534 pv = pmap_pvh_remove(&m->md, pmap, va);
2535 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2536 pvh = pa_to_pvh(pa);
2537 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2538 /* Free the remaining NPTEPG - 1 pv entries. */
2539 va_last = va + NBPDR - PAGE_SIZE;
2543 pmap_pvh_free(&m->md, pmap, va);
2544 } while (va < va_last);
2546 #endif /* VM_NRESERVLEVEL > 0 */
2549 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2553 pv = pmap_pvh_remove(pvh, pmap, va);
2554 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2555 free_pv_entry(pmap, pv);
2559 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2561 struct md_page *pvh;
2563 rw_assert(&pvh_global_lock, RA_WLOCKED);
2564 pmap_pvh_free(&m->md, pmap, va);
2565 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2566 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2567 if (TAILQ_EMPTY(&pvh->pv_list))
2568 vm_page_aflag_clear(m, PGA_WRITEABLE);
2573 * Create a pv entry for page at pa for
2577 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2581 rw_assert(&pvh_global_lock, RA_WLOCKED);
2582 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2583 pv = get_pv_entry(pmap, FALSE);
2585 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2589 * Conditionally create a pv entry.
2592 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2596 rw_assert(&pvh_global_lock, RA_WLOCKED);
2597 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2598 if (pv_entry_count < pv_entry_high_water &&
2599 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2601 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2608 * Create the pv entries for each of the pages within a superpage.
2611 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2613 struct md_page *pvh;
2616 rw_assert(&pvh_global_lock, RA_WLOCKED);
2617 if (pv_entry_count < pv_entry_high_water &&
2618 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2620 pvh = pa_to_pvh(pa);
2621 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2628 * Fills a page table page with mappings to consecutive physical pages.
2631 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2635 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2637 newpte += PAGE_SIZE;
2642 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2643 * 2- or 4MB page mapping is invalidated.
2646 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2648 pd_entry_t newpde, oldpde;
2649 pt_entry_t *firstpte, newpte;
2652 struct spglist free;
2655 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2657 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2658 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2659 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
2661 KASSERT((oldpde & PG_W) == 0,
2662 ("pmap_demote_pde: page table page for a wired mapping"
2666 * Invalidate the 2- or 4MB page mapping and return
2667 * "failure" if the mapping was never accessed or the
2668 * allocation of the new page table page fails.
2670 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2671 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2672 VM_ALLOC_WIRED)) == NULL) {
2674 sva = trunc_4mpage(va);
2675 pmap_remove_pde(pmap, pde, sva, &free);
2676 if ((oldpde & PG_G) == 0)
2677 pmap_invalidate_pde_page(pmap, sva, oldpde);
2678 pmap_free_zero_pages(&free);
2679 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2680 " in pmap %p", va, pmap);
2683 if (va < VM_MAXUSER_ADDRESS)
2684 pmap->pm_stats.resident_count++;
2686 mptepa = VM_PAGE_TO_PHYS(mpte);
2689 * If the page mapping is in the kernel's address space, then the
2690 * KPTmap can provide access to the page table page. Otherwise,
2691 * temporarily map the page table page (mpte) into the kernel's
2692 * address space at either PADDR1 or PADDR2.
2695 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2696 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2697 if ((*PMAP1 & PG_FRAME) != mptepa) {
2698 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2700 PMAP1cpu = PCPU_GET(cpuid);
2706 if (PMAP1cpu != PCPU_GET(cpuid)) {
2707 PMAP1cpu = PCPU_GET(cpuid);
2715 mtx_lock(&PMAP2mutex);
2716 if ((*PMAP2 & PG_FRAME) != mptepa) {
2717 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2718 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2722 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2723 KASSERT((oldpde & PG_A) != 0,
2724 ("pmap_demote_pde: oldpde is missing PG_A"));
2725 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2726 ("pmap_demote_pde: oldpde is missing PG_M"));
2727 newpte = oldpde & ~PG_PS;
2728 if ((newpte & PG_PDE_PAT) != 0)
2729 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2732 * If the page table page is new, initialize it.
2734 if (mpte->wire_count == 1) {
2735 mpte->wire_count = NPTEPG;
2736 pmap_fill_ptp(firstpte, newpte);
2738 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2739 ("pmap_demote_pde: firstpte and newpte map different physical"
2743 * If the mapping has changed attributes, update the page table
2746 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2747 pmap_fill_ptp(firstpte, newpte);
2750 * Demote the mapping. This pmap is locked. The old PDE has
2751 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2752 * set. Thus, there is no danger of a race with another
2753 * processor changing the setting of PG_A and/or PG_M between
2754 * the read above and the store below.
2756 if (workaround_erratum383)
2757 pmap_update_pde(pmap, va, pde, newpde);
2758 else if (pmap == kernel_pmap)
2759 pmap_kenter_pde(va, newpde);
2761 pde_store(pde, newpde);
2762 if (firstpte == PADDR2)
2763 mtx_unlock(&PMAP2mutex);
2766 * Invalidate the recursive mapping of the page table page.
2768 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2771 * Demote the pv entry. This depends on the earlier demotion
2772 * of the mapping. Specifically, the (re)creation of a per-
2773 * page pv entry might trigger the execution of pmap_collect(),
2774 * which might reclaim a newly (re)created per-page pv entry
2775 * and destroy the associated mapping. In order to destroy
2776 * the mapping, the PDE must have already changed from mapping
2777 * the 2mpage to referencing the page table page.
2779 if ((oldpde & PG_MANAGED) != 0)
2780 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2782 pmap_pde_demotions++;
2783 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2784 " in pmap %p", va, pmap);
2789 * Removes a 2- or 4MB page mapping from the kernel pmap.
2792 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2798 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2799 mpte = pmap_remove_pt_page(pmap, va);
2801 panic("pmap_remove_kernel_pde: Missing pt page.");
2803 mptepa = VM_PAGE_TO_PHYS(mpte);
2804 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2807 * Initialize the page table page.
2809 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2812 * Remove the mapping.
2814 if (workaround_erratum383)
2815 pmap_update_pde(pmap, va, pde, newpde);
2817 pmap_kenter_pde(va, newpde);
2820 * Invalidate the recursive mapping of the page table page.
2822 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2826 * pmap_remove_pde: do the things to unmap a superpage in a process
2829 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2830 struct spglist *free)
2832 struct md_page *pvh;
2834 vm_offset_t eva, va;
2837 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2838 KASSERT((sva & PDRMASK) == 0,
2839 ("pmap_remove_pde: sva is not 4mpage aligned"));
2840 oldpde = pte_load_clear(pdq);
2842 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2845 * Machines that don't support invlpg, also don't support
2848 if ((oldpde & PG_G) != 0)
2849 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
2851 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2852 if (oldpde & PG_MANAGED) {
2853 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2854 pmap_pvh_free(pvh, pmap, sva);
2856 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2857 va < eva; va += PAGE_SIZE, m++) {
2858 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2861 vm_page_aflag_set(m, PGA_REFERENCED);
2862 if (TAILQ_EMPTY(&m->md.pv_list) &&
2863 TAILQ_EMPTY(&pvh->pv_list))
2864 vm_page_aflag_clear(m, PGA_WRITEABLE);
2867 if (pmap == kernel_pmap) {
2868 pmap_remove_kernel_pde(pmap, pdq, sva);
2870 mpte = pmap_remove_pt_page(pmap, sva);
2872 pmap->pm_stats.resident_count--;
2873 KASSERT(mpte->wire_count == NPTEPG,
2874 ("pmap_remove_pde: pte page wire count error"));
2875 mpte->wire_count = 0;
2876 pmap_add_delayed_free_list(mpte, free, FALSE);
2882 * pmap_remove_pte: do the things to unmap a page in a process
2885 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
2886 struct spglist *free)
2891 rw_assert(&pvh_global_lock, RA_WLOCKED);
2892 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2893 oldpte = pte_load_clear(ptq);
2894 KASSERT(oldpte != 0,
2895 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
2897 pmap->pm_stats.wired_count -= 1;
2899 * Machines that don't support invlpg, also don't support
2903 pmap_invalidate_page(kernel_pmap, va);
2904 pmap->pm_stats.resident_count -= 1;
2905 if (oldpte & PG_MANAGED) {
2906 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2907 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2910 vm_page_aflag_set(m, PGA_REFERENCED);
2911 pmap_remove_entry(pmap, m, va);
2913 return (pmap_unuse_pt(pmap, va, free));
2917 * Remove a single page from a process address space
2920 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
2924 rw_assert(&pvh_global_lock, RA_WLOCKED);
2925 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
2926 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2927 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
2929 pmap_remove_pte(pmap, pte, va, free);
2930 pmap_invalidate_page(pmap, va);
2934 * Remove the given range of addresses from the specified map.
2936 * It is assumed that the start and end are properly
2937 * rounded to the page size.
2940 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2945 struct spglist free;
2949 * Perform an unsynchronized read. This is, however, safe.
2951 if (pmap->pm_stats.resident_count == 0)
2957 rw_wlock(&pvh_global_lock);
2962 * special handling of removing one page. a very
2963 * common operation and easy to short circuit some
2966 if ((sva + PAGE_SIZE == eva) &&
2967 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
2968 pmap_remove_page(pmap, sva, &free);
2972 for (; sva < eva; sva = pdnxt) {
2976 * Calculate index for next page table.
2978 pdnxt = (sva + NBPDR) & ~PDRMASK;
2981 if (pmap->pm_stats.resident_count == 0)
2984 pdirindex = sva >> PDRSHIFT;
2985 ptpaddr = pmap->pm_pdir[pdirindex];
2988 * Weed out invalid mappings. Note: we assume that the page
2989 * directory table is always allocated, and in kernel virtual.
2995 * Check for large page.
2997 if ((ptpaddr & PG_PS) != 0) {
2999 * Are we removing the entire large page? If not,
3000 * demote the mapping and fall through.
3002 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3004 * The TLB entry for a PG_G mapping is
3005 * invalidated by pmap_remove_pde().
3007 if ((ptpaddr & PG_G) == 0)
3009 pmap_remove_pde(pmap,
3010 &pmap->pm_pdir[pdirindex], sva, &free);
3012 } else if (!pmap_demote_pde(pmap,
3013 &pmap->pm_pdir[pdirindex], sva)) {
3014 /* The large page mapping was destroyed. */
3020 * Limit our scan to either the end of the va represented
3021 * by the current page table page, or to the end of the
3022 * range being removed.
3027 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3033 * The TLB entry for a PG_G mapping is invalidated
3034 * by pmap_remove_pte().
3036 if ((*pte & PG_G) == 0)
3038 if (pmap_remove_pte(pmap, pte, sva, &free))
3045 pmap_invalidate_all(pmap);
3046 rw_wunlock(&pvh_global_lock);
3048 pmap_free_zero_pages(&free);
3052 * Routine: pmap_remove_all
3054 * Removes this physical page from
3055 * all physical maps in which it resides.
3056 * Reflects back modify bits to the pager.
3059 * Original versions of this routine were very
3060 * inefficient because they iteratively called
3061 * pmap_remove (slow...)
3065 pmap_remove_all(vm_page_t m)
3067 struct md_page *pvh;
3070 pt_entry_t *pte, tpte;
3073 struct spglist free;
3075 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3076 ("pmap_remove_all: page %p is not managed", m));
3078 rw_wlock(&pvh_global_lock);
3080 if ((m->flags & PG_FICTITIOUS) != 0)
3081 goto small_mappings;
3082 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3083 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3087 pde = pmap_pde(pmap, va);
3088 (void)pmap_demote_pde(pmap, pde, va);
3092 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3095 pmap->pm_stats.resident_count--;
3096 pde = pmap_pde(pmap, pv->pv_va);
3097 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3098 " a 4mpage in page %p's pv list", m));
3099 pte = pmap_pte_quick(pmap, pv->pv_va);
3100 tpte = pte_load_clear(pte);
3101 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3104 pmap->pm_stats.wired_count--;
3106 vm_page_aflag_set(m, PGA_REFERENCED);
3109 * Update the vm_page_t clean and reference bits.
3111 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3113 pmap_unuse_pt(pmap, pv->pv_va, &free);
3114 pmap_invalidate_page(pmap, pv->pv_va);
3115 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3116 free_pv_entry(pmap, pv);
3119 vm_page_aflag_clear(m, PGA_WRITEABLE);
3121 rw_wunlock(&pvh_global_lock);
3122 pmap_free_zero_pages(&free);
3126 * pmap_protect_pde: do the things to protect a 4mpage in a process
3129 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3131 pd_entry_t newpde, oldpde;
3132 vm_offset_t eva, va;
3134 boolean_t anychanged;
3136 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3137 KASSERT((sva & PDRMASK) == 0,
3138 ("pmap_protect_pde: sva is not 4mpage aligned"));
3141 oldpde = newpde = *pde;
3142 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
3143 (PG_MANAGED | PG_M | PG_RW)) {
3145 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3146 va < eva; va += PAGE_SIZE, m++)
3149 if ((prot & VM_PROT_WRITE) == 0)
3150 newpde &= ~(PG_RW | PG_M);
3151 #if defined(PAE) || defined(PAE_TABLES)
3152 if ((prot & VM_PROT_EXECUTE) == 0)
3155 if (newpde != oldpde) {
3157 * As an optimization to future operations on this PDE, clear
3158 * PG_PROMOTED. The impending invalidation will remove any
3159 * lingering 4KB page mappings from the TLB.
3161 if (!pde_cmpset(pde, oldpde, newpde & ~PG_PROMOTED))
3163 if ((oldpde & PG_G) != 0)
3164 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
3168 return (anychanged);
3172 * Set the physical protection on the
3173 * specified range of this map as requested.
3176 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3181 boolean_t anychanged, pv_lists_locked;
3183 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3184 if (prot == VM_PROT_NONE) {
3185 pmap_remove(pmap, sva, eva);
3189 #if defined(PAE) || defined(PAE_TABLES)
3190 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3191 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3194 if (prot & VM_PROT_WRITE)
3198 if (pmap_is_current(pmap))
3199 pv_lists_locked = FALSE;
3201 pv_lists_locked = TRUE;
3203 rw_wlock(&pvh_global_lock);
3209 for (; sva < eva; sva = pdnxt) {
3210 pt_entry_t obits, pbits;
3213 pdnxt = (sva + NBPDR) & ~PDRMASK;
3217 pdirindex = sva >> PDRSHIFT;
3218 ptpaddr = pmap->pm_pdir[pdirindex];
3221 * Weed out invalid mappings. Note: we assume that the page
3222 * directory table is always allocated, and in kernel virtual.
3228 * Check for large page.
3230 if ((ptpaddr & PG_PS) != 0) {
3232 * Are we protecting the entire large page? If not,
3233 * demote the mapping and fall through.
3235 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3237 * The TLB entry for a PG_G mapping is
3238 * invalidated by pmap_protect_pde().
3240 if (pmap_protect_pde(pmap,
3241 &pmap->pm_pdir[pdirindex], sva, prot))
3245 if (!pv_lists_locked) {
3246 pv_lists_locked = TRUE;
3247 if (!rw_try_wlock(&pvh_global_lock)) {
3249 pmap_invalidate_all(
3256 if (!pmap_demote_pde(pmap,
3257 &pmap->pm_pdir[pdirindex], sva)) {
3259 * The large page mapping was
3270 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3276 * Regardless of whether a pte is 32 or 64 bits in
3277 * size, PG_RW, PG_A, and PG_M are among the least
3278 * significant 32 bits.
3280 obits = pbits = *pte;
3281 if ((pbits & PG_V) == 0)
3284 if ((prot & VM_PROT_WRITE) == 0) {
3285 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3286 (PG_MANAGED | PG_M | PG_RW)) {
3287 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3290 pbits &= ~(PG_RW | PG_M);
3292 #if defined(PAE) || defined(PAE_TABLES)
3293 if ((prot & VM_PROT_EXECUTE) == 0)
3297 if (pbits != obits) {
3298 #if defined(PAE) || defined(PAE_TABLES)
3299 if (!atomic_cmpset_64(pte, obits, pbits))
3302 if (!atomic_cmpset_int((u_int *)pte, obits,
3307 pmap_invalidate_page(pmap, sva);
3314 pmap_invalidate_all(pmap);
3315 if (pv_lists_locked) {
3317 rw_wunlock(&pvh_global_lock);
3322 #if VM_NRESERVLEVEL > 0
3324 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3325 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3326 * For promotion to occur, two conditions must be met: (1) the 4KB page
3327 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3328 * mappings must have identical characteristics.
3330 * Managed (PG_MANAGED) mappings within the kernel address space are not
3331 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3332 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3336 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3339 pt_entry_t *firstpte, oldpte, pa, *pte;
3340 vm_offset_t oldpteva;
3343 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3346 * Examine the first PTE in the specified PTP. Abort if this PTE is
3347 * either invalid, unused, or does not map the first 4KB physical page
3348 * within a 2- or 4MB page.
3350 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3353 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3354 pmap_pde_p_failures++;
3355 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3356 " in pmap %p", va, pmap);
3359 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3360 pmap_pde_p_failures++;
3361 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3362 " in pmap %p", va, pmap);
3365 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3367 * When PG_M is already clear, PG_RW can be cleared without
3368 * a TLB invalidation.
3370 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3377 * Examine each of the other PTEs in the specified PTP. Abort if this
3378 * PTE maps an unexpected 4KB physical page or does not have identical
3379 * characteristics to the first PTE.
3381 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3382 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3385 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3386 pmap_pde_p_failures++;
3387 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3388 " in pmap %p", va, pmap);
3391 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3393 * When PG_M is already clear, PG_RW can be cleared
3394 * without a TLB invalidation.
3396 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3400 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3402 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3403 " in pmap %p", oldpteva, pmap);
3405 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3406 pmap_pde_p_failures++;
3407 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3408 " in pmap %p", va, pmap);
3415 * Save the page table page in its current state until the PDE
3416 * mapping the superpage is demoted by pmap_demote_pde() or
3417 * destroyed by pmap_remove_pde().
3419 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3420 KASSERT(mpte >= vm_page_array &&
3421 mpte < &vm_page_array[vm_page_array_size],
3422 ("pmap_promote_pde: page table page is out of range"));
3423 KASSERT(mpte->pindex == va >> PDRSHIFT,
3424 ("pmap_promote_pde: page table page's pindex is wrong"));
3425 if (pmap_insert_pt_page(pmap, mpte)) {
3426 pmap_pde_p_failures++;
3428 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3434 * Promote the pv entries.
3436 if ((newpde & PG_MANAGED) != 0)
3437 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3440 * Propagate the PAT index to its proper position.
3442 if ((newpde & PG_PTE_PAT) != 0)
3443 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3446 * Map the superpage.
3448 if (workaround_erratum383)
3449 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3450 else if (pmap == kernel_pmap)
3451 pmap_kenter_pde(va, PG_PROMOTED | PG_PS | newpde);
3453 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
3455 pmap_pde_promotions++;
3456 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3457 " in pmap %p", va, pmap);
3459 #endif /* VM_NRESERVLEVEL > 0 */
3462 * Insert the given physical page (p) at
3463 * the specified virtual address (v) in the
3464 * target physical map with the protection requested.
3466 * If specified, the page will be wired down, meaning
3467 * that the related pte can not be reclaimed.
3469 * NB: This is the only routine which MAY NOT lazy-evaluate
3470 * or lose information. That is, this routine must actually
3471 * insert this page into the given map NOW.
3474 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3475 u_int flags, int8_t psind)
3479 pt_entry_t newpte, origpte;
3483 boolean_t invlva, wired;
3485 va = trunc_page(va);
3487 wired = (flags & PMAP_ENTER_WIRED) != 0;
3489 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
3490 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
3491 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)",
3493 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3494 VM_OBJECT_ASSERT_LOCKED(m->object);
3496 rw_wlock(&pvh_global_lock);
3500 pde = pmap_pde(pmap, va);
3501 if (va < VM_MAXUSER_ADDRESS) {
3504 * In the case that a page table page is not resident,
3505 * we are creating it here. pmap_allocpte() handles
3508 mpte = pmap_allocpte(pmap, va, flags);
3510 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3511 ("pmap_allocpte failed with sleep allowed"));
3513 rw_wunlock(&pvh_global_lock);
3515 return (KERN_RESOURCE_SHORTAGE);
3519 * va is for KVA, so pmap_demote_pde() will never fail
3520 * to install a page table page. PG_V is also
3521 * asserted by pmap_demote_pde().
3523 KASSERT(pde != NULL && (*pde & PG_V) != 0,
3524 ("KVA %#x invalid pde pdir %#jx", va,
3525 (uintmax_t)pmap->pm_pdir[PTDPTDI]));
3526 if ((*pde & PG_PS) != 0)
3527 pmap_demote_pde(pmap, pde, va);
3529 pte = pmap_pte_quick(pmap, va);
3532 * Page Directory table entry is not valid, which should not
3533 * happen. We should have either allocated the page table
3534 * page or demoted the existing mapping above.
3537 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3538 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3541 pa = VM_PAGE_TO_PHYS(m);
3544 opa = origpte & PG_FRAME;
3547 * Mapping has not changed, must be protection or wiring change.
3549 if (origpte && (opa == pa)) {
3551 * Wiring change, just update stats. We don't worry about
3552 * wiring PT pages as they remain resident as long as there
3553 * are valid mappings in them. Hence, if a user page is wired,
3554 * the PT page will be also.
3556 if (wired && ((origpte & PG_W) == 0))
3557 pmap->pm_stats.wired_count++;
3558 else if (!wired && (origpte & PG_W))
3559 pmap->pm_stats.wired_count--;
3562 * Remove extra pte reference
3567 if (origpte & PG_MANAGED) {
3577 * Mapping has changed, invalidate old range and fall through to
3578 * handle validating new mapping.
3582 pmap->pm_stats.wired_count--;
3583 if (origpte & PG_MANAGED) {
3584 om = PHYS_TO_VM_PAGE(opa);
3585 pv = pmap_pvh_remove(&om->md, pmap, va);
3589 KASSERT(mpte->wire_count > 0,
3590 ("pmap_enter: missing reference to page table page,"
3594 pmap->pm_stats.resident_count++;
3597 * Enter on the PV list if part of our managed memory.
3599 if ((m->oflags & VPO_UNMANAGED) == 0) {
3600 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3601 ("pmap_enter: managed mapping within the clean submap"));
3603 pv = get_pv_entry(pmap, FALSE);
3605 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3607 } else if (pv != NULL)
3608 free_pv_entry(pmap, pv);
3611 * Increment counters
3614 pmap->pm_stats.wired_count++;
3618 * Now validate mapping with desired protection/wiring.
3620 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V);
3621 if ((prot & VM_PROT_WRITE) != 0) {
3623 if ((newpte & PG_MANAGED) != 0)
3624 vm_page_aflag_set(m, PGA_WRITEABLE);
3626 #if defined(PAE) || defined(PAE_TABLES)
3627 if ((prot & VM_PROT_EXECUTE) == 0)
3632 if (va < VM_MAXUSER_ADDRESS)
3634 if (pmap == kernel_pmap)
3638 * if the mapping or permission bits are different, we need
3639 * to update the pte.
3641 if ((origpte & ~(PG_M|PG_A)) != newpte) {
3643 if ((flags & VM_PROT_WRITE) != 0)
3645 if (origpte & PG_V) {
3647 origpte = pte_load_store(pte, newpte);
3648 if (origpte & PG_A) {
3649 if (origpte & PG_MANAGED)
3650 vm_page_aflag_set(om, PGA_REFERENCED);
3651 if (opa != VM_PAGE_TO_PHYS(m))
3653 #if defined(PAE) || defined(PAE_TABLES)
3654 if ((origpte & PG_NX) == 0 &&
3655 (newpte & PG_NX) != 0)
3659 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
3660 if ((origpte & PG_MANAGED) != 0)
3662 if ((prot & VM_PROT_WRITE) == 0)
3665 if ((origpte & PG_MANAGED) != 0 &&
3666 TAILQ_EMPTY(&om->md.pv_list) &&
3667 ((om->flags & PG_FICTITIOUS) != 0 ||
3668 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3669 vm_page_aflag_clear(om, PGA_WRITEABLE);
3671 pmap_invalidate_page(pmap, va);
3673 pte_store(pte, newpte);
3676 #if VM_NRESERVLEVEL > 0
3678 * If both the page table page and the reservation are fully
3679 * populated, then attempt promotion.
3681 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3682 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3683 vm_reserv_level_iffullpop(m) == 0)
3684 pmap_promote_pde(pmap, pde, va);
3688 rw_wunlock(&pvh_global_lock);
3690 return (KERN_SUCCESS);
3694 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and
3695 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
3696 * blocking, (2) a mapping already exists at the specified virtual address, or
3697 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3700 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3702 pd_entry_t *pde, newpde;
3704 rw_assert(&pvh_global_lock, RA_WLOCKED);
3705 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3706 pde = pmap_pde(pmap, va);
3708 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3709 " in pmap %p", va, pmap);
3712 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3714 if ((m->oflags & VPO_UNMANAGED) == 0) {
3715 newpde |= PG_MANAGED;
3718 * Abort this mapping if its PV entry could not be created.
3720 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) {
3721 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3722 " in pmap %p", va, pmap);
3726 #if defined(PAE) || defined(PAE_TABLES)
3727 if ((prot & VM_PROT_EXECUTE) == 0)
3730 if (va < VM_MAXUSER_ADDRESS)
3734 * Increment counters.
3736 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3739 * Map the superpage. (This is not a promoted mapping; there will not
3740 * be any lingering 4KB page mappings in the TLB.)
3742 pde_store(pde, newpde);
3744 pmap_pde_mappings++;
3745 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3746 " in pmap %p", va, pmap);
3751 * Maps a sequence of resident pages belonging to the same object.
3752 * The sequence begins with the given page m_start. This page is
3753 * mapped at the given virtual address start. Each subsequent page is
3754 * mapped at a virtual address that is offset from start by the same
3755 * amount as the page is offset from m_start within the object. The
3756 * last page in the sequence is the page with the largest offset from
3757 * m_start that can be mapped at a virtual address less than the given
3758 * virtual address end. Not every virtual page between start and end
3759 * is mapped; only those for which a resident page exists with the
3760 * corresponding offset from m_start are mapped.
3763 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3764 vm_page_t m_start, vm_prot_t prot)
3768 vm_pindex_t diff, psize;
3770 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3772 psize = atop(end - start);
3775 rw_wlock(&pvh_global_lock);
3777 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3778 va = start + ptoa(diff);
3779 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3780 m->psind == 1 && pg_ps_enabled &&
3781 pmap_enter_pde(pmap, va, m, prot))
3782 m = &m[NBPDR / PAGE_SIZE - 1];
3784 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3786 m = TAILQ_NEXT(m, listq);
3788 rw_wunlock(&pvh_global_lock);
3793 * this code makes some *MAJOR* assumptions:
3794 * 1. Current pmap & pmap exists.
3797 * 4. No page table pages.
3798 * but is *MUCH* faster than pmap_enter...
3802 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3805 rw_wlock(&pvh_global_lock);
3807 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
3808 rw_wunlock(&pvh_global_lock);
3813 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3814 vm_prot_t prot, vm_page_t mpte)
3818 struct spglist free;
3820 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3821 (m->oflags & VPO_UNMANAGED) != 0,
3822 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3823 rw_assert(&pvh_global_lock, RA_WLOCKED);
3824 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3827 * In the case that a page table page is not
3828 * resident, we are creating it here.
3830 if (va < VM_MAXUSER_ADDRESS) {
3835 * Calculate pagetable page index
3837 ptepindex = va >> PDRSHIFT;
3838 if (mpte && (mpte->pindex == ptepindex)) {
3842 * Get the page directory entry
3844 ptepa = pmap->pm_pdir[ptepindex];
3847 * If the page table page is mapped, we just increment
3848 * the hold count, and activate it.
3853 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
3856 mpte = _pmap_allocpte(pmap, ptepindex,
3857 PMAP_ENTER_NOSLEEP);
3867 * This call to vtopte makes the assumption that we are
3868 * entering the page into the current pmap. In order to support
3869 * quick entry into any pmap, one would likely use pmap_pte_quick.
3870 * But that isn't as quick as vtopte.
3882 * Enter on the PV list if part of our managed memory.
3884 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3885 !pmap_try_insert_pv_entry(pmap, va, m)) {
3888 if (pmap_unwire_ptp(pmap, mpte, &free)) {
3889 pmap_invalidate_page(pmap, va);
3890 pmap_free_zero_pages(&free);
3899 * Increment counters
3901 pmap->pm_stats.resident_count++;
3903 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3904 #if defined(PAE) || defined(PAE_TABLES)
3905 if ((prot & VM_PROT_EXECUTE) == 0)
3910 * Now validate mapping with RO protection
3912 if ((m->oflags & VPO_UNMANAGED) != 0)
3913 pte_store(pte, pa | PG_V | PG_U);
3915 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3920 * Make a temporary mapping for a physical address. This is only intended
3921 * to be used for panic dumps.
3924 pmap_kenter_temporary(vm_paddr_t pa, int i)
3928 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3929 pmap_kenter(va, pa);
3931 return ((void *)crashdumpmap);
3935 * This code maps large physical mmap regions into the
3936 * processor address space. Note that some shortcuts
3937 * are taken, but the code works.
3940 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3941 vm_pindex_t pindex, vm_size_t size)
3944 vm_paddr_t pa, ptepa;
3948 VM_OBJECT_ASSERT_WLOCKED(object);
3949 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3950 ("pmap_object_init_pt: non-device object"));
3952 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3953 if (!vm_object_populate(object, pindex, pindex + atop(size)))
3955 p = vm_page_lookup(object, pindex);
3956 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3957 ("pmap_object_init_pt: invalid page %p", p));
3958 pat_mode = p->md.pat_mode;
3961 * Abort the mapping if the first page is not physically
3962 * aligned to a 2/4MB page boundary.
3964 ptepa = VM_PAGE_TO_PHYS(p);
3965 if (ptepa & (NBPDR - 1))
3969 * Skip the first page. Abort the mapping if the rest of
3970 * the pages are not physically contiguous or have differing
3971 * memory attributes.
3973 p = TAILQ_NEXT(p, listq);
3974 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
3976 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3977 ("pmap_object_init_pt: invalid page %p", p));
3978 if (pa != VM_PAGE_TO_PHYS(p) ||
3979 pat_mode != p->md.pat_mode)
3981 p = TAILQ_NEXT(p, listq);
3985 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
3986 * "size" is a multiple of 2/4M, adding the PAT setting to
3987 * "pa" will not affect the termination of this loop.
3990 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
3991 size; pa += NBPDR) {
3992 pde = pmap_pde(pmap, addr);
3994 pde_store(pde, pa | PG_PS | PG_M | PG_A |
3995 PG_U | PG_RW | PG_V);
3996 pmap->pm_stats.resident_count += NBPDR /
3998 pmap_pde_mappings++;
4000 /* Else continue on if the PDE is already valid. */
4008 * Clear the wired attribute from the mappings for the specified range of
4009 * addresses in the given pmap. Every valid mapping within that range
4010 * must have the wired attribute set. In contrast, invalid mappings
4011 * cannot have the wired attribute set, so they are ignored.
4013 * The wired attribute of the page table entry is not a hardware feature,
4014 * so there is no need to invalidate any TLB entries.
4017 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4022 boolean_t pv_lists_locked;
4024 if (pmap_is_current(pmap))
4025 pv_lists_locked = FALSE;
4027 pv_lists_locked = TRUE;
4029 rw_wlock(&pvh_global_lock);
4033 for (; sva < eva; sva = pdnxt) {
4034 pdnxt = (sva + NBPDR) & ~PDRMASK;
4037 pde = pmap_pde(pmap, sva);
4038 if ((*pde & PG_V) == 0)
4040 if ((*pde & PG_PS) != 0) {
4041 if ((*pde & PG_W) == 0)
4042 panic("pmap_unwire: pde %#jx is missing PG_W",
4046 * Are we unwiring the entire large page? If not,
4047 * demote the mapping and fall through.
4049 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4051 * Regardless of whether a pde (or pte) is 32
4052 * or 64 bits in size, PG_W is among the least
4053 * significant 32 bits.
4055 atomic_clear_int((u_int *)pde, PG_W);
4056 pmap->pm_stats.wired_count -= NBPDR /
4060 if (!pv_lists_locked) {
4061 pv_lists_locked = TRUE;
4062 if (!rw_try_wlock(&pvh_global_lock)) {
4069 if (!pmap_demote_pde(pmap, pde, sva))
4070 panic("pmap_unwire: demotion failed");
4075 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4077 if ((*pte & PG_V) == 0)
4079 if ((*pte & PG_W) == 0)
4080 panic("pmap_unwire: pte %#jx is missing PG_W",
4084 * PG_W must be cleared atomically. Although the pmap
4085 * lock synchronizes access to PG_W, another processor
4086 * could be setting PG_M and/or PG_A concurrently.
4088 * PG_W is among the least significant 32 bits.
4090 atomic_clear_int((u_int *)pte, PG_W);
4091 pmap->pm_stats.wired_count--;
4094 if (pv_lists_locked) {
4096 rw_wunlock(&pvh_global_lock);
4103 * Copy the range specified by src_addr/len
4104 * from the source map to the range dst_addr/len
4105 * in the destination map.
4107 * This routine is only advisory and need not do anything.
4111 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4112 vm_offset_t src_addr)
4114 struct spglist free;
4116 vm_offset_t end_addr = src_addr + len;
4119 if (dst_addr != src_addr)
4122 if (!pmap_is_current(src_pmap))
4125 rw_wlock(&pvh_global_lock);
4126 if (dst_pmap < src_pmap) {
4127 PMAP_LOCK(dst_pmap);
4128 PMAP_LOCK(src_pmap);
4130 PMAP_LOCK(src_pmap);
4131 PMAP_LOCK(dst_pmap);
4134 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4135 pt_entry_t *src_pte, *dst_pte;
4136 vm_page_t dstmpte, srcmpte;
4137 pd_entry_t srcptepaddr;
4140 KASSERT(addr < UPT_MIN_ADDRESS,
4141 ("pmap_copy: invalid to pmap_copy page tables"));
4143 pdnxt = (addr + NBPDR) & ~PDRMASK;
4146 ptepindex = addr >> PDRSHIFT;
4148 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4149 if (srcptepaddr == 0)
4152 if (srcptepaddr & PG_PS) {
4153 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4155 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4156 ((srcptepaddr & PG_MANAGED) == 0 ||
4157 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4159 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4161 dst_pmap->pm_stats.resident_count +=
4163 pmap_pde_mappings++;
4168 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4169 KASSERT(srcmpte->wire_count > 0,
4170 ("pmap_copy: source page table page is unused"));
4172 if (pdnxt > end_addr)
4175 src_pte = vtopte(addr);
4176 while (addr < pdnxt) {
4180 * we only virtual copy managed pages
4182 if ((ptetemp & PG_MANAGED) != 0) {
4183 dstmpte = pmap_allocpte(dst_pmap, addr,
4184 PMAP_ENTER_NOSLEEP);
4185 if (dstmpte == NULL)
4187 dst_pte = pmap_pte_quick(dst_pmap, addr);
4188 if (*dst_pte == 0 &&
4189 pmap_try_insert_pv_entry(dst_pmap, addr,
4190 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4192 * Clear the wired, modified, and
4193 * accessed (referenced) bits
4196 *dst_pte = ptetemp & ~(PG_W | PG_M |
4198 dst_pmap->pm_stats.resident_count++;
4201 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4203 pmap_invalidate_page(dst_pmap,
4205 pmap_free_zero_pages(&free);
4209 if (dstmpte->wire_count >= srcmpte->wire_count)
4218 rw_wunlock(&pvh_global_lock);
4219 PMAP_UNLOCK(src_pmap);
4220 PMAP_UNLOCK(dst_pmap);
4224 * Zero 1 page of virtual memory mapped from a hardware page by the caller.
4226 static __inline void
4227 pagezero(void *page)
4229 #if defined(I686_CPU)
4230 if (cpu_class == CPUCLASS_686) {
4231 if (cpu_feature & CPUID_SSE2)
4232 sse2_pagezero(page);
4234 i686_pagezero(page);
4237 bzero(page, PAGE_SIZE);
4241 * Zero the specified hardware page.
4244 pmap_zero_page(vm_page_t m)
4246 pt_entry_t *cmap_pte2;
4251 cmap_pte2 = pc->pc_cmap_pte2;
4252 mtx_lock(&pc->pc_cmap_lock);
4254 panic("pmap_zero_page: CMAP2 busy");
4255 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4256 pmap_cache_bits(m->md.pat_mode, 0);
4257 invlcaddr(pc->pc_cmap_addr2);
4258 pagezero(pc->pc_cmap_addr2);
4262 * Unpin the thread before releasing the lock. Otherwise the thread
4263 * could be rescheduled while still bound to the current CPU, only
4264 * to unpin itself immediately upon resuming execution.
4267 mtx_unlock(&pc->pc_cmap_lock);
4271 * Zero an an area within a single hardware page. off and size must not
4272 * cover an area beyond a single hardware page.
4275 pmap_zero_page_area(vm_page_t m, int off, int size)
4277 pt_entry_t *cmap_pte2;
4282 cmap_pte2 = pc->pc_cmap_pte2;
4283 mtx_lock(&pc->pc_cmap_lock);
4285 panic("pmap_zero_page_area: CMAP2 busy");
4286 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4287 pmap_cache_bits(m->md.pat_mode, 0);
4288 invlcaddr(pc->pc_cmap_addr2);
4289 if (off == 0 && size == PAGE_SIZE)
4290 pagezero(pc->pc_cmap_addr2);
4292 bzero(pc->pc_cmap_addr2 + off, size);
4295 mtx_unlock(&pc->pc_cmap_lock);
4299 * Copy 1 specified hardware page to another.
4302 pmap_copy_page(vm_page_t src, vm_page_t dst)
4304 pt_entry_t *cmap_pte1, *cmap_pte2;
4309 cmap_pte1 = pc->pc_cmap_pte1;
4310 cmap_pte2 = pc->pc_cmap_pte2;
4311 mtx_lock(&pc->pc_cmap_lock);
4313 panic("pmap_copy_page: CMAP1 busy");
4315 panic("pmap_copy_page: CMAP2 busy");
4316 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4317 pmap_cache_bits(src->md.pat_mode, 0);
4318 invlcaddr(pc->pc_cmap_addr1);
4319 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4320 pmap_cache_bits(dst->md.pat_mode, 0);
4321 invlcaddr(pc->pc_cmap_addr2);
4322 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE);
4326 mtx_unlock(&pc->pc_cmap_lock);
4329 int unmapped_buf_allowed = 1;
4332 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4333 vm_offset_t b_offset, int xfersize)
4335 vm_page_t a_pg, b_pg;
4337 vm_offset_t a_pg_offset, b_pg_offset;
4338 pt_entry_t *cmap_pte1, *cmap_pte2;
4344 cmap_pte1 = pc->pc_cmap_pte1;
4345 cmap_pte2 = pc->pc_cmap_pte2;
4346 mtx_lock(&pc->pc_cmap_lock);
4347 if (*cmap_pte1 != 0)
4348 panic("pmap_copy_pages: CMAP1 busy");
4349 if (*cmap_pte2 != 0)
4350 panic("pmap_copy_pages: CMAP2 busy");
4351 while (xfersize > 0) {
4352 a_pg = ma[a_offset >> PAGE_SHIFT];
4353 a_pg_offset = a_offset & PAGE_MASK;
4354 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4355 b_pg = mb[b_offset >> PAGE_SHIFT];
4356 b_pg_offset = b_offset & PAGE_MASK;
4357 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4358 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4359 pmap_cache_bits(a_pg->md.pat_mode, 0);
4360 invlcaddr(pc->pc_cmap_addr1);
4361 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4362 PG_M | pmap_cache_bits(b_pg->md.pat_mode, 0);
4363 invlcaddr(pc->pc_cmap_addr2);
4364 a_cp = pc->pc_cmap_addr1 + a_pg_offset;
4365 b_cp = pc->pc_cmap_addr2 + b_pg_offset;
4366 bcopy(a_cp, b_cp, cnt);
4374 mtx_unlock(&pc->pc_cmap_lock);
4378 * Returns true if the pmap's pv is one of the first
4379 * 16 pvs linked to from this page. This count may
4380 * be changed upwards or downwards in the future; it
4381 * is only necessary that true be returned for a small
4382 * subset of pmaps for proper page aging.
4385 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4387 struct md_page *pvh;
4392 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4393 ("pmap_page_exists_quick: page %p is not managed", m));
4395 rw_wlock(&pvh_global_lock);
4396 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4397 if (PV_PMAP(pv) == pmap) {
4405 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4406 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4407 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4408 if (PV_PMAP(pv) == pmap) {
4417 rw_wunlock(&pvh_global_lock);
4422 * pmap_page_wired_mappings:
4424 * Return the number of managed mappings to the given physical page
4428 pmap_page_wired_mappings(vm_page_t m)
4433 if ((m->oflags & VPO_UNMANAGED) != 0)
4435 rw_wlock(&pvh_global_lock);
4436 count = pmap_pvh_wired_mappings(&m->md, count);
4437 if ((m->flags & PG_FICTITIOUS) == 0) {
4438 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4441 rw_wunlock(&pvh_global_lock);
4446 * pmap_pvh_wired_mappings:
4448 * Return the updated number "count" of managed mappings that are wired.
4451 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4457 rw_assert(&pvh_global_lock, RA_WLOCKED);
4459 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4462 pte = pmap_pte_quick(pmap, pv->pv_va);
4463 if ((*pte & PG_W) != 0)
4472 * Returns TRUE if the given page is mapped individually or as part of
4473 * a 4mpage. Otherwise, returns FALSE.
4476 pmap_page_is_mapped(vm_page_t m)
4480 if ((m->oflags & VPO_UNMANAGED) != 0)
4482 rw_wlock(&pvh_global_lock);
4483 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4484 ((m->flags & PG_FICTITIOUS) == 0 &&
4485 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4486 rw_wunlock(&pvh_global_lock);
4491 * Remove all pages from specified address space
4492 * this aids process exit speeds. Also, this code
4493 * is special cased for current process only, but
4494 * can have the more generic (and slightly slower)
4495 * mode enabled. This is much faster than pmap_remove
4496 * in the case of running down an entire address space.
4499 pmap_remove_pages(pmap_t pmap)
4501 pt_entry_t *pte, tpte;
4502 vm_page_t m, mpte, mt;
4504 struct md_page *pvh;
4505 struct pv_chunk *pc, *npc;
4506 struct spglist free;
4509 uint32_t inuse, bitmask;
4512 if (pmap != PCPU_GET(curpmap)) {
4513 printf("warning: pmap_remove_pages called with non-current pmap\n");
4517 rw_wlock(&pvh_global_lock);
4520 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4521 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4524 for (field = 0; field < _NPCM; field++) {
4525 inuse = ~pc->pc_map[field] & pc_freemask[field];
4526 while (inuse != 0) {
4528 bitmask = 1UL << bit;
4529 idx = field * 32 + bit;
4530 pv = &pc->pc_pventry[idx];
4533 pte = pmap_pde(pmap, pv->pv_va);
4535 if ((tpte & PG_PS) == 0) {
4536 pte = vtopte(pv->pv_va);
4537 tpte = *pte & ~PG_PTE_PAT;
4542 "TPTE at %p IS ZERO @ VA %08x\n",
4548 * We cannot remove wired pages from a process' mapping at this time
4555 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4556 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4557 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4558 m, (uintmax_t)m->phys_addr,
4561 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4562 m < &vm_page_array[vm_page_array_size],
4563 ("pmap_remove_pages: bad tpte %#jx",
4569 * Update the vm_page_t clean/reference bits.
4571 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4572 if ((tpte & PG_PS) != 0) {
4573 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4580 PV_STAT(pv_entry_frees++);
4581 PV_STAT(pv_entry_spare++);
4583 pc->pc_map[field] |= bitmask;
4584 if ((tpte & PG_PS) != 0) {
4585 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4586 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4587 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4588 if (TAILQ_EMPTY(&pvh->pv_list)) {
4589 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4590 if (TAILQ_EMPTY(&mt->md.pv_list))
4591 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4593 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
4595 pmap->pm_stats.resident_count--;
4596 KASSERT(mpte->wire_count == NPTEPG,
4597 ("pmap_remove_pages: pte page wire count error"));
4598 mpte->wire_count = 0;
4599 pmap_add_delayed_free_list(mpte, &free, FALSE);
4602 pmap->pm_stats.resident_count--;
4603 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4604 if (TAILQ_EMPTY(&m->md.pv_list) &&
4605 (m->flags & PG_FICTITIOUS) == 0) {
4606 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4607 if (TAILQ_EMPTY(&pvh->pv_list))
4608 vm_page_aflag_clear(m, PGA_WRITEABLE);
4610 pmap_unuse_pt(pmap, pv->pv_va, &free);
4615 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4620 pmap_invalidate_all(pmap);
4621 rw_wunlock(&pvh_global_lock);
4623 pmap_free_zero_pages(&free);
4629 * Return whether or not the specified physical page was modified
4630 * in any physical maps.
4633 pmap_is_modified(vm_page_t m)
4637 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4638 ("pmap_is_modified: page %p is not managed", m));
4641 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4642 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4643 * is clear, no PTEs can have PG_M set.
4645 VM_OBJECT_ASSERT_WLOCKED(m->object);
4646 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4648 rw_wlock(&pvh_global_lock);
4649 rv = pmap_is_modified_pvh(&m->md) ||
4650 ((m->flags & PG_FICTITIOUS) == 0 &&
4651 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4652 rw_wunlock(&pvh_global_lock);
4657 * Returns TRUE if any of the given mappings were used to modify
4658 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4659 * mappings are supported.
4662 pmap_is_modified_pvh(struct md_page *pvh)
4669 rw_assert(&pvh_global_lock, RA_WLOCKED);
4672 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4675 pte = pmap_pte_quick(pmap, pv->pv_va);
4676 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4686 * pmap_is_prefaultable:
4688 * Return whether or not the specified virtual address is elgible
4692 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4700 pde = pmap_pde(pmap, addr);
4701 if (*pde != 0 && (*pde & PG_PS) == 0) {
4710 * pmap_is_referenced:
4712 * Return whether or not the specified physical page was referenced
4713 * in any physical maps.
4716 pmap_is_referenced(vm_page_t m)
4720 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4721 ("pmap_is_referenced: page %p is not managed", m));
4722 rw_wlock(&pvh_global_lock);
4723 rv = pmap_is_referenced_pvh(&m->md) ||
4724 ((m->flags & PG_FICTITIOUS) == 0 &&
4725 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4726 rw_wunlock(&pvh_global_lock);
4731 * Returns TRUE if any of the given mappings were referenced and FALSE
4732 * otherwise. Both page and 4mpage mappings are supported.
4735 pmap_is_referenced_pvh(struct md_page *pvh)
4742 rw_assert(&pvh_global_lock, RA_WLOCKED);
4745 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4748 pte = pmap_pte_quick(pmap, pv->pv_va);
4749 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4759 * Clear the write and modified bits in each of the given page's mappings.
4762 pmap_remove_write(vm_page_t m)
4764 struct md_page *pvh;
4765 pv_entry_t next_pv, pv;
4768 pt_entry_t oldpte, *pte;
4771 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4772 ("pmap_remove_write: page %p is not managed", m));
4775 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4776 * set by another thread while the object is locked. Thus,
4777 * if PGA_WRITEABLE is clear, no page table entries need updating.
4779 VM_OBJECT_ASSERT_WLOCKED(m->object);
4780 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4782 rw_wlock(&pvh_global_lock);
4784 if ((m->flags & PG_FICTITIOUS) != 0)
4785 goto small_mappings;
4786 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4787 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4791 pde = pmap_pde(pmap, va);
4792 if ((*pde & PG_RW) != 0)
4793 (void)pmap_demote_pde(pmap, pde, va);
4797 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4800 pde = pmap_pde(pmap, pv->pv_va);
4801 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
4802 " a 4mpage in page %p's pv list", m));
4803 pte = pmap_pte_quick(pmap, pv->pv_va);
4806 if ((oldpte & PG_RW) != 0) {
4808 * Regardless of whether a pte is 32 or 64 bits
4809 * in size, PG_RW and PG_M are among the least
4810 * significant 32 bits.
4812 if (!atomic_cmpset_int((u_int *)pte, oldpte,
4813 oldpte & ~(PG_RW | PG_M)))
4815 if ((oldpte & PG_M) != 0)
4817 pmap_invalidate_page(pmap, pv->pv_va);
4821 vm_page_aflag_clear(m, PGA_WRITEABLE);
4823 rw_wunlock(&pvh_global_lock);
4827 * pmap_ts_referenced:
4829 * Return a count of reference bits for a page, clearing those bits.
4830 * It is not necessary for every reference bit to be cleared, but it
4831 * is necessary that 0 only be returned when there are truly no
4832 * reference bits set.
4834 * As an optimization, update the page's dirty field if a modified bit is
4835 * found while counting reference bits. This opportunistic update can be
4836 * performed at low cost and can eliminate the need for some future calls
4837 * to pmap_is_modified(). However, since this function stops after
4838 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4839 * dirty pages. Those dirty pages will only be detected by a future call
4840 * to pmap_is_modified().
4843 pmap_ts_referenced(vm_page_t m)
4845 struct md_page *pvh;
4853 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4854 ("pmap_ts_referenced: page %p is not managed", m));
4855 pa = VM_PAGE_TO_PHYS(m);
4856 pvh = pa_to_pvh(pa);
4857 rw_wlock(&pvh_global_lock);
4859 if ((m->flags & PG_FICTITIOUS) != 0 ||
4860 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4861 goto small_mappings;
4866 pde = pmap_pde(pmap, pv->pv_va);
4867 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4869 * Although "*pde" is mapping a 2/4MB page, because
4870 * this function is called at a 4KB page granularity,
4871 * we only update the 4KB page under test.
4875 if ((*pde & PG_A) != 0) {
4877 * Since this reference bit is shared by either 1024
4878 * or 512 4KB pages, it should not be cleared every
4879 * time it is tested. Apply a simple "hash" function
4880 * on the physical page number, the virtual superpage
4881 * number, and the pmap address to select one 4KB page
4882 * out of the 1024 or 512 on which testing the
4883 * reference bit will result in clearing that bit.
4884 * This function is designed to avoid the selection of
4885 * the same 4KB page for every 2- or 4MB page mapping.
4887 * On demotion, a mapping that hasn't been referenced
4888 * is simply destroyed. To avoid the possibility of a
4889 * subsequent page fault on a demoted wired mapping,
4890 * always leave its reference bit set. Moreover,
4891 * since the superpage is wired, the current state of
4892 * its reference bit won't affect page replacement.
4894 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
4895 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
4896 (*pde & PG_W) == 0) {
4897 atomic_clear_int((u_int *)pde, PG_A);
4898 pmap_invalidate_page(pmap, pv->pv_va);
4903 /* Rotate the PV list if it has more than one entry. */
4904 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4905 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4906 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4908 if (rtval >= PMAP_TS_REFERENCED_MAX)
4910 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4912 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4918 pde = pmap_pde(pmap, pv->pv_va);
4919 KASSERT((*pde & PG_PS) == 0,
4920 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
4922 pte = pmap_pte_quick(pmap, pv->pv_va);
4923 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4925 if ((*pte & PG_A) != 0) {
4926 atomic_clear_int((u_int *)pte, PG_A);
4927 pmap_invalidate_page(pmap, pv->pv_va);
4931 /* Rotate the PV list if it has more than one entry. */
4932 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4933 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4934 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4936 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
4937 PMAP_TS_REFERENCED_MAX);
4940 rw_wunlock(&pvh_global_lock);
4945 * Apply the given advice to the specified range of addresses within the
4946 * given pmap. Depending on the advice, clear the referenced and/or
4947 * modified flags in each mapping and set the mapped page's dirty field.
4950 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4952 pd_entry_t oldpde, *pde;
4954 vm_offset_t va, pdnxt;
4956 boolean_t anychanged, pv_lists_locked;
4958 if (advice != MADV_DONTNEED && advice != MADV_FREE)
4960 if (pmap_is_current(pmap))
4961 pv_lists_locked = FALSE;
4963 pv_lists_locked = TRUE;
4965 rw_wlock(&pvh_global_lock);
4970 for (; sva < eva; sva = pdnxt) {
4971 pdnxt = (sva + NBPDR) & ~PDRMASK;
4974 pde = pmap_pde(pmap, sva);
4976 if ((oldpde & PG_V) == 0)
4978 else if ((oldpde & PG_PS) != 0) {
4979 if ((oldpde & PG_MANAGED) == 0)
4981 if (!pv_lists_locked) {
4982 pv_lists_locked = TRUE;
4983 if (!rw_try_wlock(&pvh_global_lock)) {
4985 pmap_invalidate_all(pmap);
4991 if (!pmap_demote_pde(pmap, pde, sva)) {
4993 * The large page mapping was destroyed.
4999 * Unless the page mappings are wired, remove the
5000 * mapping to a single page so that a subsequent
5001 * access may repromote. Since the underlying page
5002 * table page is fully populated, this removal never
5003 * frees a page table page.
5005 if ((oldpde & PG_W) == 0) {
5006 pte = pmap_pte_quick(pmap, sva);
5007 KASSERT((*pte & PG_V) != 0,
5008 ("pmap_advise: invalid PTE"));
5009 pmap_remove_pte(pmap, pte, sva, NULL);
5016 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
5018 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
5020 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5021 if (advice == MADV_DONTNEED) {
5023 * Future calls to pmap_is_modified()
5024 * can be avoided by making the page
5027 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
5030 atomic_clear_int((u_int *)pte, PG_M | PG_A);
5031 } else if ((*pte & PG_A) != 0)
5032 atomic_clear_int((u_int *)pte, PG_A);
5035 if ((*pte & PG_G) != 0) {
5043 pmap_invalidate_range(pmap, va, sva);
5048 pmap_invalidate_range(pmap, va, sva);
5051 pmap_invalidate_all(pmap);
5052 if (pv_lists_locked) {
5054 rw_wunlock(&pvh_global_lock);
5060 * Clear the modify bits on the specified physical page.
5063 pmap_clear_modify(vm_page_t m)
5065 struct md_page *pvh;
5066 pv_entry_t next_pv, pv;
5068 pd_entry_t oldpde, *pde;
5069 pt_entry_t oldpte, *pte;
5072 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5073 ("pmap_clear_modify: page %p is not managed", m));
5074 VM_OBJECT_ASSERT_WLOCKED(m->object);
5075 KASSERT(!vm_page_xbusied(m),
5076 ("pmap_clear_modify: page %p is exclusive busied", m));
5079 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5080 * If the object containing the page is locked and the page is not
5081 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5083 if ((m->aflags & PGA_WRITEABLE) == 0)
5085 rw_wlock(&pvh_global_lock);
5087 if ((m->flags & PG_FICTITIOUS) != 0)
5088 goto small_mappings;
5089 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5090 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5094 pde = pmap_pde(pmap, va);
5096 if ((oldpde & PG_RW) != 0) {
5097 if (pmap_demote_pde(pmap, pde, va)) {
5098 if ((oldpde & PG_W) == 0) {
5100 * Write protect the mapping to a
5101 * single page so that a subsequent
5102 * write access may repromote.
5104 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5106 pte = pmap_pte_quick(pmap, va);
5108 if ((oldpte & PG_V) != 0) {
5110 * Regardless of whether a pte is 32 or 64 bits
5111 * in size, PG_RW and PG_M are among the least
5112 * significant 32 bits.
5114 while (!atomic_cmpset_int((u_int *)pte,
5116 oldpte & ~(PG_M | PG_RW)))
5119 pmap_invalidate_page(pmap, va);
5127 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5130 pde = pmap_pde(pmap, pv->pv_va);
5131 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5132 " a 4mpage in page %p's pv list", m));
5133 pte = pmap_pte_quick(pmap, pv->pv_va);
5134 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5136 * Regardless of whether a pte is 32 or 64 bits
5137 * in size, PG_M is among the least significant
5140 atomic_clear_int((u_int *)pte, PG_M);
5141 pmap_invalidate_page(pmap, pv->pv_va);
5146 rw_wunlock(&pvh_global_lock);
5150 * Miscellaneous support routines follow
5153 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5154 static __inline void
5155 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5160 * The cache mode bits are all in the low 32-bits of the
5161 * PTE, so we can just spin on updating the low 32-bits.
5164 opte = *(u_int *)pte;
5165 npte = opte & ~PG_PTE_CACHE;
5167 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5170 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5171 static __inline void
5172 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5177 * The cache mode bits are all in the low 32-bits of the
5178 * PDE, so we can just spin on updating the low 32-bits.
5181 opde = *(u_int *)pde;
5182 npde = opde & ~PG_PDE_CACHE;
5184 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5188 * Map a set of physical memory pages into the kernel virtual
5189 * address space. Return a pointer to where it is mapped. This
5190 * routine is intended to be used for mapping device memory,
5194 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5196 struct pmap_preinit_mapping *ppim;
5197 vm_offset_t va, offset;
5201 offset = pa & PAGE_MASK;
5202 size = round_page(offset + size);
5205 if (pa < KERNLOAD && pa + size <= KERNLOAD)
5207 else if (!pmap_initialized) {
5209 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5210 ppim = pmap_preinit_mapping + i;
5211 if (ppim->va == 0) {
5215 ppim->va = virtual_avail;
5216 virtual_avail += size;
5222 panic("%s: too many preinit mappings", __func__);
5225 * If we have a preinit mapping, re-use it.
5227 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5228 ppim = pmap_preinit_mapping + i;
5229 if (ppim->pa == pa && ppim->sz == size &&
5231 return ((void *)(ppim->va + offset));
5233 va = kva_alloc(size);
5235 panic("%s: Couldn't allocate KVA", __func__);
5237 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5238 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5239 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5240 pmap_invalidate_cache_range(va, va + size, FALSE);
5241 return ((void *)(va + offset));
5245 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5248 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5252 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5255 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5259 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5261 struct pmap_preinit_mapping *ppim;
5265 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD)
5267 offset = va & PAGE_MASK;
5268 size = round_page(offset + size);
5269 va = trunc_page(va);
5270 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5271 ppim = pmap_preinit_mapping + i;
5272 if (ppim->va == va && ppim->sz == size) {
5273 if (pmap_initialized)
5279 if (va + size == virtual_avail)
5284 if (pmap_initialized)
5289 * Sets the memory attribute for the specified page.
5292 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5295 m->md.pat_mode = ma;
5296 if ((m->flags & PG_FICTITIOUS) != 0)
5300 * If "m" is a normal page, flush it from the cache.
5301 * See pmap_invalidate_cache_range().
5303 * First, try to find an existing mapping of the page by sf
5304 * buffer. sf_buf_invalidate_cache() modifies mapping and
5305 * flushes the cache.
5307 if (sf_buf_invalidate_cache(m))
5311 * If page is not mapped by sf buffer, but CPU does not
5312 * support self snoop, map the page transient and do
5313 * invalidation. In the worst case, whole cache is flushed by
5314 * pmap_invalidate_cache_range().
5316 if ((cpu_feature & CPUID_SS) == 0)
5321 pmap_flush_page(vm_page_t m)
5323 pt_entry_t *cmap_pte2;
5325 vm_offset_t sva, eva;
5328 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5329 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5332 cmap_pte2 = pc->pc_cmap_pte2;
5333 mtx_lock(&pc->pc_cmap_lock);
5335 panic("pmap_flush_page: CMAP2 busy");
5336 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5337 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0);
5338 invlcaddr(pc->pc_cmap_addr2);
5339 sva = (vm_offset_t)pc->pc_cmap_addr2;
5340 eva = sva + PAGE_SIZE;
5343 * Use mfence or sfence despite the ordering implied by
5344 * mtx_{un,}lock() because clflush on non-Intel CPUs
5345 * and clflushopt are not guaranteed to be ordered by
5346 * any other instruction.
5350 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5352 for (; sva < eva; sva += cpu_clflush_line_size) {
5360 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5364 mtx_unlock(&pc->pc_cmap_lock);
5366 pmap_invalidate_cache();
5370 * Changes the specified virtual address range's memory type to that given by
5371 * the parameter "mode". The specified virtual address range must be
5372 * completely contained within either the kernel map.
5374 * Returns zero if the change completed successfully, and either EINVAL or
5375 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5376 * of the virtual address range was not mapped, and ENOMEM is returned if
5377 * there was insufficient memory available to complete the change.
5380 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5382 vm_offset_t base, offset, tmpva;
5385 int cache_bits_pte, cache_bits_pde;
5388 base = trunc_page(va);
5389 offset = va & PAGE_MASK;
5390 size = round_page(offset + size);
5393 * Only supported on kernel virtual addresses above the recursive map.
5395 if (base < VM_MIN_KERNEL_ADDRESS)
5398 cache_bits_pde = pmap_cache_bits(mode, 1);
5399 cache_bits_pte = pmap_cache_bits(mode, 0);
5403 * Pages that aren't mapped aren't supported. Also break down
5404 * 2/4MB pages into 4KB pages if required.
5406 PMAP_LOCK(kernel_pmap);
5407 for (tmpva = base; tmpva < base + size; ) {
5408 pde = pmap_pde(kernel_pmap, tmpva);
5410 PMAP_UNLOCK(kernel_pmap);
5415 * If the current 2/4MB page already has
5416 * the required memory type, then we need not
5417 * demote this page. Just increment tmpva to
5418 * the next 2/4MB page frame.
5420 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5421 tmpva = trunc_4mpage(tmpva) + NBPDR;
5426 * If the current offset aligns with a 2/4MB
5427 * page frame and there is at least 2/4MB left
5428 * within the range, then we need not break
5429 * down this page into 4KB pages.
5431 if ((tmpva & PDRMASK) == 0 &&
5432 tmpva + PDRMASK < base + size) {
5436 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5437 PMAP_UNLOCK(kernel_pmap);
5441 pte = vtopte(tmpva);
5443 PMAP_UNLOCK(kernel_pmap);
5448 PMAP_UNLOCK(kernel_pmap);
5451 * Ok, all the pages exist, so run through them updating their
5452 * cache mode if required.
5454 for (tmpva = base; tmpva < base + size; ) {
5455 pde = pmap_pde(kernel_pmap, tmpva);
5457 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5458 pmap_pde_attr(pde, cache_bits_pde);
5461 tmpva = trunc_4mpage(tmpva) + NBPDR;
5463 pte = vtopte(tmpva);
5464 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5465 pmap_pte_attr(pte, cache_bits_pte);
5473 * Flush CPU caches to make sure any data isn't cached that
5474 * shouldn't be, etc.
5477 pmap_invalidate_range(kernel_pmap, base, tmpva);
5478 pmap_invalidate_cache_range(base, tmpva, FALSE);
5484 * perform the pmap work for mincore
5487 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5490 pt_entry_t *ptep, pte;
5496 pdep = pmap_pde(pmap, addr);
5498 if (*pdep & PG_PS) {
5500 /* Compute the physical address of the 4KB page. */
5501 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5503 val = MINCORE_SUPER;
5505 ptep = pmap_pte(pmap, addr);
5507 pmap_pte_release(ptep);
5508 pa = pte & PG_FRAME;
5516 if ((pte & PG_V) != 0) {
5517 val |= MINCORE_INCORE;
5518 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5519 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5520 if ((pte & PG_A) != 0)
5521 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5523 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5524 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5525 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5526 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5527 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5530 PA_UNLOCK_COND(*locked_pa);
5536 pmap_activate(struct thread *td)
5538 pmap_t pmap, oldpmap;
5543 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5544 oldpmap = PCPU_GET(curpmap);
5545 cpuid = PCPU_GET(cpuid);
5547 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5548 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5550 CPU_CLR(cpuid, &oldpmap->pm_active);
5551 CPU_SET(cpuid, &pmap->pm_active);
5553 #if defined(PAE) || defined(PAE_TABLES)
5554 cr3 = vtophys(pmap->pm_pdpt);
5556 cr3 = vtophys(pmap->pm_pdir);
5559 * pmap_activate is for the current thread on the current cpu
5561 td->td_pcb->pcb_cr3 = cr3;
5563 PCPU_SET(curpmap, pmap);
5568 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5573 * Increase the starting virtual address of the given mapping if a
5574 * different alignment might result in more superpage mappings.
5577 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5578 vm_offset_t *addr, vm_size_t size)
5580 vm_offset_t superpage_offset;
5584 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5585 offset += ptoa(object->pg_color);
5586 superpage_offset = offset & PDRMASK;
5587 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5588 (*addr & PDRMASK) == superpage_offset)
5590 if ((*addr & PDRMASK) < superpage_offset)
5591 *addr = (*addr & ~PDRMASK) + superpage_offset;
5593 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5597 pmap_quick_enter_page(vm_page_t m)
5603 qaddr = PCPU_GET(qmap_addr);
5604 pte = vtopte(qaddr);
5606 KASSERT(*pte == 0, ("pmap_quick_enter_page: PTE busy"));
5607 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5608 pmap_cache_bits(pmap_page_get_memattr(m), 0);
5615 pmap_quick_remove_page(vm_offset_t addr)
5620 qaddr = PCPU_GET(qmap_addr);
5621 pte = vtopte(qaddr);
5623 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5624 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5630 #if defined(PMAP_DEBUG)
5631 pmap_pid_dump(int pid)
5638 sx_slock(&allproc_lock);
5639 FOREACH_PROC_IN_SYSTEM(p) {
5640 if (p->p_pid != pid)
5646 pmap = vmspace_pmap(p->p_vmspace);
5647 for (i = 0; i < NPDEPTD; i++) {
5650 vm_offset_t base = i << PDRSHIFT;
5652 pde = &pmap->pm_pdir[i];
5653 if (pde && pmap_pde_v(pde)) {
5654 for (j = 0; j < NPTEPG; j++) {
5655 vm_offset_t va = base + (j << PAGE_SHIFT);
5656 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5661 sx_sunlock(&allproc_lock);
5664 pte = pmap_pte(pmap, va);
5665 if (pte && pmap_pte_v(pte)) {
5669 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5670 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5671 va, pa, m->hold_count, m->wire_count, m->flags);
5686 sx_sunlock(&allproc_lock);