2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * This code is derived from software contributed to Berkeley by
12 * the Systems Programming Group of the University of Utah Computer
13 * Science Department and William Jolitz of UUNET Technologies Inc.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 * must display the following acknowledgement:
25 * This product includes software developed by the University of
26 * California, Berkeley and its contributors.
27 * 4. Neither the name of the University nor the names of its contributors
28 * may be used to endorse or promote products derived from this software
29 * without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
46 * Copyright (c) 2003 Networks Associates Technology, Inc.
47 * All rights reserved.
49 * This software was developed for the FreeBSD Project by Jake Burkholder,
50 * Safeport Network Services, and Network Associates Laboratories, the
51 * Security Research Division of Network Associates, Inc. under
52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
53 * CHATS research program.
55 * Redistribution and use in source and binary forms, with or without
56 * modification, are permitted provided that the following conditions
58 * 1. Redistributions of source code must retain the above copyright
59 * notice, this list of conditions and the following disclaimer.
60 * 2. Redistributions in binary form must reproduce the above copyright
61 * notice, this list of conditions and the following disclaimer in the
62 * documentation and/or other materials provided with the distribution.
64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
77 #include <sys/cdefs.h>
78 __FBSDID("$FreeBSD$");
81 * Manages physical address maps.
83 * Since the information managed by this module is
84 * also stored by the logical address mapping module,
85 * this module may throw away valid virtual-to-physical
86 * mappings at almost any time. However, invalidations
87 * of virtual-to-physical mappings must be done as
90 * In order to cope with hardware architectures which
91 * make virtual-to-physical map invalidates expensive,
92 * this module may delay invalidate or reduced protection
93 * operations until such time as they are actually
94 * necessary. This module is given full information as
95 * to which processors are currently using which maps,
96 * and to when physical maps must be made correct.
101 #include "opt_pmap.h"
103 #include "opt_xbox.h"
105 #include <sys/param.h>
106 #include <sys/systm.h>
107 #include <sys/kernel.h>
109 #include <sys/lock.h>
110 #include <sys/malloc.h>
111 #include <sys/mman.h>
112 #include <sys/msgbuf.h>
113 #include <sys/mutex.h>
114 #include <sys/proc.h>
115 #include <sys/rwlock.h>
116 #include <sys/sf_buf.h>
118 #include <sys/vmmeter.h>
119 #include <sys/sched.h>
120 #include <sys/sysctl.h>
124 #include <sys/cpuset.h>
128 #include <vm/vm_param.h>
129 #include <vm/vm_kern.h>
130 #include <vm/vm_page.h>
131 #include <vm/vm_map.h>
132 #include <vm/vm_object.h>
133 #include <vm/vm_extern.h>
134 #include <vm/vm_pageout.h>
135 #include <vm/vm_pager.h>
136 #include <vm/vm_radix.h>
137 #include <vm/vm_reserv.h>
142 #include <machine/intr_machdep.h>
143 #include <machine/apicvar.h>
145 #include <machine/cpu.h>
146 #include <machine/cputypes.h>
147 #include <machine/md_var.h>
148 #include <machine/pcb.h>
149 #include <machine/specialreg.h>
151 #include <machine/smp.h>
155 #include <machine/xbox.h>
158 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
159 #define CPU_ENABLE_SSE
162 #ifndef PMAP_SHPGPERPROC
163 #define PMAP_SHPGPERPROC 200
166 #if !defined(DIAGNOSTIC)
167 #ifdef __GNUC_GNU_INLINE__
168 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
170 #define PMAP_INLINE extern inline
177 #define PV_STAT(x) do { x ; } while (0)
179 #define PV_STAT(x) do { } while (0)
182 #define pa_index(pa) ((pa) >> PDRSHIFT)
183 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
186 * Get PDEs and PTEs for user/kernel address space
188 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
189 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
191 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
192 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
193 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
194 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
195 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
197 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
198 atomic_clear_int((u_int *)(pte), PG_W))
199 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
201 struct pmap kernel_pmap_store;
202 LIST_HEAD(pmaplist, pmap);
203 static struct pmaplist allpmaps;
204 static struct mtx allpmaps_lock;
206 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
207 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
208 int pgeflag = 0; /* PG_G or-in */
209 int pseflag = 0; /* PG_PS or-in */
211 static int nkpt = NKPT;
212 vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR;
213 extern u_int32_t KERNend;
214 extern u_int32_t KPTphys;
218 static uma_zone_t pdptzone;
221 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
223 static int pat_works = 1;
224 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
225 "Is page attribute table fully functional?");
227 static int pg_ps_enabled = 1;
228 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0,
229 "Are large page mappings enabled?");
231 #define PAT_INDEX_SIZE 8
232 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
234 static struct rwlock_padalign pvh_global_lock;
237 * Data for the pv entry allocation mechanism
239 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
240 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
241 static struct md_page *pv_table;
242 static int shpgperproc = PMAP_SHPGPERPROC;
244 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
245 int pv_maxchunks; /* How many chunks we have KVA for */
246 vm_offset_t pv_vafree; /* freelist stored in the PTE */
249 * All those kernel PT submaps that BSD is so fond of
258 static struct sysmaps sysmaps_pcpu[MAXCPU];
259 pt_entry_t *CMAP1 = 0;
260 static pt_entry_t *CMAP3;
261 static pd_entry_t *KPTD;
262 caddr_t CADDR1 = 0, ptvmmap = 0;
263 static caddr_t CADDR3;
264 struct msgbuf *msgbufp = 0;
269 static caddr_t crashdumpmap;
271 static pt_entry_t *PMAP1 = 0, *PMAP2;
272 static pt_entry_t *PADDR1 = 0, *PADDR2;
275 static int PMAP1changedcpu;
276 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
278 "Number of times pmap_pte_quick changed CPU with same PMAP1");
280 static int PMAP1changed;
281 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
283 "Number of times pmap_pte_quick changed PMAP1");
284 static int PMAP1unchanged;
285 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
287 "Number of times pmap_pte_quick didn't change PMAP1");
288 static struct mtx PMAP2mutex;
290 static void free_pv_chunk(struct pv_chunk *pc);
291 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
292 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
293 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
294 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
295 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
296 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
297 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
299 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
301 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
302 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
304 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
305 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
306 static void pmap_flush_page(vm_page_t m);
307 static void pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
308 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
309 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
310 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
311 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
312 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
313 static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va);
314 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
315 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
316 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
318 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
319 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
321 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
323 static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte);
324 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
326 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
328 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
329 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
331 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
333 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
335 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags);
337 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, int flags);
338 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, vm_page_t *free);
339 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
340 static void pmap_pte_release(pt_entry_t *pte);
341 static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *);
343 static void *pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait);
345 static void pmap_set_pg(void);
347 static __inline void pagezero(void *page);
349 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
350 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
353 * If you get an error here, then you set KVA_PAGES wrong! See the
354 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be
355 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE.
357 CTASSERT(KERNBASE % (1 << 24) == 0);
360 * Bootstrap the system enough to run with virtual memory.
362 * On the i386 this is called after mapping has already been enabled
363 * and just syncs the pmap module with what has already been done.
364 * [We can't call it easily with mapping off since the kernel is not
365 * mapped with PA == VA, hence we would have to relocate every address
366 * from the linked base (virtual) address "KERNBASE" to the actual
367 * (physical) address starting relative to 0]
370 pmap_bootstrap(vm_paddr_t firstaddr)
373 pt_entry_t *pte, *unused;
374 struct sysmaps *sysmaps;
378 * Initialize the first available kernel virtual address. However,
379 * using "firstaddr" may waste a few pages of the kernel virtual
380 * address space, because locore may not have mapped every physical
381 * page that it allocated. Preferably, locore would provide a first
382 * unused virtual address in addition to "firstaddr".
384 virtual_avail = (vm_offset_t) KERNBASE + firstaddr;
386 virtual_end = VM_MAX_KERNEL_ADDRESS;
389 * Initialize the kernel pmap (which is statically allocated).
391 PMAP_LOCK_INIT(kernel_pmap);
392 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD);
394 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT);
396 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
397 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
400 * Initialize the global pv list lock.
402 rw_init(&pvh_global_lock, "pmap pv global");
404 LIST_INIT(&allpmaps);
407 * Request a spin mutex so that changes to allpmaps cannot be
408 * preempted by smp_rendezvous_cpus(). Otherwise,
409 * pmap_update_pde_kernel() could access allpmaps while it is
412 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
413 mtx_lock_spin(&allpmaps_lock);
414 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
415 mtx_unlock_spin(&allpmaps_lock);
418 * Reserve some special page table entries/VA space for temporary
421 #define SYSMAP(c, p, v, n) \
422 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
428 * CMAP1/CMAP2 are used for zeroing and copying pages.
429 * CMAP3 is used for the idle process page zeroing.
431 for (i = 0; i < MAXCPU; i++) {
432 sysmaps = &sysmaps_pcpu[i];
433 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF);
434 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1)
435 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1)
437 SYSMAP(caddr_t, CMAP1, CADDR1, 1)
438 SYSMAP(caddr_t, CMAP3, CADDR3, 1)
443 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
446 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
448 SYSMAP(caddr_t, unused, ptvmmap, 1)
451 * msgbufp is used to map the system message buffer.
453 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
456 * KPTmap is used by pmap_kextract().
458 * KPTmap is first initialized by locore. However, that initial
459 * KPTmap can only support NKPT page table pages. Here, a larger
460 * KPTmap is created that can support KVA_PAGES page table pages.
462 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
464 for (i = 0; i < NKPT; i++)
465 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V;
468 * Adjust the start of the KPTD and KPTmap so that the implementation
469 * of pmap_kextract() and pmap_growkernel() can be made simpler.
472 KPTmap -= i386_btop(KPTDI << PDRSHIFT);
475 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
478 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
479 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
481 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
486 * Leave in place an identity mapping (virt == phys) for the low 1 MB
487 * physical memory region that is used by the ACPI wakeup code. This
488 * mapping must not have PG_G set.
491 /* FIXME: This is gross, but needed for the XBOX. Since we are in such
492 * an early stadium, we cannot yet neatly map video memory ... :-(
493 * Better fixes are very welcome! */
494 if (!arch_i386_is_xbox)
496 for (i = 1; i < NKPT; i++)
499 /* Initialize the PAT MSR if present. */
502 /* Turn on PG_G on kernel page(s) */
512 int pat_table[PAT_INDEX_SIZE];
517 /* Set default PAT index table. */
518 for (i = 0; i < PAT_INDEX_SIZE; i++)
520 pat_table[PAT_WRITE_BACK] = 0;
521 pat_table[PAT_WRITE_THROUGH] = 1;
522 pat_table[PAT_UNCACHEABLE] = 3;
523 pat_table[PAT_WRITE_COMBINING] = 3;
524 pat_table[PAT_WRITE_PROTECTED] = 3;
525 pat_table[PAT_UNCACHED] = 3;
527 /* Bail if this CPU doesn't implement PAT. */
528 if ((cpu_feature & CPUID_PAT) == 0) {
529 for (i = 0; i < PAT_INDEX_SIZE; i++)
530 pat_index[i] = pat_table[i];
536 * Due to some Intel errata, we can only safely use the lower 4
539 * Intel Pentium III Processor Specification Update
540 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
543 * Intel Pentium IV Processor Specification Update
544 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
546 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
547 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
550 /* Initialize default PAT entries. */
551 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
552 PAT_VALUE(1, PAT_WRITE_THROUGH) |
553 PAT_VALUE(2, PAT_UNCACHED) |
554 PAT_VALUE(3, PAT_UNCACHEABLE) |
555 PAT_VALUE(4, PAT_WRITE_BACK) |
556 PAT_VALUE(5, PAT_WRITE_THROUGH) |
557 PAT_VALUE(6, PAT_UNCACHED) |
558 PAT_VALUE(7, PAT_UNCACHEABLE);
562 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
563 * Program 5 and 6 as WP and WC.
564 * Leave 4 and 7 as WB and UC.
566 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
567 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
568 PAT_VALUE(6, PAT_WRITE_COMBINING);
569 pat_table[PAT_UNCACHED] = 2;
570 pat_table[PAT_WRITE_PROTECTED] = 5;
571 pat_table[PAT_WRITE_COMBINING] = 6;
574 * Just replace PAT Index 2 with WC instead of UC-.
576 pat_msr &= ~PAT_MASK(2);
577 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
578 pat_table[PAT_WRITE_COMBINING] = 2;
583 load_cr4(cr4 & ~CR4_PGE);
585 /* Disable caches (CD = 1, NW = 0). */
587 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
589 /* Flushes caches and TLBs. */
593 /* Update PAT and index table. */
594 wrmsr(MSR_PAT, pat_msr);
595 for (i = 0; i < PAT_INDEX_SIZE; i++)
596 pat_index[i] = pat_table[i];
598 /* Flush caches and TLBs again. */
602 /* Restore caches and PGE. */
608 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on.
614 vm_offset_t va, endva;
619 endva = KERNBASE + KERNend;
622 va = KERNBASE + KERNLOAD;
624 pdir_pde(PTD, va) |= pgeflag;
625 invltlb(); /* Play it safe, invltlb() every time */
629 va = (vm_offset_t)btext;
634 invltlb(); /* Play it safe, invltlb() every time */
641 * Initialize a vm_page's machine-dependent fields.
644 pmap_page_init(vm_page_t m)
647 TAILQ_INIT(&m->md.pv_list);
648 m->md.pat_mode = PAT_WRITE_BACK;
653 pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait)
656 /* Inform UMA that this allocator uses kernel_map/object. */
657 *flags = UMA_SLAB_KERNEL;
658 return ((void *)kmem_alloc_contig(kernel_map, bytes, wait, 0x0ULL,
659 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
664 * ABuse the pte nodes for unmapped kva to thread a kva freelist through.
666 * - Must deal with pages in order to ensure that none of the PG_* bits
667 * are ever set, PG_V in particular.
668 * - Assumes we can write to ptes without pte_store() atomic ops, even
669 * on PAE systems. This should be ok.
670 * - Assumes nothing will ever test these addresses for 0 to indicate
671 * no mapping instead of correctly checking PG_V.
672 * - Assumes a vm_offset_t will fit in a pte (true for i386).
673 * Because PG_V is never set, there can be no mappings to invalidate.
676 pmap_ptelist_alloc(vm_offset_t *head)
683 return (va); /* Out of memory */
687 panic("pmap_ptelist_alloc: va with PG_V set!");
693 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
698 panic("pmap_ptelist_free: freeing va with PG_V set!");
700 *pte = *head; /* virtual! PG_V is 0 though */
705 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
711 for (i = npages - 1; i >= 0; i--) {
712 va = (vm_offset_t)base + i * PAGE_SIZE;
713 pmap_ptelist_free(head, va);
719 * Initialize the pmap module.
720 * Called by vm_init, to initialize any structures that the pmap
721 * system needs to map virtual memory.
731 * Initialize the vm page array entries for the kernel pmap's
734 for (i = 0; i < NKPT; i++) {
735 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
736 KASSERT(mpte >= vm_page_array &&
737 mpte < &vm_page_array[vm_page_array_size],
738 ("pmap_init: page table page is out of range"));
739 mpte->pindex = i + KPTDI;
740 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
744 * Initialize the address space (zone) for the pv entries. Set a
745 * high water mark so that the system can recover from excessive
746 * numbers of pv entries.
748 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
749 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
750 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
751 pv_entry_max = roundup(pv_entry_max, _NPCPV);
752 pv_entry_high_water = 9 * (pv_entry_max / 10);
755 * If the kernel is running in a virtual machine on an AMD Family 10h
756 * processor, then it must assume that MCA is enabled by the virtual
759 if (vm_guest == VM_GUEST_VM && cpu_vendor_id == CPU_VENDOR_AMD &&
760 CPUID_TO_FAMILY(cpu_id) == 0x10)
761 workaround_erratum383 = 1;
764 * Are large page mappings supported and enabled?
766 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
769 else if (pg_ps_enabled) {
770 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
771 ("pmap_init: can't assign to pagesizes[1]"));
772 pagesizes[1] = NBPDR;
776 * Calculate the size of the pv head table for superpages.
778 for (i = 0; phys_avail[i + 1]; i += 2);
779 pv_npg = round_4mpage(phys_avail[(i - 2) + 1]) / NBPDR;
782 * Allocate memory for the pv head table for superpages.
784 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
786 pv_table = (struct md_page *)kmem_alloc(kernel_map, s);
787 for (i = 0; i < pv_npg; i++)
788 TAILQ_INIT(&pv_table[i].pv_list);
790 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
791 pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map,
792 PAGE_SIZE * pv_maxchunks);
793 if (pv_chunkbase == NULL)
794 panic("pmap_init: not enough kvm for pv chunks");
795 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
797 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
798 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
799 UMA_ZONE_VM | UMA_ZONE_NOFREE);
800 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
805 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
806 "Max number of PV entries");
807 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
808 "Page share factor per proc");
810 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
811 "2/4MB page mapping counters");
813 static u_long pmap_pde_demotions;
814 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
815 &pmap_pde_demotions, 0, "2/4MB page demotions");
817 static u_long pmap_pde_mappings;
818 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
819 &pmap_pde_mappings, 0, "2/4MB page mappings");
821 static u_long pmap_pde_p_failures;
822 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
823 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
825 static u_long pmap_pde_promotions;
826 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
827 &pmap_pde_promotions, 0, "2/4MB page promotions");
829 /***************************************************
830 * Low level helper routines.....
831 ***************************************************/
834 * Determine the appropriate bits to set in a PTE or PDE for a specified
838 pmap_cache_bits(int mode, boolean_t is_pde)
840 int cache_bits, pat_flag, pat_idx;
842 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
843 panic("Unknown caching mode %d\n", mode);
845 /* The PAT bit is different for PTE's and PDE's. */
846 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
848 /* Map the caching mode to a PAT index. */
849 pat_idx = pat_index[mode];
851 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
854 cache_bits |= pat_flag;
856 cache_bits |= PG_NC_PCD;
858 cache_bits |= PG_NC_PWT;
863 * The caller is responsible for maintaining TLB consistency.
866 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
870 boolean_t PTD_updated;
873 mtx_lock_spin(&allpmaps_lock);
874 LIST_FOREACH(pmap, &allpmaps, pm_list) {
875 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] &
878 pde = pmap_pde(pmap, va);
879 pde_store(pde, newpde);
881 mtx_unlock_spin(&allpmaps_lock);
883 ("pmap_kenter_pde: current page table is not in allpmaps"));
887 * After changing the page size for the specified virtual address in the page
888 * table, flush the corresponding entries from the processor's TLB. Only the
889 * calling processor's TLB is affected.
891 * The calling thread must be pinned to a processor.
894 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
898 if ((newpde & PG_PS) == 0)
899 /* Demotion: flush a specific 2MB page mapping. */
901 else if ((newpde & PG_G) == 0)
903 * Promotion: flush every 4KB page mapping from the TLB
904 * because there are too many to flush individually.
909 * Promotion: flush every 4KB page mapping from the TLB,
910 * including any global (PG_G) mappings.
913 load_cr4(cr4 & ~CR4_PGE);
915 * Although preemption at this point could be detrimental to
916 * performance, it would not lead to an error. PG_G is simply
917 * ignored if CR4.PGE is clear. Moreover, in case this block
918 * is re-entered, the load_cr4() either above or below will
919 * modify CR4.PGE flushing the TLB.
921 load_cr4(cr4 | CR4_PGE);
926 * For SMP, these functions have to use the IPI mechanism for coherence.
928 * N.B.: Before calling any of the following TLB invalidation functions,
929 * the calling processor must ensure that all stores updating a non-
930 * kernel page table are globally performed. Otherwise, another
931 * processor could cache an old, pre-update entry without being
932 * invalidated. This can happen one of two ways: (1) The pmap becomes
933 * active on another processor after its pm_active field is checked by
934 * one of the following functions but before a store updating the page
935 * table is globally performed. (2) The pmap becomes active on another
936 * processor before its pm_active field is checked but due to
937 * speculative loads one of the following functions stills reads the
938 * pmap as inactive on the other processor.
940 * The kernel page table is exempt because its pm_active field is
941 * immutable. The kernel page table is always active on every
945 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
951 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
955 cpuid = PCPU_GET(cpuid);
956 other_cpus = all_cpus;
957 CPU_CLR(cpuid, &other_cpus);
958 if (CPU_ISSET(cpuid, &pmap->pm_active))
960 CPU_AND(&other_cpus, &pmap->pm_active);
961 if (!CPU_EMPTY(&other_cpus))
962 smp_masked_invlpg(other_cpus, va);
968 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
975 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
976 for (addr = sva; addr < eva; addr += PAGE_SIZE)
978 smp_invlpg_range(sva, eva);
980 cpuid = PCPU_GET(cpuid);
981 other_cpus = all_cpus;
982 CPU_CLR(cpuid, &other_cpus);
983 if (CPU_ISSET(cpuid, &pmap->pm_active))
984 for (addr = sva; addr < eva; addr += PAGE_SIZE)
986 CPU_AND(&other_cpus, &pmap->pm_active);
987 if (!CPU_EMPTY(&other_cpus))
988 smp_masked_invlpg_range(other_cpus, sva, eva);
994 pmap_invalidate_all(pmap_t pmap)
1000 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1004 cpuid = PCPU_GET(cpuid);
1005 other_cpus = all_cpus;
1006 CPU_CLR(cpuid, &other_cpus);
1007 if (CPU_ISSET(cpuid, &pmap->pm_active))
1009 CPU_AND(&other_cpus, &pmap->pm_active);
1010 if (!CPU_EMPTY(&other_cpus))
1011 smp_masked_invltlb(other_cpus);
1017 pmap_invalidate_cache(void)
1027 cpuset_t invalidate; /* processors that invalidate their TLB */
1031 u_int store; /* processor that updates the PDE */
1035 pmap_update_pde_kernel(void *arg)
1037 struct pde_action *act = arg;
1041 if (act->store == PCPU_GET(cpuid)) {
1044 * Elsewhere, this operation requires allpmaps_lock for
1045 * synchronization. Here, it does not because it is being
1046 * performed in the context of an all_cpus rendezvous.
1048 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1049 pde = pmap_pde(pmap, act->va);
1050 pde_store(pde, act->newpde);
1056 pmap_update_pde_user(void *arg)
1058 struct pde_action *act = arg;
1060 if (act->store == PCPU_GET(cpuid))
1061 pde_store(act->pde, act->newpde);
1065 pmap_update_pde_teardown(void *arg)
1067 struct pde_action *act = arg;
1069 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1070 pmap_update_pde_invalidate(act->va, act->newpde);
1074 * Change the page size for the specified virtual address in a way that
1075 * prevents any possibility of the TLB ever having two entries that map the
1076 * same virtual address using different page sizes. This is the recommended
1077 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1078 * machine check exception for a TLB state that is improperly diagnosed as a
1082 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1084 struct pde_action act;
1085 cpuset_t active, other_cpus;
1089 cpuid = PCPU_GET(cpuid);
1090 other_cpus = all_cpus;
1091 CPU_CLR(cpuid, &other_cpus);
1092 if (pmap == kernel_pmap)
1095 active = pmap->pm_active;
1096 if (CPU_OVERLAP(&active, &other_cpus)) {
1098 act.invalidate = active;
1101 act.newpde = newpde;
1102 CPU_SET(cpuid, &active);
1103 smp_rendezvous_cpus(active,
1104 smp_no_rendevous_barrier, pmap == kernel_pmap ?
1105 pmap_update_pde_kernel : pmap_update_pde_user,
1106 pmap_update_pde_teardown, &act);
1108 if (pmap == kernel_pmap)
1109 pmap_kenter_pde(va, newpde);
1111 pde_store(pde, newpde);
1112 if (CPU_ISSET(cpuid, &active))
1113 pmap_update_pde_invalidate(va, newpde);
1119 * Normal, non-SMP, 486+ invalidation functions.
1120 * We inline these within pmap.c for speed.
1123 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1126 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1131 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1135 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1136 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1141 pmap_invalidate_all(pmap_t pmap)
1144 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1149 pmap_invalidate_cache(void)
1156 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1159 if (pmap == kernel_pmap)
1160 pmap_kenter_pde(va, newpde);
1162 pde_store(pde, newpde);
1163 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1164 pmap_update_pde_invalidate(va, newpde);
1168 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1171 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
1174 KASSERT((sva & PAGE_MASK) == 0,
1175 ("pmap_invalidate_cache_range: sva not page-aligned"));
1176 KASSERT((eva & PAGE_MASK) == 0,
1177 ("pmap_invalidate_cache_range: eva not page-aligned"));
1179 if (cpu_feature & CPUID_SS)
1180 ; /* If "Self Snoop" is supported, do nothing. */
1181 else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1182 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1186 * XXX: Some CPUs fault, hang, or trash the local APIC
1187 * registers if we use CLFLUSH on the local APIC
1188 * range. The local APIC is always uncached, so we
1189 * don't need to flush for that range anyway.
1191 if (pmap_kextract(sva) == lapic_paddr)
1195 * Otherwise, do per-cache line flush. Use the mfence
1196 * instruction to insure that previous stores are
1197 * included in the write-back. The processor
1198 * propagates flush to other processors in the cache
1202 for (; sva < eva; sva += cpu_clflush_line_size)
1208 * No targeted cache flush methods are supported by CPU,
1209 * or the supplied range is bigger than 2MB.
1210 * Globally invalidate cache.
1212 pmap_invalidate_cache();
1217 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1221 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1222 (cpu_feature & CPUID_CLFSH) == 0) {
1223 pmap_invalidate_cache();
1225 for (i = 0; i < count; i++)
1226 pmap_flush_page(pages[i]);
1231 * Are we current address space or kernel? N.B. We return FALSE when
1232 * a pmap's page table is in use because a kernel thread is borrowing
1233 * it. The borrowed page table can change spontaneously, making any
1234 * dependence on its continued use subject to a race condition.
1237 pmap_is_current(pmap_t pmap)
1240 return (pmap == kernel_pmap ||
1241 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) &&
1242 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME)));
1246 * If the given pmap is not the current or kernel pmap, the returned pte must
1247 * be released by passing it to pmap_pte_release().
1250 pmap_pte(pmap_t pmap, vm_offset_t va)
1255 pde = pmap_pde(pmap, va);
1259 /* are we current address space or kernel? */
1260 if (pmap_is_current(pmap))
1261 return (vtopte(va));
1262 mtx_lock(&PMAP2mutex);
1263 newpf = *pde & PG_FRAME;
1264 if ((*PMAP2 & PG_FRAME) != newpf) {
1265 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1266 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1268 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1274 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1277 static __inline void
1278 pmap_pte_release(pt_entry_t *pte)
1281 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1282 mtx_unlock(&PMAP2mutex);
1285 static __inline void
1286 invlcaddr(void *caddr)
1289 invlpg((u_int)caddr);
1293 * Super fast pmap_pte routine best used when scanning
1294 * the pv lists. This eliminates many coarse-grained
1295 * invltlb calls. Note that many of the pv list
1296 * scans are across different pmaps. It is very wasteful
1297 * to do an entire invltlb for checking a single mapping.
1299 * If the given pmap is not the current pmap, pvh_global_lock
1300 * must be held and curthread pinned to a CPU.
1303 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1308 pde = pmap_pde(pmap, va);
1312 /* are we current address space or kernel? */
1313 if (pmap_is_current(pmap))
1314 return (vtopte(va));
1315 rw_assert(&pvh_global_lock, RA_WLOCKED);
1316 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1317 newpf = *pde & PG_FRAME;
1318 if ((*PMAP1 & PG_FRAME) != newpf) {
1319 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1321 PMAP1cpu = PCPU_GET(cpuid);
1327 if (PMAP1cpu != PCPU_GET(cpuid)) {
1328 PMAP1cpu = PCPU_GET(cpuid);
1334 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1340 * Routine: pmap_extract
1342 * Extract the physical page address associated
1343 * with the given map/virtual_address pair.
1346 pmap_extract(pmap_t pmap, vm_offset_t va)
1354 pde = pmap->pm_pdir[va >> PDRSHIFT];
1356 if ((pde & PG_PS) != 0)
1357 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1359 pte = pmap_pte(pmap, va);
1360 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK);
1361 pmap_pte_release(pte);
1369 * Routine: pmap_extract_and_hold
1371 * Atomically extract and hold the physical page
1372 * with the given pmap and virtual address pair
1373 * if that mapping permits the given protection.
1376 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1379 pt_entry_t pte, *ptep;
1387 pde = *pmap_pde(pmap, va);
1390 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1391 if (vm_page_pa_tryrelock(pmap, (pde &
1392 PG_PS_FRAME) | (va & PDRMASK), &pa))
1394 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1399 ptep = pmap_pte(pmap, va);
1401 pmap_pte_release(ptep);
1403 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1404 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1407 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1417 /***************************************************
1418 * Low level mapping routines.....
1419 ***************************************************/
1422 * Add a wired page to the kva.
1423 * Note: not SMP coherent.
1425 * This function may be used before pmap_bootstrap() is called.
1428 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1433 pte_store(pte, pa | PG_RW | PG_V | pgeflag);
1436 static __inline void
1437 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1442 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0));
1446 * Remove a page from the kernel pagetables.
1447 * Note: not SMP coherent.
1449 * This function may be used before pmap_bootstrap() is called.
1452 pmap_kremove(vm_offset_t va)
1461 * Used to map a range of physical addresses into kernel
1462 * virtual address space.
1464 * The value passed in '*virt' is a suggested virtual address for
1465 * the mapping. Architectures which can support a direct-mapped
1466 * physical to virtual region can return the appropriate address
1467 * within that region, leaving '*virt' unchanged. Other
1468 * architectures should map the pages starting at '*virt' and
1469 * update '*virt' with the first usable address after the mapped
1473 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1475 vm_offset_t va, sva;
1476 vm_paddr_t superpage_offset;
1481 * Does the physical address range's size and alignment permit at
1482 * least one superpage mapping to be created?
1484 superpage_offset = start & PDRMASK;
1485 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1487 * Increase the starting virtual address so that its alignment
1488 * does not preclude the use of superpage mappings.
1490 if ((va & PDRMASK) < superpage_offset)
1491 va = (va & ~PDRMASK) + superpage_offset;
1492 else if ((va & PDRMASK) > superpage_offset)
1493 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1496 while (start < end) {
1497 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1499 KASSERT((va & PDRMASK) == 0,
1500 ("pmap_map: misaligned va %#x", va));
1501 newpde = start | PG_PS | pgeflag | PG_RW | PG_V;
1502 pmap_kenter_pde(va, newpde);
1506 pmap_kenter(va, start);
1511 pmap_invalidate_range(kernel_pmap, sva, va);
1518 * Add a list of wired pages to the kva
1519 * this routine is only used for temporary
1520 * kernel mappings that do not need to have
1521 * page modification or references recorded.
1522 * Note that old mappings are simply written
1523 * over. The page *must* be wired.
1524 * Note: SMP coherent. Uses a ranged shootdown IPI.
1527 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1529 pt_entry_t *endpte, oldpte, pa, *pte;
1534 endpte = pte + count;
1535 while (pte < endpte) {
1537 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1538 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1540 pte_store(pte, pa | pgeflag | PG_RW | PG_V);
1544 if (__predict_false((oldpte & PG_V) != 0))
1545 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1550 * This routine tears out page mappings from the
1551 * kernel -- it is meant only for temporary mappings.
1552 * Note: SMP coherent. Uses a ranged shootdown IPI.
1555 pmap_qremove(vm_offset_t sva, int count)
1560 while (count-- > 0) {
1564 pmap_invalidate_range(kernel_pmap, sva, va);
1567 /***************************************************
1568 * Page table page management routines.....
1569 ***************************************************/
1570 static __inline void
1571 pmap_free_zero_pages(vm_page_t free)
1575 while (free != NULL) {
1577 free = (void *)m->object;
1579 /* Preserve the page's PG_ZERO setting. */
1580 vm_page_free_toq(m);
1585 * Schedule the specified unused page table page to be freed. Specifically,
1586 * add the page to the specified list of pages that will be released to the
1587 * physical memory manager after the TLB has been updated.
1589 static __inline void
1590 pmap_add_delayed_free_list(vm_page_t m, vm_page_t *free, boolean_t set_PG_ZERO)
1594 m->flags |= PG_ZERO;
1596 m->flags &= ~PG_ZERO;
1597 m->object = (void *)*free;
1602 * Inserts the specified page table page into the specified pmap's collection
1603 * of idle page table pages. Each of a pmap's page table pages is responsible
1604 * for mapping a distinct range of virtual addresses. The pmap's collection is
1605 * ordered by this virtual address range.
1607 static __inline void
1608 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1611 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1612 vm_radix_insert(&pmap->pm_root, mpte);
1616 * Looks for a page table page mapping the specified virtual address in the
1617 * specified pmap's collection of idle page table pages. Returns NULL if there
1618 * is no page table page corresponding to the specified virtual address.
1620 static __inline vm_page_t
1621 pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va)
1624 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1625 return (vm_radix_lookup(&pmap->pm_root, va >> PDRSHIFT));
1629 * Removes the specified page table page from the specified pmap's collection
1630 * of idle page table pages. The specified page table page must be a member of
1631 * the pmap's collection.
1633 static __inline void
1634 pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte)
1637 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1638 vm_radix_remove(&pmap->pm_root, mpte->pindex);
1642 * Decrements a page table page's wire count, which is used to record the
1643 * number of valid page table entries within the page. If the wire count
1644 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1645 * page table page was unmapped and FALSE otherwise.
1647 static inline boolean_t
1648 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, vm_page_t *free)
1652 if (m->wire_count == 0) {
1653 _pmap_unwire_ptp(pmap, m, free);
1660 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, vm_page_t *free)
1665 * unmap the page table page
1667 pmap->pm_pdir[m->pindex] = 0;
1668 --pmap->pm_stats.resident_count;
1671 * This is a release store so that the ordinary store unmapping
1672 * the page table page is globally performed before TLB shoot-
1675 atomic_subtract_rel_int(&cnt.v_wire_count, 1);
1678 * Do an invltlb to make the invalidated mapping
1679 * take effect immediately.
1681 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex);
1682 pmap_invalidate_page(pmap, pteva);
1685 * Put page on a list so that it is released after
1686 * *ALL* TLB shootdown is done
1688 pmap_add_delayed_free_list(m, free, TRUE);
1692 * After removing a page table entry, this routine is used to
1693 * conditionally free the page, and manage the hold/wire counts.
1696 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free)
1701 if (va >= VM_MAXUSER_ADDRESS)
1703 ptepde = *pmap_pde(pmap, va);
1704 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1705 return (pmap_unwire_ptp(pmap, mpte, free));
1709 * Initialize the pmap for the swapper process.
1712 pmap_pinit0(pmap_t pmap)
1715 PMAP_LOCK_INIT(pmap);
1717 * Since the page table directory is shared with the kernel pmap,
1718 * which is already included in the list "allpmaps", this pmap does
1719 * not need to be inserted into that list.
1721 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD);
1723 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT);
1725 pmap->pm_root.rt_root = 0;
1726 CPU_ZERO(&pmap->pm_active);
1727 PCPU_SET(curpmap, pmap);
1728 TAILQ_INIT(&pmap->pm_pvchunk);
1729 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1733 * Initialize a preallocated and zeroed pmap structure,
1734 * such as one in a vmspace structure.
1737 pmap_pinit(pmap_t pmap)
1739 vm_page_t m, ptdpg[NPGPTD];
1743 PMAP_LOCK_INIT(pmap);
1746 * No need to allocate page table space yet but we do need a valid
1747 * page directory table.
1749 if (pmap->pm_pdir == NULL) {
1750 pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map,
1752 if (pmap->pm_pdir == NULL) {
1753 PMAP_LOCK_DESTROY(pmap);
1757 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
1758 KASSERT(((vm_offset_t)pmap->pm_pdpt &
1759 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
1760 ("pmap_pinit: pdpt misaligned"));
1761 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
1762 ("pmap_pinit: pdpt above 4g"));
1764 pmap->pm_root.rt_root = 0;
1766 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1767 ("pmap_pinit: pmap has reserved page table page(s)"));
1770 * allocate the page directory page(s)
1772 for (i = 0; i < NPGPTD;) {
1773 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1774 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1782 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD);
1784 for (i = 0; i < NPGPTD; i++)
1785 if ((ptdpg[i]->flags & PG_ZERO) == 0)
1786 pagezero(pmap->pm_pdir + (i * NPDEPG));
1788 mtx_lock_spin(&allpmaps_lock);
1789 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1790 /* Copy the kernel page table directory entries. */
1791 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t));
1792 mtx_unlock_spin(&allpmaps_lock);
1794 /* install self-referential address mapping entry(s) */
1795 for (i = 0; i < NPGPTD; i++) {
1796 pa = VM_PAGE_TO_PHYS(ptdpg[i]);
1797 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M;
1799 pmap->pm_pdpt[i] = pa | PG_V;
1803 CPU_ZERO(&pmap->pm_active);
1804 TAILQ_INIT(&pmap->pm_pvchunk);
1805 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1811 * this routine is called if the page table page is not
1815 _pmap_allocpte(pmap_t pmap, u_int ptepindex, int flags)
1820 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT ||
1821 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK,
1822 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK"));
1825 * Allocate a page table page.
1827 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1828 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1829 if (flags & M_WAITOK) {
1831 rw_wunlock(&pvh_global_lock);
1833 rw_wlock(&pvh_global_lock);
1838 * Indicate the need to retry. While waiting, the page table
1839 * page may have been allocated.
1843 if ((m->flags & PG_ZERO) == 0)
1847 * Map the pagetable page into the process address space, if
1848 * it isn't already there.
1851 pmap->pm_stats.resident_count++;
1853 ptepa = VM_PAGE_TO_PHYS(m);
1854 pmap->pm_pdir[ptepindex] =
1855 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
1861 pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags)
1867 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT ||
1868 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK,
1869 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK"));
1872 * Calculate pagetable page index
1874 ptepindex = va >> PDRSHIFT;
1877 * Get the page directory entry
1879 ptepa = pmap->pm_pdir[ptepindex];
1882 * This supports switching from a 4MB page to a
1885 if (ptepa & PG_PS) {
1886 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
1887 ptepa = pmap->pm_pdir[ptepindex];
1891 * If the page table page is mapped, we just increment the
1892 * hold count, and activate it.
1895 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
1899 * Here if the pte page isn't mapped, or if it has
1902 m = _pmap_allocpte(pmap, ptepindex, flags);
1903 if (m == NULL && (flags & M_WAITOK))
1910 /***************************************************
1911 * Pmap allocation/deallocation routines.
1912 ***************************************************/
1916 * Deal with a SMP shootdown of other users of the pmap that we are
1917 * trying to dispose of. This can be a bit hairy.
1919 static cpuset_t *lazymask;
1920 static u_int lazyptd;
1921 static volatile u_int lazywait;
1923 void pmap_lazyfix_action(void);
1926 pmap_lazyfix_action(void)
1930 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++;
1932 if (rcr3() == lazyptd)
1933 load_cr3(curpcb->pcb_cr3);
1934 CPU_CLR_ATOMIC(PCPU_GET(cpuid), lazymask);
1935 atomic_store_rel_int(&lazywait, 1);
1939 pmap_lazyfix_self(u_int cpuid)
1942 if (rcr3() == lazyptd)
1943 load_cr3(curpcb->pcb_cr3);
1944 CPU_CLR_ATOMIC(cpuid, lazymask);
1949 pmap_lazyfix(pmap_t pmap)
1951 cpuset_t mymask, mask;
1955 mask = pmap->pm_active;
1956 while (!CPU_EMPTY(&mask)) {
1959 /* Find least significant set bit. */
1960 lsb = cpusetobj_ffs(&mask);
1963 CPU_SETOF(lsb, &mask);
1964 mtx_lock_spin(&smp_ipi_mtx);
1966 lazyptd = vtophys(pmap->pm_pdpt);
1968 lazyptd = vtophys(pmap->pm_pdir);
1970 cpuid = PCPU_GET(cpuid);
1972 /* Use a cpuset just for having an easy check. */
1973 CPU_SETOF(cpuid, &mymask);
1974 if (!CPU_CMP(&mask, &mymask)) {
1975 lazymask = &pmap->pm_active;
1976 pmap_lazyfix_self(cpuid);
1978 atomic_store_rel_int((u_int *)&lazymask,
1979 (u_int)&pmap->pm_active);
1980 atomic_store_rel_int(&lazywait, 0);
1981 ipi_selected(mask, IPI_LAZYPMAP);
1982 while (lazywait == 0) {
1988 mtx_unlock_spin(&smp_ipi_mtx);
1990 printf("pmap_lazyfix: spun for 50000000\n");
1991 mask = pmap->pm_active;
1998 * Cleaning up on uniprocessor is easy. For various reasons, we're
1999 * unlikely to have to even execute this code, including the fact
2000 * that the cleanup is deferred until the parent does a wait(2), which
2001 * means that another userland process has run.
2004 pmap_lazyfix(pmap_t pmap)
2008 cr3 = vtophys(pmap->pm_pdir);
2009 if (cr3 == rcr3()) {
2010 load_cr3(curpcb->pcb_cr3);
2011 CPU_CLR(PCPU_GET(cpuid), &pmap->pm_active);
2017 * Release any resources held by the given physical map.
2018 * Called when a pmap initialized by pmap_pinit is being released.
2019 * Should only be called if the map contains no valid mappings.
2022 pmap_release(pmap_t pmap)
2024 vm_page_t m, ptdpg[NPGPTD];
2027 KASSERT(pmap->pm_stats.resident_count == 0,
2028 ("pmap_release: pmap resident count %ld != 0",
2029 pmap->pm_stats.resident_count));
2030 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2031 ("pmap_release: pmap has reserved page table page(s)"));
2034 mtx_lock_spin(&allpmaps_lock);
2035 LIST_REMOVE(pmap, pm_list);
2036 mtx_unlock_spin(&allpmaps_lock);
2038 for (i = 0; i < NPGPTD; i++)
2039 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] &
2042 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) *
2043 sizeof(*pmap->pm_pdir));
2045 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2047 for (i = 0; i < NPGPTD; i++) {
2050 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2051 ("pmap_release: got wrong ptd page"));
2054 atomic_subtract_int(&cnt.v_wire_count, 1);
2055 vm_page_free_zero(m);
2057 PMAP_LOCK_DESTROY(pmap);
2061 kvm_size(SYSCTL_HANDLER_ARGS)
2063 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2065 return (sysctl_handle_long(oidp, &ksize, 0, req));
2067 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2068 0, 0, kvm_size, "IU", "Size of KVM");
2071 kvm_free(SYSCTL_HANDLER_ARGS)
2073 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2075 return (sysctl_handle_long(oidp, &kfree, 0, req));
2077 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2078 0, 0, kvm_free, "IU", "Amount of KVM free");
2081 * grow the number of kernel page table entries, if needed
2084 pmap_growkernel(vm_offset_t addr)
2086 vm_paddr_t ptppaddr;
2090 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2091 addr = roundup2(addr, NBPDR);
2092 if (addr - 1 >= kernel_map->max_offset)
2093 addr = kernel_map->max_offset;
2094 while (kernel_vm_end < addr) {
2095 if (pdir_pde(PTD, kernel_vm_end)) {
2096 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2097 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2098 kernel_vm_end = kernel_map->max_offset;
2104 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2105 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2108 panic("pmap_growkernel: no memory to grow kernel");
2112 if ((nkpg->flags & PG_ZERO) == 0)
2113 pmap_zero_page(nkpg);
2114 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2115 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2116 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir;
2118 pmap_kenter_pde(kernel_vm_end, newpdir);
2119 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2120 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2121 kernel_vm_end = kernel_map->max_offset;
2128 /***************************************************
2129 * page management routines.
2130 ***************************************************/
2132 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2133 CTASSERT(_NPCM == 11);
2134 CTASSERT(_NPCPV == 336);
2136 static __inline struct pv_chunk *
2137 pv_to_chunk(pv_entry_t pv)
2140 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2143 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2145 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2146 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2148 static const uint32_t pc_freemask[_NPCM] = {
2149 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2150 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2151 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2152 PC_FREE0_9, PC_FREE10
2155 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2156 "Current number of pv entries");
2159 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2161 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2162 "Current number of pv entry chunks");
2163 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2164 "Current number of pv entry chunks allocated");
2165 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2166 "Current number of pv entry chunks frees");
2167 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2168 "Number of times tried to get a chunk page but failed.");
2170 static long pv_entry_frees, pv_entry_allocs;
2171 static int pv_entry_spare;
2173 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2174 "Current number of pv entry frees");
2175 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2176 "Current number of pv entry allocs");
2177 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2178 "Current number of spare pv entries");
2182 * We are in a serious low memory condition. Resort to
2183 * drastic measures to free some pages so we can allocate
2184 * another pv entry chunk.
2187 pmap_pv_reclaim(pmap_t locked_pmap)
2190 struct pv_chunk *pc;
2191 struct md_page *pvh;
2194 pt_entry_t *pte, tpte;
2197 vm_page_t free, m, m_pc;
2199 int bit, field, freed;
2201 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2204 TAILQ_INIT(&newtail);
2205 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2207 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2208 if (pmap != pc->pc_pmap) {
2210 pmap_invalidate_all(pmap);
2211 if (pmap != locked_pmap)
2215 /* Avoid deadlock and lock recursion. */
2216 if (pmap > locked_pmap)
2218 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2220 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2226 * Destroy every non-wired, 4 KB page mapping in the chunk.
2229 for (field = 0; field < _NPCM; field++) {
2230 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2231 inuse != 0; inuse &= ~(1UL << bit)) {
2233 pv = &pc->pc_pventry[field * 32 + bit];
2235 pde = pmap_pde(pmap, va);
2236 if ((*pde & PG_PS) != 0)
2238 pte = pmap_pte(pmap, va);
2240 if ((tpte & PG_W) == 0)
2241 tpte = pte_load_clear(pte);
2242 pmap_pte_release(pte);
2243 if ((tpte & PG_W) != 0)
2246 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2248 if ((tpte & PG_G) != 0)
2249 pmap_invalidate_page(pmap, va);
2250 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2251 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2253 if ((tpte & PG_A) != 0)
2254 vm_page_aflag_set(m, PGA_REFERENCED);
2255 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2256 if (TAILQ_EMPTY(&m->md.pv_list) &&
2257 (m->flags & PG_FICTITIOUS) == 0) {
2258 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2259 if (TAILQ_EMPTY(&pvh->pv_list)) {
2260 vm_page_aflag_clear(m,
2264 pc->pc_map[field] |= 1UL << bit;
2265 pmap_unuse_pt(pmap, va, &free);
2270 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2273 /* Every freed mapping is for a 4 KB page. */
2274 pmap->pm_stats.resident_count -= freed;
2275 PV_STAT(pv_entry_frees += freed);
2276 PV_STAT(pv_entry_spare += freed);
2277 pv_entry_count -= freed;
2278 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2279 for (field = 0; field < _NPCM; field++)
2280 if (pc->pc_map[field] != pc_freemask[field]) {
2281 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2283 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2286 * One freed pv entry in locked_pmap is
2289 if (pmap == locked_pmap)
2293 if (field == _NPCM) {
2294 PV_STAT(pv_entry_spare -= _NPCPV);
2295 PV_STAT(pc_chunk_count--);
2296 PV_STAT(pc_chunk_frees++);
2297 /* Entire chunk is free; return it. */
2298 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2299 pmap_qremove((vm_offset_t)pc, 1);
2300 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2305 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2307 pmap_invalidate_all(pmap);
2308 if (pmap != locked_pmap)
2311 if (m_pc == NULL && pv_vafree != 0 && free != NULL) {
2313 free = (void *)m_pc->object;
2314 /* Recycle a freed page table page. */
2315 m_pc->wire_count = 1;
2316 atomic_add_int(&cnt.v_wire_count, 1);
2318 pmap_free_zero_pages(free);
2323 * free the pv_entry back to the free list
2326 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2328 struct pv_chunk *pc;
2329 int idx, field, bit;
2331 rw_assert(&pvh_global_lock, RA_WLOCKED);
2332 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2333 PV_STAT(pv_entry_frees++);
2334 PV_STAT(pv_entry_spare++);
2336 pc = pv_to_chunk(pv);
2337 idx = pv - &pc->pc_pventry[0];
2340 pc->pc_map[field] |= 1ul << bit;
2341 for (idx = 0; idx < _NPCM; idx++)
2342 if (pc->pc_map[idx] != pc_freemask[idx]) {
2344 * 98% of the time, pc is already at the head of the
2345 * list. If it isn't already, move it to the head.
2347 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2349 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2350 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2355 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2360 free_pv_chunk(struct pv_chunk *pc)
2364 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2365 PV_STAT(pv_entry_spare -= _NPCPV);
2366 PV_STAT(pc_chunk_count--);
2367 PV_STAT(pc_chunk_frees++);
2368 /* entire chunk is free, return it */
2369 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2370 pmap_qremove((vm_offset_t)pc, 1);
2371 vm_page_unwire(m, 0);
2373 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2377 * get a new pv_entry, allocating a block from the system
2381 get_pv_entry(pmap_t pmap, boolean_t try)
2383 static const struct timeval printinterval = { 60, 0 };
2384 static struct timeval lastprint;
2387 struct pv_chunk *pc;
2390 rw_assert(&pvh_global_lock, RA_WLOCKED);
2391 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2392 PV_STAT(pv_entry_allocs++);
2394 if (pv_entry_count > pv_entry_high_water)
2395 if (ratecheck(&lastprint, &printinterval))
2396 printf("Approaching the limit on PV entries, consider "
2397 "increasing either the vm.pmap.shpgperproc or the "
2398 "vm.pmap.pv_entry_max tunable.\n");
2400 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2402 for (field = 0; field < _NPCM; field++) {
2403 if (pc->pc_map[field]) {
2404 bit = bsfl(pc->pc_map[field]);
2408 if (field < _NPCM) {
2409 pv = &pc->pc_pventry[field * 32 + bit];
2410 pc->pc_map[field] &= ~(1ul << bit);
2411 /* If this was the last item, move it to tail */
2412 for (field = 0; field < _NPCM; field++)
2413 if (pc->pc_map[field] != 0) {
2414 PV_STAT(pv_entry_spare--);
2415 return (pv); /* not full, return */
2417 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2418 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2419 PV_STAT(pv_entry_spare--);
2424 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2425 * global lock. If "pv_vafree" is currently non-empty, it will
2426 * remain non-empty until pmap_ptelist_alloc() completes.
2428 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2429 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2432 PV_STAT(pc_chunk_tryfail++);
2435 m = pmap_pv_reclaim(pmap);
2439 PV_STAT(pc_chunk_count++);
2440 PV_STAT(pc_chunk_allocs++);
2441 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2442 pmap_qenter((vm_offset_t)pc, &m, 1);
2444 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2445 for (field = 1; field < _NPCM; field++)
2446 pc->pc_map[field] = pc_freemask[field];
2447 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2448 pv = &pc->pc_pventry[0];
2449 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2450 PV_STAT(pv_entry_spare += _NPCPV - 1);
2454 static __inline pv_entry_t
2455 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2459 rw_assert(&pvh_global_lock, RA_WLOCKED);
2460 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2461 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2462 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2470 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2472 struct md_page *pvh;
2474 vm_offset_t va_last;
2477 rw_assert(&pvh_global_lock, RA_WLOCKED);
2478 KASSERT((pa & PDRMASK) == 0,
2479 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2482 * Transfer the 4mpage's pv entry for this mapping to the first
2485 pvh = pa_to_pvh(pa);
2486 va = trunc_4mpage(va);
2487 pv = pmap_pvh_remove(pvh, pmap, va);
2488 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2489 m = PHYS_TO_VM_PAGE(pa);
2490 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2491 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2492 va_last = va + NBPDR - PAGE_SIZE;
2495 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2496 ("pmap_pv_demote_pde: page %p is not managed", m));
2498 pmap_insert_entry(pmap, va, m);
2499 } while (va < va_last);
2503 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2505 struct md_page *pvh;
2507 vm_offset_t va_last;
2510 rw_assert(&pvh_global_lock, RA_WLOCKED);
2511 KASSERT((pa & PDRMASK) == 0,
2512 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2515 * Transfer the first page's pv entry for this mapping to the
2516 * 4mpage's pv list. Aside from avoiding the cost of a call
2517 * to get_pv_entry(), a transfer avoids the possibility that
2518 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2519 * removes one of the mappings that is being promoted.
2521 m = PHYS_TO_VM_PAGE(pa);
2522 va = trunc_4mpage(va);
2523 pv = pmap_pvh_remove(&m->md, pmap, va);
2524 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2525 pvh = pa_to_pvh(pa);
2526 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2527 /* Free the remaining NPTEPG - 1 pv entries. */
2528 va_last = va + NBPDR - PAGE_SIZE;
2532 pmap_pvh_free(&m->md, pmap, va);
2533 } while (va < va_last);
2537 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2541 pv = pmap_pvh_remove(pvh, pmap, va);
2542 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2543 free_pv_entry(pmap, pv);
2547 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2549 struct md_page *pvh;
2551 rw_assert(&pvh_global_lock, RA_WLOCKED);
2552 pmap_pvh_free(&m->md, pmap, va);
2553 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2554 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2555 if (TAILQ_EMPTY(&pvh->pv_list))
2556 vm_page_aflag_clear(m, PGA_WRITEABLE);
2561 * Create a pv entry for page at pa for
2565 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2569 rw_assert(&pvh_global_lock, RA_WLOCKED);
2570 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2571 pv = get_pv_entry(pmap, FALSE);
2573 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2577 * Conditionally create a pv entry.
2580 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2584 rw_assert(&pvh_global_lock, RA_WLOCKED);
2585 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2586 if (pv_entry_count < pv_entry_high_water &&
2587 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2589 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2596 * Create the pv entries for each of the pages within a superpage.
2599 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2601 struct md_page *pvh;
2604 rw_assert(&pvh_global_lock, RA_WLOCKED);
2605 if (pv_entry_count < pv_entry_high_water &&
2606 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2608 pvh = pa_to_pvh(pa);
2609 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2616 * Fills a page table page with mappings to consecutive physical pages.
2619 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2623 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2625 newpte += PAGE_SIZE;
2630 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2631 * 2- or 4MB page mapping is invalidated.
2634 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2636 pd_entry_t newpde, oldpde;
2637 pt_entry_t *firstpte, newpte;
2639 vm_page_t free, mpte;
2641 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2643 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2644 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2645 mpte = pmap_lookup_pt_page(pmap, va);
2647 pmap_remove_pt_page(pmap, mpte);
2649 KASSERT((oldpde & PG_W) == 0,
2650 ("pmap_demote_pde: page table page for a wired mapping"
2654 * Invalidate the 2- or 4MB page mapping and return
2655 * "failure" if the mapping was never accessed or the
2656 * allocation of the new page table page fails.
2658 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2659 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2660 VM_ALLOC_WIRED)) == NULL) {
2662 pmap_remove_pde(pmap, pde, trunc_4mpage(va), &free);
2663 pmap_invalidate_page(pmap, trunc_4mpage(va));
2664 pmap_free_zero_pages(free);
2665 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2666 " in pmap %p", va, pmap);
2669 if (va < VM_MAXUSER_ADDRESS)
2670 pmap->pm_stats.resident_count++;
2672 mptepa = VM_PAGE_TO_PHYS(mpte);
2675 * If the page mapping is in the kernel's address space, then the
2676 * KPTmap can provide access to the page table page. Otherwise,
2677 * temporarily map the page table page (mpte) into the kernel's
2678 * address space at either PADDR1 or PADDR2.
2681 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2682 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2683 if ((*PMAP1 & PG_FRAME) != mptepa) {
2684 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2686 PMAP1cpu = PCPU_GET(cpuid);
2692 if (PMAP1cpu != PCPU_GET(cpuid)) {
2693 PMAP1cpu = PCPU_GET(cpuid);
2701 mtx_lock(&PMAP2mutex);
2702 if ((*PMAP2 & PG_FRAME) != mptepa) {
2703 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2704 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2708 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2709 KASSERT((oldpde & PG_A) != 0,
2710 ("pmap_demote_pde: oldpde is missing PG_A"));
2711 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2712 ("pmap_demote_pde: oldpde is missing PG_M"));
2713 newpte = oldpde & ~PG_PS;
2714 if ((newpte & PG_PDE_PAT) != 0)
2715 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2718 * If the page table page is new, initialize it.
2720 if (mpte->wire_count == 1) {
2721 mpte->wire_count = NPTEPG;
2722 pmap_fill_ptp(firstpte, newpte);
2724 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2725 ("pmap_demote_pde: firstpte and newpte map different physical"
2729 * If the mapping has changed attributes, update the page table
2732 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2733 pmap_fill_ptp(firstpte, newpte);
2736 * Demote the mapping. This pmap is locked. The old PDE has
2737 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2738 * set. Thus, there is no danger of a race with another
2739 * processor changing the setting of PG_A and/or PG_M between
2740 * the read above and the store below.
2742 if (workaround_erratum383)
2743 pmap_update_pde(pmap, va, pde, newpde);
2744 else if (pmap == kernel_pmap)
2745 pmap_kenter_pde(va, newpde);
2747 pde_store(pde, newpde);
2748 if (firstpte == PADDR2)
2749 mtx_unlock(&PMAP2mutex);
2752 * Invalidate the recursive mapping of the page table page.
2754 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2757 * Demote the pv entry. This depends on the earlier demotion
2758 * of the mapping. Specifically, the (re)creation of a per-
2759 * page pv entry might trigger the execution of pmap_collect(),
2760 * which might reclaim a newly (re)created per-page pv entry
2761 * and destroy the associated mapping. In order to destroy
2762 * the mapping, the PDE must have already changed from mapping
2763 * the 2mpage to referencing the page table page.
2765 if ((oldpde & PG_MANAGED) != 0)
2766 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2768 pmap_pde_demotions++;
2769 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2770 " in pmap %p", va, pmap);
2775 * pmap_remove_pde: do the things to unmap a superpage in a process
2778 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2781 struct md_page *pvh;
2783 vm_offset_t eva, va;
2786 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2787 KASSERT((sva & PDRMASK) == 0,
2788 ("pmap_remove_pde: sva is not 4mpage aligned"));
2789 oldpde = pte_load_clear(pdq);
2791 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2794 * Machines that don't support invlpg, also don't support
2798 pmap_invalidate_page(kernel_pmap, sva);
2799 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2800 if (oldpde & PG_MANAGED) {
2801 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2802 pmap_pvh_free(pvh, pmap, sva);
2804 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2805 va < eva; va += PAGE_SIZE, m++) {
2806 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2809 vm_page_aflag_set(m, PGA_REFERENCED);
2810 if (TAILQ_EMPTY(&m->md.pv_list) &&
2811 TAILQ_EMPTY(&pvh->pv_list))
2812 vm_page_aflag_clear(m, PGA_WRITEABLE);
2815 if (pmap == kernel_pmap) {
2816 if (!pmap_demote_pde(pmap, pdq, sva))
2817 panic("pmap_remove_pde: failed demotion");
2819 mpte = pmap_lookup_pt_page(pmap, sva);
2821 pmap_remove_pt_page(pmap, mpte);
2822 pmap->pm_stats.resident_count--;
2823 KASSERT(mpte->wire_count == NPTEPG,
2824 ("pmap_remove_pde: pte page wire count error"));
2825 mpte->wire_count = 0;
2826 pmap_add_delayed_free_list(mpte, free, FALSE);
2827 atomic_subtract_int(&cnt.v_wire_count, 1);
2833 * pmap_remove_pte: do the things to unmap a page in a process
2836 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free)
2841 rw_assert(&pvh_global_lock, RA_WLOCKED);
2842 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2843 oldpte = pte_load_clear(ptq);
2844 KASSERT(oldpte != 0,
2845 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
2847 pmap->pm_stats.wired_count -= 1;
2849 * Machines that don't support invlpg, also don't support
2853 pmap_invalidate_page(kernel_pmap, va);
2854 pmap->pm_stats.resident_count -= 1;
2855 if (oldpte & PG_MANAGED) {
2856 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2857 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2860 vm_page_aflag_set(m, PGA_REFERENCED);
2861 pmap_remove_entry(pmap, m, va);
2863 return (pmap_unuse_pt(pmap, va, free));
2867 * Remove a single page from a process address space
2870 pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free)
2874 rw_assert(&pvh_global_lock, RA_WLOCKED);
2875 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
2876 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2877 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
2879 pmap_remove_pte(pmap, pte, va, free);
2880 pmap_invalidate_page(pmap, va);
2884 * Remove the given range of addresses from the specified map.
2886 * It is assumed that the start and end are properly
2887 * rounded to the page size.
2890 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2895 vm_page_t free = NULL;
2899 * Perform an unsynchronized read. This is, however, safe.
2901 if (pmap->pm_stats.resident_count == 0)
2906 rw_wlock(&pvh_global_lock);
2911 * special handling of removing one page. a very
2912 * common operation and easy to short circuit some
2915 if ((sva + PAGE_SIZE == eva) &&
2916 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
2917 pmap_remove_page(pmap, sva, &free);
2921 for (; sva < eva; sva = pdnxt) {
2925 * Calculate index for next page table.
2927 pdnxt = (sva + NBPDR) & ~PDRMASK;
2930 if (pmap->pm_stats.resident_count == 0)
2933 pdirindex = sva >> PDRSHIFT;
2934 ptpaddr = pmap->pm_pdir[pdirindex];
2937 * Weed out invalid mappings. Note: we assume that the page
2938 * directory table is always allocated, and in kernel virtual.
2944 * Check for large page.
2946 if ((ptpaddr & PG_PS) != 0) {
2948 * Are we removing the entire large page? If not,
2949 * demote the mapping and fall through.
2951 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
2953 * The TLB entry for a PG_G mapping is
2954 * invalidated by pmap_remove_pde().
2956 if ((ptpaddr & PG_G) == 0)
2958 pmap_remove_pde(pmap,
2959 &pmap->pm_pdir[pdirindex], sva, &free);
2961 } else if (!pmap_demote_pde(pmap,
2962 &pmap->pm_pdir[pdirindex], sva)) {
2963 /* The large page mapping was destroyed. */
2969 * Limit our scan to either the end of the va represented
2970 * by the current page table page, or to the end of the
2971 * range being removed.
2976 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
2982 * The TLB entry for a PG_G mapping is invalidated
2983 * by pmap_remove_pte().
2985 if ((*pte & PG_G) == 0)
2987 if (pmap_remove_pte(pmap, pte, sva, &free))
2994 pmap_invalidate_all(pmap);
2995 rw_wunlock(&pvh_global_lock);
2997 pmap_free_zero_pages(free);
3001 * Routine: pmap_remove_all
3003 * Removes this physical page from
3004 * all physical maps in which it resides.
3005 * Reflects back modify bits to the pager.
3008 * Original versions of this routine were very
3009 * inefficient because they iteratively called
3010 * pmap_remove (slow...)
3014 pmap_remove_all(vm_page_t m)
3016 struct md_page *pvh;
3019 pt_entry_t *pte, tpte;
3024 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3025 ("pmap_remove_all: page %p is not managed", m));
3027 rw_wlock(&pvh_global_lock);
3029 if ((m->flags & PG_FICTITIOUS) != 0)
3030 goto small_mappings;
3031 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3032 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3036 pde = pmap_pde(pmap, va);
3037 (void)pmap_demote_pde(pmap, pde, va);
3041 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3044 pmap->pm_stats.resident_count--;
3045 pde = pmap_pde(pmap, pv->pv_va);
3046 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3047 " a 4mpage in page %p's pv list", m));
3048 pte = pmap_pte_quick(pmap, pv->pv_va);
3049 tpte = pte_load_clear(pte);
3050 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3053 pmap->pm_stats.wired_count--;
3055 vm_page_aflag_set(m, PGA_REFERENCED);
3058 * Update the vm_page_t clean and reference bits.
3060 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3062 pmap_unuse_pt(pmap, pv->pv_va, &free);
3063 pmap_invalidate_page(pmap, pv->pv_va);
3064 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3065 free_pv_entry(pmap, pv);
3068 vm_page_aflag_clear(m, PGA_WRITEABLE);
3070 rw_wunlock(&pvh_global_lock);
3071 pmap_free_zero_pages(free);
3075 * pmap_protect_pde: do the things to protect a 4mpage in a process
3078 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3080 pd_entry_t newpde, oldpde;
3081 vm_offset_t eva, va;
3083 boolean_t anychanged;
3085 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3086 KASSERT((sva & PDRMASK) == 0,
3087 ("pmap_protect_pde: sva is not 4mpage aligned"));
3090 oldpde = newpde = *pde;
3091 if (oldpde & PG_MANAGED) {
3093 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3094 va < eva; va += PAGE_SIZE, m++)
3095 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3098 if ((prot & VM_PROT_WRITE) == 0)
3099 newpde &= ~(PG_RW | PG_M);
3101 if ((prot & VM_PROT_EXECUTE) == 0)
3104 if (newpde != oldpde) {
3105 if (!pde_cmpset(pde, oldpde, newpde))
3108 pmap_invalidate_page(pmap, sva);
3112 return (anychanged);
3116 * Set the physical protection on the
3117 * specified range of this map as requested.
3120 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3125 boolean_t anychanged, pv_lists_locked;
3127 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
3128 pmap_remove(pmap, sva, eva);
3133 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3134 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3137 if (prot & VM_PROT_WRITE)
3141 if (pmap_is_current(pmap))
3142 pv_lists_locked = FALSE;
3144 pv_lists_locked = TRUE;
3146 rw_wlock(&pvh_global_lock);
3152 for (; sva < eva; sva = pdnxt) {
3153 pt_entry_t obits, pbits;
3156 pdnxt = (sva + NBPDR) & ~PDRMASK;
3160 pdirindex = sva >> PDRSHIFT;
3161 ptpaddr = pmap->pm_pdir[pdirindex];
3164 * Weed out invalid mappings. Note: we assume that the page
3165 * directory table is always allocated, and in kernel virtual.
3171 * Check for large page.
3173 if ((ptpaddr & PG_PS) != 0) {
3175 * Are we protecting the entire large page? If not,
3176 * demote the mapping and fall through.
3178 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3180 * The TLB entry for a PG_G mapping is
3181 * invalidated by pmap_protect_pde().
3183 if (pmap_protect_pde(pmap,
3184 &pmap->pm_pdir[pdirindex], sva, prot))
3188 if (!pv_lists_locked) {
3189 pv_lists_locked = TRUE;
3190 if (!rw_try_wlock(&pvh_global_lock)) {
3192 pmap_invalidate_all(
3199 if (!pmap_demote_pde(pmap,
3200 &pmap->pm_pdir[pdirindex], sva)) {
3202 * The large page mapping was
3213 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3219 * Regardless of whether a pte is 32 or 64 bits in
3220 * size, PG_RW, PG_A, and PG_M are among the least
3221 * significant 32 bits.
3223 obits = pbits = *pte;
3224 if ((pbits & PG_V) == 0)
3227 if ((prot & VM_PROT_WRITE) == 0) {
3228 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3229 (PG_MANAGED | PG_M | PG_RW)) {
3230 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3233 pbits &= ~(PG_RW | PG_M);
3236 if ((prot & VM_PROT_EXECUTE) == 0)
3240 if (pbits != obits) {
3242 if (!atomic_cmpset_64(pte, obits, pbits))
3245 if (!atomic_cmpset_int((u_int *)pte, obits,
3250 pmap_invalidate_page(pmap, sva);
3257 pmap_invalidate_all(pmap);
3258 if (pv_lists_locked) {
3260 rw_wunlock(&pvh_global_lock);
3266 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3267 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3268 * For promotion to occur, two conditions must be met: (1) the 4KB page
3269 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3270 * mappings must have identical characteristics.
3272 * Managed (PG_MANAGED) mappings within the kernel address space are not
3273 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3274 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3278 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3281 pt_entry_t *firstpte, oldpte, pa, *pte;
3282 vm_offset_t oldpteva;
3285 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3288 * Examine the first PTE in the specified PTP. Abort if this PTE is
3289 * either invalid, unused, or does not map the first 4KB physical page
3290 * within a 2- or 4MB page.
3292 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3295 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3296 pmap_pde_p_failures++;
3297 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3298 " in pmap %p", va, pmap);
3301 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3302 pmap_pde_p_failures++;
3303 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3304 " in pmap %p", va, pmap);
3307 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3309 * When PG_M is already clear, PG_RW can be cleared without
3310 * a TLB invalidation.
3312 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3319 * Examine each of the other PTEs in the specified PTP. Abort if this
3320 * PTE maps an unexpected 4KB physical page or does not have identical
3321 * characteristics to the first PTE.
3323 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3324 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3327 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3328 pmap_pde_p_failures++;
3329 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3330 " in pmap %p", va, pmap);
3333 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3335 * When PG_M is already clear, PG_RW can be cleared
3336 * without a TLB invalidation.
3338 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3342 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3344 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3345 " in pmap %p", oldpteva, pmap);
3347 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3348 pmap_pde_p_failures++;
3349 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3350 " in pmap %p", va, pmap);
3357 * Save the page table page in its current state until the PDE
3358 * mapping the superpage is demoted by pmap_demote_pde() or
3359 * destroyed by pmap_remove_pde().
3361 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3362 KASSERT(mpte >= vm_page_array &&
3363 mpte < &vm_page_array[vm_page_array_size],
3364 ("pmap_promote_pde: page table page is out of range"));
3365 KASSERT(mpte->pindex == va >> PDRSHIFT,
3366 ("pmap_promote_pde: page table page's pindex is wrong"));
3367 pmap_insert_pt_page(pmap, mpte);
3370 * Promote the pv entries.
3372 if ((newpde & PG_MANAGED) != 0)
3373 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3376 * Propagate the PAT index to its proper position.
3378 if ((newpde & PG_PTE_PAT) != 0)
3379 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3382 * Map the superpage.
3384 if (workaround_erratum383)
3385 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3386 else if (pmap == kernel_pmap)
3387 pmap_kenter_pde(va, PG_PS | newpde);
3389 pde_store(pde, PG_PS | newpde);
3391 pmap_pde_promotions++;
3392 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3393 " in pmap %p", va, pmap);
3397 * Insert the given physical page (p) at
3398 * the specified virtual address (v) in the
3399 * target physical map with the protection requested.
3401 * If specified, the page will be wired down, meaning
3402 * that the related pte can not be reclaimed.
3404 * NB: This is the only routine which MAY NOT lazy-evaluate
3405 * or lose information. That is, this routine must actually
3406 * insert this page into the given map NOW.
3409 pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
3410 vm_prot_t prot, boolean_t wired)
3414 pt_entry_t newpte, origpte;
3420 va = trunc_page(va);
3421 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
3422 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
3423 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)",
3425 if ((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) == 0)
3426 VM_OBJECT_ASSERT_WLOCKED(m->object);
3430 rw_wlock(&pvh_global_lock);
3435 * In the case that a page table page is not
3436 * resident, we are creating it here.
3438 if (va < VM_MAXUSER_ADDRESS) {
3439 mpte = pmap_allocpte(pmap, va, M_WAITOK);
3442 pde = pmap_pde(pmap, va);
3443 if ((*pde & PG_PS) != 0)
3444 panic("pmap_enter: attempted pmap_enter on 4MB page");
3445 pte = pmap_pte_quick(pmap, va);
3448 * Page Directory table entry not valid, we need a new PT page
3451 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3452 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3455 pa = VM_PAGE_TO_PHYS(m);
3458 opa = origpte & PG_FRAME;
3461 * Mapping has not changed, must be protection or wiring change.
3463 if (origpte && (opa == pa)) {
3465 * Wiring change, just update stats. We don't worry about
3466 * wiring PT pages as they remain resident as long as there
3467 * are valid mappings in them. Hence, if a user page is wired,
3468 * the PT page will be also.
3470 if (wired && ((origpte & PG_W) == 0))
3471 pmap->pm_stats.wired_count++;
3472 else if (!wired && (origpte & PG_W))
3473 pmap->pm_stats.wired_count--;
3476 * Remove extra pte reference
3481 if (origpte & PG_MANAGED) {
3491 * Mapping has changed, invalidate old range and fall through to
3492 * handle validating new mapping.
3496 pmap->pm_stats.wired_count--;
3497 if (origpte & PG_MANAGED) {
3498 om = PHYS_TO_VM_PAGE(opa);
3499 pv = pmap_pvh_remove(&om->md, pmap, va);
3503 KASSERT(mpte->wire_count > 0,
3504 ("pmap_enter: missing reference to page table page,"
3508 pmap->pm_stats.resident_count++;
3511 * Enter on the PV list if part of our managed memory.
3513 if ((m->oflags & VPO_UNMANAGED) == 0) {
3514 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3515 ("pmap_enter: managed mapping within the clean submap"));
3517 pv = get_pv_entry(pmap, FALSE);
3519 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3521 } else if (pv != NULL)
3522 free_pv_entry(pmap, pv);
3525 * Increment counters
3528 pmap->pm_stats.wired_count++;
3532 * Now validate mapping with desired protection/wiring.
3534 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V);
3535 if ((prot & VM_PROT_WRITE) != 0) {
3537 if ((newpte & PG_MANAGED) != 0)
3538 vm_page_aflag_set(m, PGA_WRITEABLE);
3541 if ((prot & VM_PROT_EXECUTE) == 0)
3546 if (va < VM_MAXUSER_ADDRESS)
3548 if (pmap == kernel_pmap)
3552 * if the mapping or permission bits are different, we need
3553 * to update the pte.
3555 if ((origpte & ~(PG_M|PG_A)) != newpte) {
3557 if ((access & VM_PROT_WRITE) != 0)
3559 if (origpte & PG_V) {
3561 origpte = pte_load_store(pte, newpte);
3562 if (origpte & PG_A) {
3563 if (origpte & PG_MANAGED)
3564 vm_page_aflag_set(om, PGA_REFERENCED);
3565 if (opa != VM_PAGE_TO_PHYS(m))
3568 if ((origpte & PG_NX) == 0 &&
3569 (newpte & PG_NX) != 0)
3573 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
3574 if ((origpte & PG_MANAGED) != 0)
3576 if ((prot & VM_PROT_WRITE) == 0)
3579 if ((origpte & PG_MANAGED) != 0 &&
3580 TAILQ_EMPTY(&om->md.pv_list) &&
3581 ((om->flags & PG_FICTITIOUS) != 0 ||
3582 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3583 vm_page_aflag_clear(om, PGA_WRITEABLE);
3585 pmap_invalidate_page(pmap, va);
3587 pte_store(pte, newpte);
3591 * If both the page table page and the reservation are fully
3592 * populated, then attempt promotion.
3594 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3595 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3596 vm_reserv_level_iffullpop(m) == 0)
3597 pmap_promote_pde(pmap, pde, va);
3600 rw_wunlock(&pvh_global_lock);
3605 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and
3606 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
3607 * blocking, (2) a mapping already exists at the specified virtual address, or
3608 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3611 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3613 pd_entry_t *pde, newpde;
3615 rw_assert(&pvh_global_lock, RA_WLOCKED);
3616 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3617 pde = pmap_pde(pmap, va);
3619 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3620 " in pmap %p", va, pmap);
3623 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3625 if ((m->oflags & VPO_UNMANAGED) == 0) {
3626 newpde |= PG_MANAGED;
3629 * Abort this mapping if its PV entry could not be created.
3631 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) {
3632 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3633 " in pmap %p", va, pmap);
3638 if ((prot & VM_PROT_EXECUTE) == 0)
3641 if (va < VM_MAXUSER_ADDRESS)
3645 * Increment counters.
3647 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3650 * Map the superpage.
3652 pde_store(pde, newpde);
3654 pmap_pde_mappings++;
3655 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3656 " in pmap %p", va, pmap);
3661 * Maps a sequence of resident pages belonging to the same object.
3662 * The sequence begins with the given page m_start. This page is
3663 * mapped at the given virtual address start. Each subsequent page is
3664 * mapped at a virtual address that is offset from start by the same
3665 * amount as the page is offset from m_start within the object. The
3666 * last page in the sequence is the page with the largest offset from
3667 * m_start that can be mapped at a virtual address less than the given
3668 * virtual address end. Not every virtual page between start and end
3669 * is mapped; only those for which a resident page exists with the
3670 * corresponding offset from m_start are mapped.
3673 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3674 vm_page_t m_start, vm_prot_t prot)
3678 vm_pindex_t diff, psize;
3680 VM_OBJECT_ASSERT_WLOCKED(m_start->object);
3681 psize = atop(end - start);
3684 rw_wlock(&pvh_global_lock);
3686 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3687 va = start + ptoa(diff);
3688 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3689 (VM_PAGE_TO_PHYS(m) & PDRMASK) == 0 &&
3690 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0 &&
3691 pmap_enter_pde(pmap, va, m, prot))
3692 m = &m[NBPDR / PAGE_SIZE - 1];
3694 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3696 m = TAILQ_NEXT(m, listq);
3698 rw_wunlock(&pvh_global_lock);
3703 * this code makes some *MAJOR* assumptions:
3704 * 1. Current pmap & pmap exists.
3707 * 4. No page table pages.
3708 * but is *MUCH* faster than pmap_enter...
3712 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3715 rw_wlock(&pvh_global_lock);
3717 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
3718 rw_wunlock(&pvh_global_lock);
3723 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3724 vm_prot_t prot, vm_page_t mpte)
3730 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3731 (m->oflags & VPO_UNMANAGED) != 0,
3732 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3733 rw_assert(&pvh_global_lock, RA_WLOCKED);
3734 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3737 * In the case that a page table page is not
3738 * resident, we are creating it here.
3740 if (va < VM_MAXUSER_ADDRESS) {
3745 * Calculate pagetable page index
3747 ptepindex = va >> PDRSHIFT;
3748 if (mpte && (mpte->pindex == ptepindex)) {
3752 * Get the page directory entry
3754 ptepa = pmap->pm_pdir[ptepindex];
3757 * If the page table page is mapped, we just increment
3758 * the hold count, and activate it.
3763 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
3766 mpte = _pmap_allocpte(pmap, ptepindex,
3777 * This call to vtopte makes the assumption that we are
3778 * entering the page into the current pmap. In order to support
3779 * quick entry into any pmap, one would likely use pmap_pte_quick.
3780 * But that isn't as quick as vtopte.
3792 * Enter on the PV list if part of our managed memory.
3794 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3795 !pmap_try_insert_pv_entry(pmap, va, m)) {
3798 if (pmap_unwire_ptp(pmap, mpte, &free)) {
3799 pmap_invalidate_page(pmap, va);
3800 pmap_free_zero_pages(free);
3809 * Increment counters
3811 pmap->pm_stats.resident_count++;
3813 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3815 if ((prot & VM_PROT_EXECUTE) == 0)
3820 * Now validate mapping with RO protection
3822 if ((m->oflags & VPO_UNMANAGED) != 0)
3823 pte_store(pte, pa | PG_V | PG_U);
3825 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3830 * Make a temporary mapping for a physical address. This is only intended
3831 * to be used for panic dumps.
3834 pmap_kenter_temporary(vm_paddr_t pa, int i)
3838 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3839 pmap_kenter(va, pa);
3841 return ((void *)crashdumpmap);
3845 * This code maps large physical mmap regions into the
3846 * processor address space. Note that some shortcuts
3847 * are taken, but the code works.
3850 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3851 vm_pindex_t pindex, vm_size_t size)
3854 vm_paddr_t pa, ptepa;
3858 VM_OBJECT_ASSERT_WLOCKED(object);
3859 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3860 ("pmap_object_init_pt: non-device object"));
3862 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3863 if (!vm_object_populate(object, pindex, pindex + atop(size)))
3865 p = vm_page_lookup(object, pindex);
3866 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3867 ("pmap_object_init_pt: invalid page %p", p));
3868 pat_mode = p->md.pat_mode;
3871 * Abort the mapping if the first page is not physically
3872 * aligned to a 2/4MB page boundary.
3874 ptepa = VM_PAGE_TO_PHYS(p);
3875 if (ptepa & (NBPDR - 1))
3879 * Skip the first page. Abort the mapping if the rest of
3880 * the pages are not physically contiguous or have differing
3881 * memory attributes.
3883 p = TAILQ_NEXT(p, listq);
3884 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
3886 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3887 ("pmap_object_init_pt: invalid page %p", p));
3888 if (pa != VM_PAGE_TO_PHYS(p) ||
3889 pat_mode != p->md.pat_mode)
3891 p = TAILQ_NEXT(p, listq);
3895 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
3896 * "size" is a multiple of 2/4M, adding the PAT setting to
3897 * "pa" will not affect the termination of this loop.
3900 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
3901 size; pa += NBPDR) {
3902 pde = pmap_pde(pmap, addr);
3904 pde_store(pde, pa | PG_PS | PG_M | PG_A |
3905 PG_U | PG_RW | PG_V);
3906 pmap->pm_stats.resident_count += NBPDR /
3908 pmap_pde_mappings++;
3910 /* Else continue on if the PDE is already valid. */
3918 * Routine: pmap_change_wiring
3919 * Function: Change the wiring attribute for a map/virtual-address
3921 * In/out conditions:
3922 * The mapping must already exist in the pmap.
3925 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
3929 boolean_t are_queues_locked;
3931 are_queues_locked = FALSE;
3934 pde = pmap_pde(pmap, va);
3935 if ((*pde & PG_PS) != 0) {
3936 if (!wired != ((*pde & PG_W) == 0)) {
3937 if (!are_queues_locked) {
3938 are_queues_locked = TRUE;
3939 if (!rw_try_wlock(&pvh_global_lock)) {
3941 rw_wlock(&pvh_global_lock);
3945 if (!pmap_demote_pde(pmap, pde, va))
3946 panic("pmap_change_wiring: demotion failed");
3950 pte = pmap_pte(pmap, va);
3952 if (wired && !pmap_pte_w(pte))
3953 pmap->pm_stats.wired_count++;
3954 else if (!wired && pmap_pte_w(pte))
3955 pmap->pm_stats.wired_count--;
3958 * Wiring is not a hardware characteristic so there is no need to
3961 pmap_pte_set_w(pte, wired);
3962 pmap_pte_release(pte);
3964 if (are_queues_locked)
3965 rw_wunlock(&pvh_global_lock);
3972 * Copy the range specified by src_addr/len
3973 * from the source map to the range dst_addr/len
3974 * in the destination map.
3976 * This routine is only advisory and need not do anything.
3980 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3981 vm_offset_t src_addr)
3985 vm_offset_t end_addr = src_addr + len;
3988 if (dst_addr != src_addr)
3991 if (!pmap_is_current(src_pmap))
3994 rw_wlock(&pvh_global_lock);
3995 if (dst_pmap < src_pmap) {
3996 PMAP_LOCK(dst_pmap);
3997 PMAP_LOCK(src_pmap);
3999 PMAP_LOCK(src_pmap);
4000 PMAP_LOCK(dst_pmap);
4003 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4004 pt_entry_t *src_pte, *dst_pte;
4005 vm_page_t dstmpte, srcmpte;
4006 pd_entry_t srcptepaddr;
4009 KASSERT(addr < UPT_MIN_ADDRESS,
4010 ("pmap_copy: invalid to pmap_copy page tables"));
4012 pdnxt = (addr + NBPDR) & ~PDRMASK;
4015 ptepindex = addr >> PDRSHIFT;
4017 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4018 if (srcptepaddr == 0)
4021 if (srcptepaddr & PG_PS) {
4022 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4023 ((srcptepaddr & PG_MANAGED) == 0 ||
4024 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4026 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4028 dst_pmap->pm_stats.resident_count +=
4034 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4035 KASSERT(srcmpte->wire_count > 0,
4036 ("pmap_copy: source page table page is unused"));
4038 if (pdnxt > end_addr)
4041 src_pte = vtopte(addr);
4042 while (addr < pdnxt) {
4046 * we only virtual copy managed pages
4048 if ((ptetemp & PG_MANAGED) != 0) {
4049 dstmpte = pmap_allocpte(dst_pmap, addr,
4051 if (dstmpte == NULL)
4053 dst_pte = pmap_pte_quick(dst_pmap, addr);
4054 if (*dst_pte == 0 &&
4055 pmap_try_insert_pv_entry(dst_pmap, addr,
4056 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4058 * Clear the wired, modified, and
4059 * accessed (referenced) bits
4062 *dst_pte = ptetemp & ~(PG_W | PG_M |
4064 dst_pmap->pm_stats.resident_count++;
4067 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4069 pmap_invalidate_page(dst_pmap,
4071 pmap_free_zero_pages(free);
4075 if (dstmpte->wire_count >= srcmpte->wire_count)
4084 rw_wunlock(&pvh_global_lock);
4085 PMAP_UNLOCK(src_pmap);
4086 PMAP_UNLOCK(dst_pmap);
4089 static __inline void
4090 pagezero(void *page)
4092 #if defined(I686_CPU)
4093 if (cpu_class == CPUCLASS_686) {
4094 #if defined(CPU_ENABLE_SSE)
4095 if (cpu_feature & CPUID_SSE2)
4096 sse2_pagezero(page);
4099 i686_pagezero(page);
4102 bzero(page, PAGE_SIZE);
4106 * pmap_zero_page zeros the specified hardware page by mapping
4107 * the page into KVM and using bzero to clear its contents.
4110 pmap_zero_page(vm_page_t m)
4112 struct sysmaps *sysmaps;
4114 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4115 mtx_lock(&sysmaps->lock);
4116 if (*sysmaps->CMAP2)
4117 panic("pmap_zero_page: CMAP2 busy");
4119 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4120 pmap_cache_bits(m->md.pat_mode, 0);
4121 invlcaddr(sysmaps->CADDR2);
4122 pagezero(sysmaps->CADDR2);
4123 *sysmaps->CMAP2 = 0;
4125 mtx_unlock(&sysmaps->lock);
4129 * pmap_zero_page_area zeros the specified hardware page by mapping
4130 * the page into KVM and using bzero to clear its contents.
4132 * off and size may not cover an area beyond a single hardware page.
4135 pmap_zero_page_area(vm_page_t m, int off, int size)
4137 struct sysmaps *sysmaps;
4139 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4140 mtx_lock(&sysmaps->lock);
4141 if (*sysmaps->CMAP2)
4142 panic("pmap_zero_page_area: CMAP2 busy");
4144 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4145 pmap_cache_bits(m->md.pat_mode, 0);
4146 invlcaddr(sysmaps->CADDR2);
4147 if (off == 0 && size == PAGE_SIZE)
4148 pagezero(sysmaps->CADDR2);
4150 bzero((char *)sysmaps->CADDR2 + off, size);
4151 *sysmaps->CMAP2 = 0;
4153 mtx_unlock(&sysmaps->lock);
4157 * pmap_zero_page_idle zeros the specified hardware page by mapping
4158 * the page into KVM and using bzero to clear its contents. This
4159 * is intended to be called from the vm_pagezero process only and
4163 pmap_zero_page_idle(vm_page_t m)
4167 panic("pmap_zero_page_idle: CMAP3 busy");
4169 *CMAP3 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4170 pmap_cache_bits(m->md.pat_mode, 0);
4178 * pmap_copy_page copies the specified (machine independent)
4179 * page by mapping the page into virtual memory and using
4180 * bcopy to copy the page, one machine dependent page at a
4184 pmap_copy_page(vm_page_t src, vm_page_t dst)
4186 struct sysmaps *sysmaps;
4188 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4189 mtx_lock(&sysmaps->lock);
4190 if (*sysmaps->CMAP1)
4191 panic("pmap_copy_page: CMAP1 busy");
4192 if (*sysmaps->CMAP2)
4193 panic("pmap_copy_page: CMAP2 busy");
4195 invlpg((u_int)sysmaps->CADDR1);
4196 invlpg((u_int)sysmaps->CADDR2);
4197 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4198 pmap_cache_bits(src->md.pat_mode, 0);
4199 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4200 pmap_cache_bits(dst->md.pat_mode, 0);
4201 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE);
4202 *sysmaps->CMAP1 = 0;
4203 *sysmaps->CMAP2 = 0;
4205 mtx_unlock(&sysmaps->lock);
4209 * Returns true if the pmap's pv is one of the first
4210 * 16 pvs linked to from this page. This count may
4211 * be changed upwards or downwards in the future; it
4212 * is only necessary that true be returned for a small
4213 * subset of pmaps for proper page aging.
4216 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4218 struct md_page *pvh;
4223 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4224 ("pmap_page_exists_quick: page %p is not managed", m));
4226 rw_wlock(&pvh_global_lock);
4227 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4228 if (PV_PMAP(pv) == pmap) {
4236 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4237 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4238 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4239 if (PV_PMAP(pv) == pmap) {
4248 rw_wunlock(&pvh_global_lock);
4253 * pmap_page_wired_mappings:
4255 * Return the number of managed mappings to the given physical page
4259 pmap_page_wired_mappings(vm_page_t m)
4264 if ((m->oflags & VPO_UNMANAGED) != 0)
4266 rw_wlock(&pvh_global_lock);
4267 count = pmap_pvh_wired_mappings(&m->md, count);
4268 if ((m->flags & PG_FICTITIOUS) == 0) {
4269 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4272 rw_wunlock(&pvh_global_lock);
4277 * pmap_pvh_wired_mappings:
4279 * Return the updated number "count" of managed mappings that are wired.
4282 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4288 rw_assert(&pvh_global_lock, RA_WLOCKED);
4290 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4293 pte = pmap_pte_quick(pmap, pv->pv_va);
4294 if ((*pte & PG_W) != 0)
4303 * Returns TRUE if the given page is mapped individually or as part of
4304 * a 4mpage. Otherwise, returns FALSE.
4307 pmap_page_is_mapped(vm_page_t m)
4311 if ((m->oflags & VPO_UNMANAGED) != 0)
4313 rw_wlock(&pvh_global_lock);
4314 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4315 ((m->flags & PG_FICTITIOUS) == 0 &&
4316 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4317 rw_wunlock(&pvh_global_lock);
4322 * Remove all pages from specified address space
4323 * this aids process exit speeds. Also, this code
4324 * is special cased for current process only, but
4325 * can have the more generic (and slightly slower)
4326 * mode enabled. This is much faster than pmap_remove
4327 * in the case of running down an entire address space.
4330 pmap_remove_pages(pmap_t pmap)
4332 pt_entry_t *pte, tpte;
4333 vm_page_t free = NULL;
4334 vm_page_t m, mpte, mt;
4336 struct md_page *pvh;
4337 struct pv_chunk *pc, *npc;
4340 uint32_t inuse, bitmask;
4343 if (pmap != PCPU_GET(curpmap)) {
4344 printf("warning: pmap_remove_pages called with non-current pmap\n");
4347 rw_wlock(&pvh_global_lock);
4350 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4351 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4354 for (field = 0; field < _NPCM; field++) {
4355 inuse = ~pc->pc_map[field] & pc_freemask[field];
4356 while (inuse != 0) {
4358 bitmask = 1UL << bit;
4359 idx = field * 32 + bit;
4360 pv = &pc->pc_pventry[idx];
4363 pte = pmap_pde(pmap, pv->pv_va);
4365 if ((tpte & PG_PS) == 0) {
4366 pte = vtopte(pv->pv_va);
4367 tpte = *pte & ~PG_PTE_PAT;
4372 "TPTE at %p IS ZERO @ VA %08x\n",
4378 * We cannot remove wired pages from a process' mapping at this time
4385 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4386 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4387 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4388 m, (uintmax_t)m->phys_addr,
4391 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4392 m < &vm_page_array[vm_page_array_size],
4393 ("pmap_remove_pages: bad tpte %#jx",
4399 * Update the vm_page_t clean/reference bits.
4401 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4402 if ((tpte & PG_PS) != 0) {
4403 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4410 PV_STAT(pv_entry_frees++);
4411 PV_STAT(pv_entry_spare++);
4413 pc->pc_map[field] |= bitmask;
4414 if ((tpte & PG_PS) != 0) {
4415 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4416 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4417 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4418 if (TAILQ_EMPTY(&pvh->pv_list)) {
4419 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4420 if (TAILQ_EMPTY(&mt->md.pv_list))
4421 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4423 mpte = pmap_lookup_pt_page(pmap, pv->pv_va);
4425 pmap_remove_pt_page(pmap, mpte);
4426 pmap->pm_stats.resident_count--;
4427 KASSERT(mpte->wire_count == NPTEPG,
4428 ("pmap_remove_pages: pte page wire count error"));
4429 mpte->wire_count = 0;
4430 pmap_add_delayed_free_list(mpte, &free, FALSE);
4431 atomic_subtract_int(&cnt.v_wire_count, 1);
4434 pmap->pm_stats.resident_count--;
4435 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4436 if (TAILQ_EMPTY(&m->md.pv_list) &&
4437 (m->flags & PG_FICTITIOUS) == 0) {
4438 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4439 if (TAILQ_EMPTY(&pvh->pv_list))
4440 vm_page_aflag_clear(m, PGA_WRITEABLE);
4442 pmap_unuse_pt(pmap, pv->pv_va, &free);
4447 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4452 pmap_invalidate_all(pmap);
4453 rw_wunlock(&pvh_global_lock);
4455 pmap_free_zero_pages(free);
4461 * Return whether or not the specified physical page was modified
4462 * in any physical maps.
4465 pmap_is_modified(vm_page_t m)
4469 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4470 ("pmap_is_modified: page %p is not managed", m));
4473 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be
4474 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4475 * is clear, no PTEs can have PG_M set.
4477 VM_OBJECT_ASSERT_WLOCKED(m->object);
4478 if ((m->oflags & VPO_BUSY) == 0 &&
4479 (m->aflags & PGA_WRITEABLE) == 0)
4481 rw_wlock(&pvh_global_lock);
4482 rv = pmap_is_modified_pvh(&m->md) ||
4483 ((m->flags & PG_FICTITIOUS) == 0 &&
4484 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4485 rw_wunlock(&pvh_global_lock);
4490 * Returns TRUE if any of the given mappings were used to modify
4491 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4492 * mappings are supported.
4495 pmap_is_modified_pvh(struct md_page *pvh)
4502 rw_assert(&pvh_global_lock, RA_WLOCKED);
4505 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4508 pte = pmap_pte_quick(pmap, pv->pv_va);
4509 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4519 * pmap_is_prefaultable:
4521 * Return whether or not the specified virtual address is elgible
4525 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4533 pde = pmap_pde(pmap, addr);
4534 if (*pde != 0 && (*pde & PG_PS) == 0) {
4543 * pmap_is_referenced:
4545 * Return whether or not the specified physical page was referenced
4546 * in any physical maps.
4549 pmap_is_referenced(vm_page_t m)
4553 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4554 ("pmap_is_referenced: page %p is not managed", m));
4555 rw_wlock(&pvh_global_lock);
4556 rv = pmap_is_referenced_pvh(&m->md) ||
4557 ((m->flags & PG_FICTITIOUS) == 0 &&
4558 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4559 rw_wunlock(&pvh_global_lock);
4564 * Returns TRUE if any of the given mappings were referenced and FALSE
4565 * otherwise. Both page and 4mpage mappings are supported.
4568 pmap_is_referenced_pvh(struct md_page *pvh)
4575 rw_assert(&pvh_global_lock, RA_WLOCKED);
4578 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4581 pte = pmap_pte_quick(pmap, pv->pv_va);
4582 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4592 * Clear the write and modified bits in each of the given page's mappings.
4595 pmap_remove_write(vm_page_t m)
4597 struct md_page *pvh;
4598 pv_entry_t next_pv, pv;
4601 pt_entry_t oldpte, *pte;
4604 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4605 ("pmap_remove_write: page %p is not managed", m));
4608 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
4609 * another thread while the object is locked. Thus, if PGA_WRITEABLE
4610 * is clear, no page table entries need updating.
4612 VM_OBJECT_ASSERT_WLOCKED(m->object);
4613 if ((m->oflags & VPO_BUSY) == 0 &&
4614 (m->aflags & PGA_WRITEABLE) == 0)
4616 rw_wlock(&pvh_global_lock);
4618 if ((m->flags & PG_FICTITIOUS) != 0)
4619 goto small_mappings;
4620 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4621 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4625 pde = pmap_pde(pmap, va);
4626 if ((*pde & PG_RW) != 0)
4627 (void)pmap_demote_pde(pmap, pde, va);
4631 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4634 pde = pmap_pde(pmap, pv->pv_va);
4635 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
4636 " a 4mpage in page %p's pv list", m));
4637 pte = pmap_pte_quick(pmap, pv->pv_va);
4640 if ((oldpte & PG_RW) != 0) {
4642 * Regardless of whether a pte is 32 or 64 bits
4643 * in size, PG_RW and PG_M are among the least
4644 * significant 32 bits.
4646 if (!atomic_cmpset_int((u_int *)pte, oldpte,
4647 oldpte & ~(PG_RW | PG_M)))
4649 if ((oldpte & PG_M) != 0)
4651 pmap_invalidate_page(pmap, pv->pv_va);
4655 vm_page_aflag_clear(m, PGA_WRITEABLE);
4657 rw_wunlock(&pvh_global_lock);
4661 * pmap_ts_referenced:
4663 * Return a count of reference bits for a page, clearing those bits.
4664 * It is not necessary for every reference bit to be cleared, but it
4665 * is necessary that 0 only be returned when there are truly no
4666 * reference bits set.
4668 * XXX: The exact number of bits to check and clear is a matter that
4669 * should be tested and standardized at some point in the future for
4670 * optimal aging of shared pages.
4673 pmap_ts_referenced(vm_page_t m)
4675 struct md_page *pvh;
4676 pv_entry_t pv, pvf, pvn;
4678 pd_entry_t oldpde, *pde;
4683 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4684 ("pmap_ts_referenced: page %p is not managed", m));
4685 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4686 rw_wlock(&pvh_global_lock);
4688 if ((m->flags & PG_FICTITIOUS) != 0)
4689 goto small_mappings;
4690 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, pvn) {
4694 pde = pmap_pde(pmap, va);
4696 if ((oldpde & PG_A) != 0) {
4697 if (pmap_demote_pde(pmap, pde, va)) {
4698 if ((oldpde & PG_W) == 0) {
4700 * Remove the mapping to a single page
4701 * so that a subsequent access may
4702 * repromote. Since the underlying
4703 * page table page is fully populated,
4704 * this removal never frees a page
4707 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4709 pmap_remove_page(pmap, va, NULL);
4721 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4724 pvn = TAILQ_NEXT(pv, pv_next);
4725 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4726 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4729 pde = pmap_pde(pmap, pv->pv_va);
4730 KASSERT((*pde & PG_PS) == 0, ("pmap_ts_referenced:"
4731 " found a 4mpage in page %p's pv list", m));
4732 pte = pmap_pte_quick(pmap, pv->pv_va);
4733 if ((*pte & PG_A) != 0) {
4734 atomic_clear_int((u_int *)pte, PG_A);
4735 pmap_invalidate_page(pmap, pv->pv_va);
4741 } while ((pv = pvn) != NULL && pv != pvf);
4745 rw_wunlock(&pvh_global_lock);
4750 * Clear the modify bits on the specified physical page.
4753 pmap_clear_modify(vm_page_t m)
4755 struct md_page *pvh;
4756 pv_entry_t next_pv, pv;
4758 pd_entry_t oldpde, *pde;
4759 pt_entry_t oldpte, *pte;
4762 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4763 ("pmap_clear_modify: page %p is not managed", m));
4764 VM_OBJECT_ASSERT_WLOCKED(m->object);
4765 KASSERT((m->oflags & VPO_BUSY) == 0,
4766 ("pmap_clear_modify: page %p is busy", m));
4769 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
4770 * If the object containing the page is locked and the page is not
4771 * VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set.
4773 if ((m->aflags & PGA_WRITEABLE) == 0)
4775 rw_wlock(&pvh_global_lock);
4777 if ((m->flags & PG_FICTITIOUS) != 0)
4778 goto small_mappings;
4779 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4780 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4784 pde = pmap_pde(pmap, va);
4786 if ((oldpde & PG_RW) != 0) {
4787 if (pmap_demote_pde(pmap, pde, va)) {
4788 if ((oldpde & PG_W) == 0) {
4790 * Write protect the mapping to a
4791 * single page so that a subsequent
4792 * write access may repromote.
4794 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4796 pte = pmap_pte_quick(pmap, va);
4798 if ((oldpte & PG_V) != 0) {
4800 * Regardless of whether a pte is 32 or 64 bits
4801 * in size, PG_RW and PG_M are among the least
4802 * significant 32 bits.
4804 while (!atomic_cmpset_int((u_int *)pte,
4806 oldpte & ~(PG_M | PG_RW)))
4809 pmap_invalidate_page(pmap, va);
4817 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4820 pde = pmap_pde(pmap, pv->pv_va);
4821 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
4822 " a 4mpage in page %p's pv list", m));
4823 pte = pmap_pte_quick(pmap, pv->pv_va);
4824 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4826 * Regardless of whether a pte is 32 or 64 bits
4827 * in size, PG_M is among the least significant
4830 atomic_clear_int((u_int *)pte, PG_M);
4831 pmap_invalidate_page(pmap, pv->pv_va);
4836 rw_wunlock(&pvh_global_lock);
4840 * pmap_clear_reference:
4842 * Clear the reference bit on the specified physical page.
4845 pmap_clear_reference(vm_page_t m)
4847 struct md_page *pvh;
4848 pv_entry_t next_pv, pv;
4850 pd_entry_t oldpde, *pde;
4854 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4855 ("pmap_clear_reference: page %p is not managed", m));
4856 rw_wlock(&pvh_global_lock);
4858 if ((m->flags & PG_FICTITIOUS) != 0)
4859 goto small_mappings;
4860 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4861 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4865 pde = pmap_pde(pmap, va);
4867 if ((oldpde & PG_A) != 0) {
4868 if (pmap_demote_pde(pmap, pde, va)) {
4870 * Remove the mapping to a single page so
4871 * that a subsequent access may repromote.
4872 * Since the underlying page table page is
4873 * fully populated, this removal never frees
4874 * a page table page.
4876 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4878 pmap_remove_page(pmap, va, NULL);
4884 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4887 pde = pmap_pde(pmap, pv->pv_va);
4888 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_reference: found"
4889 " a 4mpage in page %p's pv list", m));
4890 pte = pmap_pte_quick(pmap, pv->pv_va);
4891 if ((*pte & PG_A) != 0) {
4893 * Regardless of whether a pte is 32 or 64 bits
4894 * in size, PG_A is among the least significant
4897 atomic_clear_int((u_int *)pte, PG_A);
4898 pmap_invalidate_page(pmap, pv->pv_va);
4903 rw_wunlock(&pvh_global_lock);
4907 * Miscellaneous support routines follow
4910 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
4911 static __inline void
4912 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
4917 * The cache mode bits are all in the low 32-bits of the
4918 * PTE, so we can just spin on updating the low 32-bits.
4921 opte = *(u_int *)pte;
4922 npte = opte & ~PG_PTE_CACHE;
4924 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
4927 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
4928 static __inline void
4929 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
4934 * The cache mode bits are all in the low 32-bits of the
4935 * PDE, so we can just spin on updating the low 32-bits.
4938 opde = *(u_int *)pde;
4939 npde = opde & ~PG_PDE_CACHE;
4941 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
4945 * Map a set of physical memory pages into the kernel virtual
4946 * address space. Return a pointer to where it is mapped. This
4947 * routine is intended to be used for mapping device memory,
4951 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
4953 vm_offset_t va, offset;
4956 offset = pa & PAGE_MASK;
4957 size = round_page(offset + size);
4960 if (pa < KERNLOAD && pa + size <= KERNLOAD)
4963 va = kmem_alloc_nofault(kernel_map, size);
4965 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
4967 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
4968 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
4969 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
4970 pmap_invalidate_cache_range(va, va + size);
4971 return ((void *)(va + offset));
4975 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
4978 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
4982 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
4985 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
4989 pmap_unmapdev(vm_offset_t va, vm_size_t size)
4991 vm_offset_t base, offset;
4993 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD)
4995 base = trunc_page(va);
4996 offset = va & PAGE_MASK;
4997 size = round_page(offset + size);
4998 kmem_free(kernel_map, base, size);
5002 * Sets the memory attribute for the specified page.
5005 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5008 m->md.pat_mode = ma;
5009 if ((m->flags & PG_FICTITIOUS) != 0)
5013 * If "m" is a normal page, flush it from the cache.
5014 * See pmap_invalidate_cache_range().
5016 * First, try to find an existing mapping of the page by sf
5017 * buffer. sf_buf_invalidate_cache() modifies mapping and
5018 * flushes the cache.
5020 if (sf_buf_invalidate_cache(m))
5024 * If page is not mapped by sf buffer, but CPU does not
5025 * support self snoop, map the page transient and do
5026 * invalidation. In the worst case, whole cache is flushed by
5027 * pmap_invalidate_cache_range().
5029 if ((cpu_feature & CPUID_SS) == 0)
5034 pmap_flush_page(vm_page_t m)
5036 struct sysmaps *sysmaps;
5037 vm_offset_t sva, eva;
5039 if ((cpu_feature & CPUID_CLFSH) != 0) {
5040 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
5041 mtx_lock(&sysmaps->lock);
5042 if (*sysmaps->CMAP2)
5043 panic("pmap_flush_page: CMAP2 busy");
5045 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5046 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0);
5047 invlcaddr(sysmaps->CADDR2);
5048 sva = (vm_offset_t)sysmaps->CADDR2;
5049 eva = sva + PAGE_SIZE;
5052 * Use mfence despite the ordering implied by
5053 * mtx_{un,}lock() because clflush is not guaranteed
5054 * to be ordered by any other instruction.
5057 for (; sva < eva; sva += cpu_clflush_line_size)
5060 *sysmaps->CMAP2 = 0;
5062 mtx_unlock(&sysmaps->lock);
5064 pmap_invalidate_cache();
5068 * Changes the specified virtual address range's memory type to that given by
5069 * the parameter "mode". The specified virtual address range must be
5070 * completely contained within either the kernel map.
5072 * Returns zero if the change completed successfully, and either EINVAL or
5073 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5074 * of the virtual address range was not mapped, and ENOMEM is returned if
5075 * there was insufficient memory available to complete the change.
5078 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5080 vm_offset_t base, offset, tmpva;
5083 int cache_bits_pte, cache_bits_pde;
5086 base = trunc_page(va);
5087 offset = va & PAGE_MASK;
5088 size = round_page(offset + size);
5091 * Only supported on kernel virtual addresses above the recursive map.
5093 if (base < VM_MIN_KERNEL_ADDRESS)
5096 cache_bits_pde = pmap_cache_bits(mode, 1);
5097 cache_bits_pte = pmap_cache_bits(mode, 0);
5101 * Pages that aren't mapped aren't supported. Also break down
5102 * 2/4MB pages into 4KB pages if required.
5104 PMAP_LOCK(kernel_pmap);
5105 for (tmpva = base; tmpva < base + size; ) {
5106 pde = pmap_pde(kernel_pmap, tmpva);
5108 PMAP_UNLOCK(kernel_pmap);
5113 * If the current 2/4MB page already has
5114 * the required memory type, then we need not
5115 * demote this page. Just increment tmpva to
5116 * the next 2/4MB page frame.
5118 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5119 tmpva = trunc_4mpage(tmpva) + NBPDR;
5124 * If the current offset aligns with a 2/4MB
5125 * page frame and there is at least 2/4MB left
5126 * within the range, then we need not break
5127 * down this page into 4KB pages.
5129 if ((tmpva & PDRMASK) == 0 &&
5130 tmpva + PDRMASK < base + size) {
5134 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5135 PMAP_UNLOCK(kernel_pmap);
5139 pte = vtopte(tmpva);
5141 PMAP_UNLOCK(kernel_pmap);
5146 PMAP_UNLOCK(kernel_pmap);
5149 * Ok, all the pages exist, so run through them updating their
5150 * cache mode if required.
5152 for (tmpva = base; tmpva < base + size; ) {
5153 pde = pmap_pde(kernel_pmap, tmpva);
5155 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5156 pmap_pde_attr(pde, cache_bits_pde);
5159 tmpva = trunc_4mpage(tmpva) + NBPDR;
5161 pte = vtopte(tmpva);
5162 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5163 pmap_pte_attr(pte, cache_bits_pte);
5171 * Flush CPU caches to make sure any data isn't cached that
5172 * shouldn't be, etc.
5175 pmap_invalidate_range(kernel_pmap, base, tmpva);
5176 pmap_invalidate_cache_range(base, tmpva);
5182 * perform the pmap work for mincore
5185 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5188 pt_entry_t *ptep, pte;
5194 pdep = pmap_pde(pmap, addr);
5196 if (*pdep & PG_PS) {
5198 /* Compute the physical address of the 4KB page. */
5199 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5201 val = MINCORE_SUPER;
5203 ptep = pmap_pte(pmap, addr);
5205 pmap_pte_release(ptep);
5206 pa = pte & PG_FRAME;
5214 if ((pte & PG_V) != 0) {
5215 val |= MINCORE_INCORE;
5216 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5217 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5218 if ((pte & PG_A) != 0)
5219 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5221 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5222 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5223 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5224 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5225 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5228 PA_UNLOCK_COND(*locked_pa);
5234 pmap_activate(struct thread *td)
5236 pmap_t pmap, oldpmap;
5241 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5242 oldpmap = PCPU_GET(curpmap);
5243 cpuid = PCPU_GET(cpuid);
5245 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5246 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5248 CPU_CLR(cpuid, &oldpmap->pm_active);
5249 CPU_SET(cpuid, &pmap->pm_active);
5252 cr3 = vtophys(pmap->pm_pdpt);
5254 cr3 = vtophys(pmap->pm_pdir);
5257 * pmap_activate is for the current thread on the current cpu
5259 td->td_pcb->pcb_cr3 = cr3;
5261 PCPU_SET(curpmap, pmap);
5266 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5271 * Increase the starting virtual address of the given mapping if a
5272 * different alignment might result in more superpage mappings.
5275 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5276 vm_offset_t *addr, vm_size_t size)
5278 vm_offset_t superpage_offset;
5282 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5283 offset += ptoa(object->pg_color);
5284 superpage_offset = offset & PDRMASK;
5285 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5286 (*addr & PDRMASK) == superpage_offset)
5288 if ((*addr & PDRMASK) < superpage_offset)
5289 *addr = (*addr & ~PDRMASK) + superpage_offset;
5291 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5295 #if defined(PMAP_DEBUG)
5296 pmap_pid_dump(int pid)
5303 sx_slock(&allproc_lock);
5304 FOREACH_PROC_IN_SYSTEM(p) {
5305 if (p->p_pid != pid)
5311 pmap = vmspace_pmap(p->p_vmspace);
5312 for (i = 0; i < NPDEPTD; i++) {
5315 vm_offset_t base = i << PDRSHIFT;
5317 pde = &pmap->pm_pdir[i];
5318 if (pde && pmap_pde_v(pde)) {
5319 for (j = 0; j < NPTEPG; j++) {
5320 vm_offset_t va = base + (j << PAGE_SHIFT);
5321 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5326 sx_sunlock(&allproc_lock);
5329 pte = pmap_pte(pmap, va);
5330 if (pte && pmap_pte_v(pte)) {
5334 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5335 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5336 va, pa, m->hold_count, m->wire_count, m->flags);
5351 sx_sunlock(&allproc_lock);
5358 static void pads(pmap_t pm);
5359 void pmap_pvdump(vm_paddr_t pa);
5361 /* print address space of pmap*/
5369 if (pm == kernel_pmap)
5371 for (i = 0; i < NPDEPTD; i++)
5373 for (j = 0; j < NPTEPG; j++) {
5374 va = (i << PDRSHIFT) + (j << PAGE_SHIFT);
5375 if (pm == kernel_pmap && va < KERNBASE)
5377 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS)
5379 ptep = pmap_pte(pm, va);
5380 if (pmap_pte_v(ptep))
5381 printf("%x:%x ", va, *ptep);
5387 pmap_pvdump(vm_paddr_t pa)
5393 printf("pa %x", pa);
5394 m = PHYS_TO_VM_PAGE(pa);
5395 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5397 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va);