2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
50 * Copyright (c) 2018 The FreeBSD Foundation
51 * All rights reserved.
53 * This software was developed for the FreeBSD Project by Jake Burkholder,
54 * Safeport Network Services, and Network Associates Laboratories, the
55 * Security Research Division of Network Associates, Inc. under
56 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
57 * CHATS research program.
59 * Portions of this software were developed by
60 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
61 * the FreeBSD Foundation.
63 * Redistribution and use in source and binary forms, with or without
64 * modification, are permitted provided that the following conditions
66 * 1. Redistributions of source code must retain the above copyright
67 * notice, this list of conditions and the following disclaimer.
68 * 2. Redistributions in binary form must reproduce the above copyright
69 * notice, this list of conditions and the following disclaimer in the
70 * documentation and/or other materials provided with the distribution.
72 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
73 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
75 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
78 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
79 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
80 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
81 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
85 #include <sys/cdefs.h>
86 __FBSDID("$FreeBSD$");
89 * Manages physical address maps.
91 * Since the information managed by this module is
92 * also stored by the logical address mapping module,
93 * this module may throw away valid virtual-to-physical
94 * mappings at almost any time. However, invalidations
95 * of virtual-to-physical mappings must be done as
98 * In order to cope with hardware architectures which
99 * make virtual-to-physical map invalidates expensive,
100 * this module may delay invalidate or reduced protection
101 * operations until such time as they are actually
102 * necessary. This module is given full information as
103 * to which processors are currently using which maps,
104 * and to when physical maps must be made correct.
107 #include "opt_apic.h"
109 #include "opt_pmap.h"
113 #include <sys/param.h>
114 #include <sys/systm.h>
115 #include <sys/kernel.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/proc.h>
123 #include <sys/rwlock.h>
124 #include <sys/sf_buf.h>
126 #include <sys/vmmeter.h>
127 #include <sys/sched.h>
128 #include <sys/sysctl.h>
130 #include <sys/vmem.h>
133 #include <vm/vm_param.h>
134 #include <vm/vm_kern.h>
135 #include <vm/vm_page.h>
136 #include <vm/vm_map.h>
137 #include <vm/vm_object.h>
138 #include <vm/vm_extern.h>
139 #include <vm/vm_pageout.h>
140 #include <vm/vm_pager.h>
141 #include <vm/vm_phys.h>
142 #include <vm/vm_radix.h>
143 #include <vm/vm_reserv.h>
148 #include <machine/intr_machdep.h>
149 #include <x86/apicvar.h>
151 #include <machine/bootinfo.h>
152 #include <machine/cpu.h>
153 #include <machine/cputypes.h>
154 #include <machine/md_var.h>
155 #include <machine/pcb.h>
156 #include <machine/specialreg.h>
158 #include <machine/smp.h>
161 #ifndef PMAP_SHPGPERPROC
162 #define PMAP_SHPGPERPROC 200
165 #if !defined(DIAGNOSTIC)
166 #ifdef __GNUC_GNU_INLINE__
167 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
169 #define PMAP_INLINE extern inline
176 #define PV_STAT(x) do { x ; } while (0)
178 #define PV_STAT(x) do { } while (0)
181 #define pa_index(pa) ((pa) >> PDRSHIFT)
182 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
185 * Get PDEs and PTEs for user/kernel address space
187 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
188 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
190 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
191 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
192 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
193 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
194 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
196 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
197 atomic_clear_int((u_int *)(pte), PG_W))
198 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
200 struct pmap kernel_pmap_store;
202 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
203 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
204 int pgeflag = 0; /* PG_G or-in */
205 int pseflag = 0; /* PG_PS or-in */
207 static int nkpt = NKPT;
208 vm_offset_t kernel_vm_end = /* 0 + */ NKPT * NBPDR;
210 #if defined(PAE) || defined(PAE_TABLES)
212 static uma_zone_t pdptzone;
215 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
217 static int pat_works = 1;
218 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
219 "Is page attribute table fully functional?");
221 static int pg_ps_enabled = 1;
222 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
223 &pg_ps_enabled, 0, "Are large page mappings enabled?");
225 #define PAT_INDEX_SIZE 8
226 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
229 * pmap_mapdev support pre initialization (i.e. console)
231 #define PMAP_PREINIT_MAPPING_COUNT 8
232 static struct pmap_preinit_mapping {
237 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
238 static int pmap_initialized;
240 static struct rwlock_padalign pvh_global_lock;
243 * Data for the pv entry allocation mechanism
245 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
246 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
247 static struct md_page *pv_table;
248 static int shpgperproc = PMAP_SHPGPERPROC;
250 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
251 int pv_maxchunks; /* How many chunks we have KVA for */
252 vm_offset_t pv_vafree; /* freelist stored in the PTE */
255 * All those kernel PT submaps that BSD is so fond of
258 static pd_entry_t *KPTD;
265 static caddr_t crashdumpmap;
267 static pt_entry_t *PMAP1 = NULL, *PMAP2, *PMAP3;
268 static pt_entry_t *PADDR1 = NULL, *PADDR2, *PADDR3;
270 static int PMAP1cpu, PMAP3cpu;
271 static int PMAP1changedcpu;
272 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
274 "Number of times pmap_pte_quick changed CPU with same PMAP1");
276 static int PMAP1changed;
277 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
279 "Number of times pmap_pte_quick changed PMAP1");
280 static int PMAP1unchanged;
281 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
283 "Number of times pmap_pte_quick didn't change PMAP1");
284 static struct mtx PMAP2mutex;
288 static void free_pv_chunk(struct pv_chunk *pc);
289 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
290 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
291 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
292 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
293 #if VM_NRESERVLEVEL > 0
294 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
296 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
297 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
299 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
301 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
302 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
304 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
305 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
306 static void pmap_flush_page(vm_page_t m);
307 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
308 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
310 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
311 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
312 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
313 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
314 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
315 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
316 #if VM_NRESERVLEVEL > 0
317 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
319 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
321 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
322 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
323 struct spglist *free);
324 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
325 struct spglist *free);
326 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
327 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
328 struct spglist *free);
329 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
331 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
332 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
334 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
336 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
338 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
340 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
341 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
342 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
343 static void pmap_pte_release(pt_entry_t *pte);
344 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
345 #if defined(PAE) || defined(PAE_TABLES)
346 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain,
347 uint8_t *flags, int wait);
349 static void pmap_init_trm(void);
351 static __inline void pagezero(void *page);
353 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
354 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
356 void pmap_cold(void);
358 u_long physfree; /* phys addr of next free page */
359 u_long vm86phystk; /* PA of vm86/bios stack */
360 u_long vm86paddr; /* address of vm86 region */
361 int vm86pa; /* phys addr of vm86 region */
362 u_long KERNend; /* phys addr end of kernel (just after bss) */
363 pd_entry_t *IdlePTD; /* phys addr of kernel PTD */
364 #if defined(PAE) || defined(PAE_TABLES)
365 pdpt_entry_t *IdlePDPT; /* phys addr of kernel PDPT */
367 pt_entry_t *KPTmap; /* address of kernel page tables */
368 u_long KPTphys; /* phys addr of kernel page tables */
369 extern u_long tramp_idleptd;
372 allocpages(u_int cnt, u_long *physfree)
377 *physfree += PAGE_SIZE * cnt;
378 bzero((void *)res, PAGE_SIZE * cnt);
383 pmap_cold_map(u_long pa, u_long va, u_long cnt)
387 for (pt = (pt_entry_t *)KPTphys + atop(va); cnt > 0;
388 cnt--, pt++, va += PAGE_SIZE, pa += PAGE_SIZE)
389 *pt = pa | PG_V | PG_RW | PG_A | PG_M;
393 pmap_cold_mapident(u_long pa, u_long cnt)
396 pmap_cold_map(pa, pa, cnt);
399 _Static_assert(2 * NBPDR == KERNBASE, "Broken double-map of zero PTD");
402 * Called from locore.s before paging is enabled. Sets up the first
403 * kernel page table. Since kernel is mapped with PA == VA, this code
404 * does not require relocations.
413 physfree = (u_long)&_end;
414 if (bootinfo.bi_esymtab != 0)
415 physfree = bootinfo.bi_esymtab;
416 if (bootinfo.bi_kernend != 0)
417 physfree = bootinfo.bi_kernend;
418 physfree = roundup2(physfree, NBPDR);
421 /* Allocate Kernel Page Tables */
422 KPTphys = allocpages(NKPT, &physfree);
423 KPTmap = (pt_entry_t *)KPTphys;
425 /* Allocate Page Table Directory */
426 #if defined(PAE) || defined(PAE_TABLES)
427 /* XXX only need 32 bytes (easier for now) */
428 IdlePDPT = (pdpt_entry_t *)allocpages(1, &physfree);
430 IdlePTD = (pd_entry_t *)allocpages(NPGPTD, &physfree);
433 * Allocate KSTACK. Leave a guard page between IdlePTD and
434 * proc0kstack, to control stack overflow for thread0 and
435 * prevent corruption of the page table. We leak the guard
436 * physical memory due to 1:1 mappings.
438 allocpages(1, &physfree);
439 proc0kstack = allocpages(TD0_KSTACK_PAGES, &physfree);
441 /* vm86/bios stack */
442 vm86phystk = allocpages(1, &physfree);
444 /* pgtable + ext + IOPAGES */
445 vm86paddr = vm86pa = allocpages(3, &physfree);
447 /* Install page tables into PTD. Page table page 1 is wasted. */
448 for (a = 0; a < NKPT; a++)
449 IdlePTD[a] = (KPTphys + ptoa(a)) | PG_V | PG_RW | PG_A | PG_M;
451 #if defined(PAE) || defined(PAE_TABLES)
452 /* PAE install PTD pointers into PDPT */
453 for (a = 0; a < NPGPTD; a++)
454 IdlePDPT[a] = ((u_int)IdlePTD + ptoa(a)) | PG_V;
458 * Install recursive mapping for kernel page tables into
461 for (a = 0; a < NPGPTD; a++)
462 IdlePTD[PTDPTDI + a] = ((u_int)IdlePTD + ptoa(a)) | PG_V |
466 * Initialize page table pages mapping physical address zero
467 * through the (physical) end of the kernel. Many of these
468 * pages must be reserved, and we reserve them all and map
469 * them linearly for convenience. We do this even if we've
470 * enabled PSE above; we'll just switch the corresponding
471 * kernel PDEs before we turn on paging.
473 * This and all other page table entries allow read and write
474 * access for various reasons. Kernel mappings never have any
475 * access restrictions.
477 pmap_cold_mapident(0, atop(NBPDR));
478 pmap_cold_map(0, NBPDR, atop(NBPDR));
479 pmap_cold_mapident(KERNBASE, atop(KERNend - KERNBASE));
481 /* Map page table directory */
482 #if defined(PAE) || defined(PAE_TABLES)
483 pmap_cold_mapident((u_long)IdlePDPT, 1);
485 pmap_cold_mapident((u_long)IdlePTD, NPGPTD);
487 /* Map early KPTmap. It is really pmap_cold_mapident. */
488 pmap_cold_map(KPTphys, (u_long)KPTmap, NKPT);
490 /* Map proc0kstack */
491 pmap_cold_mapident(proc0kstack, TD0_KSTACK_PAGES);
492 /* ISA hole already mapped */
494 pmap_cold_mapident(vm86phystk, 1);
495 pmap_cold_mapident(vm86pa, 3);
497 /* Map page 0 into the vm86 page table */
498 *(pt_entry_t *)vm86pa = 0 | PG_RW | PG_U | PG_A | PG_M | PG_V;
500 /* ...likewise for the ISA hole for vm86 */
501 for (pt = (pt_entry_t *)vm86pa + atop(ISA_HOLE_START), a = 0;
502 a < atop(ISA_HOLE_LENGTH); a++, pt++)
503 *pt = (ISA_HOLE_START + ptoa(a)) | PG_RW | PG_U | PG_A |
506 /* Enable PSE, PGE, VME, and PAE if configured. */
508 if ((cpu_feature & CPUID_PSE) != 0) {
511 * Superpage mapping of the kernel text. Existing 4k
512 * page table pages are wasted.
514 for (a = KERNBASE; a < KERNend; a += NBPDR)
515 IdlePTD[a >> PDRSHIFT] = a | PG_PS | PG_A | PG_M |
518 if ((cpu_feature & CPUID_PGE) != 0) {
522 ncr4 |= (cpu_feature & CPUID_VME) != 0 ? CR4_VME : 0;
523 #if defined(PAE) || defined(PAE_TABLES)
527 load_cr4(rcr4() | ncr4);
529 /* Now enable paging */
530 #if defined(PAE) || defined(PAE_TABLES)
531 cr3 = (u_int)IdlePDPT;
533 cr3 = (u_int)IdlePTD;
537 load_cr0(rcr0() | CR0_PG);
540 * Now running relocated at KERNBASE where the system is
545 * Remove the lowest part of the double mapping of low memory
546 * to get some null pointer checks.
549 load_cr3(cr3); /* invalidate TLB */
553 * Bootstrap the system enough to run with virtual memory.
555 * On the i386 this is called after mapping has already been enabled
556 * in locore.s with the page table created in pmap_cold(),
557 * and just syncs the pmap module with what has already been done.
560 pmap_bootstrap(vm_paddr_t firstaddr)
563 pt_entry_t *pte, *unused;
568 * Add a physical memory segment (vm_phys_seg) corresponding to the
569 * preallocated kernel page table pages so that vm_page structures
570 * representing these pages will be created. The vm_page structures
571 * are required for promotion of the corresponding kernel virtual
572 * addresses to superpage mappings.
574 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
577 * Initialize the first available kernel virtual address. However,
578 * using "firstaddr" may waste a few pages of the kernel virtual
579 * address space, because locore may not have mapped every physical
580 * page that it allocated. Preferably, locore would provide a first
581 * unused virtual address in addition to "firstaddr".
583 virtual_avail = (vm_offset_t)firstaddr;
585 virtual_end = VM_MAX_KERNEL_ADDRESS;
588 * Initialize the kernel pmap (which is statically allocated).
590 PMAP_LOCK_INIT(kernel_pmap);
591 kernel_pmap->pm_pdir = IdlePTD;
592 #if defined(PAE) || defined(PAE_TABLES)
593 kernel_pmap->pm_pdpt = IdlePDPT;
595 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
596 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
599 * Initialize the global pv list lock.
601 rw_init(&pvh_global_lock, "pmap pv global");
604 * Reserve some special page table entries/VA space for temporary
607 #define SYSMAP(c, p, v, n) \
608 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
615 * Initialize temporary map objects on the current CPU for use
617 * CMAP1/CMAP2 are used for zeroing and copying pages.
618 * CMAP3 is used for the boot-time memory test.
621 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
622 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1)
623 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1)
624 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1)
626 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
631 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
634 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
636 SYSMAP(caddr_t, unused, ptvmmap, 1)
639 * msgbufp is used to map the system message buffer.
641 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
644 * KPTmap is used by pmap_kextract().
646 * KPTmap is first initialized by locore. However, that initial
647 * KPTmap can only support NKPT page table pages. Here, a larger
648 * KPTmap is created that can support KVA_PAGES page table pages.
650 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
652 for (i = 0; i < NKPT; i++)
653 KPTD[i] = (KPTphys + ptoa(i)) | PG_RW | PG_V;
656 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
659 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
660 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
661 SYSMAP(pt_entry_t *, PMAP3, PADDR3, 1)
663 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
668 * Initialize the PAT MSR if present.
669 * pmap_init_pat() clears and sets CR4_PGE, which, as a
670 * side-effect, invalidates stale PG_G TLB entries that might
671 * have been created in our pre-boot environment. We assume
672 * that PAT support implies PGE and in reverse, PGE presence
673 * comes with PAT. Both features were added for Pentium Pro.
679 pmap_init_reserved_pages(void)
687 mtx_init(&pc->pc_copyout_mlock, "cpmlk", NULL, MTX_DEF |
689 pc->pc_copyout_maddr = kva_alloc(ptoa(2));
690 if (pc->pc_copyout_maddr == 0)
691 panic("unable to allocate non-sleepable copyout KVA");
692 sx_init(&pc->pc_copyout_slock, "cpslk");
693 pc->pc_copyout_saddr = kva_alloc(ptoa(2));
694 if (pc->pc_copyout_saddr == 0)
695 panic("unable to allocate sleepable copyout KVA");
696 pc->pc_pmap_eh_va = kva_alloc(ptoa(1));
697 if (pc->pc_pmap_eh_va == 0)
698 panic("unable to allocate pmap_extract_and_hold KVA");
699 pc->pc_pmap_eh_ptep = (char *)vtopte(pc->pc_pmap_eh_va);
702 * Skip if the mappings have already been initialized,
703 * i.e. this is the BSP.
705 if (pc->pc_cmap_addr1 != 0)
708 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
709 pages = kva_alloc(PAGE_SIZE * 3);
711 panic("unable to allocate CMAP KVA");
712 pc->pc_cmap_pte1 = vtopte(pages);
713 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE);
714 pc->pc_cmap_addr1 = (caddr_t)pages;
715 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE);
716 pc->pc_qmap_addr = pages + atop(2);
720 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
728 int pat_table[PAT_INDEX_SIZE];
733 /* Set default PAT index table. */
734 for (i = 0; i < PAT_INDEX_SIZE; i++)
736 pat_table[PAT_WRITE_BACK] = 0;
737 pat_table[PAT_WRITE_THROUGH] = 1;
738 pat_table[PAT_UNCACHEABLE] = 3;
739 pat_table[PAT_WRITE_COMBINING] = 3;
740 pat_table[PAT_WRITE_PROTECTED] = 3;
741 pat_table[PAT_UNCACHED] = 3;
744 * Bail if this CPU doesn't implement PAT.
745 * We assume that PAT support implies PGE.
747 if ((cpu_feature & CPUID_PAT) == 0) {
748 for (i = 0; i < PAT_INDEX_SIZE; i++)
749 pat_index[i] = pat_table[i];
755 * Due to some Intel errata, we can only safely use the lower 4
758 * Intel Pentium III Processor Specification Update
759 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
762 * Intel Pentium IV Processor Specification Update
763 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
765 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
766 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
769 /* Initialize default PAT entries. */
770 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
771 PAT_VALUE(1, PAT_WRITE_THROUGH) |
772 PAT_VALUE(2, PAT_UNCACHED) |
773 PAT_VALUE(3, PAT_UNCACHEABLE) |
774 PAT_VALUE(4, PAT_WRITE_BACK) |
775 PAT_VALUE(5, PAT_WRITE_THROUGH) |
776 PAT_VALUE(6, PAT_UNCACHED) |
777 PAT_VALUE(7, PAT_UNCACHEABLE);
781 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
782 * Program 5 and 6 as WP and WC.
783 * Leave 4 and 7 as WB and UC.
785 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
786 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
787 PAT_VALUE(6, PAT_WRITE_COMBINING);
788 pat_table[PAT_UNCACHED] = 2;
789 pat_table[PAT_WRITE_PROTECTED] = 5;
790 pat_table[PAT_WRITE_COMBINING] = 6;
793 * Just replace PAT Index 2 with WC instead of UC-.
795 pat_msr &= ~PAT_MASK(2);
796 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
797 pat_table[PAT_WRITE_COMBINING] = 2;
802 load_cr4(cr4 & ~CR4_PGE);
804 /* Disable caches (CD = 1, NW = 0). */
806 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
808 /* Flushes caches and TLBs. */
812 /* Update PAT and index table. */
813 wrmsr(MSR_PAT, pat_msr);
814 for (i = 0; i < PAT_INDEX_SIZE; i++)
815 pat_index[i] = pat_table[i];
817 /* Flush caches and TLBs again. */
821 /* Restore caches and PGE. */
827 * Initialize a vm_page's machine-dependent fields.
830 pmap_page_init(vm_page_t m)
833 TAILQ_INIT(&m->md.pv_list);
834 m->md.pat_mode = PAT_WRITE_BACK;
837 #if defined(PAE) || defined(PAE_TABLES)
839 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain, uint8_t *flags,
843 /* Inform UMA that this allocator uses kernel_map/object. */
844 *flags = UMA_SLAB_KERNEL;
845 return ((void *)kmem_alloc_contig_domain(domain, bytes, wait, 0x0ULL,
846 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
851 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
853 * - Must deal with pages in order to ensure that none of the PG_* bits
854 * are ever set, PG_V in particular.
855 * - Assumes we can write to ptes without pte_store() atomic ops, even
856 * on PAE systems. This should be ok.
857 * - Assumes nothing will ever test these addresses for 0 to indicate
858 * no mapping instead of correctly checking PG_V.
859 * - Assumes a vm_offset_t will fit in a pte (true for i386).
860 * Because PG_V is never set, there can be no mappings to invalidate.
863 pmap_ptelist_alloc(vm_offset_t *head)
870 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
874 panic("pmap_ptelist_alloc: va with PG_V set!");
880 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
885 panic("pmap_ptelist_free: freeing va with PG_V set!");
887 *pte = *head; /* virtual! PG_V is 0 though */
892 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
898 for (i = npages - 1; i >= 0; i--) {
899 va = (vm_offset_t)base + i * PAGE_SIZE;
900 pmap_ptelist_free(head, va);
906 * Initialize the pmap module.
907 * Called by vm_init, to initialize any structures that the pmap
908 * system needs to map virtual memory.
913 struct pmap_preinit_mapping *ppim;
919 * Initialize the vm page array entries for the kernel pmap's
922 for (i = 0; i < NKPT; i++) {
923 mpte = PHYS_TO_VM_PAGE(KPTphys + ptoa(i));
924 KASSERT(mpte >= vm_page_array &&
925 mpte < &vm_page_array[vm_page_array_size],
926 ("pmap_init: page table page is out of range"));
927 mpte->pindex = i + KPTDI;
928 mpte->phys_addr = KPTphys + ptoa(i);
932 * Initialize the address space (zone) for the pv entries. Set a
933 * high water mark so that the system can recover from excessive
934 * numbers of pv entries.
936 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
937 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
938 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
939 pv_entry_max = roundup(pv_entry_max, _NPCPV);
940 pv_entry_high_water = 9 * (pv_entry_max / 10);
943 * If the kernel is running on a virtual machine, then it must assume
944 * that MCA is enabled by the hypervisor. Moreover, the kernel must
945 * be prepared for the hypervisor changing the vendor and family that
946 * are reported by CPUID. Consequently, the workaround for AMD Family
947 * 10h Erratum 383 is enabled if the processor's feature set does not
948 * include at least one feature that is only supported by older Intel
949 * or newer AMD processors.
951 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
952 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
953 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
955 workaround_erratum383 = 1;
958 * Are large page mappings supported and enabled?
960 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
963 else if (pg_ps_enabled) {
964 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
965 ("pmap_init: can't assign to pagesizes[1]"));
966 pagesizes[1] = NBPDR;
970 * Calculate the size of the pv head table for superpages.
971 * Handle the possibility that "vm_phys_segs[...].end" is zero.
973 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
974 PAGE_SIZE) / NBPDR + 1;
977 * Allocate memory for the pv head table for superpages.
979 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
981 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
983 for (i = 0; i < pv_npg; i++)
984 TAILQ_INIT(&pv_table[i].pv_list);
986 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
987 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
988 if (pv_chunkbase == NULL)
989 panic("pmap_init: not enough kvm for pv chunks");
990 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
991 #if defined(PAE) || defined(PAE_TABLES)
992 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
993 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
994 UMA_ZONE_VM | UMA_ZONE_NOFREE);
995 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
998 pmap_initialized = 1;
1003 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1004 ppim = pmap_preinit_mapping + i;
1007 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
1008 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
1014 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
1015 "Max number of PV entries");
1016 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
1017 "Page share factor per proc");
1019 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1020 "2/4MB page mapping counters");
1022 static u_long pmap_pde_demotions;
1023 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1024 &pmap_pde_demotions, 0, "2/4MB page demotions");
1026 static u_long pmap_pde_mappings;
1027 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1028 &pmap_pde_mappings, 0, "2/4MB page mappings");
1030 static u_long pmap_pde_p_failures;
1031 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1032 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
1034 static u_long pmap_pde_promotions;
1035 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1036 &pmap_pde_promotions, 0, "2/4MB page promotions");
1038 /***************************************************
1039 * Low level helper routines.....
1040 ***************************************************/
1043 * Determine the appropriate bits to set in a PTE or PDE for a specified
1047 pmap_cache_bits(int mode, boolean_t is_pde)
1049 int cache_bits, pat_flag, pat_idx;
1051 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
1052 panic("Unknown caching mode %d\n", mode);
1054 /* The PAT bit is different for PTE's and PDE's. */
1055 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
1057 /* Map the caching mode to a PAT index. */
1058 pat_idx = pat_index[mode];
1060 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1063 cache_bits |= pat_flag;
1065 cache_bits |= PG_NC_PCD;
1067 cache_bits |= PG_NC_PWT;
1068 return (cache_bits);
1072 * The caller is responsible for maintaining TLB consistency.
1075 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
1079 pde = pmap_pde(kernel_pmap, va);
1080 pde_store(pde, newpde);
1084 * After changing the page size for the specified virtual address in the page
1085 * table, flush the corresponding entries from the processor's TLB. Only the
1086 * calling processor's TLB is affected.
1088 * The calling thread must be pinned to a processor.
1091 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
1094 if ((newpde & PG_PS) == 0)
1095 /* Demotion: flush a specific 2MB page mapping. */
1097 else /* if ((newpde & PG_G) == 0) */
1099 * Promotion: flush every 4KB page mapping from the TLB
1100 * because there are too many to flush individually.
1115 * For SMP, these functions have to use the IPI mechanism for coherence.
1117 * N.B.: Before calling any of the following TLB invalidation functions,
1118 * the calling processor must ensure that all stores updating a non-
1119 * kernel page table are globally performed. Otherwise, another
1120 * processor could cache an old, pre-update entry without being
1121 * invalidated. This can happen one of two ways: (1) The pmap becomes
1122 * active on another processor after its pm_active field is checked by
1123 * one of the following functions but before a store updating the page
1124 * table is globally performed. (2) The pmap becomes active on another
1125 * processor before its pm_active field is checked but due to
1126 * speculative loads one of the following functions stills reads the
1127 * pmap as inactive on the other processor.
1129 * The kernel page table is exempt because its pm_active field is
1130 * immutable. The kernel page table is always active on every
1134 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1136 cpuset_t *mask, other_cpus;
1140 if (pmap == kernel_pmap) {
1143 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1146 cpuid = PCPU_GET(cpuid);
1147 other_cpus = all_cpus;
1148 CPU_CLR(cpuid, &other_cpus);
1149 CPU_AND(&other_cpus, &pmap->pm_active);
1152 smp_masked_invlpg(*mask, va, pmap);
1156 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1157 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1160 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1162 cpuset_t *mask, other_cpus;
1166 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1167 pmap_invalidate_all(pmap);
1172 if (pmap == kernel_pmap) {
1173 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1176 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1179 cpuid = PCPU_GET(cpuid);
1180 other_cpus = all_cpus;
1181 CPU_CLR(cpuid, &other_cpus);
1182 CPU_AND(&other_cpus, &pmap->pm_active);
1185 smp_masked_invlpg_range(*mask, sva, eva, pmap);
1190 pmap_invalidate_all(pmap_t pmap)
1192 cpuset_t *mask, other_cpus;
1196 if (pmap == kernel_pmap) {
1199 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1202 cpuid = PCPU_GET(cpuid);
1203 other_cpus = all_cpus;
1204 CPU_CLR(cpuid, &other_cpus);
1205 CPU_AND(&other_cpus, &pmap->pm_active);
1208 smp_masked_invltlb(*mask, pmap);
1213 pmap_invalidate_cache(void)
1223 cpuset_t invalidate; /* processors that invalidate their TLB */
1227 u_int store; /* processor that updates the PDE */
1231 pmap_update_pde_kernel(void *arg)
1233 struct pde_action *act = arg;
1236 if (act->store == PCPU_GET(cpuid)) {
1237 pde = pmap_pde(kernel_pmap, act->va);
1238 pde_store(pde, act->newpde);
1243 pmap_update_pde_user(void *arg)
1245 struct pde_action *act = arg;
1247 if (act->store == PCPU_GET(cpuid))
1248 pde_store(act->pde, act->newpde);
1252 pmap_update_pde_teardown(void *arg)
1254 struct pde_action *act = arg;
1256 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1257 pmap_update_pde_invalidate(act->va, act->newpde);
1261 * Change the page size for the specified virtual address in a way that
1262 * prevents any possibility of the TLB ever having two entries that map the
1263 * same virtual address using different page sizes. This is the recommended
1264 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1265 * machine check exception for a TLB state that is improperly diagnosed as a
1269 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1271 struct pde_action act;
1272 cpuset_t active, other_cpus;
1276 cpuid = PCPU_GET(cpuid);
1277 other_cpus = all_cpus;
1278 CPU_CLR(cpuid, &other_cpus);
1279 if (pmap == kernel_pmap)
1282 active = pmap->pm_active;
1283 if (CPU_OVERLAP(&active, &other_cpus)) {
1285 act.invalidate = active;
1288 act.newpde = newpde;
1289 CPU_SET(cpuid, &active);
1290 smp_rendezvous_cpus(active,
1291 smp_no_rendezvous_barrier, pmap == kernel_pmap ?
1292 pmap_update_pde_kernel : pmap_update_pde_user,
1293 pmap_update_pde_teardown, &act);
1295 if (pmap == kernel_pmap)
1296 pmap_kenter_pde(va, newpde);
1298 pde_store(pde, newpde);
1299 if (CPU_ISSET(cpuid, &active))
1300 pmap_update_pde_invalidate(va, newpde);
1306 * Normal, non-SMP, 486+ invalidation functions.
1307 * We inline these within pmap.c for speed.
1310 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1313 if (pmap == kernel_pmap)
1318 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1322 if (pmap == kernel_pmap)
1323 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1328 pmap_invalidate_all(pmap_t pmap)
1331 if (pmap == kernel_pmap)
1336 pmap_invalidate_cache(void)
1343 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1346 if (pmap == kernel_pmap)
1347 pmap_kenter_pde(va, newpde);
1349 pde_store(pde, newpde);
1350 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1351 pmap_update_pde_invalidate(va, newpde);
1356 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1360 * When the PDE has PG_PROMOTED set, the 2- or 4MB page mapping was
1361 * created by a promotion that did not invalidate the 512 or 1024 4KB
1362 * page mappings that might exist in the TLB. Consequently, at this
1363 * point, the TLB may hold both 4KB and 2- or 4MB page mappings for
1364 * the address range [va, va + NBPDR). Therefore, the entire range
1365 * must be invalidated here. In contrast, when PG_PROMOTED is clear,
1366 * the TLB will not hold any 4KB page mappings for the address range
1367 * [va, va + NBPDR), and so a single INVLPG suffices to invalidate the
1368 * 2- or 4MB page mapping from the TLB.
1370 if ((pde & PG_PROMOTED) != 0)
1371 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
1373 pmap_invalidate_page(pmap, va);
1376 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1379 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1383 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
1385 KASSERT((sva & PAGE_MASK) == 0,
1386 ("pmap_invalidate_cache_range: sva not page-aligned"));
1387 KASSERT((eva & PAGE_MASK) == 0,
1388 ("pmap_invalidate_cache_range: eva not page-aligned"));
1391 if ((cpu_feature & CPUID_SS) != 0 && !force)
1392 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1393 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
1394 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1397 * XXX: Some CPUs fault, hang, or trash the local APIC
1398 * registers if we use CLFLUSH on the local APIC
1399 * range. The local APIC is always uncached, so we
1400 * don't need to flush for that range anyway.
1402 if (pmap_kextract(sva) == lapic_paddr)
1406 * Otherwise, do per-cache line flush. Use the sfence
1407 * instruction to insure that previous stores are
1408 * included in the write-back. The processor
1409 * propagates flush to other processors in the cache
1413 for (; sva < eva; sva += cpu_clflush_line_size)
1416 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1417 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1419 if (pmap_kextract(sva) == lapic_paddr)
1423 * Writes are ordered by CLFLUSH on Intel CPUs.
1425 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1427 for (; sva < eva; sva += cpu_clflush_line_size)
1429 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1434 * No targeted cache flush methods are supported by CPU,
1435 * or the supplied range is bigger than 2MB.
1436 * Globally invalidate cache.
1438 pmap_invalidate_cache();
1443 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1447 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1448 (cpu_feature & CPUID_CLFSH) == 0) {
1449 pmap_invalidate_cache();
1451 for (i = 0; i < count; i++)
1452 pmap_flush_page(pages[i]);
1457 * Are we current address space or kernel?
1460 pmap_is_current(pmap_t pmap)
1463 return (pmap == kernel_pmap);
1467 * If the given pmap is not the current or kernel pmap, the returned pte must
1468 * be released by passing it to pmap_pte_release().
1471 pmap_pte(pmap_t pmap, vm_offset_t va)
1476 pde = pmap_pde(pmap, va);
1480 /* are we current address space or kernel? */
1481 if (pmap_is_current(pmap))
1482 return (vtopte(va));
1483 mtx_lock(&PMAP2mutex);
1484 newpf = *pde & PG_FRAME;
1485 if ((*PMAP2 & PG_FRAME) != newpf) {
1486 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1487 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1489 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1495 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1498 static __inline void
1499 pmap_pte_release(pt_entry_t *pte)
1502 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1503 mtx_unlock(&PMAP2mutex);
1507 * NB: The sequence of updating a page table followed by accesses to the
1508 * corresponding pages is subject to the situation described in the "AMD64
1509 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1510 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1511 * right after modifying the PTE bits is crucial.
1513 static __inline void
1514 invlcaddr(void *caddr)
1517 invlpg((u_int)caddr);
1521 * Super fast pmap_pte routine best used when scanning
1522 * the pv lists. This eliminates many coarse-grained
1523 * invltlb calls. Note that many of the pv list
1524 * scans are across different pmaps. It is very wasteful
1525 * to do an entire invltlb for checking a single mapping.
1527 * If the given pmap is not the current pmap, pvh_global_lock
1528 * must be held and curthread pinned to a CPU.
1531 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1536 pde = pmap_pde(pmap, va);
1540 /* are we current address space or kernel? */
1541 if (pmap_is_current(pmap))
1542 return (vtopte(va));
1543 rw_assert(&pvh_global_lock, RA_WLOCKED);
1544 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1545 newpf = *pde & PG_FRAME;
1546 if ((*PMAP1 & PG_FRAME) != newpf) {
1547 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1549 PMAP1cpu = PCPU_GET(cpuid);
1555 if (PMAP1cpu != PCPU_GET(cpuid)) {
1556 PMAP1cpu = PCPU_GET(cpuid);
1562 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1568 pmap_pte_quick3(pmap_t pmap, vm_offset_t va)
1573 pde = pmap_pde(pmap, va);
1577 rw_assert(&pvh_global_lock, RA_WLOCKED);
1578 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1579 newpf = *pde & PG_FRAME;
1580 if ((*PMAP3 & PG_FRAME) != newpf) {
1581 *PMAP3 = newpf | PG_RW | PG_V | PG_A | PG_M;
1583 PMAP3cpu = PCPU_GET(cpuid);
1589 if (PMAP3cpu != PCPU_GET(cpuid)) {
1590 PMAP3cpu = PCPU_GET(cpuid);
1596 return (PADDR3 + (i386_btop(va) & (NPTEPG - 1)));
1602 pmap_pte_ufast(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1604 pt_entry_t *eh_ptep, pte, *ptep;
1606 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1609 eh_ptep = (pt_entry_t *)PCPU_GET(pmap_eh_ptep);
1610 if ((*eh_ptep & PG_FRAME) != pde) {
1611 *eh_ptep = pde | PG_RW | PG_V | PG_A | PG_M;
1612 invlcaddr((void *)PCPU_GET(pmap_eh_va));
1614 ptep = (pt_entry_t *)PCPU_GET(pmap_eh_va) + (i386_btop(va) &
1622 * Routine: pmap_extract
1624 * Extract the physical page address associated
1625 * with the given map/virtual_address pair.
1628 pmap_extract(pmap_t pmap, vm_offset_t va)
1636 pde = pmap->pm_pdir[va >> PDRSHIFT];
1638 if ((pde & PG_PS) != 0)
1639 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1641 pte = pmap_pte_ufast(pmap, va, pde);
1642 rtval = (pte & PG_FRAME) | (va & PAGE_MASK);
1650 * Routine: pmap_extract_and_hold
1652 * Atomically extract and hold the physical page
1653 * with the given pmap and virtual address pair
1654 * if that mapping permits the given protection.
1657 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1668 pde = *pmap_pde(pmap, va);
1671 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1672 if (vm_page_pa_tryrelock(pmap, (pde &
1673 PG_PS_FRAME) | (va & PDRMASK), &pa))
1675 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1680 pte = pmap_pte_ufast(pmap, va, pde);
1682 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1683 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1686 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1696 /***************************************************
1697 * Low level mapping routines.....
1698 ***************************************************/
1701 * Add a wired page to the kva.
1702 * Note: not SMP coherent.
1704 * This function may be used before pmap_bootstrap() is called.
1707 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1712 pte_store(pte, pa | PG_RW | PG_V);
1715 static __inline void
1716 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1721 pte_store(pte, pa | PG_RW | PG_V | pmap_cache_bits(mode, 0));
1725 * Remove a page from the kernel pagetables.
1726 * Note: not SMP coherent.
1728 * This function may be used before pmap_bootstrap() is called.
1731 pmap_kremove(vm_offset_t va)
1740 * Used to map a range of physical addresses into kernel
1741 * virtual address space.
1743 * The value passed in '*virt' is a suggested virtual address for
1744 * the mapping. Architectures which can support a direct-mapped
1745 * physical to virtual region can return the appropriate address
1746 * within that region, leaving '*virt' unchanged. Other
1747 * architectures should map the pages starting at '*virt' and
1748 * update '*virt' with the first usable address after the mapped
1752 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1754 vm_offset_t va, sva;
1755 vm_paddr_t superpage_offset;
1760 * Does the physical address range's size and alignment permit at
1761 * least one superpage mapping to be created?
1763 superpage_offset = start & PDRMASK;
1764 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1766 * Increase the starting virtual address so that its alignment
1767 * does not preclude the use of superpage mappings.
1769 if ((va & PDRMASK) < superpage_offset)
1770 va = (va & ~PDRMASK) + superpage_offset;
1771 else if ((va & PDRMASK) > superpage_offset)
1772 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1775 while (start < end) {
1776 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1778 KASSERT((va & PDRMASK) == 0,
1779 ("pmap_map: misaligned va %#x", va));
1780 newpde = start | PG_PS | PG_RW | PG_V;
1781 pmap_kenter_pde(va, newpde);
1785 pmap_kenter(va, start);
1790 pmap_invalidate_range(kernel_pmap, sva, va);
1797 * Add a list of wired pages to the kva
1798 * this routine is only used for temporary
1799 * kernel mappings that do not need to have
1800 * page modification or references recorded.
1801 * Note that old mappings are simply written
1802 * over. The page *must* be wired.
1803 * Note: SMP coherent. Uses a ranged shootdown IPI.
1806 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1808 pt_entry_t *endpte, oldpte, pa, *pte;
1813 endpte = pte + count;
1814 while (pte < endpte) {
1816 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1817 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1819 #if defined(PAE) || defined(PAE_TABLES)
1820 pte_store(pte, pa | pg_nx | PG_RW | PG_V);
1822 pte_store(pte, pa | PG_RW | PG_V);
1827 if (__predict_false((oldpte & PG_V) != 0))
1828 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1833 * This routine tears out page mappings from the
1834 * kernel -- it is meant only for temporary mappings.
1835 * Note: SMP coherent. Uses a ranged shootdown IPI.
1838 pmap_qremove(vm_offset_t sva, int count)
1843 while (count-- > 0) {
1847 pmap_invalidate_range(kernel_pmap, sva, va);
1850 /***************************************************
1851 * Page table page management routines.....
1852 ***************************************************/
1854 * Schedule the specified unused page table page to be freed. Specifically,
1855 * add the page to the specified list of pages that will be released to the
1856 * physical memory manager after the TLB has been updated.
1858 static __inline void
1859 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1860 boolean_t set_PG_ZERO)
1864 m->flags |= PG_ZERO;
1866 m->flags &= ~PG_ZERO;
1867 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1871 * Inserts the specified page table page into the specified pmap's collection
1872 * of idle page table pages. Each of a pmap's page table pages is responsible
1873 * for mapping a distinct range of virtual addresses. The pmap's collection is
1874 * ordered by this virtual address range.
1877 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1880 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1881 return (vm_radix_insert(&pmap->pm_root, mpte));
1885 * Removes the page table page mapping the specified virtual address from the
1886 * specified pmap's collection of idle page table pages, and returns it.
1887 * Otherwise, returns NULL if there is no page table page corresponding to the
1888 * specified virtual address.
1890 static __inline vm_page_t
1891 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
1894 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1895 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT));
1899 * Decrements a page table page's wire count, which is used to record the
1900 * number of valid page table entries within the page. If the wire count
1901 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1902 * page table page was unmapped and FALSE otherwise.
1904 static inline boolean_t
1905 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1909 if (m->wire_count == 0) {
1910 _pmap_unwire_ptp(pmap, m, free);
1917 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1921 * unmap the page table page
1923 pmap->pm_pdir[m->pindex] = 0;
1924 --pmap->pm_stats.resident_count;
1927 * There is not need to invalidate the recursive mapping since
1928 * we never instantiate such mapping for the usermode pmaps,
1929 * and never remove page table pages from the kernel pmap.
1930 * Put page on a list so that it is released since all TLB
1931 * shootdown is done.
1933 MPASS(pmap != kernel_pmap);
1934 pmap_add_delayed_free_list(m, free, TRUE);
1938 * After removing a page table entry, this routine is used to
1939 * conditionally free the page, and manage the hold/wire counts.
1942 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1947 if (pmap == kernel_pmap)
1949 ptepde = *pmap_pde(pmap, va);
1950 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1951 return (pmap_unwire_ptp(pmap, mpte, free));
1955 * Initialize the pmap for the swapper process.
1958 pmap_pinit0(pmap_t pmap)
1961 PMAP_LOCK_INIT(pmap);
1962 pmap->pm_pdir = IdlePTD;
1963 #if defined(PAE) || defined(PAE_TABLES)
1964 pmap->pm_pdpt = IdlePDPT;
1966 pmap->pm_root.rt_root = 0;
1967 CPU_ZERO(&pmap->pm_active);
1968 PCPU_SET(curpmap, pmap);
1969 TAILQ_INIT(&pmap->pm_pvchunk);
1970 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1974 * Initialize a preallocated and zeroed pmap structure,
1975 * such as one in a vmspace structure.
1978 pmap_pinit(pmap_t pmap)
1984 * No need to allocate page table space yet but we do need a valid
1985 * page directory table.
1987 if (pmap->pm_pdir == NULL) {
1988 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
1989 if (pmap->pm_pdir == NULL)
1991 #if defined(PAE) || defined(PAE_TABLES)
1992 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
1993 KASSERT(((vm_offset_t)pmap->pm_pdpt &
1994 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
1995 ("pmap_pinit: pdpt misaligned"));
1996 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
1997 ("pmap_pinit: pdpt above 4g"));
1999 pmap->pm_root.rt_root = 0;
2001 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2002 ("pmap_pinit: pmap has reserved page table page(s)"));
2005 * allocate the page directory page(s)
2007 for (i = 0; i < NPGPTD;) {
2008 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2009 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2013 pmap->pm_ptdpg[i] = m;
2014 #if defined(PAE) || defined(PAE_TABLES)
2015 pmap->pm_pdpt[i] = VM_PAGE_TO_PHYS(m) | PG_V;
2021 pmap_qenter((vm_offset_t)pmap->pm_pdir, pmap->pm_ptdpg, NPGPTD);
2023 for (i = 0; i < NPGPTD; i++)
2024 if ((pmap->pm_ptdpg[i]->flags & PG_ZERO) == 0)
2025 pagezero(pmap->pm_pdir + (i * NPDEPG));
2027 /* Install the trampoline mapping. */
2028 pmap->pm_pdir[TRPTDI] = PTD[TRPTDI];
2030 CPU_ZERO(&pmap->pm_active);
2031 TAILQ_INIT(&pmap->pm_pvchunk);
2032 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2038 * this routine is called if the page table page is not
2042 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
2048 * Allocate a page table page.
2050 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2051 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2052 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2054 rw_wunlock(&pvh_global_lock);
2056 rw_wlock(&pvh_global_lock);
2061 * Indicate the need to retry. While waiting, the page table
2062 * page may have been allocated.
2066 if ((m->flags & PG_ZERO) == 0)
2070 * Map the pagetable page into the process address space, if
2071 * it isn't already there.
2074 pmap->pm_stats.resident_count++;
2076 ptepa = VM_PAGE_TO_PHYS(m);
2077 pmap->pm_pdir[ptepindex] =
2078 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
2084 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
2091 * Calculate pagetable page index
2093 ptepindex = va >> PDRSHIFT;
2096 * Get the page directory entry
2098 ptepa = pmap->pm_pdir[ptepindex];
2101 * This supports switching from a 4MB page to a
2104 if (ptepa & PG_PS) {
2105 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
2106 ptepa = pmap->pm_pdir[ptepindex];
2110 * If the page table page is mapped, we just increment the
2111 * hold count, and activate it.
2114 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
2118 * Here if the pte page isn't mapped, or if it has
2121 m = _pmap_allocpte(pmap, ptepindex, flags);
2122 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2129 /***************************************************
2130 * Pmap allocation/deallocation routines.
2131 ***************************************************/
2134 * Release any resources held by the given physical map.
2135 * Called when a pmap initialized by pmap_pinit is being released.
2136 * Should only be called if the map contains no valid mappings.
2139 pmap_release(pmap_t pmap)
2144 KASSERT(pmap->pm_stats.resident_count == 0,
2145 ("pmap_release: pmap resident count %ld != 0",
2146 pmap->pm_stats.resident_count));
2147 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2148 ("pmap_release: pmap has reserved page table page(s)"));
2149 KASSERT(CPU_EMPTY(&pmap->pm_active),
2150 ("releasing active pmap %p", pmap));
2152 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2154 for (i = 0; i < NPGPTD; i++) {
2155 m = pmap->pm_ptdpg[i];
2156 #if defined(PAE) || defined(PAE_TABLES)
2157 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2158 ("pmap_release: got wrong ptd page"));
2160 vm_page_unwire_noq(m);
2166 kvm_size(SYSCTL_HANDLER_ARGS)
2168 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2170 return (sysctl_handle_long(oidp, &ksize, 0, req));
2172 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2173 0, 0, kvm_size, "IU", "Size of KVM");
2176 kvm_free(SYSCTL_HANDLER_ARGS)
2178 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2180 return (sysctl_handle_long(oidp, &kfree, 0, req));
2182 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2183 0, 0, kvm_free, "IU", "Amount of KVM free");
2186 * grow the number of kernel page table entries, if needed
2189 pmap_growkernel(vm_offset_t addr)
2191 vm_paddr_t ptppaddr;
2195 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2196 addr = roundup2(addr, NBPDR);
2197 if (addr - 1 >= kernel_map->max_offset)
2198 addr = kernel_map->max_offset;
2199 while (kernel_vm_end < addr) {
2200 if (pdir_pde(PTD, kernel_vm_end)) {
2201 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2202 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2203 kernel_vm_end = kernel_map->max_offset;
2209 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2210 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2213 panic("pmap_growkernel: no memory to grow kernel");
2217 if ((nkpg->flags & PG_ZERO) == 0)
2218 pmap_zero_page(nkpg);
2219 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2220 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2221 pdir_pde(KPTD, kernel_vm_end) = newpdir;
2223 pmap_kenter_pde(kernel_vm_end, newpdir);
2224 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2225 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2226 kernel_vm_end = kernel_map->max_offset;
2233 /***************************************************
2234 * page management routines.
2235 ***************************************************/
2237 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2238 CTASSERT(_NPCM == 11);
2239 CTASSERT(_NPCPV == 336);
2241 static __inline struct pv_chunk *
2242 pv_to_chunk(pv_entry_t pv)
2245 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2248 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2250 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2251 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2253 static const uint32_t pc_freemask[_NPCM] = {
2254 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2255 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2256 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2257 PC_FREE0_9, PC_FREE10
2260 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2261 "Current number of pv entries");
2264 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2266 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2267 "Current number of pv entry chunks");
2268 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2269 "Current number of pv entry chunks allocated");
2270 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2271 "Current number of pv entry chunks frees");
2272 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2273 "Number of times tried to get a chunk page but failed.");
2275 static long pv_entry_frees, pv_entry_allocs;
2276 static int pv_entry_spare;
2278 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2279 "Current number of pv entry frees");
2280 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2281 "Current number of pv entry allocs");
2282 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2283 "Current number of spare pv entries");
2287 * We are in a serious low memory condition. Resort to
2288 * drastic measures to free some pages so we can allocate
2289 * another pv entry chunk.
2292 pmap_pv_reclaim(pmap_t locked_pmap)
2295 struct pv_chunk *pc;
2296 struct md_page *pvh;
2299 pt_entry_t *pte, tpte;
2303 struct spglist free;
2305 int bit, field, freed;
2307 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2311 TAILQ_INIT(&newtail);
2312 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2313 SLIST_EMPTY(&free))) {
2314 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2315 if (pmap != pc->pc_pmap) {
2317 pmap_invalidate_all(pmap);
2318 if (pmap != locked_pmap)
2322 /* Avoid deadlock and lock recursion. */
2323 if (pmap > locked_pmap)
2325 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2327 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2333 * Destroy every non-wired, 4 KB page mapping in the chunk.
2336 for (field = 0; field < _NPCM; field++) {
2337 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2338 inuse != 0; inuse &= ~(1UL << bit)) {
2340 pv = &pc->pc_pventry[field * 32 + bit];
2342 pde = pmap_pde(pmap, va);
2343 if ((*pde & PG_PS) != 0)
2345 pte = pmap_pte(pmap, va);
2347 if ((tpte & PG_W) == 0)
2348 tpte = pte_load_clear(pte);
2349 pmap_pte_release(pte);
2350 if ((tpte & PG_W) != 0)
2353 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2355 if ((tpte & PG_G) != 0)
2356 pmap_invalidate_page(pmap, va);
2357 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2358 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2360 if ((tpte & PG_A) != 0)
2361 vm_page_aflag_set(m, PGA_REFERENCED);
2362 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2363 if (TAILQ_EMPTY(&m->md.pv_list) &&
2364 (m->flags & PG_FICTITIOUS) == 0) {
2365 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2366 if (TAILQ_EMPTY(&pvh->pv_list)) {
2367 vm_page_aflag_clear(m,
2371 pc->pc_map[field] |= 1UL << bit;
2372 pmap_unuse_pt(pmap, va, &free);
2377 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2380 /* Every freed mapping is for a 4 KB page. */
2381 pmap->pm_stats.resident_count -= freed;
2382 PV_STAT(pv_entry_frees += freed);
2383 PV_STAT(pv_entry_spare += freed);
2384 pv_entry_count -= freed;
2385 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2386 for (field = 0; field < _NPCM; field++)
2387 if (pc->pc_map[field] != pc_freemask[field]) {
2388 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2390 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2393 * One freed pv entry in locked_pmap is
2396 if (pmap == locked_pmap)
2400 if (field == _NPCM) {
2401 PV_STAT(pv_entry_spare -= _NPCPV);
2402 PV_STAT(pc_chunk_count--);
2403 PV_STAT(pc_chunk_frees++);
2404 /* Entire chunk is free; return it. */
2405 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2406 pmap_qremove((vm_offset_t)pc, 1);
2407 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2412 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2414 pmap_invalidate_all(pmap);
2415 if (pmap != locked_pmap)
2418 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2419 m_pc = SLIST_FIRST(&free);
2420 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2421 /* Recycle a freed page table page. */
2422 m_pc->wire_count = 1;
2424 vm_page_free_pages_toq(&free, true);
2429 * free the pv_entry back to the free list
2432 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2434 struct pv_chunk *pc;
2435 int idx, field, bit;
2437 rw_assert(&pvh_global_lock, RA_WLOCKED);
2438 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2439 PV_STAT(pv_entry_frees++);
2440 PV_STAT(pv_entry_spare++);
2442 pc = pv_to_chunk(pv);
2443 idx = pv - &pc->pc_pventry[0];
2446 pc->pc_map[field] |= 1ul << bit;
2447 for (idx = 0; idx < _NPCM; idx++)
2448 if (pc->pc_map[idx] != pc_freemask[idx]) {
2450 * 98% of the time, pc is already at the head of the
2451 * list. If it isn't already, move it to the head.
2453 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2455 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2456 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2461 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2466 free_pv_chunk(struct pv_chunk *pc)
2470 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2471 PV_STAT(pv_entry_spare -= _NPCPV);
2472 PV_STAT(pc_chunk_count--);
2473 PV_STAT(pc_chunk_frees++);
2474 /* entire chunk is free, return it */
2475 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2476 pmap_qremove((vm_offset_t)pc, 1);
2477 vm_page_unwire(m, PQ_NONE);
2479 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2483 * get a new pv_entry, allocating a block from the system
2487 get_pv_entry(pmap_t pmap, boolean_t try)
2489 static const struct timeval printinterval = { 60, 0 };
2490 static struct timeval lastprint;
2493 struct pv_chunk *pc;
2496 rw_assert(&pvh_global_lock, RA_WLOCKED);
2497 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2498 PV_STAT(pv_entry_allocs++);
2500 if (pv_entry_count > pv_entry_high_water)
2501 if (ratecheck(&lastprint, &printinterval))
2502 printf("Approaching the limit on PV entries, consider "
2503 "increasing either the vm.pmap.shpgperproc or the "
2504 "vm.pmap.pv_entry_max tunable.\n");
2506 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2508 for (field = 0; field < _NPCM; field++) {
2509 if (pc->pc_map[field]) {
2510 bit = bsfl(pc->pc_map[field]);
2514 if (field < _NPCM) {
2515 pv = &pc->pc_pventry[field * 32 + bit];
2516 pc->pc_map[field] &= ~(1ul << bit);
2517 /* If this was the last item, move it to tail */
2518 for (field = 0; field < _NPCM; field++)
2519 if (pc->pc_map[field] != 0) {
2520 PV_STAT(pv_entry_spare--);
2521 return (pv); /* not full, return */
2523 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2524 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2525 PV_STAT(pv_entry_spare--);
2530 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2531 * global lock. If "pv_vafree" is currently non-empty, it will
2532 * remain non-empty until pmap_ptelist_alloc() completes.
2534 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2535 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2538 PV_STAT(pc_chunk_tryfail++);
2541 m = pmap_pv_reclaim(pmap);
2545 PV_STAT(pc_chunk_count++);
2546 PV_STAT(pc_chunk_allocs++);
2547 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2548 pmap_qenter((vm_offset_t)pc, &m, 1);
2550 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2551 for (field = 1; field < _NPCM; field++)
2552 pc->pc_map[field] = pc_freemask[field];
2553 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2554 pv = &pc->pc_pventry[0];
2555 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2556 PV_STAT(pv_entry_spare += _NPCPV - 1);
2560 static __inline pv_entry_t
2561 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2565 rw_assert(&pvh_global_lock, RA_WLOCKED);
2566 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2567 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2568 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2576 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2578 struct md_page *pvh;
2580 vm_offset_t va_last;
2583 rw_assert(&pvh_global_lock, RA_WLOCKED);
2584 KASSERT((pa & PDRMASK) == 0,
2585 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2588 * Transfer the 4mpage's pv entry for this mapping to the first
2591 pvh = pa_to_pvh(pa);
2592 va = trunc_4mpage(va);
2593 pv = pmap_pvh_remove(pvh, pmap, va);
2594 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2595 m = PHYS_TO_VM_PAGE(pa);
2596 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2597 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2598 va_last = va + NBPDR - PAGE_SIZE;
2601 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2602 ("pmap_pv_demote_pde: page %p is not managed", m));
2604 pmap_insert_entry(pmap, va, m);
2605 } while (va < va_last);
2608 #if VM_NRESERVLEVEL > 0
2610 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2612 struct md_page *pvh;
2614 vm_offset_t va_last;
2617 rw_assert(&pvh_global_lock, RA_WLOCKED);
2618 KASSERT((pa & PDRMASK) == 0,
2619 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2622 * Transfer the first page's pv entry for this mapping to the
2623 * 4mpage's pv list. Aside from avoiding the cost of a call
2624 * to get_pv_entry(), a transfer avoids the possibility that
2625 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2626 * removes one of the mappings that is being promoted.
2628 m = PHYS_TO_VM_PAGE(pa);
2629 va = trunc_4mpage(va);
2630 pv = pmap_pvh_remove(&m->md, pmap, va);
2631 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2632 pvh = pa_to_pvh(pa);
2633 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2634 /* Free the remaining NPTEPG - 1 pv entries. */
2635 va_last = va + NBPDR - PAGE_SIZE;
2639 pmap_pvh_free(&m->md, pmap, va);
2640 } while (va < va_last);
2642 #endif /* VM_NRESERVLEVEL > 0 */
2645 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2649 pv = pmap_pvh_remove(pvh, pmap, va);
2650 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2651 free_pv_entry(pmap, pv);
2655 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2657 struct md_page *pvh;
2659 rw_assert(&pvh_global_lock, RA_WLOCKED);
2660 pmap_pvh_free(&m->md, pmap, va);
2661 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2662 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2663 if (TAILQ_EMPTY(&pvh->pv_list))
2664 vm_page_aflag_clear(m, PGA_WRITEABLE);
2669 * Create a pv entry for page at pa for
2673 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2677 rw_assert(&pvh_global_lock, RA_WLOCKED);
2678 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2679 pv = get_pv_entry(pmap, FALSE);
2681 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2685 * Conditionally create a pv entry.
2688 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2692 rw_assert(&pvh_global_lock, RA_WLOCKED);
2693 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2694 if (pv_entry_count < pv_entry_high_water &&
2695 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2697 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2704 * Create the pv entries for each of the pages within a superpage.
2707 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2709 struct md_page *pvh;
2712 rw_assert(&pvh_global_lock, RA_WLOCKED);
2713 if (pv_entry_count < pv_entry_high_water &&
2714 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2716 pvh = pa_to_pvh(pa);
2717 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2724 * Fills a page table page with mappings to consecutive physical pages.
2727 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2731 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2733 newpte += PAGE_SIZE;
2738 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2739 * 2- or 4MB page mapping is invalidated.
2742 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2744 pd_entry_t newpde, oldpde;
2745 pt_entry_t *firstpte, newpte;
2748 struct spglist free;
2751 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2753 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2754 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2755 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
2757 KASSERT((oldpde & PG_W) == 0,
2758 ("pmap_demote_pde: page table page for a wired mapping"
2762 * Invalidate the 2- or 4MB page mapping and return
2763 * "failure" if the mapping was never accessed or the
2764 * allocation of the new page table page fails.
2766 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2767 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2768 VM_ALLOC_WIRED)) == NULL) {
2770 sva = trunc_4mpage(va);
2771 pmap_remove_pde(pmap, pde, sva, &free);
2772 if ((oldpde & PG_G) == 0)
2773 pmap_invalidate_pde_page(pmap, sva, oldpde);
2774 vm_page_free_pages_toq(&free, true);
2775 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2776 " in pmap %p", va, pmap);
2779 if (pmap != kernel_pmap)
2780 pmap->pm_stats.resident_count++;
2782 mptepa = VM_PAGE_TO_PHYS(mpte);
2785 * If the page mapping is in the kernel's address space, then the
2786 * KPTmap can provide access to the page table page. Otherwise,
2787 * temporarily map the page table page (mpte) into the kernel's
2788 * address space at either PADDR1 or PADDR2.
2790 if (pmap == kernel_pmap)
2791 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2792 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2793 if ((*PMAP1 & PG_FRAME) != mptepa) {
2794 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2796 PMAP1cpu = PCPU_GET(cpuid);
2802 if (PMAP1cpu != PCPU_GET(cpuid)) {
2803 PMAP1cpu = PCPU_GET(cpuid);
2811 mtx_lock(&PMAP2mutex);
2812 if ((*PMAP2 & PG_FRAME) != mptepa) {
2813 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2814 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2818 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2819 KASSERT((oldpde & PG_A) != 0,
2820 ("pmap_demote_pde: oldpde is missing PG_A"));
2821 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2822 ("pmap_demote_pde: oldpde is missing PG_M"));
2823 newpte = oldpde & ~PG_PS;
2824 if ((newpte & PG_PDE_PAT) != 0)
2825 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2828 * If the page table page is new, initialize it.
2830 if (mpte->wire_count == 1) {
2831 mpte->wire_count = NPTEPG;
2832 pmap_fill_ptp(firstpte, newpte);
2834 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2835 ("pmap_demote_pde: firstpte and newpte map different physical"
2839 * If the mapping has changed attributes, update the page table
2842 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2843 pmap_fill_ptp(firstpte, newpte);
2846 * Demote the mapping. This pmap is locked. The old PDE has
2847 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2848 * set. Thus, there is no danger of a race with another
2849 * processor changing the setting of PG_A and/or PG_M between
2850 * the read above and the store below.
2852 if (workaround_erratum383)
2853 pmap_update_pde(pmap, va, pde, newpde);
2854 else if (pmap == kernel_pmap)
2855 pmap_kenter_pde(va, newpde);
2857 pde_store(pde, newpde);
2858 if (firstpte == PADDR2)
2859 mtx_unlock(&PMAP2mutex);
2862 * Invalidate the recursive mapping of the page table page.
2864 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2867 * Demote the pv entry. This depends on the earlier demotion
2868 * of the mapping. Specifically, the (re)creation of a per-
2869 * page pv entry might trigger the execution of pmap_collect(),
2870 * which might reclaim a newly (re)created per-page pv entry
2871 * and destroy the associated mapping. In order to destroy
2872 * the mapping, the PDE must have already changed from mapping
2873 * the 2mpage to referencing the page table page.
2875 if ((oldpde & PG_MANAGED) != 0)
2876 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2878 pmap_pde_demotions++;
2879 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2880 " in pmap %p", va, pmap);
2885 * Removes a 2- or 4MB page mapping from the kernel pmap.
2888 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2894 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2895 mpte = pmap_remove_pt_page(pmap, va);
2897 panic("pmap_remove_kernel_pde: Missing pt page.");
2899 mptepa = VM_PAGE_TO_PHYS(mpte);
2900 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2903 * Initialize the page table page.
2905 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2908 * Remove the mapping.
2910 if (workaround_erratum383)
2911 pmap_update_pde(pmap, va, pde, newpde);
2913 pmap_kenter_pde(va, newpde);
2916 * Invalidate the recursive mapping of the page table page.
2918 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2922 * pmap_remove_pde: do the things to unmap a superpage in a process
2925 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2926 struct spglist *free)
2928 struct md_page *pvh;
2930 vm_offset_t eva, va;
2933 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2934 KASSERT((sva & PDRMASK) == 0,
2935 ("pmap_remove_pde: sva is not 4mpage aligned"));
2936 oldpde = pte_load_clear(pdq);
2938 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2941 * Machines that don't support invlpg, also don't support
2944 if ((oldpde & PG_G) != 0)
2945 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
2947 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2948 if (oldpde & PG_MANAGED) {
2949 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2950 pmap_pvh_free(pvh, pmap, sva);
2952 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2953 va < eva; va += PAGE_SIZE, m++) {
2954 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2957 vm_page_aflag_set(m, PGA_REFERENCED);
2958 if (TAILQ_EMPTY(&m->md.pv_list) &&
2959 TAILQ_EMPTY(&pvh->pv_list))
2960 vm_page_aflag_clear(m, PGA_WRITEABLE);
2963 if (pmap == kernel_pmap) {
2964 pmap_remove_kernel_pde(pmap, pdq, sva);
2966 mpte = pmap_remove_pt_page(pmap, sva);
2968 pmap->pm_stats.resident_count--;
2969 KASSERT(mpte->wire_count == NPTEPG,
2970 ("pmap_remove_pde: pte page wire count error"));
2971 mpte->wire_count = 0;
2972 pmap_add_delayed_free_list(mpte, free, FALSE);
2978 * pmap_remove_pte: do the things to unmap a page in a process
2981 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
2982 struct spglist *free)
2987 rw_assert(&pvh_global_lock, RA_WLOCKED);
2988 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2989 oldpte = pte_load_clear(ptq);
2990 KASSERT(oldpte != 0,
2991 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
2993 pmap->pm_stats.wired_count -= 1;
2995 * Machines that don't support invlpg, also don't support
2999 pmap_invalidate_page(kernel_pmap, va);
3000 pmap->pm_stats.resident_count -= 1;
3001 if (oldpte & PG_MANAGED) {
3002 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
3003 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3006 vm_page_aflag_set(m, PGA_REFERENCED);
3007 pmap_remove_entry(pmap, m, va);
3009 return (pmap_unuse_pt(pmap, va, free));
3013 * Remove a single page from a process address space
3016 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
3020 rw_assert(&pvh_global_lock, RA_WLOCKED);
3021 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3022 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3023 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
3025 pmap_remove_pte(pmap, pte, va, free);
3026 pmap_invalidate_page(pmap, va);
3030 * Remove the given range of addresses from the specified map.
3032 * It is assumed that the start and end are properly
3033 * rounded to the page size.
3036 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3041 struct spglist free;
3045 * Perform an unsynchronized read. This is, however, safe.
3047 if (pmap->pm_stats.resident_count == 0)
3053 rw_wlock(&pvh_global_lock);
3058 * special handling of removing one page. a very
3059 * common operation and easy to short circuit some
3062 if ((sva + PAGE_SIZE == eva) &&
3063 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
3064 pmap_remove_page(pmap, sva, &free);
3068 for (; sva < eva; sva = pdnxt) {
3072 * Calculate index for next page table.
3074 pdnxt = (sva + NBPDR) & ~PDRMASK;
3077 if (pmap->pm_stats.resident_count == 0)
3080 pdirindex = sva >> PDRSHIFT;
3081 ptpaddr = pmap->pm_pdir[pdirindex];
3084 * Weed out invalid mappings. Note: we assume that the page
3085 * directory table is always allocated, and in kernel virtual.
3091 * Check for large page.
3093 if ((ptpaddr & PG_PS) != 0) {
3095 * Are we removing the entire large page? If not,
3096 * demote the mapping and fall through.
3098 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3100 * The TLB entry for a PG_G mapping is
3101 * invalidated by pmap_remove_pde().
3103 if ((ptpaddr & PG_G) == 0)
3105 pmap_remove_pde(pmap,
3106 &pmap->pm_pdir[pdirindex], sva, &free);
3108 } else if (!pmap_demote_pde(pmap,
3109 &pmap->pm_pdir[pdirindex], sva)) {
3110 /* The large page mapping was destroyed. */
3116 * Limit our scan to either the end of the va represented
3117 * by the current page table page, or to the end of the
3118 * range being removed.
3123 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3129 * The TLB entry for a PG_G mapping is invalidated
3130 * by pmap_remove_pte().
3132 if ((*pte & PG_G) == 0)
3134 if (pmap_remove_pte(pmap, pte, sva, &free))
3141 pmap_invalidate_all(pmap);
3142 rw_wunlock(&pvh_global_lock);
3144 vm_page_free_pages_toq(&free, true);
3148 * Routine: pmap_remove_all
3150 * Removes this physical page from
3151 * all physical maps in which it resides.
3152 * Reflects back modify bits to the pager.
3155 * Original versions of this routine were very
3156 * inefficient because they iteratively called
3157 * pmap_remove (slow...)
3161 pmap_remove_all(vm_page_t m)
3163 struct md_page *pvh;
3166 pt_entry_t *pte, tpte;
3169 struct spglist free;
3171 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3172 ("pmap_remove_all: page %p is not managed", m));
3174 rw_wlock(&pvh_global_lock);
3176 if ((m->flags & PG_FICTITIOUS) != 0)
3177 goto small_mappings;
3178 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3179 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3183 pde = pmap_pde(pmap, va);
3184 (void)pmap_demote_pde(pmap, pde, va);
3188 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3191 pmap->pm_stats.resident_count--;
3192 pde = pmap_pde(pmap, pv->pv_va);
3193 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3194 " a 4mpage in page %p's pv list", m));
3195 pte = pmap_pte_quick(pmap, pv->pv_va);
3196 tpte = pte_load_clear(pte);
3197 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3200 pmap->pm_stats.wired_count--;
3202 vm_page_aflag_set(m, PGA_REFERENCED);
3205 * Update the vm_page_t clean and reference bits.
3207 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3209 pmap_unuse_pt(pmap, pv->pv_va, &free);
3210 pmap_invalidate_page(pmap, pv->pv_va);
3211 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3212 free_pv_entry(pmap, pv);
3215 vm_page_aflag_clear(m, PGA_WRITEABLE);
3217 rw_wunlock(&pvh_global_lock);
3218 vm_page_free_pages_toq(&free, true);
3222 * pmap_protect_pde: do the things to protect a 4mpage in a process
3225 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3227 pd_entry_t newpde, oldpde;
3228 vm_offset_t eva, va;
3230 boolean_t anychanged;
3232 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3233 KASSERT((sva & PDRMASK) == 0,
3234 ("pmap_protect_pde: sva is not 4mpage aligned"));
3237 oldpde = newpde = *pde;
3238 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
3239 (PG_MANAGED | PG_M | PG_RW)) {
3241 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3242 va < eva; va += PAGE_SIZE, m++)
3245 if ((prot & VM_PROT_WRITE) == 0)
3246 newpde &= ~(PG_RW | PG_M);
3247 #if defined(PAE) || defined(PAE_TABLES)
3248 if ((prot & VM_PROT_EXECUTE) == 0)
3251 if (newpde != oldpde) {
3253 * As an optimization to future operations on this PDE, clear
3254 * PG_PROMOTED. The impending invalidation will remove any
3255 * lingering 4KB page mappings from the TLB.
3257 if (!pde_cmpset(pde, oldpde, newpde & ~PG_PROMOTED))
3259 if ((oldpde & PG_G) != 0)
3260 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
3264 return (anychanged);
3268 * Set the physical protection on the
3269 * specified range of this map as requested.
3272 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3277 boolean_t anychanged, pv_lists_locked;
3279 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3280 if (prot == VM_PROT_NONE) {
3281 pmap_remove(pmap, sva, eva);
3285 #if defined(PAE) || defined(PAE_TABLES)
3286 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3287 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3290 if (prot & VM_PROT_WRITE)
3294 if (pmap_is_current(pmap))
3295 pv_lists_locked = FALSE;
3297 pv_lists_locked = TRUE;
3299 rw_wlock(&pvh_global_lock);
3305 for (; sva < eva; sva = pdnxt) {
3306 pt_entry_t obits, pbits;
3309 pdnxt = (sva + NBPDR) & ~PDRMASK;
3313 pdirindex = sva >> PDRSHIFT;
3314 ptpaddr = pmap->pm_pdir[pdirindex];
3317 * Weed out invalid mappings. Note: we assume that the page
3318 * directory table is always allocated, and in kernel virtual.
3324 * Check for large page.
3326 if ((ptpaddr & PG_PS) != 0) {
3328 * Are we protecting the entire large page? If not,
3329 * demote the mapping and fall through.
3331 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3333 * The TLB entry for a PG_G mapping is
3334 * invalidated by pmap_protect_pde().
3336 if (pmap_protect_pde(pmap,
3337 &pmap->pm_pdir[pdirindex], sva, prot))
3341 if (!pv_lists_locked) {
3342 pv_lists_locked = TRUE;
3343 if (!rw_try_wlock(&pvh_global_lock)) {
3345 pmap_invalidate_all(
3352 if (!pmap_demote_pde(pmap,
3353 &pmap->pm_pdir[pdirindex], sva)) {
3355 * The large page mapping was
3366 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3372 * Regardless of whether a pte is 32 or 64 bits in
3373 * size, PG_RW, PG_A, and PG_M are among the least
3374 * significant 32 bits.
3376 obits = pbits = *pte;
3377 if ((pbits & PG_V) == 0)
3380 if ((prot & VM_PROT_WRITE) == 0) {
3381 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3382 (PG_MANAGED | PG_M | PG_RW)) {
3383 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3386 pbits &= ~(PG_RW | PG_M);
3388 #if defined(PAE) || defined(PAE_TABLES)
3389 if ((prot & VM_PROT_EXECUTE) == 0)
3393 if (pbits != obits) {
3394 #if defined(PAE) || defined(PAE_TABLES)
3395 if (!atomic_cmpset_64(pte, obits, pbits))
3398 if (!atomic_cmpset_int((u_int *)pte, obits,
3403 pmap_invalidate_page(pmap, sva);
3410 pmap_invalidate_all(pmap);
3411 if (pv_lists_locked) {
3413 rw_wunlock(&pvh_global_lock);
3418 #if VM_NRESERVLEVEL > 0
3420 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3421 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3422 * For promotion to occur, two conditions must be met: (1) the 4KB page
3423 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3424 * mappings must have identical characteristics.
3426 * Managed (PG_MANAGED) mappings within the kernel address space are not
3427 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3428 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3432 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3435 pt_entry_t *firstpte, oldpte, pa, *pte;
3436 vm_offset_t oldpteva;
3439 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3442 * Examine the first PTE in the specified PTP. Abort if this PTE is
3443 * either invalid, unused, or does not map the first 4KB physical page
3444 * within a 2- or 4MB page.
3446 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3449 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3450 pmap_pde_p_failures++;
3451 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3452 " in pmap %p", va, pmap);
3455 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3456 pmap_pde_p_failures++;
3457 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3458 " in pmap %p", va, pmap);
3461 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3463 * When PG_M is already clear, PG_RW can be cleared without
3464 * a TLB invalidation.
3466 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3473 * Examine each of the other PTEs in the specified PTP. Abort if this
3474 * PTE maps an unexpected 4KB physical page or does not have identical
3475 * characteristics to the first PTE.
3477 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3478 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3481 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3482 pmap_pde_p_failures++;
3483 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3484 " in pmap %p", va, pmap);
3487 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3489 * When PG_M is already clear, PG_RW can be cleared
3490 * without a TLB invalidation.
3492 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3496 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3498 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3499 " in pmap %p", oldpteva, pmap);
3501 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3502 pmap_pde_p_failures++;
3503 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3504 " in pmap %p", va, pmap);
3511 * Save the page table page in its current state until the PDE
3512 * mapping the superpage is demoted by pmap_demote_pde() or
3513 * destroyed by pmap_remove_pde().
3515 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3516 KASSERT(mpte >= vm_page_array &&
3517 mpte < &vm_page_array[vm_page_array_size],
3518 ("pmap_promote_pde: page table page is out of range"));
3519 KASSERT(mpte->pindex == va >> PDRSHIFT,
3520 ("pmap_promote_pde: page table page's pindex is wrong"));
3521 if (pmap_insert_pt_page(pmap, mpte)) {
3522 pmap_pde_p_failures++;
3524 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3530 * Promote the pv entries.
3532 if ((newpde & PG_MANAGED) != 0)
3533 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3536 * Propagate the PAT index to its proper position.
3538 if ((newpde & PG_PTE_PAT) != 0)
3539 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3542 * Map the superpage.
3544 if (workaround_erratum383)
3545 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3546 else if (pmap == kernel_pmap)
3547 pmap_kenter_pde(va, PG_PROMOTED | PG_PS | newpde);
3549 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
3551 pmap_pde_promotions++;
3552 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3553 " in pmap %p", va, pmap);
3555 #endif /* VM_NRESERVLEVEL > 0 */
3558 * Insert the given physical page (p) at
3559 * the specified virtual address (v) in the
3560 * target physical map with the protection requested.
3562 * If specified, the page will be wired down, meaning
3563 * that the related pte can not be reclaimed.
3565 * NB: This is the only routine which MAY NOT lazy-evaluate
3566 * or lose information. That is, this routine must actually
3567 * insert this page into the given map NOW.
3570 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3571 u_int flags, int8_t psind)
3575 pt_entry_t newpte, origpte;
3579 boolean_t invlva, wired;
3581 va = trunc_page(va);
3583 wired = (flags & PMAP_ENTER_WIRED) != 0;
3585 KASSERT((pmap == kernel_pmap && va < VM_MAX_KERNEL_ADDRESS) ||
3586 (pmap != kernel_pmap && va < VM_MAXUSER_ADDRESS),
3587 ("pmap_enter: toobig k%d %#x", pmap == kernel_pmap, va));
3588 KASSERT(va < PMAP_TRM_MIN_ADDRESS,
3589 ("pmap_enter: invalid to pmap_enter into trampoline (va: 0x%x)",
3591 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3592 VM_OBJECT_ASSERT_LOCKED(m->object);
3594 rw_wlock(&pvh_global_lock);
3598 pde = pmap_pde(pmap, va);
3599 if (pmap != kernel_pmap) {
3602 * In the case that a page table page is not resident,
3603 * we are creating it here. pmap_allocpte() handles
3606 mpte = pmap_allocpte(pmap, va, flags);
3608 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3609 ("pmap_allocpte failed with sleep allowed"));
3611 rw_wunlock(&pvh_global_lock);
3613 return (KERN_RESOURCE_SHORTAGE);
3617 * va is for KVA, so pmap_demote_pde() will never fail
3618 * to install a page table page. PG_V is also
3619 * asserted by pmap_demote_pde().
3621 KASSERT(pde != NULL && (*pde & PG_V) != 0,
3622 ("KVA %#x invalid pde pdir %#jx", va,
3623 (uintmax_t)pmap->pm_pdir[PTDPTDI]));
3624 if ((*pde & PG_PS) != 0)
3625 pmap_demote_pde(pmap, pde, va);
3627 pte = pmap_pte_quick(pmap, va);
3630 * Page Directory table entry is not valid, which should not
3631 * happen. We should have either allocated the page table
3632 * page or demoted the existing mapping above.
3635 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3636 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3639 pa = VM_PAGE_TO_PHYS(m);
3642 opa = origpte & PG_FRAME;
3645 * Mapping has not changed, must be protection or wiring change.
3647 if (origpte && (opa == pa)) {
3649 * Wiring change, just update stats. We don't worry about
3650 * wiring PT pages as they remain resident as long as there
3651 * are valid mappings in them. Hence, if a user page is wired,
3652 * the PT page will be also.
3654 if (wired && ((origpte & PG_W) == 0))
3655 pmap->pm_stats.wired_count++;
3656 else if (!wired && (origpte & PG_W))
3657 pmap->pm_stats.wired_count--;
3660 * Remove extra pte reference
3665 if (origpte & PG_MANAGED) {
3675 * Mapping has changed, invalidate old range and fall through to
3676 * handle validating new mapping.
3680 pmap->pm_stats.wired_count--;
3681 if (origpte & PG_MANAGED) {
3682 om = PHYS_TO_VM_PAGE(opa);
3683 pv = pmap_pvh_remove(&om->md, pmap, va);
3687 KASSERT(mpte->wire_count > 0,
3688 ("pmap_enter: missing reference to page table page,"
3692 pmap->pm_stats.resident_count++;
3695 * Enter on the PV list if part of our managed memory.
3697 if ((m->oflags & VPO_UNMANAGED) == 0) {
3698 KASSERT(pmap != kernel_pmap || va < kmi.clean_sva ||
3699 va >= kmi.clean_eva,
3700 ("pmap_enter: managed mapping within the clean submap"));
3702 pv = get_pv_entry(pmap, FALSE);
3704 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3706 } else if (pv != NULL)
3707 free_pv_entry(pmap, pv);
3710 * Increment counters
3713 pmap->pm_stats.wired_count++;
3717 * Now validate mapping with desired protection/wiring.
3719 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V);
3720 if ((prot & VM_PROT_WRITE) != 0) {
3722 if ((newpte & PG_MANAGED) != 0)
3723 vm_page_aflag_set(m, PGA_WRITEABLE);
3725 #if defined(PAE) || defined(PAE_TABLES)
3726 if ((prot & VM_PROT_EXECUTE) == 0)
3731 if (pmap != kernel_pmap)
3735 * if the mapping or permission bits are different, we need
3736 * to update the pte.
3738 if ((origpte & ~(PG_M|PG_A)) != newpte) {
3740 if ((flags & VM_PROT_WRITE) != 0)
3742 if (origpte & PG_V) {
3744 origpte = pte_load_store(pte, newpte);
3745 if (origpte & PG_A) {
3746 if (origpte & PG_MANAGED)
3747 vm_page_aflag_set(om, PGA_REFERENCED);
3748 if (opa != VM_PAGE_TO_PHYS(m))
3750 #if defined(PAE) || defined(PAE_TABLES)
3751 if ((origpte & PG_NX) == 0 &&
3752 (newpte & PG_NX) != 0)
3756 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
3757 if ((origpte & PG_MANAGED) != 0)
3759 if ((prot & VM_PROT_WRITE) == 0)
3762 if ((origpte & PG_MANAGED) != 0 &&
3763 TAILQ_EMPTY(&om->md.pv_list) &&
3764 ((om->flags & PG_FICTITIOUS) != 0 ||
3765 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3766 vm_page_aflag_clear(om, PGA_WRITEABLE);
3768 pmap_invalidate_page(pmap, va);
3770 pte_store(pte, newpte);
3773 #if VM_NRESERVLEVEL > 0
3775 * If both the page table page and the reservation are fully
3776 * populated, then attempt promotion.
3778 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3779 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3780 vm_reserv_level_iffullpop(m) == 0)
3781 pmap_promote_pde(pmap, pde, va);
3785 rw_wunlock(&pvh_global_lock);
3787 return (KERN_SUCCESS);
3791 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and
3792 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
3793 * blocking, (2) a mapping already exists at the specified virtual address, or
3794 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3797 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3799 pd_entry_t *pde, newpde;
3801 rw_assert(&pvh_global_lock, RA_WLOCKED);
3802 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3803 pde = pmap_pde(pmap, va);
3805 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3806 " in pmap %p", va, pmap);
3809 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3811 if ((m->oflags & VPO_UNMANAGED) == 0) {
3812 newpde |= PG_MANAGED;
3815 * Abort this mapping if its PV entry could not be created.
3817 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) {
3818 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3819 " in pmap %p", va, pmap);
3823 #if defined(PAE) || defined(PAE_TABLES)
3824 if ((prot & VM_PROT_EXECUTE) == 0)
3827 if (va < VM_MAXUSER_ADDRESS)
3831 * Increment counters.
3833 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3836 * Map the superpage. (This is not a promoted mapping; there will not
3837 * be any lingering 4KB page mappings in the TLB.)
3839 pde_store(pde, newpde);
3841 pmap_pde_mappings++;
3842 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3843 " in pmap %p", va, pmap);
3848 * Maps a sequence of resident pages belonging to the same object.
3849 * The sequence begins with the given page m_start. This page is
3850 * mapped at the given virtual address start. Each subsequent page is
3851 * mapped at a virtual address that is offset from start by the same
3852 * amount as the page is offset from m_start within the object. The
3853 * last page in the sequence is the page with the largest offset from
3854 * m_start that can be mapped at a virtual address less than the given
3855 * virtual address end. Not every virtual page between start and end
3856 * is mapped; only those for which a resident page exists with the
3857 * corresponding offset from m_start are mapped.
3860 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3861 vm_page_t m_start, vm_prot_t prot)
3865 vm_pindex_t diff, psize;
3867 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3869 psize = atop(end - start);
3872 rw_wlock(&pvh_global_lock);
3874 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3875 va = start + ptoa(diff);
3876 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3877 m->psind == 1 && pg_ps_enabled &&
3878 pmap_enter_pde(pmap, va, m, prot))
3879 m = &m[NBPDR / PAGE_SIZE - 1];
3881 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3883 m = TAILQ_NEXT(m, listq);
3885 rw_wunlock(&pvh_global_lock);
3890 * this code makes some *MAJOR* assumptions:
3891 * 1. Current pmap & pmap exists.
3894 * 4. No page table pages.
3895 * but is *MUCH* faster than pmap_enter...
3899 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3902 rw_wlock(&pvh_global_lock);
3904 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
3905 rw_wunlock(&pvh_global_lock);
3910 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3911 vm_prot_t prot, vm_page_t mpte)
3915 struct spglist free;
3917 KASSERT(pmap != kernel_pmap || va < kmi.clean_sva ||
3918 va >= kmi.clean_eva || (m->oflags & VPO_UNMANAGED) != 0,
3919 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3920 rw_assert(&pvh_global_lock, RA_WLOCKED);
3921 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3924 * In the case that a page table page is not
3925 * resident, we are creating it here.
3927 if (pmap != kernel_pmap) {
3932 * Calculate pagetable page index
3934 ptepindex = va >> PDRSHIFT;
3935 if (mpte && (mpte->pindex == ptepindex)) {
3939 * Get the page directory entry
3941 ptepa = pmap->pm_pdir[ptepindex];
3944 * If the page table page is mapped, we just increment
3945 * the hold count, and activate it.
3950 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
3953 mpte = _pmap_allocpte(pmap, ptepindex,
3954 PMAP_ENTER_NOSLEEP);
3964 pte = pmap_pte_quick(pmap, va);
3975 * Enter on the PV list if part of our managed memory.
3977 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3978 !pmap_try_insert_pv_entry(pmap, va, m)) {
3981 if (pmap_unwire_ptp(pmap, mpte, &free)) {
3982 pmap_invalidate_page(pmap, va);
3983 vm_page_free_pages_toq(&free, true);
3993 * Increment counters
3995 pmap->pm_stats.resident_count++;
3997 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3998 #if defined(PAE) || defined(PAE_TABLES)
3999 if ((prot & VM_PROT_EXECUTE) == 0)
4004 * Now validate mapping with RO protection
4006 if ((m->oflags & VPO_UNMANAGED) != 0)
4007 pte_store(pte, pa | PG_V | PG_U);
4009 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
4015 * Make a temporary mapping for a physical address. This is only intended
4016 * to be used for panic dumps.
4019 pmap_kenter_temporary(vm_paddr_t pa, int i)
4023 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
4024 pmap_kenter(va, pa);
4026 return ((void *)crashdumpmap);
4030 * This code maps large physical mmap regions into the
4031 * processor address space. Note that some shortcuts
4032 * are taken, but the code works.
4035 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4036 vm_pindex_t pindex, vm_size_t size)
4039 vm_paddr_t pa, ptepa;
4043 VM_OBJECT_ASSERT_WLOCKED(object);
4044 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4045 ("pmap_object_init_pt: non-device object"));
4047 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
4048 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4050 p = vm_page_lookup(object, pindex);
4051 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4052 ("pmap_object_init_pt: invalid page %p", p));
4053 pat_mode = p->md.pat_mode;
4056 * Abort the mapping if the first page is not physically
4057 * aligned to a 2/4MB page boundary.
4059 ptepa = VM_PAGE_TO_PHYS(p);
4060 if (ptepa & (NBPDR - 1))
4064 * Skip the first page. Abort the mapping if the rest of
4065 * the pages are not physically contiguous or have differing
4066 * memory attributes.
4068 p = TAILQ_NEXT(p, listq);
4069 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4071 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4072 ("pmap_object_init_pt: invalid page %p", p));
4073 if (pa != VM_PAGE_TO_PHYS(p) ||
4074 pat_mode != p->md.pat_mode)
4076 p = TAILQ_NEXT(p, listq);
4080 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
4081 * "size" is a multiple of 2/4M, adding the PAT setting to
4082 * "pa" will not affect the termination of this loop.
4085 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
4086 size; pa += NBPDR) {
4087 pde = pmap_pde(pmap, addr);
4089 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4090 PG_U | PG_RW | PG_V);
4091 pmap->pm_stats.resident_count += NBPDR /
4093 pmap_pde_mappings++;
4095 /* Else continue on if the PDE is already valid. */
4103 * Clear the wired attribute from the mappings for the specified range of
4104 * addresses in the given pmap. Every valid mapping within that range
4105 * must have the wired attribute set. In contrast, invalid mappings
4106 * cannot have the wired attribute set, so they are ignored.
4108 * The wired attribute of the page table entry is not a hardware feature,
4109 * so there is no need to invalidate any TLB entries.
4112 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4117 boolean_t pv_lists_locked;
4119 if (pmap_is_current(pmap))
4120 pv_lists_locked = FALSE;
4122 pv_lists_locked = TRUE;
4124 rw_wlock(&pvh_global_lock);
4128 for (; sva < eva; sva = pdnxt) {
4129 pdnxt = (sva + NBPDR) & ~PDRMASK;
4132 pde = pmap_pde(pmap, sva);
4133 if ((*pde & PG_V) == 0)
4135 if ((*pde & PG_PS) != 0) {
4136 if ((*pde & PG_W) == 0)
4137 panic("pmap_unwire: pde %#jx is missing PG_W",
4141 * Are we unwiring the entire large page? If not,
4142 * demote the mapping and fall through.
4144 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4146 * Regardless of whether a pde (or pte) is 32
4147 * or 64 bits in size, PG_W is among the least
4148 * significant 32 bits.
4150 atomic_clear_int((u_int *)pde, PG_W);
4151 pmap->pm_stats.wired_count -= NBPDR /
4155 if (!pv_lists_locked) {
4156 pv_lists_locked = TRUE;
4157 if (!rw_try_wlock(&pvh_global_lock)) {
4164 if (!pmap_demote_pde(pmap, pde, sva))
4165 panic("pmap_unwire: demotion failed");
4170 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4172 if ((*pte & PG_V) == 0)
4174 if ((*pte & PG_W) == 0)
4175 panic("pmap_unwire: pte %#jx is missing PG_W",
4179 * PG_W must be cleared atomically. Although the pmap
4180 * lock synchronizes access to PG_W, another processor
4181 * could be setting PG_M and/or PG_A concurrently.
4183 * PG_W is among the least significant 32 bits.
4185 atomic_clear_int((u_int *)pte, PG_W);
4186 pmap->pm_stats.wired_count--;
4189 if (pv_lists_locked) {
4191 rw_wunlock(&pvh_global_lock);
4198 * Copy the range specified by src_addr/len
4199 * from the source map to the range dst_addr/len
4200 * in the destination map.
4202 * This routine is only advisory and need not do anything. Since
4203 * current pmap is always the kernel pmap when executing in
4204 * kernel, and we do not copy from the kernel pmap to a user
4205 * pmap, this optimization is not usable in 4/4G full split i386
4210 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4211 vm_offset_t src_addr)
4213 struct spglist free;
4214 pt_entry_t *src_pte, *dst_pte, ptetemp;
4215 pd_entry_t srcptepaddr;
4216 vm_page_t dstmpte, srcmpte;
4217 vm_offset_t addr, end_addr, pdnxt;
4220 if (dst_addr != src_addr)
4223 end_addr = src_addr + len;
4225 rw_wlock(&pvh_global_lock);
4226 if (dst_pmap < src_pmap) {
4227 PMAP_LOCK(dst_pmap);
4228 PMAP_LOCK(src_pmap);
4230 PMAP_LOCK(src_pmap);
4231 PMAP_LOCK(dst_pmap);
4234 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4235 KASSERT(addr < PMAP_TRM_MIN_ADDRESS,
4236 ("pmap_copy: invalid to pmap_copy the trampoline"));
4238 pdnxt = (addr + NBPDR) & ~PDRMASK;
4241 ptepindex = addr >> PDRSHIFT;
4243 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4244 if (srcptepaddr == 0)
4247 if (srcptepaddr & PG_PS) {
4248 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4250 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4251 ((srcptepaddr & PG_MANAGED) == 0 ||
4252 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4254 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4256 dst_pmap->pm_stats.resident_count +=
4258 pmap_pde_mappings++;
4263 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4264 KASSERT(srcmpte->wire_count > 0,
4265 ("pmap_copy: source page table page is unused"));
4267 if (pdnxt > end_addr)
4270 src_pte = pmap_pte_quick3(src_pmap, addr);
4271 while (addr < pdnxt) {
4274 * we only virtual copy managed pages
4276 if ((ptetemp & PG_MANAGED) != 0) {
4277 dstmpte = pmap_allocpte(dst_pmap, addr,
4278 PMAP_ENTER_NOSLEEP);
4279 if (dstmpte == NULL)
4281 dst_pte = pmap_pte_quick(dst_pmap, addr);
4282 if (*dst_pte == 0 &&
4283 pmap_try_insert_pv_entry(dst_pmap, addr,
4284 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4286 * Clear the wired, modified, and
4287 * accessed (referenced) bits
4290 *dst_pte = ptetemp & ~(PG_W | PG_M |
4292 dst_pmap->pm_stats.resident_count++;
4295 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4297 pmap_invalidate_page(dst_pmap,
4299 vm_page_free_pages_toq(&free,
4304 if (dstmpte->wire_count >= srcmpte->wire_count)
4313 rw_wunlock(&pvh_global_lock);
4314 PMAP_UNLOCK(src_pmap);
4315 PMAP_UNLOCK(dst_pmap);
4319 * Zero 1 page of virtual memory mapped from a hardware page by the caller.
4321 static __inline void
4322 pagezero(void *page)
4324 #if defined(I686_CPU)
4325 if (cpu_class == CPUCLASS_686) {
4326 if (cpu_feature & CPUID_SSE2)
4327 sse2_pagezero(page);
4329 i686_pagezero(page);
4332 bzero(page, PAGE_SIZE);
4336 * Zero the specified hardware page.
4339 pmap_zero_page(vm_page_t m)
4341 pt_entry_t *cmap_pte2;
4346 cmap_pte2 = pc->pc_cmap_pte2;
4347 mtx_lock(&pc->pc_cmap_lock);
4349 panic("pmap_zero_page: CMAP2 busy");
4350 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4351 pmap_cache_bits(m->md.pat_mode, 0);
4352 invlcaddr(pc->pc_cmap_addr2);
4353 pagezero(pc->pc_cmap_addr2);
4357 * Unpin the thread before releasing the lock. Otherwise the thread
4358 * could be rescheduled while still bound to the current CPU, only
4359 * to unpin itself immediately upon resuming execution.
4362 mtx_unlock(&pc->pc_cmap_lock);
4366 * Zero an an area within a single hardware page. off and size must not
4367 * cover an area beyond a single hardware page.
4370 pmap_zero_page_area(vm_page_t m, int off, int size)
4372 pt_entry_t *cmap_pte2;
4377 cmap_pte2 = pc->pc_cmap_pte2;
4378 mtx_lock(&pc->pc_cmap_lock);
4380 panic("pmap_zero_page_area: CMAP2 busy");
4381 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4382 pmap_cache_bits(m->md.pat_mode, 0);
4383 invlcaddr(pc->pc_cmap_addr2);
4384 if (off == 0 && size == PAGE_SIZE)
4385 pagezero(pc->pc_cmap_addr2);
4387 bzero(pc->pc_cmap_addr2 + off, size);
4390 mtx_unlock(&pc->pc_cmap_lock);
4394 * Copy 1 specified hardware page to another.
4397 pmap_copy_page(vm_page_t src, vm_page_t dst)
4399 pt_entry_t *cmap_pte1, *cmap_pte2;
4404 cmap_pte1 = pc->pc_cmap_pte1;
4405 cmap_pte2 = pc->pc_cmap_pte2;
4406 mtx_lock(&pc->pc_cmap_lock);
4408 panic("pmap_copy_page: CMAP1 busy");
4410 panic("pmap_copy_page: CMAP2 busy");
4411 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4412 pmap_cache_bits(src->md.pat_mode, 0);
4413 invlcaddr(pc->pc_cmap_addr1);
4414 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4415 pmap_cache_bits(dst->md.pat_mode, 0);
4416 invlcaddr(pc->pc_cmap_addr2);
4417 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE);
4421 mtx_unlock(&pc->pc_cmap_lock);
4424 int unmapped_buf_allowed = 1;
4427 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4428 vm_offset_t b_offset, int xfersize)
4430 vm_page_t a_pg, b_pg;
4432 vm_offset_t a_pg_offset, b_pg_offset;
4433 pt_entry_t *cmap_pte1, *cmap_pte2;
4439 cmap_pte1 = pc->pc_cmap_pte1;
4440 cmap_pte2 = pc->pc_cmap_pte2;
4441 mtx_lock(&pc->pc_cmap_lock);
4442 if (*cmap_pte1 != 0)
4443 panic("pmap_copy_pages: CMAP1 busy");
4444 if (*cmap_pte2 != 0)
4445 panic("pmap_copy_pages: CMAP2 busy");
4446 while (xfersize > 0) {
4447 a_pg = ma[a_offset >> PAGE_SHIFT];
4448 a_pg_offset = a_offset & PAGE_MASK;
4449 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4450 b_pg = mb[b_offset >> PAGE_SHIFT];
4451 b_pg_offset = b_offset & PAGE_MASK;
4452 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4453 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4454 pmap_cache_bits(a_pg->md.pat_mode, 0);
4455 invlcaddr(pc->pc_cmap_addr1);
4456 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4457 PG_M | pmap_cache_bits(b_pg->md.pat_mode, 0);
4458 invlcaddr(pc->pc_cmap_addr2);
4459 a_cp = pc->pc_cmap_addr1 + a_pg_offset;
4460 b_cp = pc->pc_cmap_addr2 + b_pg_offset;
4461 bcopy(a_cp, b_cp, cnt);
4469 mtx_unlock(&pc->pc_cmap_lock);
4473 * Returns true if the pmap's pv is one of the first
4474 * 16 pvs linked to from this page. This count may
4475 * be changed upwards or downwards in the future; it
4476 * is only necessary that true be returned for a small
4477 * subset of pmaps for proper page aging.
4480 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4482 struct md_page *pvh;
4487 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4488 ("pmap_page_exists_quick: page %p is not managed", m));
4490 rw_wlock(&pvh_global_lock);
4491 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4492 if (PV_PMAP(pv) == pmap) {
4500 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4501 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4502 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4503 if (PV_PMAP(pv) == pmap) {
4512 rw_wunlock(&pvh_global_lock);
4517 * pmap_page_wired_mappings:
4519 * Return the number of managed mappings to the given physical page
4523 pmap_page_wired_mappings(vm_page_t m)
4528 if ((m->oflags & VPO_UNMANAGED) != 0)
4530 rw_wlock(&pvh_global_lock);
4531 count = pmap_pvh_wired_mappings(&m->md, count);
4532 if ((m->flags & PG_FICTITIOUS) == 0) {
4533 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4536 rw_wunlock(&pvh_global_lock);
4541 * pmap_pvh_wired_mappings:
4543 * Return the updated number "count" of managed mappings that are wired.
4546 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4552 rw_assert(&pvh_global_lock, RA_WLOCKED);
4554 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4557 pte = pmap_pte_quick(pmap, pv->pv_va);
4558 if ((*pte & PG_W) != 0)
4567 * Returns TRUE if the given page is mapped individually or as part of
4568 * a 4mpage. Otherwise, returns FALSE.
4571 pmap_page_is_mapped(vm_page_t m)
4575 if ((m->oflags & VPO_UNMANAGED) != 0)
4577 rw_wlock(&pvh_global_lock);
4578 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4579 ((m->flags & PG_FICTITIOUS) == 0 &&
4580 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4581 rw_wunlock(&pvh_global_lock);
4586 * Remove all pages from specified address space
4587 * this aids process exit speeds. Also, this code
4588 * is special cased for current process only, but
4589 * can have the more generic (and slightly slower)
4590 * mode enabled. This is much faster than pmap_remove
4591 * in the case of running down an entire address space.
4594 pmap_remove_pages(pmap_t pmap)
4596 pt_entry_t *pte, tpte;
4597 vm_page_t m, mpte, mt;
4599 struct md_page *pvh;
4600 struct pv_chunk *pc, *npc;
4601 struct spglist free;
4604 uint32_t inuse, bitmask;
4607 if (pmap != PCPU_GET(curpmap)) {
4608 printf("warning: pmap_remove_pages called with non-current pmap\n");
4612 rw_wlock(&pvh_global_lock);
4615 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4616 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4619 for (field = 0; field < _NPCM; field++) {
4620 inuse = ~pc->pc_map[field] & pc_freemask[field];
4621 while (inuse != 0) {
4623 bitmask = 1UL << bit;
4624 idx = field * 32 + bit;
4625 pv = &pc->pc_pventry[idx];
4628 pte = pmap_pde(pmap, pv->pv_va);
4630 if ((tpte & PG_PS) == 0) {
4631 pte = pmap_pte_quick(pmap, pv->pv_va);
4632 tpte = *pte & ~PG_PTE_PAT;
4637 "TPTE at %p IS ZERO @ VA %08x\n",
4643 * We cannot remove wired pages from a process' mapping at this time
4650 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4651 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4652 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4653 m, (uintmax_t)m->phys_addr,
4656 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4657 m < &vm_page_array[vm_page_array_size],
4658 ("pmap_remove_pages: bad tpte %#jx",
4664 * Update the vm_page_t clean/reference bits.
4666 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4667 if ((tpte & PG_PS) != 0) {
4668 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4675 PV_STAT(pv_entry_frees++);
4676 PV_STAT(pv_entry_spare++);
4678 pc->pc_map[field] |= bitmask;
4679 if ((tpte & PG_PS) != 0) {
4680 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4681 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4682 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4683 if (TAILQ_EMPTY(&pvh->pv_list)) {
4684 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4685 if (TAILQ_EMPTY(&mt->md.pv_list))
4686 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4688 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
4690 pmap->pm_stats.resident_count--;
4691 KASSERT(mpte->wire_count == NPTEPG,
4692 ("pmap_remove_pages: pte page wire count error"));
4693 mpte->wire_count = 0;
4694 pmap_add_delayed_free_list(mpte, &free, FALSE);
4697 pmap->pm_stats.resident_count--;
4698 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4699 if (TAILQ_EMPTY(&m->md.pv_list) &&
4700 (m->flags & PG_FICTITIOUS) == 0) {
4701 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4702 if (TAILQ_EMPTY(&pvh->pv_list))
4703 vm_page_aflag_clear(m, PGA_WRITEABLE);
4705 pmap_unuse_pt(pmap, pv->pv_va, &free);
4710 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4715 pmap_invalidate_all(pmap);
4716 rw_wunlock(&pvh_global_lock);
4718 vm_page_free_pages_toq(&free, true);
4724 * Return whether or not the specified physical page was modified
4725 * in any physical maps.
4728 pmap_is_modified(vm_page_t m)
4732 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4733 ("pmap_is_modified: page %p is not managed", m));
4736 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4737 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4738 * is clear, no PTEs can have PG_M set.
4740 VM_OBJECT_ASSERT_WLOCKED(m->object);
4741 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4743 rw_wlock(&pvh_global_lock);
4744 rv = pmap_is_modified_pvh(&m->md) ||
4745 ((m->flags & PG_FICTITIOUS) == 0 &&
4746 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4747 rw_wunlock(&pvh_global_lock);
4752 * Returns TRUE if any of the given mappings were used to modify
4753 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4754 * mappings are supported.
4757 pmap_is_modified_pvh(struct md_page *pvh)
4764 rw_assert(&pvh_global_lock, RA_WLOCKED);
4767 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4770 pte = pmap_pte_quick(pmap, pv->pv_va);
4771 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4781 * pmap_is_prefaultable:
4783 * Return whether or not the specified virtual address is elgible
4787 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4794 pde = *pmap_pde(pmap, addr);
4795 if (pde != 0 && (pde & PG_PS) == 0)
4796 rv = pmap_pte_ufast(pmap, addr, pde) == 0;
4802 * pmap_is_referenced:
4804 * Return whether or not the specified physical page was referenced
4805 * in any physical maps.
4808 pmap_is_referenced(vm_page_t m)
4812 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4813 ("pmap_is_referenced: page %p is not managed", m));
4814 rw_wlock(&pvh_global_lock);
4815 rv = pmap_is_referenced_pvh(&m->md) ||
4816 ((m->flags & PG_FICTITIOUS) == 0 &&
4817 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4818 rw_wunlock(&pvh_global_lock);
4823 * Returns TRUE if any of the given mappings were referenced and FALSE
4824 * otherwise. Both page and 4mpage mappings are supported.
4827 pmap_is_referenced_pvh(struct md_page *pvh)
4834 rw_assert(&pvh_global_lock, RA_WLOCKED);
4837 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4840 pte = pmap_pte_quick(pmap, pv->pv_va);
4841 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4851 * Clear the write and modified bits in each of the given page's mappings.
4854 pmap_remove_write(vm_page_t m)
4856 struct md_page *pvh;
4857 pv_entry_t next_pv, pv;
4860 pt_entry_t oldpte, *pte;
4863 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4864 ("pmap_remove_write: page %p is not managed", m));
4867 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4868 * set by another thread while the object is locked. Thus,
4869 * if PGA_WRITEABLE is clear, no page table entries need updating.
4871 VM_OBJECT_ASSERT_WLOCKED(m->object);
4872 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4874 rw_wlock(&pvh_global_lock);
4876 if ((m->flags & PG_FICTITIOUS) != 0)
4877 goto small_mappings;
4878 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4879 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4883 pde = pmap_pde(pmap, va);
4884 if ((*pde & PG_RW) != 0)
4885 (void)pmap_demote_pde(pmap, pde, va);
4889 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4892 pde = pmap_pde(pmap, pv->pv_va);
4893 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
4894 " a 4mpage in page %p's pv list", m));
4895 pte = pmap_pte_quick(pmap, pv->pv_va);
4898 if ((oldpte & PG_RW) != 0) {
4900 * Regardless of whether a pte is 32 or 64 bits
4901 * in size, PG_RW and PG_M are among the least
4902 * significant 32 bits.
4904 if (!atomic_cmpset_int((u_int *)pte, oldpte,
4905 oldpte & ~(PG_RW | PG_M)))
4907 if ((oldpte & PG_M) != 0)
4909 pmap_invalidate_page(pmap, pv->pv_va);
4913 vm_page_aflag_clear(m, PGA_WRITEABLE);
4915 rw_wunlock(&pvh_global_lock);
4919 * pmap_ts_referenced:
4921 * Return a count of reference bits for a page, clearing those bits.
4922 * It is not necessary for every reference bit to be cleared, but it
4923 * is necessary that 0 only be returned when there are truly no
4924 * reference bits set.
4926 * As an optimization, update the page's dirty field if a modified bit is
4927 * found while counting reference bits. This opportunistic update can be
4928 * performed at low cost and can eliminate the need for some future calls
4929 * to pmap_is_modified(). However, since this function stops after
4930 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4931 * dirty pages. Those dirty pages will only be detected by a future call
4932 * to pmap_is_modified().
4935 pmap_ts_referenced(vm_page_t m)
4937 struct md_page *pvh;
4945 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4946 ("pmap_ts_referenced: page %p is not managed", m));
4947 pa = VM_PAGE_TO_PHYS(m);
4948 pvh = pa_to_pvh(pa);
4949 rw_wlock(&pvh_global_lock);
4951 if ((m->flags & PG_FICTITIOUS) != 0 ||
4952 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4953 goto small_mappings;
4958 pde = pmap_pde(pmap, pv->pv_va);
4959 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4961 * Although "*pde" is mapping a 2/4MB page, because
4962 * this function is called at a 4KB page granularity,
4963 * we only update the 4KB page under test.
4967 if ((*pde & PG_A) != 0) {
4969 * Since this reference bit is shared by either 1024
4970 * or 512 4KB pages, it should not be cleared every
4971 * time it is tested. Apply a simple "hash" function
4972 * on the physical page number, the virtual superpage
4973 * number, and the pmap address to select one 4KB page
4974 * out of the 1024 or 512 on which testing the
4975 * reference bit will result in clearing that bit.
4976 * This function is designed to avoid the selection of
4977 * the same 4KB page for every 2- or 4MB page mapping.
4979 * On demotion, a mapping that hasn't been referenced
4980 * is simply destroyed. To avoid the possibility of a
4981 * subsequent page fault on a demoted wired mapping,
4982 * always leave its reference bit set. Moreover,
4983 * since the superpage is wired, the current state of
4984 * its reference bit won't affect page replacement.
4986 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
4987 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
4988 (*pde & PG_W) == 0) {
4989 atomic_clear_int((u_int *)pde, PG_A);
4990 pmap_invalidate_page(pmap, pv->pv_va);
4995 /* Rotate the PV list if it has more than one entry. */
4996 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4997 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4998 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5000 if (rtval >= PMAP_TS_REFERENCED_MAX)
5002 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5004 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5010 pde = pmap_pde(pmap, pv->pv_va);
5011 KASSERT((*pde & PG_PS) == 0,
5012 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
5014 pte = pmap_pte_quick(pmap, pv->pv_va);
5015 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5017 if ((*pte & PG_A) != 0) {
5018 atomic_clear_int((u_int *)pte, PG_A);
5019 pmap_invalidate_page(pmap, pv->pv_va);
5023 /* Rotate the PV list if it has more than one entry. */
5024 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5025 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5026 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5028 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
5029 PMAP_TS_REFERENCED_MAX);
5032 rw_wunlock(&pvh_global_lock);
5037 * Apply the given advice to the specified range of addresses within the
5038 * given pmap. Depending on the advice, clear the referenced and/or
5039 * modified flags in each mapping and set the mapped page's dirty field.
5042 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5044 pd_entry_t oldpde, *pde;
5046 vm_offset_t va, pdnxt;
5048 boolean_t anychanged, pv_lists_locked;
5050 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5052 if (pmap_is_current(pmap))
5053 pv_lists_locked = FALSE;
5055 pv_lists_locked = TRUE;
5057 rw_wlock(&pvh_global_lock);
5062 for (; sva < eva; sva = pdnxt) {
5063 pdnxt = (sva + NBPDR) & ~PDRMASK;
5066 pde = pmap_pde(pmap, sva);
5068 if ((oldpde & PG_V) == 0)
5070 else if ((oldpde & PG_PS) != 0) {
5071 if ((oldpde & PG_MANAGED) == 0)
5073 if (!pv_lists_locked) {
5074 pv_lists_locked = TRUE;
5075 if (!rw_try_wlock(&pvh_global_lock)) {
5077 pmap_invalidate_all(pmap);
5083 if (!pmap_demote_pde(pmap, pde, sva)) {
5085 * The large page mapping was destroyed.
5091 * Unless the page mappings are wired, remove the
5092 * mapping to a single page so that a subsequent
5093 * access may repromote. Since the underlying page
5094 * table page is fully populated, this removal never
5095 * frees a page table page.
5097 if ((oldpde & PG_W) == 0) {
5098 pte = pmap_pte_quick(pmap, sva);
5099 KASSERT((*pte & PG_V) != 0,
5100 ("pmap_advise: invalid PTE"));
5101 pmap_remove_pte(pmap, pte, sva, NULL);
5108 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
5110 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
5112 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5113 if (advice == MADV_DONTNEED) {
5115 * Future calls to pmap_is_modified()
5116 * can be avoided by making the page
5119 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
5122 atomic_clear_int((u_int *)pte, PG_M | PG_A);
5123 } else if ((*pte & PG_A) != 0)
5124 atomic_clear_int((u_int *)pte, PG_A);
5127 if ((*pte & PG_G) != 0) {
5135 pmap_invalidate_range(pmap, va, sva);
5140 pmap_invalidate_range(pmap, va, sva);
5143 pmap_invalidate_all(pmap);
5144 if (pv_lists_locked) {
5146 rw_wunlock(&pvh_global_lock);
5152 * Clear the modify bits on the specified physical page.
5155 pmap_clear_modify(vm_page_t m)
5157 struct md_page *pvh;
5158 pv_entry_t next_pv, pv;
5160 pd_entry_t oldpde, *pde;
5161 pt_entry_t oldpte, *pte;
5164 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5165 ("pmap_clear_modify: page %p is not managed", m));
5166 VM_OBJECT_ASSERT_WLOCKED(m->object);
5167 KASSERT(!vm_page_xbusied(m),
5168 ("pmap_clear_modify: page %p is exclusive busied", m));
5171 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5172 * If the object containing the page is locked and the page is not
5173 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5175 if ((m->aflags & PGA_WRITEABLE) == 0)
5177 rw_wlock(&pvh_global_lock);
5179 if ((m->flags & PG_FICTITIOUS) != 0)
5180 goto small_mappings;
5181 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5182 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5186 pde = pmap_pde(pmap, va);
5188 if ((oldpde & PG_RW) != 0) {
5189 if (pmap_demote_pde(pmap, pde, va)) {
5190 if ((oldpde & PG_W) == 0) {
5192 * Write protect the mapping to a
5193 * single page so that a subsequent
5194 * write access may repromote.
5196 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5198 pte = pmap_pte_quick(pmap, va);
5200 if ((oldpte & PG_V) != 0) {
5202 * Regardless of whether a pte is 32 or 64 bits
5203 * in size, PG_RW and PG_M are among the least
5204 * significant 32 bits.
5206 while (!atomic_cmpset_int((u_int *)pte,
5208 oldpte & ~(PG_M | PG_RW)))
5211 pmap_invalidate_page(pmap, va);
5219 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5222 pde = pmap_pde(pmap, pv->pv_va);
5223 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5224 " a 4mpage in page %p's pv list", m));
5225 pte = pmap_pte_quick(pmap, pv->pv_va);
5226 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5228 * Regardless of whether a pte is 32 or 64 bits
5229 * in size, PG_M is among the least significant
5232 atomic_clear_int((u_int *)pte, PG_M);
5233 pmap_invalidate_page(pmap, pv->pv_va);
5238 rw_wunlock(&pvh_global_lock);
5242 * Miscellaneous support routines follow
5245 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5246 static __inline void
5247 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5252 * The cache mode bits are all in the low 32-bits of the
5253 * PTE, so we can just spin on updating the low 32-bits.
5256 opte = *(u_int *)pte;
5257 npte = opte & ~PG_PTE_CACHE;
5259 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5262 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5263 static __inline void
5264 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5269 * The cache mode bits are all in the low 32-bits of the
5270 * PDE, so we can just spin on updating the low 32-bits.
5273 opde = *(u_int *)pde;
5274 npde = opde & ~PG_PDE_CACHE;
5276 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5280 * Map a set of physical memory pages into the kernel virtual
5281 * address space. Return a pointer to where it is mapped. This
5282 * routine is intended to be used for mapping device memory,
5286 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5288 struct pmap_preinit_mapping *ppim;
5289 vm_offset_t va, offset;
5293 offset = pa & PAGE_MASK;
5294 size = round_page(offset + size);
5297 if (pa < PMAP_MAP_LOW && pa + size <= PMAP_MAP_LOW)
5298 va = pa + PMAP_MAP_LOW;
5299 else if (!pmap_initialized) {
5301 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5302 ppim = pmap_preinit_mapping + i;
5303 if (ppim->va == 0) {
5307 ppim->va = virtual_avail;
5308 virtual_avail += size;
5314 panic("%s: too many preinit mappings", __func__);
5317 * If we have a preinit mapping, re-use it.
5319 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5320 ppim = pmap_preinit_mapping + i;
5321 if (ppim->pa == pa && ppim->sz == size &&
5323 return ((void *)(ppim->va + offset));
5325 va = kva_alloc(size);
5327 panic("%s: Couldn't allocate KVA", __func__);
5329 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5330 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5331 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5332 pmap_invalidate_cache_range(va, va + size, FALSE);
5333 return ((void *)(va + offset));
5337 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5340 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5344 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5347 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5351 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5353 struct pmap_preinit_mapping *ppim;
5357 if (va >= PMAP_MAP_LOW && va <= KERNBASE && va + size <= KERNBASE)
5359 offset = va & PAGE_MASK;
5360 size = round_page(offset + size);
5361 va = trunc_page(va);
5362 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5363 ppim = pmap_preinit_mapping + i;
5364 if (ppim->va == va && ppim->sz == size) {
5365 if (pmap_initialized)
5371 if (va + size == virtual_avail)
5376 if (pmap_initialized)
5381 * Sets the memory attribute for the specified page.
5384 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5387 m->md.pat_mode = ma;
5388 if ((m->flags & PG_FICTITIOUS) != 0)
5392 * If "m" is a normal page, flush it from the cache.
5393 * See pmap_invalidate_cache_range().
5395 * First, try to find an existing mapping of the page by sf
5396 * buffer. sf_buf_invalidate_cache() modifies mapping and
5397 * flushes the cache.
5399 if (sf_buf_invalidate_cache(m))
5403 * If page is not mapped by sf buffer, but CPU does not
5404 * support self snoop, map the page transient and do
5405 * invalidation. In the worst case, whole cache is flushed by
5406 * pmap_invalidate_cache_range().
5408 if ((cpu_feature & CPUID_SS) == 0)
5413 pmap_flush_page(vm_page_t m)
5415 pt_entry_t *cmap_pte2;
5417 vm_offset_t sva, eva;
5420 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5421 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5424 cmap_pte2 = pc->pc_cmap_pte2;
5425 mtx_lock(&pc->pc_cmap_lock);
5427 panic("pmap_flush_page: CMAP2 busy");
5428 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5429 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0);
5430 invlcaddr(pc->pc_cmap_addr2);
5431 sva = (vm_offset_t)pc->pc_cmap_addr2;
5432 eva = sva + PAGE_SIZE;
5435 * Use mfence or sfence despite the ordering implied by
5436 * mtx_{un,}lock() because clflush on non-Intel CPUs
5437 * and clflushopt are not guaranteed to be ordered by
5438 * any other instruction.
5442 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5444 for (; sva < eva; sva += cpu_clflush_line_size) {
5452 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5456 mtx_unlock(&pc->pc_cmap_lock);
5458 pmap_invalidate_cache();
5462 * Changes the specified virtual address range's memory type to that given by
5463 * the parameter "mode". The specified virtual address range must be
5464 * completely contained within either the kernel map.
5466 * Returns zero if the change completed successfully, and either EINVAL or
5467 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5468 * of the virtual address range was not mapped, and ENOMEM is returned if
5469 * there was insufficient memory available to complete the change.
5472 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5474 vm_offset_t base, offset, tmpva;
5477 int cache_bits_pte, cache_bits_pde;
5480 base = trunc_page(va);
5481 offset = va & PAGE_MASK;
5482 size = round_page(offset + size);
5485 * Only supported on kernel virtual addresses above the recursive map.
5487 if (base < VM_MIN_KERNEL_ADDRESS)
5490 cache_bits_pde = pmap_cache_bits(mode, 1);
5491 cache_bits_pte = pmap_cache_bits(mode, 0);
5495 * Pages that aren't mapped aren't supported. Also break down
5496 * 2/4MB pages into 4KB pages if required.
5498 PMAP_LOCK(kernel_pmap);
5499 for (tmpva = base; tmpva < base + size; ) {
5500 pde = pmap_pde(kernel_pmap, tmpva);
5502 PMAP_UNLOCK(kernel_pmap);
5507 * If the current 2/4MB page already has
5508 * the required memory type, then we need not
5509 * demote this page. Just increment tmpva to
5510 * the next 2/4MB page frame.
5512 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5513 tmpva = trunc_4mpage(tmpva) + NBPDR;
5518 * If the current offset aligns with a 2/4MB
5519 * page frame and there is at least 2/4MB left
5520 * within the range, then we need not break
5521 * down this page into 4KB pages.
5523 if ((tmpva & PDRMASK) == 0 &&
5524 tmpva + PDRMASK < base + size) {
5528 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5529 PMAP_UNLOCK(kernel_pmap);
5533 pte = vtopte(tmpva);
5535 PMAP_UNLOCK(kernel_pmap);
5540 PMAP_UNLOCK(kernel_pmap);
5543 * Ok, all the pages exist, so run through them updating their
5544 * cache mode if required.
5546 for (tmpva = base; tmpva < base + size; ) {
5547 pde = pmap_pde(kernel_pmap, tmpva);
5549 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5550 pmap_pde_attr(pde, cache_bits_pde);
5553 tmpva = trunc_4mpage(tmpva) + NBPDR;
5555 pte = vtopte(tmpva);
5556 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5557 pmap_pte_attr(pte, cache_bits_pte);
5565 * Flush CPU caches to make sure any data isn't cached that
5566 * shouldn't be, etc.
5569 pmap_invalidate_range(kernel_pmap, base, tmpva);
5570 pmap_invalidate_cache_range(base, tmpva, FALSE);
5576 * perform the pmap work for mincore
5579 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5588 pde = *pmap_pde(pmap, addr);
5590 if ((pde & PG_PS) != 0) {
5592 /* Compute the physical address of the 4KB page. */
5593 pa = ((pde & PG_PS_FRAME) | (addr & PDRMASK)) &
5595 val = MINCORE_SUPER;
5597 pte = pmap_pte_ufast(pmap, addr, pde);
5598 pa = pte & PG_FRAME;
5606 if ((pte & PG_V) != 0) {
5607 val |= MINCORE_INCORE;
5608 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5609 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5610 if ((pte & PG_A) != 0)
5611 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5613 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5614 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5615 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5616 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5617 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5620 PA_UNLOCK_COND(*locked_pa);
5626 pmap_activate(struct thread *td)
5628 pmap_t pmap, oldpmap;
5633 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5634 oldpmap = PCPU_GET(curpmap);
5635 cpuid = PCPU_GET(cpuid);
5637 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5638 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5640 CPU_CLR(cpuid, &oldpmap->pm_active);
5641 CPU_SET(cpuid, &pmap->pm_active);
5643 #if defined(PAE) || defined(PAE_TABLES)
5644 cr3 = vtophys(pmap->pm_pdpt);
5646 cr3 = vtophys(pmap->pm_pdir);
5649 * pmap_activate is for the current thread on the current cpu
5651 td->td_pcb->pcb_cr3 = cr3;
5652 PCPU_SET(curpmap, pmap);
5657 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5662 * Increase the starting virtual address of the given mapping if a
5663 * different alignment might result in more superpage mappings.
5666 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5667 vm_offset_t *addr, vm_size_t size)
5669 vm_offset_t superpage_offset;
5673 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5674 offset += ptoa(object->pg_color);
5675 superpage_offset = offset & PDRMASK;
5676 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5677 (*addr & PDRMASK) == superpage_offset)
5679 if ((*addr & PDRMASK) < superpage_offset)
5680 *addr = (*addr & ~PDRMASK) + superpage_offset;
5682 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5686 pmap_quick_enter_page(vm_page_t m)
5692 qaddr = PCPU_GET(qmap_addr);
5693 pte = vtopte(qaddr);
5695 KASSERT(*pte == 0, ("pmap_quick_enter_page: PTE busy"));
5696 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5697 pmap_cache_bits(pmap_page_get_memattr(m), 0);
5704 pmap_quick_remove_page(vm_offset_t addr)
5709 qaddr = PCPU_GET(qmap_addr);
5710 pte = vtopte(qaddr);
5712 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5713 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5719 static vmem_t *pmap_trm_arena;
5720 static vmem_addr_t pmap_trm_arena_last = PMAP_TRM_MIN_ADDRESS;
5721 static int trm_guard = PAGE_SIZE;
5724 pmap_trm_import(void *unused __unused, vmem_size_t size, int flags,
5728 vmem_addr_t af, addr, prev_addr;
5729 pt_entry_t *trm_pte;
5731 prev_addr = atomic_load_long(&pmap_trm_arena_last);
5732 size = round_page(size) + trm_guard;
5734 if (prev_addr + size < prev_addr || prev_addr + size < size ||
5735 prev_addr + size > PMAP_TRM_MAX_ADDRESS)
5737 addr = prev_addr + size;
5738 if (atomic_fcmpset_int(&pmap_trm_arena_last, &prev_addr, addr))
5741 prev_addr += trm_guard;
5742 trm_pte = PTmap + atop(prev_addr);
5743 for (af = prev_addr; af < addr; af += PAGE_SIZE) {
5744 m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5745 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
5746 pte_store(&trm_pte[atop(af - prev_addr)], VM_PAGE_TO_PHYS(m) |
5747 PG_M | PG_A | PG_RW | PG_V | pgeflag |
5748 pmap_cache_bits(VM_MEMATTR_DEFAULT, FALSE));
5755 void pmap_init_trm(void)
5759 TUNABLE_INT_FETCH("machdep.trm_guard", &trm_guard);
5760 if ((trm_guard & PAGE_MASK) != 0)
5762 pmap_trm_arena = vmem_create("i386trampoline", 0, 0, 1, 0, M_WAITOK);
5763 vmem_set_import(pmap_trm_arena, pmap_trm_import, NULL, NULL, PAGE_SIZE);
5764 pd_m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5765 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK | VM_ALLOC_ZERO);
5766 if ((pd_m->flags & PG_ZERO) == 0)
5767 pmap_zero_page(pd_m);
5768 PTD[TRPTDI] = VM_PAGE_TO_PHYS(pd_m) | PG_M | PG_A | PG_RW | PG_V |
5769 pmap_cache_bits(VM_MEMATTR_DEFAULT, TRUE);
5773 pmap_trm_alloc(size_t size, int flags)
5778 MPASS((flags & ~(M_WAITOK | M_NOWAIT | M_ZERO)) == 0);
5779 error = vmem_xalloc(pmap_trm_arena, roundup2(size, 4), sizeof(int),
5780 0, 0, VMEM_ADDR_MIN, VMEM_ADDR_MAX, flags | M_FIRSTFIT, &res);
5783 if ((flags & M_ZERO) != 0)
5784 bzero((void *)res, size);
5785 return ((void *)res);
5789 pmap_trm_free(void *addr, size_t size)
5792 vmem_free(pmap_trm_arena, (uintptr_t)addr, roundup2(size, 4));
5795 #if defined(PMAP_DEBUG)
5796 pmap_pid_dump(int pid)
5803 sx_slock(&allproc_lock);
5804 FOREACH_PROC_IN_SYSTEM(p) {
5805 if (p->p_pid != pid)
5811 pmap = vmspace_pmap(p->p_vmspace);
5812 for (i = 0; i < NPDEPTD; i++) {
5815 vm_offset_t base = i << PDRSHIFT;
5817 pde = &pmap->pm_pdir[i];
5818 if (pde && pmap_pde_v(pde)) {
5819 for (j = 0; j < NPTEPG; j++) {
5820 vm_offset_t va = base + (j << PAGE_SHIFT);
5821 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5826 sx_sunlock(&allproc_lock);
5829 pte = pmap_pte(pmap, va);
5830 if (pte && pmap_pte_v(pte)) {
5834 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5835 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5836 va, pa, m->hold_count, m->wire_count, m->flags);
5851 sx_sunlock(&allproc_lock);