2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * This code is derived from software contributed to Berkeley by
12 * the Systems Programming Group of the University of Utah Computer
13 * Science Department and William Jolitz of UUNET Technologies Inc.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 * must display the following acknowledgement:
25 * This product includes software developed by the University of
26 * California, Berkeley and its contributors.
27 * 4. Neither the name of the University nor the names of its contributors
28 * may be used to endorse or promote products derived from this software
29 * without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
46 * Copyright (c) 2003 Networks Associates Technology, Inc.
47 * All rights reserved.
49 * This software was developed for the FreeBSD Project by Jake Burkholder,
50 * Safeport Network Services, and Network Associates Laboratories, the
51 * Security Research Division of Network Associates, Inc. under
52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
53 * CHATS research program.
55 * Redistribution and use in source and binary forms, with or without
56 * modification, are permitted provided that the following conditions
58 * 1. Redistributions of source code must retain the above copyright
59 * notice, this list of conditions and the following disclaimer.
60 * 2. Redistributions in binary form must reproduce the above copyright
61 * notice, this list of conditions and the following disclaimer in the
62 * documentation and/or other materials provided with the distribution.
64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
77 #include <sys/cdefs.h>
78 __FBSDID("$FreeBSD$");
81 * Manages physical address maps.
83 * Since the information managed by this module is
84 * also stored by the logical address mapping module,
85 * this module may throw away valid virtual-to-physical
86 * mappings at almost any time. However, invalidations
87 * of virtual-to-physical mappings must be done as
90 * In order to cope with hardware architectures which
91 * make virtual-to-physical map invalidates expensive,
92 * this module may delay invalidate or reduced protection
93 * operations until such time as they are actually
94 * necessary. This module is given full information as
95 * to which processors are currently using which maps,
96 * and to when physical maps must be made correct.
101 #include "opt_pmap.h"
103 #include "opt_xbox.h"
105 #include <sys/param.h>
106 #include <sys/systm.h>
107 #include <sys/kernel.h>
109 #include <sys/lock.h>
110 #include <sys/malloc.h>
111 #include <sys/mman.h>
112 #include <sys/msgbuf.h>
113 #include <sys/mutex.h>
114 #include <sys/proc.h>
115 #include <sys/rwlock.h>
116 #include <sys/sf_buf.h>
118 #include <sys/vmmeter.h>
119 #include <sys/sched.h>
120 #include <sys/sysctl.h>
124 #include <vm/vm_param.h>
125 #include <vm/vm_kern.h>
126 #include <vm/vm_page.h>
127 #include <vm/vm_map.h>
128 #include <vm/vm_object.h>
129 #include <vm/vm_extern.h>
130 #include <vm/vm_pageout.h>
131 #include <vm/vm_pager.h>
132 #include <vm/vm_phys.h>
133 #include <vm/vm_radix.h>
134 #include <vm/vm_reserv.h>
139 #include <machine/intr_machdep.h>
140 #include <x86/apicvar.h>
142 #include <machine/cpu.h>
143 #include <machine/cputypes.h>
144 #include <machine/md_var.h>
145 #include <machine/pcb.h>
146 #include <machine/specialreg.h>
148 #include <machine/smp.h>
152 #include <machine/xbox.h>
155 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
156 #define CPU_ENABLE_SSE
159 #ifndef PMAP_SHPGPERPROC
160 #define PMAP_SHPGPERPROC 200
163 #if !defined(DIAGNOSTIC)
164 #ifdef __GNUC_GNU_INLINE__
165 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
167 #define PMAP_INLINE extern inline
174 #define PV_STAT(x) do { x ; } while (0)
176 #define PV_STAT(x) do { } while (0)
179 #define pa_index(pa) ((pa) >> PDRSHIFT)
180 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
183 * Get PDEs and PTEs for user/kernel address space
185 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
186 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
188 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
189 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
190 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
191 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
192 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
194 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
195 atomic_clear_int((u_int *)(pte), PG_W))
196 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
198 struct pmap kernel_pmap_store;
199 LIST_HEAD(pmaplist, pmap);
200 static struct pmaplist allpmaps;
201 static struct mtx allpmaps_lock;
203 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
204 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
205 int pgeflag = 0; /* PG_G or-in */
206 int pseflag = 0; /* PG_PS or-in */
208 static int nkpt = NKPT;
209 vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR;
210 extern u_int32_t KERNend;
211 extern u_int32_t KPTphys;
213 #if defined(PAE) || defined(PAE_TABLES)
215 static uma_zone_t pdptzone;
218 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
220 static int pat_works = 1;
221 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
222 "Is page attribute table fully functional?");
224 static int pg_ps_enabled = 1;
225 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
226 &pg_ps_enabled, 0, "Are large page mappings enabled?");
228 #define PAT_INDEX_SIZE 8
229 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
232 * pmap_mapdev support pre initialization (i.e. console)
234 #define PMAP_PREINIT_MAPPING_COUNT 8
235 static struct pmap_preinit_mapping {
240 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
241 static int pmap_initialized;
243 static struct rwlock_padalign pvh_global_lock;
246 * Data for the pv entry allocation mechanism
248 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
249 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
250 static struct md_page *pv_table;
251 static int shpgperproc = PMAP_SHPGPERPROC;
253 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
254 int pv_maxchunks; /* How many chunks we have KVA for */
255 vm_offset_t pv_vafree; /* freelist stored in the PTE */
258 * All those kernel PT submaps that BSD is so fond of
267 static struct sysmaps sysmaps_pcpu[MAXCPU];
269 static pd_entry_t *KPTD;
272 struct msgbuf *msgbufp = NULL;
277 static caddr_t crashdumpmap;
279 static pt_entry_t *PMAP1 = NULL, *PMAP2;
280 static pt_entry_t *PADDR1 = NULL, *PADDR2;
283 static int PMAP1changedcpu;
284 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
286 "Number of times pmap_pte_quick changed CPU with same PMAP1");
288 static int PMAP1changed;
289 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
291 "Number of times pmap_pte_quick changed PMAP1");
292 static int PMAP1unchanged;
293 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
295 "Number of times pmap_pte_quick didn't change PMAP1");
296 static struct mtx PMAP2mutex;
298 static void free_pv_chunk(struct pv_chunk *pc);
299 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
300 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
301 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
302 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
303 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
304 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
305 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
307 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
309 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
310 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
312 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
313 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
314 static void pmap_flush_page(vm_page_t m);
315 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
316 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
317 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
318 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
319 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
320 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
321 static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va);
322 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
323 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
324 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
326 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
327 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
328 struct spglist *free);
329 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
330 struct spglist *free);
331 static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte);
332 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
333 struct spglist *free);
334 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
336 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
337 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
339 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
341 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
343 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
345 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
346 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
347 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
348 static void pmap_pte_release(pt_entry_t *pte);
349 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
350 #if defined(PAE) || defined(PAE_TABLES)
351 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, uint8_t *flags,
354 static void pmap_set_pg(void);
356 static __inline void pagezero(void *page);
358 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
359 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
362 * If you get an error here, then you set KVA_PAGES wrong! See the
363 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be
364 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE.
366 CTASSERT(KERNBASE % (1 << 24) == 0);
369 * Bootstrap the system enough to run with virtual memory.
371 * On the i386 this is called after mapping has already been enabled
372 * and just syncs the pmap module with what has already been done.
373 * [We can't call it easily with mapping off since the kernel is not
374 * mapped with PA == VA, hence we would have to relocate every address
375 * from the linked base (virtual) address "KERNBASE" to the actual
376 * (physical) address starting relative to 0]
379 pmap_bootstrap(vm_paddr_t firstaddr)
382 pt_entry_t *pte, *unused;
383 struct sysmaps *sysmaps;
387 * Add a physical memory segment (vm_phys_seg) corresponding to the
388 * preallocated kernel page table pages so that vm_page structures
389 * representing these pages will be created. The vm_page structures
390 * are required for promotion of the corresponding kernel virtual
391 * addresses to superpage mappings.
393 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
396 * Initialize the first available kernel virtual address. However,
397 * using "firstaddr" may waste a few pages of the kernel virtual
398 * address space, because locore may not have mapped every physical
399 * page that it allocated. Preferably, locore would provide a first
400 * unused virtual address in addition to "firstaddr".
402 virtual_avail = (vm_offset_t) KERNBASE + firstaddr;
404 virtual_end = VM_MAX_KERNEL_ADDRESS;
407 * Initialize the kernel pmap (which is statically allocated).
409 PMAP_LOCK_INIT(kernel_pmap);
410 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD);
411 #if defined(PAE) || defined(PAE_TABLES)
412 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT);
414 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
415 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
418 * Initialize the global pv list lock.
420 rw_init(&pvh_global_lock, "pmap pv global");
422 LIST_INIT(&allpmaps);
425 * Request a spin mutex so that changes to allpmaps cannot be
426 * preempted by smp_rendezvous_cpus(). Otherwise,
427 * pmap_update_pde_kernel() could access allpmaps while it is
430 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
431 mtx_lock_spin(&allpmaps_lock);
432 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
433 mtx_unlock_spin(&allpmaps_lock);
436 * Reserve some special page table entries/VA space for temporary
439 #define SYSMAP(c, p, v, n) \
440 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
446 * CMAP1/CMAP2 are used for zeroing and copying pages.
447 * CMAP3 is used for the boot-time memory test.
449 for (i = 0; i < MAXCPU; i++) {
450 sysmaps = &sysmaps_pcpu[i];
451 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF);
452 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1)
453 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1)
455 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
460 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
463 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
465 SYSMAP(caddr_t, unused, ptvmmap, 1)
468 * msgbufp is used to map the system message buffer.
470 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
473 * KPTmap is used by pmap_kextract().
475 * KPTmap is first initialized by locore. However, that initial
476 * KPTmap can only support NKPT page table pages. Here, a larger
477 * KPTmap is created that can support KVA_PAGES page table pages.
479 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
481 for (i = 0; i < NKPT; i++)
482 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V;
485 * Adjust the start of the KPTD and KPTmap so that the implementation
486 * of pmap_kextract() and pmap_growkernel() can be made simpler.
489 KPTmap -= i386_btop(KPTDI << PDRSHIFT);
492 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
495 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
496 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
498 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
503 * Leave in place an identity mapping (virt == phys) for the low 1 MB
504 * physical memory region that is used by the ACPI wakeup code. This
505 * mapping must not have PG_G set.
508 /* FIXME: This is gross, but needed for the XBOX. Since we are in such
509 * an early stadium, we cannot yet neatly map video memory ... :-(
510 * Better fixes are very welcome! */
511 if (!arch_i386_is_xbox)
513 for (i = 1; i < NKPT; i++)
516 /* Initialize the PAT MSR if present. */
519 /* Turn on PG_G on kernel page(s) */
524 pmap_init_qpages(void)
531 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE);
532 if (pc->pc_qmap_addr == 0)
533 panic("pmap_init_qpages: unable to allocate KVA");
537 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_qpages, NULL);
545 int pat_table[PAT_INDEX_SIZE];
550 /* Set default PAT index table. */
551 for (i = 0; i < PAT_INDEX_SIZE; i++)
553 pat_table[PAT_WRITE_BACK] = 0;
554 pat_table[PAT_WRITE_THROUGH] = 1;
555 pat_table[PAT_UNCACHEABLE] = 3;
556 pat_table[PAT_WRITE_COMBINING] = 3;
557 pat_table[PAT_WRITE_PROTECTED] = 3;
558 pat_table[PAT_UNCACHED] = 3;
560 /* Bail if this CPU doesn't implement PAT. */
561 if ((cpu_feature & CPUID_PAT) == 0) {
562 for (i = 0; i < PAT_INDEX_SIZE; i++)
563 pat_index[i] = pat_table[i];
569 * Due to some Intel errata, we can only safely use the lower 4
572 * Intel Pentium III Processor Specification Update
573 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
576 * Intel Pentium IV Processor Specification Update
577 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
579 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
580 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
583 /* Initialize default PAT entries. */
584 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
585 PAT_VALUE(1, PAT_WRITE_THROUGH) |
586 PAT_VALUE(2, PAT_UNCACHED) |
587 PAT_VALUE(3, PAT_UNCACHEABLE) |
588 PAT_VALUE(4, PAT_WRITE_BACK) |
589 PAT_VALUE(5, PAT_WRITE_THROUGH) |
590 PAT_VALUE(6, PAT_UNCACHED) |
591 PAT_VALUE(7, PAT_UNCACHEABLE);
595 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
596 * Program 5 and 6 as WP and WC.
597 * Leave 4 and 7 as WB and UC.
599 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
600 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
601 PAT_VALUE(6, PAT_WRITE_COMBINING);
602 pat_table[PAT_UNCACHED] = 2;
603 pat_table[PAT_WRITE_PROTECTED] = 5;
604 pat_table[PAT_WRITE_COMBINING] = 6;
607 * Just replace PAT Index 2 with WC instead of UC-.
609 pat_msr &= ~PAT_MASK(2);
610 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
611 pat_table[PAT_WRITE_COMBINING] = 2;
616 load_cr4(cr4 & ~CR4_PGE);
618 /* Disable caches (CD = 1, NW = 0). */
620 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
622 /* Flushes caches and TLBs. */
626 /* Update PAT and index table. */
627 wrmsr(MSR_PAT, pat_msr);
628 for (i = 0; i < PAT_INDEX_SIZE; i++)
629 pat_index[i] = pat_table[i];
631 /* Flush caches and TLBs again. */
635 /* Restore caches and PGE. */
641 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on.
647 vm_offset_t va, endva;
652 endva = KERNBASE + KERNend;
655 va = KERNBASE + KERNLOAD;
657 pdir_pde(PTD, va) |= pgeflag;
658 invltlb(); /* Flush non-PG_G entries. */
662 va = (vm_offset_t)btext;
667 invltlb(); /* Flush non-PG_G entries. */
674 * Initialize a vm_page's machine-dependent fields.
677 pmap_page_init(vm_page_t m)
680 TAILQ_INIT(&m->md.pv_list);
681 m->md.pat_mode = PAT_WRITE_BACK;
684 #if defined(PAE) || defined(PAE_TABLES)
686 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, uint8_t *flags, int wait)
689 /* Inform UMA that this allocator uses kernel_map/object. */
690 *flags = UMA_SLAB_KERNEL;
691 return ((void *)kmem_alloc_contig(kernel_arena, bytes, wait, 0x0ULL,
692 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
697 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
699 * - Must deal with pages in order to ensure that none of the PG_* bits
700 * are ever set, PG_V in particular.
701 * - Assumes we can write to ptes without pte_store() atomic ops, even
702 * on PAE systems. This should be ok.
703 * - Assumes nothing will ever test these addresses for 0 to indicate
704 * no mapping instead of correctly checking PG_V.
705 * - Assumes a vm_offset_t will fit in a pte (true for i386).
706 * Because PG_V is never set, there can be no mappings to invalidate.
709 pmap_ptelist_alloc(vm_offset_t *head)
716 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
720 panic("pmap_ptelist_alloc: va with PG_V set!");
726 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
731 panic("pmap_ptelist_free: freeing va with PG_V set!");
733 *pte = *head; /* virtual! PG_V is 0 though */
738 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
744 for (i = npages - 1; i >= 0; i--) {
745 va = (vm_offset_t)base + i * PAGE_SIZE;
746 pmap_ptelist_free(head, va);
752 * Initialize the pmap module.
753 * Called by vm_init, to initialize any structures that the pmap
754 * system needs to map virtual memory.
759 struct pmap_preinit_mapping *ppim;
765 * Initialize the vm page array entries for the kernel pmap's
768 for (i = 0; i < NKPT; i++) {
769 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
770 KASSERT(mpte >= vm_page_array &&
771 mpte < &vm_page_array[vm_page_array_size],
772 ("pmap_init: page table page is out of range"));
773 mpte->pindex = i + KPTDI;
774 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
778 * Initialize the address space (zone) for the pv entries. Set a
779 * high water mark so that the system can recover from excessive
780 * numbers of pv entries.
782 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
783 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
784 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
785 pv_entry_max = roundup(pv_entry_max, _NPCPV);
786 pv_entry_high_water = 9 * (pv_entry_max / 10);
789 * If the kernel is running on a virtual machine, then it must assume
790 * that MCA is enabled by the hypervisor. Moreover, the kernel must
791 * be prepared for the hypervisor changing the vendor and family that
792 * are reported by CPUID. Consequently, the workaround for AMD Family
793 * 10h Erratum 383 is enabled if the processor's feature set does not
794 * include at least one feature that is only supported by older Intel
795 * or newer AMD processors.
797 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
798 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
799 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
801 workaround_erratum383 = 1;
804 * Are large page mappings supported and enabled?
806 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
809 else if (pg_ps_enabled) {
810 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
811 ("pmap_init: can't assign to pagesizes[1]"));
812 pagesizes[1] = NBPDR;
816 * Calculate the size of the pv head table for superpages.
817 * Handle the possibility that "vm_phys_segs[...].end" is zero.
819 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
820 PAGE_SIZE) / NBPDR + 1;
823 * Allocate memory for the pv head table for superpages.
825 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
827 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
829 for (i = 0; i < pv_npg; i++)
830 TAILQ_INIT(&pv_table[i].pv_list);
832 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
833 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
834 if (pv_chunkbase == NULL)
835 panic("pmap_init: not enough kvm for pv chunks");
836 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
837 #if defined(PAE) || defined(PAE_TABLES)
838 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
839 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
840 UMA_ZONE_VM | UMA_ZONE_NOFREE);
841 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
844 pmap_initialized = 1;
847 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
848 ppim = pmap_preinit_mapping + i;
851 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
852 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
857 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
858 "Max number of PV entries");
859 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
860 "Page share factor per proc");
862 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
863 "2/4MB page mapping counters");
865 static u_long pmap_pde_demotions;
866 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
867 &pmap_pde_demotions, 0, "2/4MB page demotions");
869 static u_long pmap_pde_mappings;
870 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
871 &pmap_pde_mappings, 0, "2/4MB page mappings");
873 static u_long pmap_pde_p_failures;
874 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
875 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
877 static u_long pmap_pde_promotions;
878 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
879 &pmap_pde_promotions, 0, "2/4MB page promotions");
881 /***************************************************
882 * Low level helper routines.....
883 ***************************************************/
886 * Determine the appropriate bits to set in a PTE or PDE for a specified
890 pmap_cache_bits(int mode, boolean_t is_pde)
892 int cache_bits, pat_flag, pat_idx;
894 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
895 panic("Unknown caching mode %d\n", mode);
897 /* The PAT bit is different for PTE's and PDE's. */
898 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
900 /* Map the caching mode to a PAT index. */
901 pat_idx = pat_index[mode];
903 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
906 cache_bits |= pat_flag;
908 cache_bits |= PG_NC_PCD;
910 cache_bits |= PG_NC_PWT;
915 * The caller is responsible for maintaining TLB consistency.
918 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
922 boolean_t PTD_updated;
925 mtx_lock_spin(&allpmaps_lock);
926 LIST_FOREACH(pmap, &allpmaps, pm_list) {
927 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] &
930 pde = pmap_pde(pmap, va);
931 pde_store(pde, newpde);
933 mtx_unlock_spin(&allpmaps_lock);
935 ("pmap_kenter_pde: current page table is not in allpmaps"));
939 * After changing the page size for the specified virtual address in the page
940 * table, flush the corresponding entries from the processor's TLB. Only the
941 * calling processor's TLB is affected.
943 * The calling thread must be pinned to a processor.
946 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
950 if ((newpde & PG_PS) == 0)
951 /* Demotion: flush a specific 2MB page mapping. */
953 else if ((newpde & PG_G) == 0)
955 * Promotion: flush every 4KB page mapping from the TLB
956 * because there are too many to flush individually.
961 * Promotion: flush every 4KB page mapping from the TLB,
962 * including any global (PG_G) mappings.
965 load_cr4(cr4 & ~CR4_PGE);
967 * Although preemption at this point could be detrimental to
968 * performance, it would not lead to an error. PG_G is simply
969 * ignored if CR4.PGE is clear. Moreover, in case this block
970 * is re-entered, the load_cr4() either above or below will
971 * modify CR4.PGE flushing the TLB.
973 load_cr4(cr4 | CR4_PGE);
986 load_cr4(cr4 & ~CR4_PGE);
987 load_cr4(cr4 | CR4_PGE);
994 * For SMP, these functions have to use the IPI mechanism for coherence.
996 * N.B.: Before calling any of the following TLB invalidation functions,
997 * the calling processor must ensure that all stores updating a non-
998 * kernel page table are globally performed. Otherwise, another
999 * processor could cache an old, pre-update entry without being
1000 * invalidated. This can happen one of two ways: (1) The pmap becomes
1001 * active on another processor after its pm_active field is checked by
1002 * one of the following functions but before a store updating the page
1003 * table is globally performed. (2) The pmap becomes active on another
1004 * processor before its pm_active field is checked but due to
1005 * speculative loads one of the following functions stills reads the
1006 * pmap as inactive on the other processor.
1008 * The kernel page table is exempt because its pm_active field is
1009 * immutable. The kernel page table is always active on every
1013 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1015 cpuset_t *mask, other_cpus;
1019 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1023 cpuid = PCPU_GET(cpuid);
1024 other_cpus = all_cpus;
1025 CPU_CLR(cpuid, &other_cpus);
1026 if (CPU_ISSET(cpuid, &pmap->pm_active))
1028 CPU_AND(&other_cpus, &pmap->pm_active);
1031 smp_masked_invlpg(*mask, va);
1035 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1036 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1039 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1041 cpuset_t *mask, other_cpus;
1045 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1046 pmap_invalidate_all(pmap);
1051 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1052 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1056 cpuid = PCPU_GET(cpuid);
1057 other_cpus = all_cpus;
1058 CPU_CLR(cpuid, &other_cpus);
1059 if (CPU_ISSET(cpuid, &pmap->pm_active))
1060 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1062 CPU_AND(&other_cpus, &pmap->pm_active);
1065 smp_masked_invlpg_range(*mask, sva, eva);
1070 pmap_invalidate_all(pmap_t pmap)
1072 cpuset_t *mask, other_cpus;
1076 if (pmap == kernel_pmap) {
1079 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1083 cpuid = PCPU_GET(cpuid);
1084 other_cpus = all_cpus;
1085 CPU_CLR(cpuid, &other_cpus);
1086 if (CPU_ISSET(cpuid, &pmap->pm_active))
1088 CPU_AND(&other_cpus, &pmap->pm_active);
1091 smp_masked_invltlb(*mask, pmap);
1096 pmap_invalidate_cache(void)
1106 cpuset_t invalidate; /* processors that invalidate their TLB */
1110 u_int store; /* processor that updates the PDE */
1114 pmap_update_pde_kernel(void *arg)
1116 struct pde_action *act = arg;
1120 if (act->store == PCPU_GET(cpuid)) {
1123 * Elsewhere, this operation requires allpmaps_lock for
1124 * synchronization. Here, it does not because it is being
1125 * performed in the context of an all_cpus rendezvous.
1127 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1128 pde = pmap_pde(pmap, act->va);
1129 pde_store(pde, act->newpde);
1135 pmap_update_pde_user(void *arg)
1137 struct pde_action *act = arg;
1139 if (act->store == PCPU_GET(cpuid))
1140 pde_store(act->pde, act->newpde);
1144 pmap_update_pde_teardown(void *arg)
1146 struct pde_action *act = arg;
1148 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1149 pmap_update_pde_invalidate(act->va, act->newpde);
1153 * Change the page size for the specified virtual address in a way that
1154 * prevents any possibility of the TLB ever having two entries that map the
1155 * same virtual address using different page sizes. This is the recommended
1156 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1157 * machine check exception for a TLB state that is improperly diagnosed as a
1161 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1163 struct pde_action act;
1164 cpuset_t active, other_cpus;
1168 cpuid = PCPU_GET(cpuid);
1169 other_cpus = all_cpus;
1170 CPU_CLR(cpuid, &other_cpus);
1171 if (pmap == kernel_pmap)
1174 active = pmap->pm_active;
1175 if (CPU_OVERLAP(&active, &other_cpus)) {
1177 act.invalidate = active;
1180 act.newpde = newpde;
1181 CPU_SET(cpuid, &active);
1182 smp_rendezvous_cpus(active,
1183 smp_no_rendevous_barrier, pmap == kernel_pmap ?
1184 pmap_update_pde_kernel : pmap_update_pde_user,
1185 pmap_update_pde_teardown, &act);
1187 if (pmap == kernel_pmap)
1188 pmap_kenter_pde(va, newpde);
1190 pde_store(pde, newpde);
1191 if (CPU_ISSET(cpuid, &active))
1192 pmap_update_pde_invalidate(va, newpde);
1198 * Normal, non-SMP, 486+ invalidation functions.
1199 * We inline these within pmap.c for speed.
1202 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1205 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1210 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1214 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1215 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1220 pmap_invalidate_all(pmap_t pmap)
1223 if (pmap == kernel_pmap)
1225 else if (!CPU_EMPTY(&pmap->pm_active))
1230 pmap_invalidate_cache(void)
1237 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1240 if (pmap == kernel_pmap)
1241 pmap_kenter_pde(va, newpde);
1243 pde_store(pde, newpde);
1244 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1245 pmap_update_pde_invalidate(va, newpde);
1249 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1252 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1256 sva &= ~(vm_offset_t)cpu_clflush_line_size;
1258 KASSERT((sva & PAGE_MASK) == 0,
1259 ("pmap_invalidate_cache_range: sva not page-aligned"));
1260 KASSERT((eva & PAGE_MASK) == 0,
1261 ("pmap_invalidate_cache_range: eva not page-aligned"));
1264 if ((cpu_feature & CPUID_SS) != 0 && !force)
1265 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1266 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
1267 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1270 * XXX: Some CPUs fault, hang, or trash the local APIC
1271 * registers if we use CLFLUSH on the local APIC
1272 * range. The local APIC is always uncached, so we
1273 * don't need to flush for that range anyway.
1275 if (pmap_kextract(sva) == lapic_paddr)
1279 * Otherwise, do per-cache line flush. Use the mfence
1280 * instruction to insure that previous stores are
1281 * included in the write-back. The processor
1282 * propagates flush to other processors in the cache
1286 for (; sva < eva; sva += cpu_clflush_line_size)
1289 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1290 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1292 if (pmap_kextract(sva) == lapic_paddr)
1296 * Writes are ordered by CLFLUSH on Intel CPUs.
1298 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1300 for (; sva < eva; sva += cpu_clflush_line_size)
1302 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1307 * No targeted cache flush methods are supported by CPU,
1308 * or the supplied range is bigger than 2MB.
1309 * Globally invalidate cache.
1311 pmap_invalidate_cache();
1316 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1320 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1321 (cpu_feature & CPUID_CLFSH) == 0) {
1322 pmap_invalidate_cache();
1324 for (i = 0; i < count; i++)
1325 pmap_flush_page(pages[i]);
1330 * Are we current address space or kernel?
1333 pmap_is_current(pmap_t pmap)
1336 return (pmap == kernel_pmap || pmap ==
1337 vmspace_pmap(curthread->td_proc->p_vmspace));
1341 * If the given pmap is not the current or kernel pmap, the returned pte must
1342 * be released by passing it to pmap_pte_release().
1345 pmap_pte(pmap_t pmap, vm_offset_t va)
1350 pde = pmap_pde(pmap, va);
1354 /* are we current address space or kernel? */
1355 if (pmap_is_current(pmap))
1356 return (vtopte(va));
1357 mtx_lock(&PMAP2mutex);
1358 newpf = *pde & PG_FRAME;
1359 if ((*PMAP2 & PG_FRAME) != newpf) {
1360 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1361 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1363 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1369 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1372 static __inline void
1373 pmap_pte_release(pt_entry_t *pte)
1376 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1377 mtx_unlock(&PMAP2mutex);
1381 * NB: The sequence of updating a page table followed by accesses to the
1382 * corresponding pages is subject to the situation described in the "AMD64
1383 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1384 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1385 * right after modifying the PTE bits is crucial.
1387 static __inline void
1388 invlcaddr(void *caddr)
1391 invlpg((u_int)caddr);
1395 * Super fast pmap_pte routine best used when scanning
1396 * the pv lists. This eliminates many coarse-grained
1397 * invltlb calls. Note that many of the pv list
1398 * scans are across different pmaps. It is very wasteful
1399 * to do an entire invltlb for checking a single mapping.
1401 * If the given pmap is not the current pmap, pvh_global_lock
1402 * must be held and curthread pinned to a CPU.
1405 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1410 pde = pmap_pde(pmap, va);
1414 /* are we current address space or kernel? */
1415 if (pmap_is_current(pmap))
1416 return (vtopte(va));
1417 rw_assert(&pvh_global_lock, RA_WLOCKED);
1418 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1419 newpf = *pde & PG_FRAME;
1420 if ((*PMAP1 & PG_FRAME) != newpf) {
1421 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1423 PMAP1cpu = PCPU_GET(cpuid);
1429 if (PMAP1cpu != PCPU_GET(cpuid)) {
1430 PMAP1cpu = PCPU_GET(cpuid);
1436 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1442 * Routine: pmap_extract
1444 * Extract the physical page address associated
1445 * with the given map/virtual_address pair.
1448 pmap_extract(pmap_t pmap, vm_offset_t va)
1456 pde = pmap->pm_pdir[va >> PDRSHIFT];
1458 if ((pde & PG_PS) != 0)
1459 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1461 pte = pmap_pte(pmap, va);
1462 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK);
1463 pmap_pte_release(pte);
1471 * Routine: pmap_extract_and_hold
1473 * Atomically extract and hold the physical page
1474 * with the given pmap and virtual address pair
1475 * if that mapping permits the given protection.
1478 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1481 pt_entry_t pte, *ptep;
1489 pde = *pmap_pde(pmap, va);
1492 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1493 if (vm_page_pa_tryrelock(pmap, (pde &
1494 PG_PS_FRAME) | (va & PDRMASK), &pa))
1496 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1501 ptep = pmap_pte(pmap, va);
1503 pmap_pte_release(ptep);
1505 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1506 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1509 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1519 /***************************************************
1520 * Low level mapping routines.....
1521 ***************************************************/
1524 * Add a wired page to the kva.
1525 * Note: not SMP coherent.
1527 * This function may be used before pmap_bootstrap() is called.
1530 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1535 pte_store(pte, pa | PG_RW | PG_V | pgeflag);
1538 static __inline void
1539 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1544 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0));
1548 * Remove a page from the kernel pagetables.
1549 * Note: not SMP coherent.
1551 * This function may be used before pmap_bootstrap() is called.
1554 pmap_kremove(vm_offset_t va)
1563 * Used to map a range of physical addresses into kernel
1564 * virtual address space.
1566 * The value passed in '*virt' is a suggested virtual address for
1567 * the mapping. Architectures which can support a direct-mapped
1568 * physical to virtual region can return the appropriate address
1569 * within that region, leaving '*virt' unchanged. Other
1570 * architectures should map the pages starting at '*virt' and
1571 * update '*virt' with the first usable address after the mapped
1575 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1577 vm_offset_t va, sva;
1578 vm_paddr_t superpage_offset;
1583 * Does the physical address range's size and alignment permit at
1584 * least one superpage mapping to be created?
1586 superpage_offset = start & PDRMASK;
1587 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1589 * Increase the starting virtual address so that its alignment
1590 * does not preclude the use of superpage mappings.
1592 if ((va & PDRMASK) < superpage_offset)
1593 va = (va & ~PDRMASK) + superpage_offset;
1594 else if ((va & PDRMASK) > superpage_offset)
1595 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1598 while (start < end) {
1599 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1601 KASSERT((va & PDRMASK) == 0,
1602 ("pmap_map: misaligned va %#x", va));
1603 newpde = start | PG_PS | pgeflag | PG_RW | PG_V;
1604 pmap_kenter_pde(va, newpde);
1608 pmap_kenter(va, start);
1613 pmap_invalidate_range(kernel_pmap, sva, va);
1620 * Add a list of wired pages to the kva
1621 * this routine is only used for temporary
1622 * kernel mappings that do not need to have
1623 * page modification or references recorded.
1624 * Note that old mappings are simply written
1625 * over. The page *must* be wired.
1626 * Note: SMP coherent. Uses a ranged shootdown IPI.
1629 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1631 pt_entry_t *endpte, oldpte, pa, *pte;
1636 endpte = pte + count;
1637 while (pte < endpte) {
1639 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1640 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1642 pte_store(pte, pa | pgeflag | PG_RW | PG_V);
1646 if (__predict_false((oldpte & PG_V) != 0))
1647 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1652 * This routine tears out page mappings from the
1653 * kernel -- it is meant only for temporary mappings.
1654 * Note: SMP coherent. Uses a ranged shootdown IPI.
1657 pmap_qremove(vm_offset_t sva, int count)
1662 while (count-- > 0) {
1666 pmap_invalidate_range(kernel_pmap, sva, va);
1669 /***************************************************
1670 * Page table page management routines.....
1671 ***************************************************/
1672 static __inline void
1673 pmap_free_zero_pages(struct spglist *free)
1677 while ((m = SLIST_FIRST(free)) != NULL) {
1678 SLIST_REMOVE_HEAD(free, plinks.s.ss);
1679 /* Preserve the page's PG_ZERO setting. */
1680 vm_page_free_toq(m);
1685 * Schedule the specified unused page table page to be freed. Specifically,
1686 * add the page to the specified list of pages that will be released to the
1687 * physical memory manager after the TLB has been updated.
1689 static __inline void
1690 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1691 boolean_t set_PG_ZERO)
1695 m->flags |= PG_ZERO;
1697 m->flags &= ~PG_ZERO;
1698 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1702 * Inserts the specified page table page into the specified pmap's collection
1703 * of idle page table pages. Each of a pmap's page table pages is responsible
1704 * for mapping a distinct range of virtual addresses. The pmap's collection is
1705 * ordered by this virtual address range.
1708 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1711 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1712 return (vm_radix_insert(&pmap->pm_root, mpte));
1716 * Looks for a page table page mapping the specified virtual address in the
1717 * specified pmap's collection of idle page table pages. Returns NULL if there
1718 * is no page table page corresponding to the specified virtual address.
1720 static __inline vm_page_t
1721 pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va)
1724 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1725 return (vm_radix_lookup(&pmap->pm_root, va >> PDRSHIFT));
1729 * Removes the specified page table page from the specified pmap's collection
1730 * of idle page table pages. The specified page table page must be a member of
1731 * the pmap's collection.
1733 static __inline void
1734 pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte)
1737 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1738 vm_radix_remove(&pmap->pm_root, mpte->pindex);
1742 * Decrements a page table page's wire count, which is used to record the
1743 * number of valid page table entries within the page. If the wire count
1744 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1745 * page table page was unmapped and FALSE otherwise.
1747 static inline boolean_t
1748 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1752 if (m->wire_count == 0) {
1753 _pmap_unwire_ptp(pmap, m, free);
1760 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1765 * unmap the page table page
1767 pmap->pm_pdir[m->pindex] = 0;
1768 --pmap->pm_stats.resident_count;
1771 * This is a release store so that the ordinary store unmapping
1772 * the page table page is globally performed before TLB shoot-
1775 atomic_subtract_rel_int(&vm_cnt.v_wire_count, 1);
1778 * Do an invltlb to make the invalidated mapping
1779 * take effect immediately.
1781 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex);
1782 pmap_invalidate_page(pmap, pteva);
1785 * Put page on a list so that it is released after
1786 * *ALL* TLB shootdown is done
1788 pmap_add_delayed_free_list(m, free, TRUE);
1792 * After removing a page table entry, this routine is used to
1793 * conditionally free the page, and manage the hold/wire counts.
1796 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1801 if (va >= VM_MAXUSER_ADDRESS)
1803 ptepde = *pmap_pde(pmap, va);
1804 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1805 return (pmap_unwire_ptp(pmap, mpte, free));
1809 * Initialize the pmap for the swapper process.
1812 pmap_pinit0(pmap_t pmap)
1815 PMAP_LOCK_INIT(pmap);
1817 * Since the page table directory is shared with the kernel pmap,
1818 * which is already included in the list "allpmaps", this pmap does
1819 * not need to be inserted into that list.
1821 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD);
1822 #if defined(PAE) || defined(PAE_TABLES)
1823 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT);
1825 pmap->pm_root.rt_root = 0;
1826 CPU_ZERO(&pmap->pm_active);
1827 PCPU_SET(curpmap, pmap);
1828 TAILQ_INIT(&pmap->pm_pvchunk);
1829 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1833 * Initialize a preallocated and zeroed pmap structure,
1834 * such as one in a vmspace structure.
1837 pmap_pinit(pmap_t pmap)
1839 vm_page_t m, ptdpg[NPGPTD];
1844 * No need to allocate page table space yet but we do need a valid
1845 * page directory table.
1847 if (pmap->pm_pdir == NULL) {
1848 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
1849 if (pmap->pm_pdir == NULL)
1851 #if defined(PAE) || defined(PAE_TABLES)
1852 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
1853 KASSERT(((vm_offset_t)pmap->pm_pdpt &
1854 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
1855 ("pmap_pinit: pdpt misaligned"));
1856 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
1857 ("pmap_pinit: pdpt above 4g"));
1859 pmap->pm_root.rt_root = 0;
1861 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1862 ("pmap_pinit: pmap has reserved page table page(s)"));
1865 * allocate the page directory page(s)
1867 for (i = 0; i < NPGPTD;) {
1868 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1869 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1877 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD);
1879 for (i = 0; i < NPGPTD; i++)
1880 if ((ptdpg[i]->flags & PG_ZERO) == 0)
1881 pagezero(pmap->pm_pdir + (i * NPDEPG));
1883 mtx_lock_spin(&allpmaps_lock);
1884 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1885 /* Copy the kernel page table directory entries. */
1886 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t));
1887 mtx_unlock_spin(&allpmaps_lock);
1889 /* install self-referential address mapping entry(s) */
1890 for (i = 0; i < NPGPTD; i++) {
1891 pa = VM_PAGE_TO_PHYS(ptdpg[i]);
1892 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M;
1893 #if defined(PAE) || defined(PAE_TABLES)
1894 pmap->pm_pdpt[i] = pa | PG_V;
1898 CPU_ZERO(&pmap->pm_active);
1899 TAILQ_INIT(&pmap->pm_pvchunk);
1900 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1906 * this routine is called if the page table page is not
1910 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
1916 * Allocate a page table page.
1918 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1919 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1920 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
1922 rw_wunlock(&pvh_global_lock);
1924 rw_wlock(&pvh_global_lock);
1929 * Indicate the need to retry. While waiting, the page table
1930 * page may have been allocated.
1934 if ((m->flags & PG_ZERO) == 0)
1938 * Map the pagetable page into the process address space, if
1939 * it isn't already there.
1942 pmap->pm_stats.resident_count++;
1944 ptepa = VM_PAGE_TO_PHYS(m);
1945 pmap->pm_pdir[ptepindex] =
1946 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
1952 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
1959 * Calculate pagetable page index
1961 ptepindex = va >> PDRSHIFT;
1964 * Get the page directory entry
1966 ptepa = pmap->pm_pdir[ptepindex];
1969 * This supports switching from a 4MB page to a
1972 if (ptepa & PG_PS) {
1973 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
1974 ptepa = pmap->pm_pdir[ptepindex];
1978 * If the page table page is mapped, we just increment the
1979 * hold count, and activate it.
1982 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
1986 * Here if the pte page isn't mapped, or if it has
1989 m = _pmap_allocpte(pmap, ptepindex, flags);
1990 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
1997 /***************************************************
1998 * Pmap allocation/deallocation routines.
1999 ***************************************************/
2002 * Release any resources held by the given physical map.
2003 * Called when a pmap initialized by pmap_pinit is being released.
2004 * Should only be called if the map contains no valid mappings.
2007 pmap_release(pmap_t pmap)
2009 vm_page_t m, ptdpg[NPGPTD];
2012 KASSERT(pmap->pm_stats.resident_count == 0,
2013 ("pmap_release: pmap resident count %ld != 0",
2014 pmap->pm_stats.resident_count));
2015 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2016 ("pmap_release: pmap has reserved page table page(s)"));
2017 KASSERT(CPU_EMPTY(&pmap->pm_active),
2018 ("releasing active pmap %p", pmap));
2020 mtx_lock_spin(&allpmaps_lock);
2021 LIST_REMOVE(pmap, pm_list);
2022 mtx_unlock_spin(&allpmaps_lock);
2024 for (i = 0; i < NPGPTD; i++)
2025 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] &
2028 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) *
2029 sizeof(*pmap->pm_pdir));
2031 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2033 for (i = 0; i < NPGPTD; i++) {
2035 #if defined(PAE) || defined(PAE_TABLES)
2036 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2037 ("pmap_release: got wrong ptd page"));
2040 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2041 vm_page_free_zero(m);
2046 kvm_size(SYSCTL_HANDLER_ARGS)
2048 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2050 return (sysctl_handle_long(oidp, &ksize, 0, req));
2052 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2053 0, 0, kvm_size, "IU", "Size of KVM");
2056 kvm_free(SYSCTL_HANDLER_ARGS)
2058 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2060 return (sysctl_handle_long(oidp, &kfree, 0, req));
2062 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2063 0, 0, kvm_free, "IU", "Amount of KVM free");
2066 * grow the number of kernel page table entries, if needed
2069 pmap_growkernel(vm_offset_t addr)
2071 vm_paddr_t ptppaddr;
2075 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2076 addr = roundup2(addr, NBPDR);
2077 if (addr - 1 >= kernel_map->max_offset)
2078 addr = kernel_map->max_offset;
2079 while (kernel_vm_end < addr) {
2080 if (pdir_pde(PTD, kernel_vm_end)) {
2081 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2082 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2083 kernel_vm_end = kernel_map->max_offset;
2089 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2090 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2093 panic("pmap_growkernel: no memory to grow kernel");
2097 if ((nkpg->flags & PG_ZERO) == 0)
2098 pmap_zero_page(nkpg);
2099 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2100 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2101 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir;
2103 pmap_kenter_pde(kernel_vm_end, newpdir);
2104 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2105 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2106 kernel_vm_end = kernel_map->max_offset;
2113 /***************************************************
2114 * page management routines.
2115 ***************************************************/
2117 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2118 CTASSERT(_NPCM == 11);
2119 CTASSERT(_NPCPV == 336);
2121 static __inline struct pv_chunk *
2122 pv_to_chunk(pv_entry_t pv)
2125 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2128 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2130 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2131 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2133 static const uint32_t pc_freemask[_NPCM] = {
2134 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2135 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2136 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2137 PC_FREE0_9, PC_FREE10
2140 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2141 "Current number of pv entries");
2144 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2146 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2147 "Current number of pv entry chunks");
2148 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2149 "Current number of pv entry chunks allocated");
2150 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2151 "Current number of pv entry chunks frees");
2152 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2153 "Number of times tried to get a chunk page but failed.");
2155 static long pv_entry_frees, pv_entry_allocs;
2156 static int pv_entry_spare;
2158 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2159 "Current number of pv entry frees");
2160 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2161 "Current number of pv entry allocs");
2162 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2163 "Current number of spare pv entries");
2167 * We are in a serious low memory condition. Resort to
2168 * drastic measures to free some pages so we can allocate
2169 * another pv entry chunk.
2172 pmap_pv_reclaim(pmap_t locked_pmap)
2175 struct pv_chunk *pc;
2176 struct md_page *pvh;
2179 pt_entry_t *pte, tpte;
2183 struct spglist free;
2185 int bit, field, freed;
2187 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2191 TAILQ_INIT(&newtail);
2192 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2193 SLIST_EMPTY(&free))) {
2194 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2195 if (pmap != pc->pc_pmap) {
2197 pmap_invalidate_all(pmap);
2198 if (pmap != locked_pmap)
2202 /* Avoid deadlock and lock recursion. */
2203 if (pmap > locked_pmap)
2205 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2207 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2213 * Destroy every non-wired, 4 KB page mapping in the chunk.
2216 for (field = 0; field < _NPCM; field++) {
2217 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2218 inuse != 0; inuse &= ~(1UL << bit)) {
2220 pv = &pc->pc_pventry[field * 32 + bit];
2222 pde = pmap_pde(pmap, va);
2223 if ((*pde & PG_PS) != 0)
2225 pte = pmap_pte(pmap, va);
2227 if ((tpte & PG_W) == 0)
2228 tpte = pte_load_clear(pte);
2229 pmap_pte_release(pte);
2230 if ((tpte & PG_W) != 0)
2233 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2235 if ((tpte & PG_G) != 0)
2236 pmap_invalidate_page(pmap, va);
2237 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2238 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2240 if ((tpte & PG_A) != 0)
2241 vm_page_aflag_set(m, PGA_REFERENCED);
2242 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2243 if (TAILQ_EMPTY(&m->md.pv_list) &&
2244 (m->flags & PG_FICTITIOUS) == 0) {
2245 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2246 if (TAILQ_EMPTY(&pvh->pv_list)) {
2247 vm_page_aflag_clear(m,
2251 pc->pc_map[field] |= 1UL << bit;
2252 pmap_unuse_pt(pmap, va, &free);
2257 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2260 /* Every freed mapping is for a 4 KB page. */
2261 pmap->pm_stats.resident_count -= freed;
2262 PV_STAT(pv_entry_frees += freed);
2263 PV_STAT(pv_entry_spare += freed);
2264 pv_entry_count -= freed;
2265 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2266 for (field = 0; field < _NPCM; field++)
2267 if (pc->pc_map[field] != pc_freemask[field]) {
2268 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2270 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2273 * One freed pv entry in locked_pmap is
2276 if (pmap == locked_pmap)
2280 if (field == _NPCM) {
2281 PV_STAT(pv_entry_spare -= _NPCPV);
2282 PV_STAT(pc_chunk_count--);
2283 PV_STAT(pc_chunk_frees++);
2284 /* Entire chunk is free; return it. */
2285 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2286 pmap_qremove((vm_offset_t)pc, 1);
2287 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2292 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2294 pmap_invalidate_all(pmap);
2295 if (pmap != locked_pmap)
2298 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2299 m_pc = SLIST_FIRST(&free);
2300 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2301 /* Recycle a freed page table page. */
2302 m_pc->wire_count = 1;
2303 atomic_add_int(&vm_cnt.v_wire_count, 1);
2305 pmap_free_zero_pages(&free);
2310 * free the pv_entry back to the free list
2313 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2315 struct pv_chunk *pc;
2316 int idx, field, bit;
2318 rw_assert(&pvh_global_lock, RA_WLOCKED);
2319 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2320 PV_STAT(pv_entry_frees++);
2321 PV_STAT(pv_entry_spare++);
2323 pc = pv_to_chunk(pv);
2324 idx = pv - &pc->pc_pventry[0];
2327 pc->pc_map[field] |= 1ul << bit;
2328 for (idx = 0; idx < _NPCM; idx++)
2329 if (pc->pc_map[idx] != pc_freemask[idx]) {
2331 * 98% of the time, pc is already at the head of the
2332 * list. If it isn't already, move it to the head.
2334 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2336 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2337 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2342 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2347 free_pv_chunk(struct pv_chunk *pc)
2351 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2352 PV_STAT(pv_entry_spare -= _NPCPV);
2353 PV_STAT(pc_chunk_count--);
2354 PV_STAT(pc_chunk_frees++);
2355 /* entire chunk is free, return it */
2356 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2357 pmap_qremove((vm_offset_t)pc, 1);
2358 vm_page_unwire(m, PQ_NONE);
2360 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2364 * get a new pv_entry, allocating a block from the system
2368 get_pv_entry(pmap_t pmap, boolean_t try)
2370 static const struct timeval printinterval = { 60, 0 };
2371 static struct timeval lastprint;
2374 struct pv_chunk *pc;
2377 rw_assert(&pvh_global_lock, RA_WLOCKED);
2378 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2379 PV_STAT(pv_entry_allocs++);
2381 if (pv_entry_count > pv_entry_high_water)
2382 if (ratecheck(&lastprint, &printinterval))
2383 printf("Approaching the limit on PV entries, consider "
2384 "increasing either the vm.pmap.shpgperproc or the "
2385 "vm.pmap.pv_entry_max tunable.\n");
2387 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2389 for (field = 0; field < _NPCM; field++) {
2390 if (pc->pc_map[field]) {
2391 bit = bsfl(pc->pc_map[field]);
2395 if (field < _NPCM) {
2396 pv = &pc->pc_pventry[field * 32 + bit];
2397 pc->pc_map[field] &= ~(1ul << bit);
2398 /* If this was the last item, move it to tail */
2399 for (field = 0; field < _NPCM; field++)
2400 if (pc->pc_map[field] != 0) {
2401 PV_STAT(pv_entry_spare--);
2402 return (pv); /* not full, return */
2404 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2405 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2406 PV_STAT(pv_entry_spare--);
2411 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2412 * global lock. If "pv_vafree" is currently non-empty, it will
2413 * remain non-empty until pmap_ptelist_alloc() completes.
2415 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2416 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2419 PV_STAT(pc_chunk_tryfail++);
2422 m = pmap_pv_reclaim(pmap);
2426 PV_STAT(pc_chunk_count++);
2427 PV_STAT(pc_chunk_allocs++);
2428 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2429 pmap_qenter((vm_offset_t)pc, &m, 1);
2431 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2432 for (field = 1; field < _NPCM; field++)
2433 pc->pc_map[field] = pc_freemask[field];
2434 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2435 pv = &pc->pc_pventry[0];
2436 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2437 PV_STAT(pv_entry_spare += _NPCPV - 1);
2441 static __inline pv_entry_t
2442 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2446 rw_assert(&pvh_global_lock, RA_WLOCKED);
2447 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2448 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2449 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2457 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2459 struct md_page *pvh;
2461 vm_offset_t va_last;
2464 rw_assert(&pvh_global_lock, RA_WLOCKED);
2465 KASSERT((pa & PDRMASK) == 0,
2466 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2469 * Transfer the 4mpage's pv entry for this mapping to the first
2472 pvh = pa_to_pvh(pa);
2473 va = trunc_4mpage(va);
2474 pv = pmap_pvh_remove(pvh, pmap, va);
2475 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2476 m = PHYS_TO_VM_PAGE(pa);
2477 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2478 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2479 va_last = va + NBPDR - PAGE_SIZE;
2482 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2483 ("pmap_pv_demote_pde: page %p is not managed", m));
2485 pmap_insert_entry(pmap, va, m);
2486 } while (va < va_last);
2490 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2492 struct md_page *pvh;
2494 vm_offset_t va_last;
2497 rw_assert(&pvh_global_lock, RA_WLOCKED);
2498 KASSERT((pa & PDRMASK) == 0,
2499 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2502 * Transfer the first page's pv entry for this mapping to the
2503 * 4mpage's pv list. Aside from avoiding the cost of a call
2504 * to get_pv_entry(), a transfer avoids the possibility that
2505 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2506 * removes one of the mappings that is being promoted.
2508 m = PHYS_TO_VM_PAGE(pa);
2509 va = trunc_4mpage(va);
2510 pv = pmap_pvh_remove(&m->md, pmap, va);
2511 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2512 pvh = pa_to_pvh(pa);
2513 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2514 /* Free the remaining NPTEPG - 1 pv entries. */
2515 va_last = va + NBPDR - PAGE_SIZE;
2519 pmap_pvh_free(&m->md, pmap, va);
2520 } while (va < va_last);
2524 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2528 pv = pmap_pvh_remove(pvh, pmap, va);
2529 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2530 free_pv_entry(pmap, pv);
2534 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2536 struct md_page *pvh;
2538 rw_assert(&pvh_global_lock, RA_WLOCKED);
2539 pmap_pvh_free(&m->md, pmap, va);
2540 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2541 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2542 if (TAILQ_EMPTY(&pvh->pv_list))
2543 vm_page_aflag_clear(m, PGA_WRITEABLE);
2548 * Create a pv entry for page at pa for
2552 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2556 rw_assert(&pvh_global_lock, RA_WLOCKED);
2557 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2558 pv = get_pv_entry(pmap, FALSE);
2560 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2564 * Conditionally create a pv entry.
2567 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2571 rw_assert(&pvh_global_lock, RA_WLOCKED);
2572 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2573 if (pv_entry_count < pv_entry_high_water &&
2574 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2576 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2583 * Create the pv entries for each of the pages within a superpage.
2586 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2588 struct md_page *pvh;
2591 rw_assert(&pvh_global_lock, RA_WLOCKED);
2592 if (pv_entry_count < pv_entry_high_water &&
2593 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2595 pvh = pa_to_pvh(pa);
2596 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2603 * Fills a page table page with mappings to consecutive physical pages.
2606 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2610 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2612 newpte += PAGE_SIZE;
2617 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2618 * 2- or 4MB page mapping is invalidated.
2621 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2623 pd_entry_t newpde, oldpde;
2624 pt_entry_t *firstpte, newpte;
2627 struct spglist free;
2629 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2631 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2632 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2633 if ((oldpde & PG_A) != 0 && (mpte = pmap_lookup_pt_page(pmap, va)) !=
2635 pmap_remove_pt_page(pmap, mpte);
2637 KASSERT((oldpde & PG_W) == 0,
2638 ("pmap_demote_pde: page table page for a wired mapping"
2642 * Invalidate the 2- or 4MB page mapping and return
2643 * "failure" if the mapping was never accessed or the
2644 * allocation of the new page table page fails.
2646 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2647 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2648 VM_ALLOC_WIRED)) == NULL) {
2650 pmap_remove_pde(pmap, pde, trunc_4mpage(va), &free);
2651 pmap_invalidate_page(pmap, trunc_4mpage(va));
2652 pmap_free_zero_pages(&free);
2653 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2654 " in pmap %p", va, pmap);
2657 if (va < VM_MAXUSER_ADDRESS)
2658 pmap->pm_stats.resident_count++;
2660 mptepa = VM_PAGE_TO_PHYS(mpte);
2663 * If the page mapping is in the kernel's address space, then the
2664 * KPTmap can provide access to the page table page. Otherwise,
2665 * temporarily map the page table page (mpte) into the kernel's
2666 * address space at either PADDR1 or PADDR2.
2669 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2670 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2671 if ((*PMAP1 & PG_FRAME) != mptepa) {
2672 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2674 PMAP1cpu = PCPU_GET(cpuid);
2680 if (PMAP1cpu != PCPU_GET(cpuid)) {
2681 PMAP1cpu = PCPU_GET(cpuid);
2689 mtx_lock(&PMAP2mutex);
2690 if ((*PMAP2 & PG_FRAME) != mptepa) {
2691 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2692 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2696 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2697 KASSERT((oldpde & PG_A) != 0,
2698 ("pmap_demote_pde: oldpde is missing PG_A"));
2699 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2700 ("pmap_demote_pde: oldpde is missing PG_M"));
2701 newpte = oldpde & ~PG_PS;
2702 if ((newpte & PG_PDE_PAT) != 0)
2703 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2706 * If the page table page is new, initialize it.
2708 if (mpte->wire_count == 1) {
2709 mpte->wire_count = NPTEPG;
2710 pmap_fill_ptp(firstpte, newpte);
2712 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2713 ("pmap_demote_pde: firstpte and newpte map different physical"
2717 * If the mapping has changed attributes, update the page table
2720 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2721 pmap_fill_ptp(firstpte, newpte);
2724 * Demote the mapping. This pmap is locked. The old PDE has
2725 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2726 * set. Thus, there is no danger of a race with another
2727 * processor changing the setting of PG_A and/or PG_M between
2728 * the read above and the store below.
2730 if (workaround_erratum383)
2731 pmap_update_pde(pmap, va, pde, newpde);
2732 else if (pmap == kernel_pmap)
2733 pmap_kenter_pde(va, newpde);
2735 pde_store(pde, newpde);
2736 if (firstpte == PADDR2)
2737 mtx_unlock(&PMAP2mutex);
2740 * Invalidate the recursive mapping of the page table page.
2742 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2745 * Demote the pv entry. This depends on the earlier demotion
2746 * of the mapping. Specifically, the (re)creation of a per-
2747 * page pv entry might trigger the execution of pmap_collect(),
2748 * which might reclaim a newly (re)created per-page pv entry
2749 * and destroy the associated mapping. In order to destroy
2750 * the mapping, the PDE must have already changed from mapping
2751 * the 2mpage to referencing the page table page.
2753 if ((oldpde & PG_MANAGED) != 0)
2754 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2756 pmap_pde_demotions++;
2757 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2758 " in pmap %p", va, pmap);
2763 * Removes a 2- or 4MB page mapping from the kernel pmap.
2766 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2772 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2773 mpte = pmap_lookup_pt_page(pmap, va);
2775 panic("pmap_remove_kernel_pde: Missing pt page.");
2777 pmap_remove_pt_page(pmap, mpte);
2778 mptepa = VM_PAGE_TO_PHYS(mpte);
2779 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2782 * Initialize the page table page.
2784 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2787 * Remove the mapping.
2789 if (workaround_erratum383)
2790 pmap_update_pde(pmap, va, pde, newpde);
2792 pmap_kenter_pde(va, newpde);
2795 * Invalidate the recursive mapping of the page table page.
2797 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2801 * pmap_remove_pde: do the things to unmap a superpage in a process
2804 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2805 struct spglist *free)
2807 struct md_page *pvh;
2809 vm_offset_t eva, va;
2812 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2813 KASSERT((sva & PDRMASK) == 0,
2814 ("pmap_remove_pde: sva is not 4mpage aligned"));
2815 oldpde = pte_load_clear(pdq);
2817 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2820 * Machines that don't support invlpg, also don't support
2824 pmap_invalidate_page(kernel_pmap, sva);
2825 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2826 if (oldpde & PG_MANAGED) {
2827 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2828 pmap_pvh_free(pvh, pmap, sva);
2830 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2831 va < eva; va += PAGE_SIZE, m++) {
2832 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2835 vm_page_aflag_set(m, PGA_REFERENCED);
2836 if (TAILQ_EMPTY(&m->md.pv_list) &&
2837 TAILQ_EMPTY(&pvh->pv_list))
2838 vm_page_aflag_clear(m, PGA_WRITEABLE);
2841 if (pmap == kernel_pmap) {
2842 pmap_remove_kernel_pde(pmap, pdq, sva);
2844 mpte = pmap_lookup_pt_page(pmap, sva);
2846 pmap_remove_pt_page(pmap, mpte);
2847 pmap->pm_stats.resident_count--;
2848 KASSERT(mpte->wire_count == NPTEPG,
2849 ("pmap_remove_pde: pte page wire count error"));
2850 mpte->wire_count = 0;
2851 pmap_add_delayed_free_list(mpte, free, FALSE);
2852 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2858 * pmap_remove_pte: do the things to unmap a page in a process
2861 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
2862 struct spglist *free)
2867 rw_assert(&pvh_global_lock, RA_WLOCKED);
2868 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2869 oldpte = pte_load_clear(ptq);
2870 KASSERT(oldpte != 0,
2871 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
2873 pmap->pm_stats.wired_count -= 1;
2875 * Machines that don't support invlpg, also don't support
2879 pmap_invalidate_page(kernel_pmap, va);
2880 pmap->pm_stats.resident_count -= 1;
2881 if (oldpte & PG_MANAGED) {
2882 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2883 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2886 vm_page_aflag_set(m, PGA_REFERENCED);
2887 pmap_remove_entry(pmap, m, va);
2889 return (pmap_unuse_pt(pmap, va, free));
2893 * Remove a single page from a process address space
2896 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
2900 rw_assert(&pvh_global_lock, RA_WLOCKED);
2901 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
2902 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2903 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
2905 pmap_remove_pte(pmap, pte, va, free);
2906 pmap_invalidate_page(pmap, va);
2910 * Remove the given range of addresses from the specified map.
2912 * It is assumed that the start and end are properly
2913 * rounded to the page size.
2916 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2921 struct spglist free;
2925 * Perform an unsynchronized read. This is, however, safe.
2927 if (pmap->pm_stats.resident_count == 0)
2933 rw_wlock(&pvh_global_lock);
2938 * special handling of removing one page. a very
2939 * common operation and easy to short circuit some
2942 if ((sva + PAGE_SIZE == eva) &&
2943 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
2944 pmap_remove_page(pmap, sva, &free);
2948 for (; sva < eva; sva = pdnxt) {
2952 * Calculate index for next page table.
2954 pdnxt = (sva + NBPDR) & ~PDRMASK;
2957 if (pmap->pm_stats.resident_count == 0)
2960 pdirindex = sva >> PDRSHIFT;
2961 ptpaddr = pmap->pm_pdir[pdirindex];
2964 * Weed out invalid mappings. Note: we assume that the page
2965 * directory table is always allocated, and in kernel virtual.
2971 * Check for large page.
2973 if ((ptpaddr & PG_PS) != 0) {
2975 * Are we removing the entire large page? If not,
2976 * demote the mapping and fall through.
2978 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
2980 * The TLB entry for a PG_G mapping is
2981 * invalidated by pmap_remove_pde().
2983 if ((ptpaddr & PG_G) == 0)
2985 pmap_remove_pde(pmap,
2986 &pmap->pm_pdir[pdirindex], sva, &free);
2988 } else if (!pmap_demote_pde(pmap,
2989 &pmap->pm_pdir[pdirindex], sva)) {
2990 /* The large page mapping was destroyed. */
2996 * Limit our scan to either the end of the va represented
2997 * by the current page table page, or to the end of the
2998 * range being removed.
3003 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3009 * The TLB entry for a PG_G mapping is invalidated
3010 * by pmap_remove_pte().
3012 if ((*pte & PG_G) == 0)
3014 if (pmap_remove_pte(pmap, pte, sva, &free))
3021 pmap_invalidate_all(pmap);
3022 rw_wunlock(&pvh_global_lock);
3024 pmap_free_zero_pages(&free);
3028 * Routine: pmap_remove_all
3030 * Removes this physical page from
3031 * all physical maps in which it resides.
3032 * Reflects back modify bits to the pager.
3035 * Original versions of this routine were very
3036 * inefficient because they iteratively called
3037 * pmap_remove (slow...)
3041 pmap_remove_all(vm_page_t m)
3043 struct md_page *pvh;
3046 pt_entry_t *pte, tpte;
3049 struct spglist free;
3051 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3052 ("pmap_remove_all: page %p is not managed", m));
3054 rw_wlock(&pvh_global_lock);
3056 if ((m->flags & PG_FICTITIOUS) != 0)
3057 goto small_mappings;
3058 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3059 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3063 pde = pmap_pde(pmap, va);
3064 (void)pmap_demote_pde(pmap, pde, va);
3068 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3071 pmap->pm_stats.resident_count--;
3072 pde = pmap_pde(pmap, pv->pv_va);
3073 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3074 " a 4mpage in page %p's pv list", m));
3075 pte = pmap_pte_quick(pmap, pv->pv_va);
3076 tpte = pte_load_clear(pte);
3077 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3080 pmap->pm_stats.wired_count--;
3082 vm_page_aflag_set(m, PGA_REFERENCED);
3085 * Update the vm_page_t clean and reference bits.
3087 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3089 pmap_unuse_pt(pmap, pv->pv_va, &free);
3090 pmap_invalidate_page(pmap, pv->pv_va);
3091 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3092 free_pv_entry(pmap, pv);
3095 vm_page_aflag_clear(m, PGA_WRITEABLE);
3097 rw_wunlock(&pvh_global_lock);
3098 pmap_free_zero_pages(&free);
3102 * pmap_protect_pde: do the things to protect a 4mpage in a process
3105 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3107 pd_entry_t newpde, oldpde;
3108 vm_offset_t eva, va;
3110 boolean_t anychanged;
3112 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3113 KASSERT((sva & PDRMASK) == 0,
3114 ("pmap_protect_pde: sva is not 4mpage aligned"));
3117 oldpde = newpde = *pde;
3118 if (oldpde & PG_MANAGED) {
3120 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3121 va < eva; va += PAGE_SIZE, m++)
3122 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3125 if ((prot & VM_PROT_WRITE) == 0)
3126 newpde &= ~(PG_RW | PG_M);
3127 #if defined(PAE) || defined(PAE_TABLES)
3128 if ((prot & VM_PROT_EXECUTE) == 0)
3131 if (newpde != oldpde) {
3132 if (!pde_cmpset(pde, oldpde, newpde))
3135 pmap_invalidate_page(pmap, sva);
3139 return (anychanged);
3143 * Set the physical protection on the
3144 * specified range of this map as requested.
3147 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3152 boolean_t anychanged, pv_lists_locked;
3154 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3155 if (prot == VM_PROT_NONE) {
3156 pmap_remove(pmap, sva, eva);
3160 #if defined(PAE) || defined(PAE_TABLES)
3161 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3162 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3165 if (prot & VM_PROT_WRITE)
3169 if (pmap_is_current(pmap))
3170 pv_lists_locked = FALSE;
3172 pv_lists_locked = TRUE;
3174 rw_wlock(&pvh_global_lock);
3180 for (; sva < eva; sva = pdnxt) {
3181 pt_entry_t obits, pbits;
3184 pdnxt = (sva + NBPDR) & ~PDRMASK;
3188 pdirindex = sva >> PDRSHIFT;
3189 ptpaddr = pmap->pm_pdir[pdirindex];
3192 * Weed out invalid mappings. Note: we assume that the page
3193 * directory table is always allocated, and in kernel virtual.
3199 * Check for large page.
3201 if ((ptpaddr & PG_PS) != 0) {
3203 * Are we protecting the entire large page? If not,
3204 * demote the mapping and fall through.
3206 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3208 * The TLB entry for a PG_G mapping is
3209 * invalidated by pmap_protect_pde().
3211 if (pmap_protect_pde(pmap,
3212 &pmap->pm_pdir[pdirindex], sva, prot))
3216 if (!pv_lists_locked) {
3217 pv_lists_locked = TRUE;
3218 if (!rw_try_wlock(&pvh_global_lock)) {
3220 pmap_invalidate_all(
3227 if (!pmap_demote_pde(pmap,
3228 &pmap->pm_pdir[pdirindex], sva)) {
3230 * The large page mapping was
3241 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3247 * Regardless of whether a pte is 32 or 64 bits in
3248 * size, PG_RW, PG_A, and PG_M are among the least
3249 * significant 32 bits.
3251 obits = pbits = *pte;
3252 if ((pbits & PG_V) == 0)
3255 if ((prot & VM_PROT_WRITE) == 0) {
3256 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3257 (PG_MANAGED | PG_M | PG_RW)) {
3258 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3261 pbits &= ~(PG_RW | PG_M);
3263 #if defined(PAE) || defined(PAE_TABLES)
3264 if ((prot & VM_PROT_EXECUTE) == 0)
3268 if (pbits != obits) {
3269 #if defined(PAE) || defined(PAE_TABLES)
3270 if (!atomic_cmpset_64(pte, obits, pbits))
3273 if (!atomic_cmpset_int((u_int *)pte, obits,
3278 pmap_invalidate_page(pmap, sva);
3285 pmap_invalidate_all(pmap);
3286 if (pv_lists_locked) {
3288 rw_wunlock(&pvh_global_lock);
3294 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3295 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3296 * For promotion to occur, two conditions must be met: (1) the 4KB page
3297 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3298 * mappings must have identical characteristics.
3300 * Managed (PG_MANAGED) mappings within the kernel address space are not
3301 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3302 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3306 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3309 pt_entry_t *firstpte, oldpte, pa, *pte;
3310 vm_offset_t oldpteva;
3313 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3316 * Examine the first PTE in the specified PTP. Abort if this PTE is
3317 * either invalid, unused, or does not map the first 4KB physical page
3318 * within a 2- or 4MB page.
3320 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3323 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3324 pmap_pde_p_failures++;
3325 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3326 " in pmap %p", va, pmap);
3329 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3330 pmap_pde_p_failures++;
3331 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3332 " in pmap %p", va, pmap);
3335 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3337 * When PG_M is already clear, PG_RW can be cleared without
3338 * a TLB invalidation.
3340 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3347 * Examine each of the other PTEs in the specified PTP. Abort if this
3348 * PTE maps an unexpected 4KB physical page or does not have identical
3349 * characteristics to the first PTE.
3351 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3352 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3355 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3356 pmap_pde_p_failures++;
3357 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3358 " in pmap %p", va, pmap);
3361 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3363 * When PG_M is already clear, PG_RW can be cleared
3364 * without a TLB invalidation.
3366 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3370 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3372 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3373 " in pmap %p", oldpteva, pmap);
3375 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3376 pmap_pde_p_failures++;
3377 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3378 " in pmap %p", va, pmap);
3385 * Save the page table page in its current state until the PDE
3386 * mapping the superpage is demoted by pmap_demote_pde() or
3387 * destroyed by pmap_remove_pde().
3389 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3390 KASSERT(mpte >= vm_page_array &&
3391 mpte < &vm_page_array[vm_page_array_size],
3392 ("pmap_promote_pde: page table page is out of range"));
3393 KASSERT(mpte->pindex == va >> PDRSHIFT,
3394 ("pmap_promote_pde: page table page's pindex is wrong"));
3395 if (pmap_insert_pt_page(pmap, mpte)) {
3396 pmap_pde_p_failures++;
3398 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3404 * Promote the pv entries.
3406 if ((newpde & PG_MANAGED) != 0)
3407 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3410 * Propagate the PAT index to its proper position.
3412 if ((newpde & PG_PTE_PAT) != 0)
3413 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3416 * Map the superpage.
3418 if (workaround_erratum383)
3419 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3420 else if (pmap == kernel_pmap)
3421 pmap_kenter_pde(va, PG_PS | newpde);
3423 pde_store(pde, PG_PS | newpde);
3425 pmap_pde_promotions++;
3426 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3427 " in pmap %p", va, pmap);
3431 * Insert the given physical page (p) at
3432 * the specified virtual address (v) in the
3433 * target physical map with the protection requested.
3435 * If specified, the page will be wired down, meaning
3436 * that the related pte can not be reclaimed.
3438 * NB: This is the only routine which MAY NOT lazy-evaluate
3439 * or lose information. That is, this routine must actually
3440 * insert this page into the given map NOW.
3443 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3444 u_int flags, int8_t psind)
3448 pt_entry_t newpte, origpte;
3452 boolean_t invlva, wired;
3454 va = trunc_page(va);
3456 wired = (flags & PMAP_ENTER_WIRED) != 0;
3458 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
3459 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
3460 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)",
3462 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3463 VM_OBJECT_ASSERT_LOCKED(m->object);
3465 rw_wlock(&pvh_global_lock);
3470 * In the case that a page table page is not
3471 * resident, we are creating it here.
3473 if (va < VM_MAXUSER_ADDRESS) {
3474 mpte = pmap_allocpte(pmap, va, flags);
3476 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3477 ("pmap_allocpte failed with sleep allowed"));
3479 rw_wunlock(&pvh_global_lock);
3481 return (KERN_RESOURCE_SHORTAGE);
3485 pde = pmap_pde(pmap, va);
3486 if ((*pde & PG_PS) != 0)
3487 panic("pmap_enter: attempted pmap_enter on 4MB page");
3488 pte = pmap_pte_quick(pmap, va);
3491 * Page Directory table entry not valid, we need a new PT page
3494 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3495 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3498 pa = VM_PAGE_TO_PHYS(m);
3501 opa = origpte & PG_FRAME;
3504 * Mapping has not changed, must be protection or wiring change.
3506 if (origpte && (opa == pa)) {
3508 * Wiring change, just update stats. We don't worry about
3509 * wiring PT pages as they remain resident as long as there
3510 * are valid mappings in them. Hence, if a user page is wired,
3511 * the PT page will be also.
3513 if (wired && ((origpte & PG_W) == 0))
3514 pmap->pm_stats.wired_count++;
3515 else if (!wired && (origpte & PG_W))
3516 pmap->pm_stats.wired_count--;
3519 * Remove extra pte reference
3524 if (origpte & PG_MANAGED) {
3534 * Mapping has changed, invalidate old range and fall through to
3535 * handle validating new mapping.
3539 pmap->pm_stats.wired_count--;
3540 if (origpte & PG_MANAGED) {
3541 om = PHYS_TO_VM_PAGE(opa);
3542 pv = pmap_pvh_remove(&om->md, pmap, va);
3546 KASSERT(mpte->wire_count > 0,
3547 ("pmap_enter: missing reference to page table page,"
3551 pmap->pm_stats.resident_count++;
3554 * Enter on the PV list if part of our managed memory.
3556 if ((m->oflags & VPO_UNMANAGED) == 0) {
3557 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3558 ("pmap_enter: managed mapping within the clean submap"));
3560 pv = get_pv_entry(pmap, FALSE);
3562 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3564 } else if (pv != NULL)
3565 free_pv_entry(pmap, pv);
3568 * Increment counters
3571 pmap->pm_stats.wired_count++;
3575 * Now validate mapping with desired protection/wiring.
3577 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V);
3578 if ((prot & VM_PROT_WRITE) != 0) {
3580 if ((newpte & PG_MANAGED) != 0)
3581 vm_page_aflag_set(m, PGA_WRITEABLE);
3583 #if defined(PAE) || defined(PAE_TABLES)
3584 if ((prot & VM_PROT_EXECUTE) == 0)
3589 if (va < VM_MAXUSER_ADDRESS)
3591 if (pmap == kernel_pmap)
3595 * if the mapping or permission bits are different, we need
3596 * to update the pte.
3598 if ((origpte & ~(PG_M|PG_A)) != newpte) {
3600 if ((flags & VM_PROT_WRITE) != 0)
3602 if (origpte & PG_V) {
3604 origpte = pte_load_store(pte, newpte);
3605 if (origpte & PG_A) {
3606 if (origpte & PG_MANAGED)
3607 vm_page_aflag_set(om, PGA_REFERENCED);
3608 if (opa != VM_PAGE_TO_PHYS(m))
3610 #if defined(PAE) || defined(PAE_TABLES)
3611 if ((origpte & PG_NX) == 0 &&
3612 (newpte & PG_NX) != 0)
3616 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
3617 if ((origpte & PG_MANAGED) != 0)
3619 if ((prot & VM_PROT_WRITE) == 0)
3622 if ((origpte & PG_MANAGED) != 0 &&
3623 TAILQ_EMPTY(&om->md.pv_list) &&
3624 ((om->flags & PG_FICTITIOUS) != 0 ||
3625 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3626 vm_page_aflag_clear(om, PGA_WRITEABLE);
3628 pmap_invalidate_page(pmap, va);
3630 pte_store(pte, newpte);
3634 * If both the page table page and the reservation are fully
3635 * populated, then attempt promotion.
3637 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3638 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3639 vm_reserv_level_iffullpop(m) == 0)
3640 pmap_promote_pde(pmap, pde, va);
3643 rw_wunlock(&pvh_global_lock);
3645 return (KERN_SUCCESS);
3649 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and
3650 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
3651 * blocking, (2) a mapping already exists at the specified virtual address, or
3652 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3655 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3657 pd_entry_t *pde, newpde;
3659 rw_assert(&pvh_global_lock, RA_WLOCKED);
3660 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3661 pde = pmap_pde(pmap, va);
3663 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3664 " in pmap %p", va, pmap);
3667 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3669 if ((m->oflags & VPO_UNMANAGED) == 0) {
3670 newpde |= PG_MANAGED;
3673 * Abort this mapping if its PV entry could not be created.
3675 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) {
3676 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3677 " in pmap %p", va, pmap);
3681 #if defined(PAE) || defined(PAE_TABLES)
3682 if ((prot & VM_PROT_EXECUTE) == 0)
3685 if (va < VM_MAXUSER_ADDRESS)
3689 * Increment counters.
3691 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3694 * Map the superpage.
3696 pde_store(pde, newpde);
3698 pmap_pde_mappings++;
3699 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3700 " in pmap %p", va, pmap);
3705 * Maps a sequence of resident pages belonging to the same object.
3706 * The sequence begins with the given page m_start. This page is
3707 * mapped at the given virtual address start. Each subsequent page is
3708 * mapped at a virtual address that is offset from start by the same
3709 * amount as the page is offset from m_start within the object. The
3710 * last page in the sequence is the page with the largest offset from
3711 * m_start that can be mapped at a virtual address less than the given
3712 * virtual address end. Not every virtual page between start and end
3713 * is mapped; only those for which a resident page exists with the
3714 * corresponding offset from m_start are mapped.
3717 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3718 vm_page_t m_start, vm_prot_t prot)
3722 vm_pindex_t diff, psize;
3724 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3726 psize = atop(end - start);
3729 rw_wlock(&pvh_global_lock);
3731 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3732 va = start + ptoa(diff);
3733 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3734 m->psind == 1 && pg_ps_enabled &&
3735 pmap_enter_pde(pmap, va, m, prot))
3736 m = &m[NBPDR / PAGE_SIZE - 1];
3738 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3740 m = TAILQ_NEXT(m, listq);
3742 rw_wunlock(&pvh_global_lock);
3747 * this code makes some *MAJOR* assumptions:
3748 * 1. Current pmap & pmap exists.
3751 * 4. No page table pages.
3752 * but is *MUCH* faster than pmap_enter...
3756 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3759 rw_wlock(&pvh_global_lock);
3761 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
3762 rw_wunlock(&pvh_global_lock);
3767 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3768 vm_prot_t prot, vm_page_t mpte)
3772 struct spglist free;
3774 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3775 (m->oflags & VPO_UNMANAGED) != 0,
3776 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3777 rw_assert(&pvh_global_lock, RA_WLOCKED);
3778 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3781 * In the case that a page table page is not
3782 * resident, we are creating it here.
3784 if (va < VM_MAXUSER_ADDRESS) {
3789 * Calculate pagetable page index
3791 ptepindex = va >> PDRSHIFT;
3792 if (mpte && (mpte->pindex == ptepindex)) {
3796 * Get the page directory entry
3798 ptepa = pmap->pm_pdir[ptepindex];
3801 * If the page table page is mapped, we just increment
3802 * the hold count, and activate it.
3807 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
3810 mpte = _pmap_allocpte(pmap, ptepindex,
3811 PMAP_ENTER_NOSLEEP);
3821 * This call to vtopte makes the assumption that we are
3822 * entering the page into the current pmap. In order to support
3823 * quick entry into any pmap, one would likely use pmap_pte_quick.
3824 * But that isn't as quick as vtopte.
3836 * Enter on the PV list if part of our managed memory.
3838 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3839 !pmap_try_insert_pv_entry(pmap, va, m)) {
3842 if (pmap_unwire_ptp(pmap, mpte, &free)) {
3843 pmap_invalidate_page(pmap, va);
3844 pmap_free_zero_pages(&free);
3853 * Increment counters
3855 pmap->pm_stats.resident_count++;
3857 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3858 #if defined(PAE) || defined(PAE_TABLES)
3859 if ((prot & VM_PROT_EXECUTE) == 0)
3864 * Now validate mapping with RO protection
3866 if ((m->oflags & VPO_UNMANAGED) != 0)
3867 pte_store(pte, pa | PG_V | PG_U);
3869 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3874 * Make a temporary mapping for a physical address. This is only intended
3875 * to be used for panic dumps.
3878 pmap_kenter_temporary(vm_paddr_t pa, int i)
3882 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3883 pmap_kenter(va, pa);
3885 return ((void *)crashdumpmap);
3889 * This code maps large physical mmap regions into the
3890 * processor address space. Note that some shortcuts
3891 * are taken, but the code works.
3894 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3895 vm_pindex_t pindex, vm_size_t size)
3898 vm_paddr_t pa, ptepa;
3902 VM_OBJECT_ASSERT_WLOCKED(object);
3903 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3904 ("pmap_object_init_pt: non-device object"));
3906 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3907 if (!vm_object_populate(object, pindex, pindex + atop(size)))
3909 p = vm_page_lookup(object, pindex);
3910 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3911 ("pmap_object_init_pt: invalid page %p", p));
3912 pat_mode = p->md.pat_mode;
3915 * Abort the mapping if the first page is not physically
3916 * aligned to a 2/4MB page boundary.
3918 ptepa = VM_PAGE_TO_PHYS(p);
3919 if (ptepa & (NBPDR - 1))
3923 * Skip the first page. Abort the mapping if the rest of
3924 * the pages are not physically contiguous or have differing
3925 * memory attributes.
3927 p = TAILQ_NEXT(p, listq);
3928 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
3930 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3931 ("pmap_object_init_pt: invalid page %p", p));
3932 if (pa != VM_PAGE_TO_PHYS(p) ||
3933 pat_mode != p->md.pat_mode)
3935 p = TAILQ_NEXT(p, listq);
3939 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
3940 * "size" is a multiple of 2/4M, adding the PAT setting to
3941 * "pa" will not affect the termination of this loop.
3944 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
3945 size; pa += NBPDR) {
3946 pde = pmap_pde(pmap, addr);
3948 pde_store(pde, pa | PG_PS | PG_M | PG_A |
3949 PG_U | PG_RW | PG_V);
3950 pmap->pm_stats.resident_count += NBPDR /
3952 pmap_pde_mappings++;
3954 /* Else continue on if the PDE is already valid. */
3962 * Clear the wired attribute from the mappings for the specified range of
3963 * addresses in the given pmap. Every valid mapping within that range
3964 * must have the wired attribute set. In contrast, invalid mappings
3965 * cannot have the wired attribute set, so they are ignored.
3967 * The wired attribute of the page table entry is not a hardware feature,
3968 * so there is no need to invalidate any TLB entries.
3971 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3976 boolean_t pv_lists_locked;
3978 if (pmap_is_current(pmap))
3979 pv_lists_locked = FALSE;
3981 pv_lists_locked = TRUE;
3983 rw_wlock(&pvh_global_lock);
3987 for (; sva < eva; sva = pdnxt) {
3988 pdnxt = (sva + NBPDR) & ~PDRMASK;
3991 pde = pmap_pde(pmap, sva);
3992 if ((*pde & PG_V) == 0)
3994 if ((*pde & PG_PS) != 0) {
3995 if ((*pde & PG_W) == 0)
3996 panic("pmap_unwire: pde %#jx is missing PG_W",
4000 * Are we unwiring the entire large page? If not,
4001 * demote the mapping and fall through.
4003 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4005 * Regardless of whether a pde (or pte) is 32
4006 * or 64 bits in size, PG_W is among the least
4007 * significant 32 bits.
4009 atomic_clear_int((u_int *)pde, PG_W);
4010 pmap->pm_stats.wired_count -= NBPDR /
4014 if (!pv_lists_locked) {
4015 pv_lists_locked = TRUE;
4016 if (!rw_try_wlock(&pvh_global_lock)) {
4023 if (!pmap_demote_pde(pmap, pde, sva))
4024 panic("pmap_unwire: demotion failed");
4029 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4031 if ((*pte & PG_V) == 0)
4033 if ((*pte & PG_W) == 0)
4034 panic("pmap_unwire: pte %#jx is missing PG_W",
4038 * PG_W must be cleared atomically. Although the pmap
4039 * lock synchronizes access to PG_W, another processor
4040 * could be setting PG_M and/or PG_A concurrently.
4042 * PG_W is among the least significant 32 bits.
4044 atomic_clear_int((u_int *)pte, PG_W);
4045 pmap->pm_stats.wired_count--;
4048 if (pv_lists_locked) {
4050 rw_wunlock(&pvh_global_lock);
4057 * Copy the range specified by src_addr/len
4058 * from the source map to the range dst_addr/len
4059 * in the destination map.
4061 * This routine is only advisory and need not do anything.
4065 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4066 vm_offset_t src_addr)
4068 struct spglist free;
4070 vm_offset_t end_addr = src_addr + len;
4073 if (dst_addr != src_addr)
4076 if (!pmap_is_current(src_pmap))
4079 rw_wlock(&pvh_global_lock);
4080 if (dst_pmap < src_pmap) {
4081 PMAP_LOCK(dst_pmap);
4082 PMAP_LOCK(src_pmap);
4084 PMAP_LOCK(src_pmap);
4085 PMAP_LOCK(dst_pmap);
4088 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4089 pt_entry_t *src_pte, *dst_pte;
4090 vm_page_t dstmpte, srcmpte;
4091 pd_entry_t srcptepaddr;
4094 KASSERT(addr < UPT_MIN_ADDRESS,
4095 ("pmap_copy: invalid to pmap_copy page tables"));
4097 pdnxt = (addr + NBPDR) & ~PDRMASK;
4100 ptepindex = addr >> PDRSHIFT;
4102 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4103 if (srcptepaddr == 0)
4106 if (srcptepaddr & PG_PS) {
4107 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4109 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4110 ((srcptepaddr & PG_MANAGED) == 0 ||
4111 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4113 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4115 dst_pmap->pm_stats.resident_count +=
4117 pmap_pde_mappings++;
4122 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4123 KASSERT(srcmpte->wire_count > 0,
4124 ("pmap_copy: source page table page is unused"));
4126 if (pdnxt > end_addr)
4129 src_pte = vtopte(addr);
4130 while (addr < pdnxt) {
4134 * we only virtual copy managed pages
4136 if ((ptetemp & PG_MANAGED) != 0) {
4137 dstmpte = pmap_allocpte(dst_pmap, addr,
4138 PMAP_ENTER_NOSLEEP);
4139 if (dstmpte == NULL)
4141 dst_pte = pmap_pte_quick(dst_pmap, addr);
4142 if (*dst_pte == 0 &&
4143 pmap_try_insert_pv_entry(dst_pmap, addr,
4144 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4146 * Clear the wired, modified, and
4147 * accessed (referenced) bits
4150 *dst_pte = ptetemp & ~(PG_W | PG_M |
4152 dst_pmap->pm_stats.resident_count++;
4155 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4157 pmap_invalidate_page(dst_pmap,
4159 pmap_free_zero_pages(&free);
4163 if (dstmpte->wire_count >= srcmpte->wire_count)
4172 rw_wunlock(&pvh_global_lock);
4173 PMAP_UNLOCK(src_pmap);
4174 PMAP_UNLOCK(dst_pmap);
4178 * Zero 1 page of virtual memory mapped from a hardware page by the caller.
4180 static __inline void
4181 pagezero(void *page)
4183 #if defined(I686_CPU)
4184 if (cpu_class == CPUCLASS_686) {
4185 #if defined(CPU_ENABLE_SSE)
4186 if (cpu_feature & CPUID_SSE2)
4187 sse2_pagezero(page);
4190 i686_pagezero(page);
4193 bzero(page, PAGE_SIZE);
4197 * Zero the specified hardware page.
4200 pmap_zero_page(vm_page_t m)
4202 struct sysmaps *sysmaps;
4204 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4205 mtx_lock(&sysmaps->lock);
4206 if (*sysmaps->CMAP2)
4207 panic("pmap_zero_page: CMAP2 busy");
4209 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4210 pmap_cache_bits(m->md.pat_mode, 0);
4211 invlcaddr(sysmaps->CADDR2);
4212 pagezero(sysmaps->CADDR2);
4213 *sysmaps->CMAP2 = 0;
4215 mtx_unlock(&sysmaps->lock);
4219 * Zero an an area within a single hardware page. off and size must not
4220 * cover an area beyond a single hardware page.
4223 pmap_zero_page_area(vm_page_t m, int off, int size)
4225 struct sysmaps *sysmaps;
4227 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4228 mtx_lock(&sysmaps->lock);
4229 if (*sysmaps->CMAP2)
4230 panic("pmap_zero_page_area: CMAP2 busy");
4232 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4233 pmap_cache_bits(m->md.pat_mode, 0);
4234 invlcaddr(sysmaps->CADDR2);
4235 if (off == 0 && size == PAGE_SIZE)
4236 pagezero(sysmaps->CADDR2);
4238 bzero((char *)sysmaps->CADDR2 + off, size);
4239 *sysmaps->CMAP2 = 0;
4241 mtx_unlock(&sysmaps->lock);
4245 * Copy 1 specified hardware page to another.
4248 pmap_copy_page(vm_page_t src, vm_page_t dst)
4250 struct sysmaps *sysmaps;
4252 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4253 mtx_lock(&sysmaps->lock);
4254 if (*sysmaps->CMAP1)
4255 panic("pmap_copy_page: CMAP1 busy");
4256 if (*sysmaps->CMAP2)
4257 panic("pmap_copy_page: CMAP2 busy");
4259 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4260 pmap_cache_bits(src->md.pat_mode, 0);
4261 invlcaddr(sysmaps->CADDR1);
4262 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4263 pmap_cache_bits(dst->md.pat_mode, 0);
4264 invlcaddr(sysmaps->CADDR2);
4265 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE);
4266 *sysmaps->CMAP1 = 0;
4267 *sysmaps->CMAP2 = 0;
4269 mtx_unlock(&sysmaps->lock);
4272 int unmapped_buf_allowed = 1;
4275 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4276 vm_offset_t b_offset, int xfersize)
4278 struct sysmaps *sysmaps;
4279 vm_page_t a_pg, b_pg;
4281 vm_offset_t a_pg_offset, b_pg_offset;
4284 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4285 mtx_lock(&sysmaps->lock);
4286 if (*sysmaps->CMAP1 != 0)
4287 panic("pmap_copy_pages: CMAP1 busy");
4288 if (*sysmaps->CMAP2 != 0)
4289 panic("pmap_copy_pages: CMAP2 busy");
4291 while (xfersize > 0) {
4292 a_pg = ma[a_offset >> PAGE_SHIFT];
4293 a_pg_offset = a_offset & PAGE_MASK;
4294 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4295 b_pg = mb[b_offset >> PAGE_SHIFT];
4296 b_pg_offset = b_offset & PAGE_MASK;
4297 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4298 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4299 pmap_cache_bits(a_pg->md.pat_mode, 0);
4300 invlcaddr(sysmaps->CADDR1);
4301 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4302 PG_M | pmap_cache_bits(b_pg->md.pat_mode, 0);
4303 invlcaddr(sysmaps->CADDR2);
4304 a_cp = sysmaps->CADDR1 + a_pg_offset;
4305 b_cp = sysmaps->CADDR2 + b_pg_offset;
4306 bcopy(a_cp, b_cp, cnt);
4311 *sysmaps->CMAP1 = 0;
4312 *sysmaps->CMAP2 = 0;
4314 mtx_unlock(&sysmaps->lock);
4318 * Returns true if the pmap's pv is one of the first
4319 * 16 pvs linked to from this page. This count may
4320 * be changed upwards or downwards in the future; it
4321 * is only necessary that true be returned for a small
4322 * subset of pmaps for proper page aging.
4325 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4327 struct md_page *pvh;
4332 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4333 ("pmap_page_exists_quick: page %p is not managed", m));
4335 rw_wlock(&pvh_global_lock);
4336 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4337 if (PV_PMAP(pv) == pmap) {
4345 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4346 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4347 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4348 if (PV_PMAP(pv) == pmap) {
4357 rw_wunlock(&pvh_global_lock);
4362 * pmap_page_wired_mappings:
4364 * Return the number of managed mappings to the given physical page
4368 pmap_page_wired_mappings(vm_page_t m)
4373 if ((m->oflags & VPO_UNMANAGED) != 0)
4375 rw_wlock(&pvh_global_lock);
4376 count = pmap_pvh_wired_mappings(&m->md, count);
4377 if ((m->flags & PG_FICTITIOUS) == 0) {
4378 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4381 rw_wunlock(&pvh_global_lock);
4386 * pmap_pvh_wired_mappings:
4388 * Return the updated number "count" of managed mappings that are wired.
4391 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4397 rw_assert(&pvh_global_lock, RA_WLOCKED);
4399 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4402 pte = pmap_pte_quick(pmap, pv->pv_va);
4403 if ((*pte & PG_W) != 0)
4412 * Returns TRUE if the given page is mapped individually or as part of
4413 * a 4mpage. Otherwise, returns FALSE.
4416 pmap_page_is_mapped(vm_page_t m)
4420 if ((m->oflags & VPO_UNMANAGED) != 0)
4422 rw_wlock(&pvh_global_lock);
4423 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4424 ((m->flags & PG_FICTITIOUS) == 0 &&
4425 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4426 rw_wunlock(&pvh_global_lock);
4431 * Remove all pages from specified address space
4432 * this aids process exit speeds. Also, this code
4433 * is special cased for current process only, but
4434 * can have the more generic (and slightly slower)
4435 * mode enabled. This is much faster than pmap_remove
4436 * in the case of running down an entire address space.
4439 pmap_remove_pages(pmap_t pmap)
4441 pt_entry_t *pte, tpte;
4442 vm_page_t m, mpte, mt;
4444 struct md_page *pvh;
4445 struct pv_chunk *pc, *npc;
4446 struct spglist free;
4449 uint32_t inuse, bitmask;
4452 if (pmap != PCPU_GET(curpmap)) {
4453 printf("warning: pmap_remove_pages called with non-current pmap\n");
4457 rw_wlock(&pvh_global_lock);
4460 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4461 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4464 for (field = 0; field < _NPCM; field++) {
4465 inuse = ~pc->pc_map[field] & pc_freemask[field];
4466 while (inuse != 0) {
4468 bitmask = 1UL << bit;
4469 idx = field * 32 + bit;
4470 pv = &pc->pc_pventry[idx];
4473 pte = pmap_pde(pmap, pv->pv_va);
4475 if ((tpte & PG_PS) == 0) {
4476 pte = vtopte(pv->pv_va);
4477 tpte = *pte & ~PG_PTE_PAT;
4482 "TPTE at %p IS ZERO @ VA %08x\n",
4488 * We cannot remove wired pages from a process' mapping at this time
4495 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4496 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4497 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4498 m, (uintmax_t)m->phys_addr,
4501 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4502 m < &vm_page_array[vm_page_array_size],
4503 ("pmap_remove_pages: bad tpte %#jx",
4509 * Update the vm_page_t clean/reference bits.
4511 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4512 if ((tpte & PG_PS) != 0) {
4513 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4520 PV_STAT(pv_entry_frees++);
4521 PV_STAT(pv_entry_spare++);
4523 pc->pc_map[field] |= bitmask;
4524 if ((tpte & PG_PS) != 0) {
4525 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4526 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4527 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4528 if (TAILQ_EMPTY(&pvh->pv_list)) {
4529 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4530 if (TAILQ_EMPTY(&mt->md.pv_list))
4531 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4533 mpte = pmap_lookup_pt_page(pmap, pv->pv_va);
4535 pmap_remove_pt_page(pmap, mpte);
4536 pmap->pm_stats.resident_count--;
4537 KASSERT(mpte->wire_count == NPTEPG,
4538 ("pmap_remove_pages: pte page wire count error"));
4539 mpte->wire_count = 0;
4540 pmap_add_delayed_free_list(mpte, &free, FALSE);
4541 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
4544 pmap->pm_stats.resident_count--;
4545 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4546 if (TAILQ_EMPTY(&m->md.pv_list) &&
4547 (m->flags & PG_FICTITIOUS) == 0) {
4548 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4549 if (TAILQ_EMPTY(&pvh->pv_list))
4550 vm_page_aflag_clear(m, PGA_WRITEABLE);
4552 pmap_unuse_pt(pmap, pv->pv_va, &free);
4557 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4562 pmap_invalidate_all(pmap);
4563 rw_wunlock(&pvh_global_lock);
4565 pmap_free_zero_pages(&free);
4571 * Return whether or not the specified physical page was modified
4572 * in any physical maps.
4575 pmap_is_modified(vm_page_t m)
4579 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4580 ("pmap_is_modified: page %p is not managed", m));
4583 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4584 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4585 * is clear, no PTEs can have PG_M set.
4587 VM_OBJECT_ASSERT_WLOCKED(m->object);
4588 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4590 rw_wlock(&pvh_global_lock);
4591 rv = pmap_is_modified_pvh(&m->md) ||
4592 ((m->flags & PG_FICTITIOUS) == 0 &&
4593 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4594 rw_wunlock(&pvh_global_lock);
4599 * Returns TRUE if any of the given mappings were used to modify
4600 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4601 * mappings are supported.
4604 pmap_is_modified_pvh(struct md_page *pvh)
4611 rw_assert(&pvh_global_lock, RA_WLOCKED);
4614 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4617 pte = pmap_pte_quick(pmap, pv->pv_va);
4618 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4628 * pmap_is_prefaultable:
4630 * Return whether or not the specified virtual address is elgible
4634 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4642 pde = pmap_pde(pmap, addr);
4643 if (*pde != 0 && (*pde & PG_PS) == 0) {
4652 * pmap_is_referenced:
4654 * Return whether or not the specified physical page was referenced
4655 * in any physical maps.
4658 pmap_is_referenced(vm_page_t m)
4662 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4663 ("pmap_is_referenced: page %p is not managed", m));
4664 rw_wlock(&pvh_global_lock);
4665 rv = pmap_is_referenced_pvh(&m->md) ||
4666 ((m->flags & PG_FICTITIOUS) == 0 &&
4667 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4668 rw_wunlock(&pvh_global_lock);
4673 * Returns TRUE if any of the given mappings were referenced and FALSE
4674 * otherwise. Both page and 4mpage mappings are supported.
4677 pmap_is_referenced_pvh(struct md_page *pvh)
4684 rw_assert(&pvh_global_lock, RA_WLOCKED);
4687 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4690 pte = pmap_pte_quick(pmap, pv->pv_va);
4691 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4701 * Clear the write and modified bits in each of the given page's mappings.
4704 pmap_remove_write(vm_page_t m)
4706 struct md_page *pvh;
4707 pv_entry_t next_pv, pv;
4710 pt_entry_t oldpte, *pte;
4713 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4714 ("pmap_remove_write: page %p is not managed", m));
4717 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4718 * set by another thread while the object is locked. Thus,
4719 * if PGA_WRITEABLE is clear, no page table entries need updating.
4721 VM_OBJECT_ASSERT_WLOCKED(m->object);
4722 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4724 rw_wlock(&pvh_global_lock);
4726 if ((m->flags & PG_FICTITIOUS) != 0)
4727 goto small_mappings;
4728 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4729 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4733 pde = pmap_pde(pmap, va);
4734 if ((*pde & PG_RW) != 0)
4735 (void)pmap_demote_pde(pmap, pde, va);
4739 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4742 pde = pmap_pde(pmap, pv->pv_va);
4743 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
4744 " a 4mpage in page %p's pv list", m));
4745 pte = pmap_pte_quick(pmap, pv->pv_va);
4748 if ((oldpte & PG_RW) != 0) {
4750 * Regardless of whether a pte is 32 or 64 bits
4751 * in size, PG_RW and PG_M are among the least
4752 * significant 32 bits.
4754 if (!atomic_cmpset_int((u_int *)pte, oldpte,
4755 oldpte & ~(PG_RW | PG_M)))
4757 if ((oldpte & PG_M) != 0)
4759 pmap_invalidate_page(pmap, pv->pv_va);
4763 vm_page_aflag_clear(m, PGA_WRITEABLE);
4765 rw_wunlock(&pvh_global_lock);
4768 #define PMAP_TS_REFERENCED_MAX 5
4771 * pmap_ts_referenced:
4773 * Return a count of reference bits for a page, clearing those bits.
4774 * It is not necessary for every reference bit to be cleared, but it
4775 * is necessary that 0 only be returned when there are truly no
4776 * reference bits set.
4778 * XXX: The exact number of bits to check and clear is a matter that
4779 * should be tested and standardized at some point in the future for
4780 * optimal aging of shared pages.
4782 * As an optimization, update the page's dirty field if a modified bit is
4783 * found while counting reference bits. This opportunistic update can be
4784 * performed at low cost and can eliminate the need for some future calls
4785 * to pmap_is_modified(). However, since this function stops after
4786 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4787 * dirty pages. Those dirty pages will only be detected by a future call
4788 * to pmap_is_modified().
4791 pmap_ts_referenced(vm_page_t m)
4793 struct md_page *pvh;
4801 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4802 ("pmap_ts_referenced: page %p is not managed", m));
4803 pa = VM_PAGE_TO_PHYS(m);
4804 pvh = pa_to_pvh(pa);
4805 rw_wlock(&pvh_global_lock);
4807 if ((m->flags & PG_FICTITIOUS) != 0 ||
4808 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4809 goto small_mappings;
4814 pde = pmap_pde(pmap, pv->pv_va);
4815 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4817 * Although "*pde" is mapping a 2/4MB page, because
4818 * this function is called at a 4KB page granularity,
4819 * we only update the 4KB page under test.
4823 if ((*pde & PG_A) != 0) {
4825 * Since this reference bit is shared by either 1024
4826 * or 512 4KB pages, it should not be cleared every
4827 * time it is tested. Apply a simple "hash" function
4828 * on the physical page number, the virtual superpage
4829 * number, and the pmap address to select one 4KB page
4830 * out of the 1024 or 512 on which testing the
4831 * reference bit will result in clearing that bit.
4832 * This function is designed to avoid the selection of
4833 * the same 4KB page for every 2- or 4MB page mapping.
4835 * On demotion, a mapping that hasn't been referenced
4836 * is simply destroyed. To avoid the possibility of a
4837 * subsequent page fault on a demoted wired mapping,
4838 * always leave its reference bit set. Moreover,
4839 * since the superpage is wired, the current state of
4840 * its reference bit won't affect page replacement.
4842 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
4843 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
4844 (*pde & PG_W) == 0) {
4845 atomic_clear_int((u_int *)pde, PG_A);
4846 pmap_invalidate_page(pmap, pv->pv_va);
4851 /* Rotate the PV list if it has more than one entry. */
4852 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4853 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4854 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4856 if (rtval >= PMAP_TS_REFERENCED_MAX)
4858 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4860 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4866 pde = pmap_pde(pmap, pv->pv_va);
4867 KASSERT((*pde & PG_PS) == 0,
4868 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
4870 pte = pmap_pte_quick(pmap, pv->pv_va);
4871 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4873 if ((*pte & PG_A) != 0) {
4874 atomic_clear_int((u_int *)pte, PG_A);
4875 pmap_invalidate_page(pmap, pv->pv_va);
4879 /* Rotate the PV list if it has more than one entry. */
4880 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4881 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4882 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4884 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
4885 PMAP_TS_REFERENCED_MAX);
4888 rw_wunlock(&pvh_global_lock);
4893 * Apply the given advice to the specified range of addresses within the
4894 * given pmap. Depending on the advice, clear the referenced and/or
4895 * modified flags in each mapping and set the mapped page's dirty field.
4898 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4900 pd_entry_t oldpde, *pde;
4904 boolean_t anychanged, pv_lists_locked;
4906 if (advice != MADV_DONTNEED && advice != MADV_FREE)
4908 if (pmap_is_current(pmap))
4909 pv_lists_locked = FALSE;
4911 pv_lists_locked = TRUE;
4913 rw_wlock(&pvh_global_lock);
4918 for (; sva < eva; sva = pdnxt) {
4919 pdnxt = (sva + NBPDR) & ~PDRMASK;
4922 pde = pmap_pde(pmap, sva);
4924 if ((oldpde & PG_V) == 0)
4926 else if ((oldpde & PG_PS) != 0) {
4927 if ((oldpde & PG_MANAGED) == 0)
4929 if (!pv_lists_locked) {
4930 pv_lists_locked = TRUE;
4931 if (!rw_try_wlock(&pvh_global_lock)) {
4933 pmap_invalidate_all(pmap);
4939 if (!pmap_demote_pde(pmap, pde, sva)) {
4941 * The large page mapping was destroyed.
4947 * Unless the page mappings are wired, remove the
4948 * mapping to a single page so that a subsequent
4949 * access may repromote. Since the underlying page
4950 * table page is fully populated, this removal never
4951 * frees a page table page.
4953 if ((oldpde & PG_W) == 0) {
4954 pte = pmap_pte_quick(pmap, sva);
4955 KASSERT((*pte & PG_V) != 0,
4956 ("pmap_advise: invalid PTE"));
4957 pmap_remove_pte(pmap, pte, sva, NULL);
4963 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4965 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED |
4968 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4969 if (advice == MADV_DONTNEED) {
4971 * Future calls to pmap_is_modified()
4972 * can be avoided by making the page
4975 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
4978 atomic_clear_int((u_int *)pte, PG_M | PG_A);
4979 } else if ((*pte & PG_A) != 0)
4980 atomic_clear_int((u_int *)pte, PG_A);
4983 if ((*pte & PG_G) != 0)
4984 pmap_invalidate_page(pmap, sva);
4990 pmap_invalidate_all(pmap);
4991 if (pv_lists_locked) {
4993 rw_wunlock(&pvh_global_lock);
4999 * Clear the modify bits on the specified physical page.
5002 pmap_clear_modify(vm_page_t m)
5004 struct md_page *pvh;
5005 pv_entry_t next_pv, pv;
5007 pd_entry_t oldpde, *pde;
5008 pt_entry_t oldpte, *pte;
5011 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5012 ("pmap_clear_modify: page %p is not managed", m));
5013 VM_OBJECT_ASSERT_WLOCKED(m->object);
5014 KASSERT(!vm_page_xbusied(m),
5015 ("pmap_clear_modify: page %p is exclusive busied", m));
5018 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5019 * If the object containing the page is locked and the page is not
5020 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5022 if ((m->aflags & PGA_WRITEABLE) == 0)
5024 rw_wlock(&pvh_global_lock);
5026 if ((m->flags & PG_FICTITIOUS) != 0)
5027 goto small_mappings;
5028 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5029 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5033 pde = pmap_pde(pmap, va);
5035 if ((oldpde & PG_RW) != 0) {
5036 if (pmap_demote_pde(pmap, pde, va)) {
5037 if ((oldpde & PG_W) == 0) {
5039 * Write protect the mapping to a
5040 * single page so that a subsequent
5041 * write access may repromote.
5043 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5045 pte = pmap_pte_quick(pmap, va);
5047 if ((oldpte & PG_V) != 0) {
5049 * Regardless of whether a pte is 32 or 64 bits
5050 * in size, PG_RW and PG_M are among the least
5051 * significant 32 bits.
5053 while (!atomic_cmpset_int((u_int *)pte,
5055 oldpte & ~(PG_M | PG_RW)))
5058 pmap_invalidate_page(pmap, va);
5066 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5069 pde = pmap_pde(pmap, pv->pv_va);
5070 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5071 " a 4mpage in page %p's pv list", m));
5072 pte = pmap_pte_quick(pmap, pv->pv_va);
5073 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5075 * Regardless of whether a pte is 32 or 64 bits
5076 * in size, PG_M is among the least significant
5079 atomic_clear_int((u_int *)pte, PG_M);
5080 pmap_invalidate_page(pmap, pv->pv_va);
5085 rw_wunlock(&pvh_global_lock);
5089 * Miscellaneous support routines follow
5092 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5093 static __inline void
5094 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5099 * The cache mode bits are all in the low 32-bits of the
5100 * PTE, so we can just spin on updating the low 32-bits.
5103 opte = *(u_int *)pte;
5104 npte = opte & ~PG_PTE_CACHE;
5106 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5109 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5110 static __inline void
5111 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5116 * The cache mode bits are all in the low 32-bits of the
5117 * PDE, so we can just spin on updating the low 32-bits.
5120 opde = *(u_int *)pde;
5121 npde = opde & ~PG_PDE_CACHE;
5123 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5127 * Map a set of physical memory pages into the kernel virtual
5128 * address space. Return a pointer to where it is mapped. This
5129 * routine is intended to be used for mapping device memory,
5133 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5135 struct pmap_preinit_mapping *ppim;
5136 vm_offset_t va, offset;
5140 offset = pa & PAGE_MASK;
5141 size = round_page(offset + size);
5144 if (pa < KERNLOAD && pa + size <= KERNLOAD)
5146 else if (!pmap_initialized) {
5148 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5149 ppim = pmap_preinit_mapping + i;
5150 if (ppim->va == 0) {
5154 ppim->va = virtual_avail;
5155 virtual_avail += size;
5161 panic("%s: too many preinit mappings", __func__);
5164 * If we have a preinit mapping, re-use it.
5166 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5167 ppim = pmap_preinit_mapping + i;
5168 if (ppim->pa == pa && ppim->sz == size &&
5170 return ((void *)(ppim->va + offset));
5172 va = kva_alloc(size);
5174 panic("%s: Couldn't allocate KVA", __func__);
5176 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5177 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5178 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5179 pmap_invalidate_cache_range(va, va + size, FALSE);
5180 return ((void *)(va + offset));
5184 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5187 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5191 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5194 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5198 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5200 struct pmap_preinit_mapping *ppim;
5204 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD)
5206 offset = va & PAGE_MASK;
5207 size = round_page(offset + size);
5208 va = trunc_page(va);
5209 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5210 ppim = pmap_preinit_mapping + i;
5211 if (ppim->va == va && ppim->sz == size) {
5212 if (pmap_initialized)
5218 if (va + size == virtual_avail)
5223 if (pmap_initialized)
5228 * Sets the memory attribute for the specified page.
5231 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5234 m->md.pat_mode = ma;
5235 if ((m->flags & PG_FICTITIOUS) != 0)
5239 * If "m" is a normal page, flush it from the cache.
5240 * See pmap_invalidate_cache_range().
5242 * First, try to find an existing mapping of the page by sf
5243 * buffer. sf_buf_invalidate_cache() modifies mapping and
5244 * flushes the cache.
5246 if (sf_buf_invalidate_cache(m))
5250 * If page is not mapped by sf buffer, but CPU does not
5251 * support self snoop, map the page transient and do
5252 * invalidation. In the worst case, whole cache is flushed by
5253 * pmap_invalidate_cache_range().
5255 if ((cpu_feature & CPUID_SS) == 0)
5260 pmap_flush_page(vm_page_t m)
5262 struct sysmaps *sysmaps;
5263 vm_offset_t sva, eva;
5266 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5267 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5268 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
5269 mtx_lock(&sysmaps->lock);
5270 if (*sysmaps->CMAP2)
5271 panic("pmap_flush_page: CMAP2 busy");
5273 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5274 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0);
5275 invlcaddr(sysmaps->CADDR2);
5276 sva = (vm_offset_t)sysmaps->CADDR2;
5277 eva = sva + PAGE_SIZE;
5280 * Use mfence despite the ordering implied by
5281 * mtx_{un,}lock() because clflush on non-Intel CPUs
5282 * and clflushopt are not guaranteed to be ordered by
5283 * any other instruction.
5285 if (useclflushopt || cpu_vendor_id != CPU_VENDOR_INTEL)
5287 for (; sva < eva; sva += cpu_clflush_line_size) {
5293 if (useclflushopt || cpu_vendor_id != CPU_VENDOR_INTEL)
5295 *sysmaps->CMAP2 = 0;
5297 mtx_unlock(&sysmaps->lock);
5299 pmap_invalidate_cache();
5303 * Changes the specified virtual address range's memory type to that given by
5304 * the parameter "mode". The specified virtual address range must be
5305 * completely contained within either the kernel map.
5307 * Returns zero if the change completed successfully, and either EINVAL or
5308 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5309 * of the virtual address range was not mapped, and ENOMEM is returned if
5310 * there was insufficient memory available to complete the change.
5313 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5315 vm_offset_t base, offset, tmpva;
5318 int cache_bits_pte, cache_bits_pde;
5321 base = trunc_page(va);
5322 offset = va & PAGE_MASK;
5323 size = round_page(offset + size);
5326 * Only supported on kernel virtual addresses above the recursive map.
5328 if (base < VM_MIN_KERNEL_ADDRESS)
5331 cache_bits_pde = pmap_cache_bits(mode, 1);
5332 cache_bits_pte = pmap_cache_bits(mode, 0);
5336 * Pages that aren't mapped aren't supported. Also break down
5337 * 2/4MB pages into 4KB pages if required.
5339 PMAP_LOCK(kernel_pmap);
5340 for (tmpva = base; tmpva < base + size; ) {
5341 pde = pmap_pde(kernel_pmap, tmpva);
5343 PMAP_UNLOCK(kernel_pmap);
5348 * If the current 2/4MB page already has
5349 * the required memory type, then we need not
5350 * demote this page. Just increment tmpva to
5351 * the next 2/4MB page frame.
5353 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5354 tmpva = trunc_4mpage(tmpva) + NBPDR;
5359 * If the current offset aligns with a 2/4MB
5360 * page frame and there is at least 2/4MB left
5361 * within the range, then we need not break
5362 * down this page into 4KB pages.
5364 if ((tmpva & PDRMASK) == 0 &&
5365 tmpva + PDRMASK < base + size) {
5369 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5370 PMAP_UNLOCK(kernel_pmap);
5374 pte = vtopte(tmpva);
5376 PMAP_UNLOCK(kernel_pmap);
5381 PMAP_UNLOCK(kernel_pmap);
5384 * Ok, all the pages exist, so run through them updating their
5385 * cache mode if required.
5387 for (tmpva = base; tmpva < base + size; ) {
5388 pde = pmap_pde(kernel_pmap, tmpva);
5390 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5391 pmap_pde_attr(pde, cache_bits_pde);
5394 tmpva = trunc_4mpage(tmpva) + NBPDR;
5396 pte = vtopte(tmpva);
5397 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5398 pmap_pte_attr(pte, cache_bits_pte);
5406 * Flush CPU caches to make sure any data isn't cached that
5407 * shouldn't be, etc.
5410 pmap_invalidate_range(kernel_pmap, base, tmpva);
5411 pmap_invalidate_cache_range(base, tmpva, FALSE);
5417 * perform the pmap work for mincore
5420 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5423 pt_entry_t *ptep, pte;
5429 pdep = pmap_pde(pmap, addr);
5431 if (*pdep & PG_PS) {
5433 /* Compute the physical address of the 4KB page. */
5434 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5436 val = MINCORE_SUPER;
5438 ptep = pmap_pte(pmap, addr);
5440 pmap_pte_release(ptep);
5441 pa = pte & PG_FRAME;
5449 if ((pte & PG_V) != 0) {
5450 val |= MINCORE_INCORE;
5451 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5452 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5453 if ((pte & PG_A) != 0)
5454 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5456 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5457 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5458 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5459 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5460 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5463 PA_UNLOCK_COND(*locked_pa);
5469 pmap_activate(struct thread *td)
5471 pmap_t pmap, oldpmap;
5476 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5477 oldpmap = PCPU_GET(curpmap);
5478 cpuid = PCPU_GET(cpuid);
5480 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5481 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5483 CPU_CLR(cpuid, &oldpmap->pm_active);
5484 CPU_SET(cpuid, &pmap->pm_active);
5486 #if defined(PAE) || defined(PAE_TABLES)
5487 cr3 = vtophys(pmap->pm_pdpt);
5489 cr3 = vtophys(pmap->pm_pdir);
5492 * pmap_activate is for the current thread on the current cpu
5494 td->td_pcb->pcb_cr3 = cr3;
5496 PCPU_SET(curpmap, pmap);
5501 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5506 * Increase the starting virtual address of the given mapping if a
5507 * different alignment might result in more superpage mappings.
5510 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5511 vm_offset_t *addr, vm_size_t size)
5513 vm_offset_t superpage_offset;
5517 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5518 offset += ptoa(object->pg_color);
5519 superpage_offset = offset & PDRMASK;
5520 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5521 (*addr & PDRMASK) == superpage_offset)
5523 if ((*addr & PDRMASK) < superpage_offset)
5524 *addr = (*addr & ~PDRMASK) + superpage_offset;
5526 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5530 pmap_quick_enter_page(vm_page_t m)
5536 qaddr = PCPU_GET(qmap_addr);
5537 pte = vtopte(qaddr);
5539 KASSERT(*pte == 0, ("pmap_quick_enter_page: PTE busy"));
5540 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5541 pmap_cache_bits(pmap_page_get_memattr(m), 0);
5548 pmap_quick_remove_page(vm_offset_t addr)
5553 qaddr = PCPU_GET(qmap_addr);
5554 pte = vtopte(qaddr);
5556 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5557 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5563 #if defined(PMAP_DEBUG)
5564 pmap_pid_dump(int pid)
5571 sx_slock(&allproc_lock);
5572 FOREACH_PROC_IN_SYSTEM(p) {
5573 if (p->p_pid != pid)
5579 pmap = vmspace_pmap(p->p_vmspace);
5580 for (i = 0; i < NPDEPTD; i++) {
5583 vm_offset_t base = i << PDRSHIFT;
5585 pde = &pmap->pm_pdir[i];
5586 if (pde && pmap_pde_v(pde)) {
5587 for (j = 0; j < NPTEPG; j++) {
5588 vm_offset_t va = base + (j << PAGE_SHIFT);
5589 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5594 sx_sunlock(&allproc_lock);
5597 pte = pmap_pte(pmap, va);
5598 if (pte && pmap_pte_v(pte)) {
5602 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5603 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5604 va, pa, m->hold_count, m->wire_count, m->flags);
5619 sx_sunlock(&allproc_lock);