2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
50 * Copyright (c) 2018 The FreeBSD Foundation
51 * All rights reserved.
53 * This software was developed for the FreeBSD Project by Jake Burkholder,
54 * Safeport Network Services, and Network Associates Laboratories, the
55 * Security Research Division of Network Associates, Inc. under
56 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
57 * CHATS research program.
59 * Portions of this software were developed by
60 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
61 * the FreeBSD Foundation.
63 * Redistribution and use in source and binary forms, with or without
64 * modification, are permitted provided that the following conditions
66 * 1. Redistributions of source code must retain the above copyright
67 * notice, this list of conditions and the following disclaimer.
68 * 2. Redistributions in binary form must reproduce the above copyright
69 * notice, this list of conditions and the following disclaimer in the
70 * documentation and/or other materials provided with the distribution.
72 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
73 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
75 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
78 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
79 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
80 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
81 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
85 #include <sys/cdefs.h>
86 __FBSDID("$FreeBSD$");
89 * Manages physical address maps.
91 * Since the information managed by this module is
92 * also stored by the logical address mapping module,
93 * this module may throw away valid virtual-to-physical
94 * mappings at almost any time. However, invalidations
95 * of virtual-to-physical mappings must be done as
98 * In order to cope with hardware architectures which
99 * make virtual-to-physical map invalidates expensive,
100 * this module may delay invalidate or reduced protection
101 * operations until such time as they are actually
102 * necessary. This module is given full information as
103 * to which processors are currently using which maps,
104 * and to when physical maps must be made correct.
107 #include "opt_apic.h"
109 #include "opt_pmap.h"
113 #include <sys/param.h>
114 #include <sys/systm.h>
115 #include <sys/kernel.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/proc.h>
123 #include <sys/rwlock.h>
124 #include <sys/sf_buf.h>
126 #include <sys/vmmeter.h>
127 #include <sys/sched.h>
128 #include <sys/sysctl.h>
130 #include <sys/vmem.h>
133 #include <vm/vm_param.h>
134 #include <vm/vm_kern.h>
135 #include <vm/vm_page.h>
136 #include <vm/vm_map.h>
137 #include <vm/vm_object.h>
138 #include <vm/vm_extern.h>
139 #include <vm/vm_pageout.h>
140 #include <vm/vm_pager.h>
141 #include <vm/vm_phys.h>
142 #include <vm/vm_radix.h>
143 #include <vm/vm_reserv.h>
148 #include <machine/intr_machdep.h>
149 #include <x86/apicvar.h>
151 #include <x86/ifunc.h>
152 #include <machine/bootinfo.h>
153 #include <machine/cpu.h>
154 #include <machine/cputypes.h>
155 #include <machine/md_var.h>
156 #include <machine/pcb.h>
157 #include <machine/specialreg.h>
159 #include <machine/smp.h>
161 #include <machine/pmap_base.h>
163 #if !defined(DIAGNOSTIC)
164 #ifdef __GNUC_GNU_INLINE__
165 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
167 #define PMAP_INLINE extern inline
174 #define PV_STAT(x) do { x ; } while (0)
176 #define PV_STAT(x) do { } while (0)
179 #define pa_index(pa) ((pa) >> PDRSHIFT)
180 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
183 * PTmap is recursive pagemap at top of virtual address space.
184 * Within PTmap, the page directory can be found (third indirection).
186 #define PTmap ((pt_entry_t *)(PTDPTDI << PDRSHIFT))
187 #define PTD ((pd_entry_t *)((PTDPTDI << PDRSHIFT) + (PTDPTDI * PAGE_SIZE)))
188 #define PTDpde ((pd_entry_t *)((PTDPTDI << PDRSHIFT) + (PTDPTDI * PAGE_SIZE) + \
189 (PTDPTDI * PDESIZE)))
192 * Translate a virtual address to the kernel virtual address of its page table
193 * entry (PTE). This can be used recursively. If the address of a PTE as
194 * previously returned by this macro is itself given as the argument, then the
195 * address of the page directory entry (PDE) that maps the PTE will be
198 * This macro may be used before pmap_bootstrap() is called.
200 #define vtopte(va) (PTmap + i386_btop(va))
203 * Get PDEs and PTEs for user/kernel address space
205 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
206 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
208 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
209 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
210 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
211 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
212 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
214 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
215 atomic_clear_int((u_int *)(pte), PG_W))
216 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
218 _Static_assert(sizeof(struct pmap) <= sizeof(struct pmap_KBI),
221 static int pgeflag = 0; /* PG_G or-in */
222 static int pseflag = 0; /* PG_PS or-in */
224 static int nkpt = NKPT;
228 static uma_zone_t pdptzone;
231 _Static_assert(VM_MAXUSER_ADDRESS == VADDR(TRPTDI, 0), "VM_MAXUSER_ADDRESS");
232 _Static_assert(VM_MAX_KERNEL_ADDRESS <= VADDR(PTDPTDI, 0),
233 "VM_MAX_KERNEL_ADDRESS");
234 _Static_assert(PMAP_MAP_LOW == VADDR(LOWPTDI, 0), "PMAP_MAP_LOW");
235 _Static_assert(KERNLOAD == (KERNPTDI << PDRSHIFT), "KERNLOAD");
237 extern int pat_works;
238 extern int pg_ps_enabled;
240 extern int elf32_nxstack;
242 #define PAT_INDEX_SIZE 8
243 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
246 * pmap_mapdev support pre initialization (i.e. console)
248 #define PMAP_PREINIT_MAPPING_COUNT 8
249 static struct pmap_preinit_mapping {
254 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
255 static int pmap_initialized;
257 static struct rwlock_padalign pvh_global_lock;
260 * Data for the pv entry allocation mechanism
262 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
263 extern int pv_entry_max, pv_entry_count;
264 static int pv_entry_high_water = 0;
265 static struct md_page *pv_table;
266 extern int shpgperproc;
268 static struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
269 static int pv_maxchunks; /* How many chunks we have KVA for */
270 static vm_offset_t pv_vafree; /* freelist stored in the PTE */
273 * All those kernel PT submaps that BSD is so fond of
275 static pt_entry_t *CMAP3;
276 static pd_entry_t *KPTD;
277 static caddr_t CADDR3;
282 static caddr_t crashdumpmap;
284 static pt_entry_t *PMAP1 = NULL, *PMAP2, *PMAP3;
285 static pt_entry_t *PADDR1 = NULL, *PADDR2, *PADDR3;
287 static int PMAP1cpu, PMAP3cpu;
288 extern int PMAP1changedcpu;
290 extern int PMAP1changed;
291 extern int PMAP1unchanged;
292 static struct mtx PMAP2mutex;
295 * Internal flags for pmap_enter()'s helper functions.
297 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
298 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
300 static void free_pv_chunk(struct pv_chunk *pc);
301 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
302 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
303 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
304 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
306 #if VM_NRESERVLEVEL > 0
307 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
309 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
310 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
312 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
314 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
315 static bool pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
317 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
318 u_int flags, vm_page_t m);
319 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
320 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
321 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
322 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
324 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
325 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
326 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
327 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
328 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
329 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
330 #if VM_NRESERVLEVEL > 0
331 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
333 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
335 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
336 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
337 struct spglist *free);
338 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
339 struct spglist *free);
340 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
341 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
342 struct spglist *free);
343 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
344 struct spglist *free);
345 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
347 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
348 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
350 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
352 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
354 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
356 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
357 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
358 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
359 static void pmap_pte_release(pt_entry_t *pte);
360 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
362 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain,
363 uint8_t *flags, int wait);
365 static void pmap_init_trm(void);
366 static void pmap_invalidate_all_int(pmap_t pmap);
368 static __inline void pagezero(void *page);
370 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
371 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
374 extern u_long physfree; /* phys addr of next free page */
375 extern u_long vm86phystk;/* PA of vm86/bios stack */
376 extern u_long vm86paddr;/* address of vm86 region */
377 extern int vm86pa; /* phys addr of vm86 region */
378 extern u_long KERNend; /* phys addr end of kernel (just after bss) */
380 pd_entry_t *IdlePTD_pae; /* phys addr of kernel PTD */
381 pdpt_entry_t *IdlePDPT; /* phys addr of kernel PDPT */
382 pt_entry_t *KPTmap_pae; /* address of kernel page tables */
383 #define IdlePTD IdlePTD_pae
384 #define KPTmap KPTmap_pae
386 pd_entry_t *IdlePTD_nopae;
387 pt_entry_t *KPTmap_nopae;
388 #define IdlePTD IdlePTD_nopae
389 #define KPTmap KPTmap_nopae
391 extern u_long KPTphys; /* phys addr of kernel page tables */
392 extern u_long tramp_idleptd;
395 allocpages(u_int cnt, u_long *physfree)
400 *physfree += PAGE_SIZE * cnt;
401 bzero((void *)res, PAGE_SIZE * cnt);
406 pmap_cold_map(u_long pa, u_long va, u_long cnt)
410 for (pt = (pt_entry_t *)KPTphys + atop(va); cnt > 0;
411 cnt--, pt++, va += PAGE_SIZE, pa += PAGE_SIZE)
412 *pt = pa | PG_V | PG_RW | PG_A | PG_M;
416 pmap_cold_mapident(u_long pa, u_long cnt)
419 pmap_cold_map(pa, pa, cnt);
422 _Static_assert(LOWPTDI * 2 * NBPDR == KERNBASE,
423 "Broken double-map of zero PTD");
426 __CONCAT(PMTYPE, remap_lower)(bool enable)
430 for (i = 0; i < LOWPTDI; i++)
431 IdlePTD[i] = enable ? IdlePTD[LOWPTDI + i] : 0;
432 load_cr3(rcr3()); /* invalidate TLB */
436 * Called from locore.s before paging is enabled. Sets up the first
437 * kernel page table. Since kernel is mapped with PA == VA, this code
438 * does not require relocations.
441 __CONCAT(PMTYPE, cold)(void)
447 physfree = (u_long)&_end;
448 if (bootinfo.bi_esymtab != 0)
449 physfree = bootinfo.bi_esymtab;
450 if (bootinfo.bi_kernend != 0)
451 physfree = bootinfo.bi_kernend;
452 physfree = roundup2(physfree, NBPDR);
455 /* Allocate Kernel Page Tables */
456 KPTphys = allocpages(NKPT, &physfree);
457 KPTmap = (pt_entry_t *)KPTphys;
459 /* Allocate Page Table Directory */
461 /* XXX only need 32 bytes (easier for now) */
462 IdlePDPT = (pdpt_entry_t *)allocpages(1, &physfree);
464 IdlePTD = (pd_entry_t *)allocpages(NPGPTD, &physfree);
467 * Allocate KSTACK. Leave a guard page between IdlePTD and
468 * proc0kstack, to control stack overflow for thread0 and
469 * prevent corruption of the page table. We leak the guard
470 * physical memory due to 1:1 mappings.
472 allocpages(1, &physfree);
473 proc0kstack = allocpages(TD0_KSTACK_PAGES, &physfree);
475 /* vm86/bios stack */
476 vm86phystk = allocpages(1, &physfree);
478 /* pgtable + ext + IOPAGES */
479 vm86paddr = vm86pa = allocpages(3, &physfree);
481 /* Install page tables into PTD. Page table page 1 is wasted. */
482 for (a = 0; a < NKPT; a++)
483 IdlePTD[a] = (KPTphys + ptoa(a)) | PG_V | PG_RW | PG_A | PG_M;
486 /* PAE install PTD pointers into PDPT */
487 for (a = 0; a < NPGPTD; a++)
488 IdlePDPT[a] = ((u_int)IdlePTD + ptoa(a)) | PG_V;
492 * Install recursive mapping for kernel page tables into
495 for (a = 0; a < NPGPTD; a++)
496 IdlePTD[PTDPTDI + a] = ((u_int)IdlePTD + ptoa(a)) | PG_V |
500 * Initialize page table pages mapping physical address zero
501 * through the (physical) end of the kernel. Many of these
502 * pages must be reserved, and we reserve them all and map
503 * them linearly for convenience. We do this even if we've
504 * enabled PSE above; we'll just switch the corresponding
505 * kernel PDEs before we turn on paging.
507 * This and all other page table entries allow read and write
508 * access for various reasons. Kernel mappings never have any
509 * access restrictions.
511 pmap_cold_mapident(0, atop(NBPDR) * LOWPTDI);
512 pmap_cold_map(0, NBPDR * LOWPTDI, atop(NBPDR) * LOWPTDI);
513 pmap_cold_mapident(KERNBASE, atop(KERNend - KERNBASE));
515 /* Map page table directory */
517 pmap_cold_mapident((u_long)IdlePDPT, 1);
519 pmap_cold_mapident((u_long)IdlePTD, NPGPTD);
521 /* Map early KPTmap. It is really pmap_cold_mapident. */
522 pmap_cold_map(KPTphys, (u_long)KPTmap, NKPT);
524 /* Map proc0kstack */
525 pmap_cold_mapident(proc0kstack, TD0_KSTACK_PAGES);
526 /* ISA hole already mapped */
528 pmap_cold_mapident(vm86phystk, 1);
529 pmap_cold_mapident(vm86pa, 3);
531 /* Map page 0 into the vm86 page table */
532 *(pt_entry_t *)vm86pa = 0 | PG_RW | PG_U | PG_A | PG_M | PG_V;
534 /* ...likewise for the ISA hole for vm86 */
535 for (pt = (pt_entry_t *)vm86pa + atop(ISA_HOLE_START), a = 0;
536 a < atop(ISA_HOLE_LENGTH); a++, pt++)
537 *pt = (ISA_HOLE_START + ptoa(a)) | PG_RW | PG_U | PG_A |
540 /* Enable PSE, PGE, VME, and PAE if configured. */
542 if ((cpu_feature & CPUID_PSE) != 0) {
546 * Superpage mapping of the kernel text. Existing 4k
547 * page table pages are wasted.
549 for (a = KERNBASE; a < KERNend; a += NBPDR)
550 IdlePTD[a >> PDRSHIFT] = a | PG_PS | PG_A | PG_M |
553 if ((cpu_feature & CPUID_PGE) != 0) {
557 ncr4 |= (cpu_feature & CPUID_VME) != 0 ? CR4_VME : 0;
562 load_cr4(rcr4() | ncr4);
564 /* Now enable paging */
566 cr3 = (u_int)IdlePDPT;
567 if ((cpu_feature & CPUID_PAT) == 0)
570 cr3 = (u_int)IdlePTD;
574 load_cr0(rcr0() | CR0_PG);
577 * Now running relocated at KERNBASE where the system is
582 * Remove the lowest part of the double mapping of low memory
583 * to get some null pointer checks.
585 __CONCAT(PMTYPE, remap_lower)(false);
587 kernel_vm_end = /* 0 + */ NKPT * NBPDR;
589 i386_pmap_VM_NFREEORDER = VM_NFREEORDER_PAE;
590 i386_pmap_VM_LEVEL_0_ORDER = VM_LEVEL_0_ORDER_PAE;
591 i386_pmap_PDRSHIFT = PDRSHIFT_PAE;
593 i386_pmap_VM_NFREEORDER = VM_NFREEORDER_NOPAE;
594 i386_pmap_VM_LEVEL_0_ORDER = VM_LEVEL_0_ORDER_NOPAE;
595 i386_pmap_PDRSHIFT = PDRSHIFT_NOPAE;
600 __CONCAT(PMTYPE, set_nx)(void)
604 if ((amd_feature & AMDID_NX) == 0)
608 /* EFER.EFER_NXE is set in initializecpu(). */
613 * Bootstrap the system enough to run with virtual memory.
615 * On the i386 this is called after pmap_cold() created initial
616 * kernel page table and enabled paging, and just syncs the pmap
617 * module with what has already been done.
620 __CONCAT(PMTYPE, bootstrap)(vm_paddr_t firstaddr)
623 pt_entry_t *pte, *unused;
628 res = atop(firstaddr - (vm_paddr_t)KERNLOAD);
631 * Add a physical memory segment (vm_phys_seg) corresponding to the
632 * preallocated kernel page table pages so that vm_page structures
633 * representing these pages will be created. The vm_page structures
634 * are required for promotion of the corresponding kernel virtual
635 * addresses to superpage mappings.
637 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
640 * Initialize the first available kernel virtual address.
641 * However, using "firstaddr" may waste a few pages of the
642 * kernel virtual address space, because pmap_cold() may not
643 * have mapped every physical page that it allocated.
644 * Preferably, pmap_cold() would provide a first unused
645 * virtual address in addition to "firstaddr".
647 virtual_avail = (vm_offset_t)firstaddr;
648 virtual_end = VM_MAX_KERNEL_ADDRESS;
651 * Initialize the kernel pmap (which is statically allocated).
652 * Count bootstrap data as being resident in case any of this data is
653 * later unmapped (using pmap_remove()) and freed.
655 PMAP_LOCK_INIT(kernel_pmap);
656 kernel_pmap->pm_pdir = IdlePTD;
658 kernel_pmap->pm_pdpt = IdlePDPT;
660 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
661 kernel_pmap->pm_stats.resident_count = res;
662 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
665 * Initialize the global pv list lock.
667 rw_init(&pvh_global_lock, "pmap pv global");
670 * Reserve some special page table entries/VA space for temporary
673 #define SYSMAP(c, p, v, n) \
674 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
681 * Initialize temporary map objects on the current CPU for use
683 * CMAP1/CMAP2 are used for zeroing and copying pages.
684 * CMAP3 is used for the boot-time memory test.
687 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
688 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1)
689 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1)
690 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1)
692 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
697 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
700 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
702 SYSMAP(caddr_t, unused, ptvmmap, 1)
705 * msgbufp is used to map the system message buffer.
707 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
710 * KPTmap is used by pmap_kextract().
712 * KPTmap is first initialized by pmap_cold(). However, that initial
713 * KPTmap can only support NKPT page table pages. Here, a larger
714 * KPTmap is created that can support KVA_PAGES page table pages.
716 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
718 for (i = 0; i < NKPT; i++)
719 KPTD[i] = (KPTphys + ptoa(i)) | PG_RW | PG_V;
722 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
725 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
726 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
727 SYSMAP(pt_entry_t *, PMAP3, PADDR3, 1)
729 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
734 * Initialize the PAT MSR if present.
735 * pmap_init_pat() clears and sets CR4_PGE, which, as a
736 * side-effect, invalidates stale PG_G TLB entries that might
737 * have been created in our pre-boot environment. We assume
738 * that PAT support implies PGE and in reverse, PGE presence
739 * comes with PAT. Both features were added for Pentium Pro.
745 pmap_init_reserved_pages(void)
760 mtx_init(&pc->pc_copyout_mlock, "cpmlk", NULL, MTX_DEF |
762 pc->pc_copyout_maddr = kva_alloc(ptoa(2));
763 if (pc->pc_copyout_maddr == 0)
764 panic("unable to allocate non-sleepable copyout KVA");
765 sx_init(&pc->pc_copyout_slock, "cpslk");
766 pc->pc_copyout_saddr = kva_alloc(ptoa(2));
767 if (pc->pc_copyout_saddr == 0)
768 panic("unable to allocate sleepable copyout KVA");
769 pc->pc_pmap_eh_va = kva_alloc(ptoa(1));
770 if (pc->pc_pmap_eh_va == 0)
771 panic("unable to allocate pmap_extract_and_hold KVA");
772 pc->pc_pmap_eh_ptep = (char *)vtopte(pc->pc_pmap_eh_va);
775 * Skip if the mappings have already been initialized,
776 * i.e. this is the BSP.
778 if (pc->pc_cmap_addr1 != 0)
781 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
782 pages = kva_alloc(PAGE_SIZE * 3);
784 panic("unable to allocate CMAP KVA");
785 pc->pc_cmap_pte1 = vtopte(pages);
786 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE);
787 pc->pc_cmap_addr1 = (caddr_t)pages;
788 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE);
789 pc->pc_qmap_addr = pages + ptoa(2);
793 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
799 __CONCAT(PMTYPE, init_pat)(void)
801 int pat_table[PAT_INDEX_SIZE];
806 /* Set default PAT index table. */
807 for (i = 0; i < PAT_INDEX_SIZE; i++)
809 pat_table[PAT_WRITE_BACK] = 0;
810 pat_table[PAT_WRITE_THROUGH] = 1;
811 pat_table[PAT_UNCACHEABLE] = 3;
812 pat_table[PAT_WRITE_COMBINING] = 3;
813 pat_table[PAT_WRITE_PROTECTED] = 3;
814 pat_table[PAT_UNCACHED] = 3;
817 * Bail if this CPU doesn't implement PAT.
818 * We assume that PAT support implies PGE.
820 if ((cpu_feature & CPUID_PAT) == 0) {
821 for (i = 0; i < PAT_INDEX_SIZE; i++)
822 pat_index[i] = pat_table[i];
828 * Due to some Intel errata, we can only safely use the lower 4
831 * Intel Pentium III Processor Specification Update
832 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
835 * Intel Pentium IV Processor Specification Update
836 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
838 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
839 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
842 /* Initialize default PAT entries. */
843 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
844 PAT_VALUE(1, PAT_WRITE_THROUGH) |
845 PAT_VALUE(2, PAT_UNCACHED) |
846 PAT_VALUE(3, PAT_UNCACHEABLE) |
847 PAT_VALUE(4, PAT_WRITE_BACK) |
848 PAT_VALUE(5, PAT_WRITE_THROUGH) |
849 PAT_VALUE(6, PAT_UNCACHED) |
850 PAT_VALUE(7, PAT_UNCACHEABLE);
854 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
855 * Program 5 and 6 as WP and WC.
856 * Leave 4 and 7 as WB and UC.
858 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
859 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
860 PAT_VALUE(6, PAT_WRITE_COMBINING);
861 pat_table[PAT_UNCACHED] = 2;
862 pat_table[PAT_WRITE_PROTECTED] = 5;
863 pat_table[PAT_WRITE_COMBINING] = 6;
866 * Just replace PAT Index 2 with WC instead of UC-.
868 pat_msr &= ~PAT_MASK(2);
869 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
870 pat_table[PAT_WRITE_COMBINING] = 2;
875 load_cr4(cr4 & ~CR4_PGE);
877 /* Disable caches (CD = 1, NW = 0). */
879 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
881 /* Flushes caches and TLBs. */
885 /* Update PAT and index table. */
886 wrmsr(MSR_PAT, pat_msr);
887 for (i = 0; i < PAT_INDEX_SIZE; i++)
888 pat_index[i] = pat_table[i];
890 /* Flush caches and TLBs again. */
894 /* Restore caches and PGE. */
901 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain, uint8_t *flags,
905 /* Inform UMA that this allocator uses kernel_map/object. */
906 *flags = UMA_SLAB_KERNEL;
907 return ((void *)kmem_alloc_contig_domainset(DOMAINSET_FIXED(domain),
908 bytes, wait, 0x0ULL, 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
913 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
915 * - Must deal with pages in order to ensure that none of the PG_* bits
916 * are ever set, PG_V in particular.
917 * - Assumes we can write to ptes without pte_store() atomic ops, even
918 * on PAE systems. This should be ok.
919 * - Assumes nothing will ever test these addresses for 0 to indicate
920 * no mapping instead of correctly checking PG_V.
921 * - Assumes a vm_offset_t will fit in a pte (true for i386).
922 * Because PG_V is never set, there can be no mappings to invalidate.
925 pmap_ptelist_alloc(vm_offset_t *head)
932 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
936 panic("pmap_ptelist_alloc: va with PG_V set!");
942 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
947 panic("pmap_ptelist_free: freeing va with PG_V set!");
949 *pte = *head; /* virtual! PG_V is 0 though */
954 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
960 for (i = npages - 1; i >= 0; i--) {
961 va = (vm_offset_t)base + i * PAGE_SIZE;
962 pmap_ptelist_free(head, va);
968 * Initialize the pmap module.
969 * Called by vm_init, to initialize any structures that the pmap
970 * system needs to map virtual memory.
973 __CONCAT(PMTYPE, init)(void)
975 struct pmap_preinit_mapping *ppim;
981 * Initialize the vm page array entries for the kernel pmap's
984 PMAP_LOCK(kernel_pmap);
985 for (i = 0; i < NKPT; i++) {
986 mpte = PHYS_TO_VM_PAGE(KPTphys + ptoa(i));
987 KASSERT(mpte >= vm_page_array &&
988 mpte < &vm_page_array[vm_page_array_size],
989 ("pmap_init: page table page is out of range"));
990 mpte->pindex = i + KPTDI;
991 mpte->phys_addr = KPTphys + ptoa(i);
992 mpte->wire_count = 1;
994 KERNBASE <= i << PDRSHIFT && i << PDRSHIFT < KERNend &&
995 pmap_insert_pt_page(kernel_pmap, mpte))
996 panic("pmap_init: pmap_insert_pt_page failed");
998 PMAP_UNLOCK(kernel_pmap);
1002 * Initialize the address space (zone) for the pv entries. Set a
1003 * high water mark so that the system can recover from excessive
1004 * numbers of pv entries.
1006 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1007 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1008 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1009 pv_entry_max = roundup(pv_entry_max, _NPCPV);
1010 pv_entry_high_water = 9 * (pv_entry_max / 10);
1013 * If the kernel is running on a virtual machine, then it must assume
1014 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1015 * be prepared for the hypervisor changing the vendor and family that
1016 * are reported by CPUID. Consequently, the workaround for AMD Family
1017 * 10h Erratum 383 is enabled if the processor's feature set does not
1018 * include at least one feature that is only supported by older Intel
1019 * or newer AMD processors.
1021 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
1022 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1023 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1025 workaround_erratum383 = 1;
1028 * Are large page mappings supported and enabled?
1030 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1033 else if (pg_ps_enabled) {
1034 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1035 ("pmap_init: can't assign to pagesizes[1]"));
1036 pagesizes[1] = NBPDR;
1040 * Calculate the size of the pv head table for superpages.
1041 * Handle the possibility that "vm_phys_segs[...].end" is zero.
1043 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
1044 PAGE_SIZE) / NBPDR + 1;
1047 * Allocate memory for the pv head table for superpages.
1049 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1051 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1052 for (i = 0; i < pv_npg; i++)
1053 TAILQ_INIT(&pv_table[i].pv_list);
1055 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
1056 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
1057 if (pv_chunkbase == NULL)
1058 panic("pmap_init: not enough kvm for pv chunks");
1059 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
1060 #ifdef PMAP_PAE_COMP
1061 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
1062 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
1063 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1064 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
1067 pmap_initialized = 1;
1072 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1073 ppim = pmap_preinit_mapping + i;
1076 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
1077 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
1082 extern u_long pmap_pde_demotions;
1083 extern u_long pmap_pde_mappings;
1084 extern u_long pmap_pde_p_failures;
1085 extern u_long pmap_pde_promotions;
1087 /***************************************************
1088 * Low level helper routines.....
1089 ***************************************************/
1092 __CONCAT(PMTYPE, is_valid_memattr)(pmap_t pmap __unused, vm_memattr_t mode)
1095 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
1096 pat_index[(int)mode] >= 0);
1100 * Determine the appropriate bits to set in a PTE or PDE for a specified
1104 __CONCAT(PMTYPE, cache_bits)(pmap_t pmap, int mode, boolean_t is_pde)
1106 int cache_bits, pat_flag, pat_idx;
1108 if (!pmap_is_valid_memattr(pmap, mode))
1109 panic("Unknown caching mode %d\n", mode);
1111 /* The PAT bit is different for PTE's and PDE's. */
1112 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
1114 /* Map the caching mode to a PAT index. */
1115 pat_idx = pat_index[mode];
1117 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1120 cache_bits |= pat_flag;
1122 cache_bits |= PG_NC_PCD;
1124 cache_bits |= PG_NC_PWT;
1125 return (cache_bits);
1129 __CONCAT(PMTYPE, ps_enabled)(pmap_t pmap __unused)
1132 return (pg_ps_enabled);
1136 * The caller is responsible for maintaining TLB consistency.
1139 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
1143 pde = pmap_pde(kernel_pmap, va);
1144 pde_store(pde, newpde);
1148 * After changing the page size for the specified virtual address in the page
1149 * table, flush the corresponding entries from the processor's TLB. Only the
1150 * calling processor's TLB is affected.
1152 * The calling thread must be pinned to a processor.
1155 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
1158 if ((newpde & PG_PS) == 0)
1159 /* Demotion: flush a specific 2MB page mapping. */
1161 else /* if ((newpde & PG_G) == 0) */
1163 * Promotion: flush every 4KB page mapping from the TLB
1164 * because there are too many to flush individually.
1171 * For SMP, these functions have to use the IPI mechanism for coherence.
1173 * N.B.: Before calling any of the following TLB invalidation functions,
1174 * the calling processor must ensure that all stores updating a non-
1175 * kernel page table are globally performed. Otherwise, another
1176 * processor could cache an old, pre-update entry without being
1177 * invalidated. This can happen one of two ways: (1) The pmap becomes
1178 * active on another processor after its pm_active field is checked by
1179 * one of the following functions but before a store updating the page
1180 * table is globally performed. (2) The pmap becomes active on another
1181 * processor before its pm_active field is checked but due to
1182 * speculative loads one of the following functions stills reads the
1183 * pmap as inactive on the other processor.
1185 * The kernel page table is exempt because its pm_active field is
1186 * immutable. The kernel page table is always active on every
1190 pmap_invalidate_page_int(pmap_t pmap, vm_offset_t va)
1192 cpuset_t *mask, other_cpus;
1196 if (pmap == kernel_pmap) {
1199 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1202 cpuid = PCPU_GET(cpuid);
1203 other_cpus = all_cpus;
1204 CPU_CLR(cpuid, &other_cpus);
1205 CPU_AND(&other_cpus, &pmap->pm_active);
1208 smp_masked_invlpg(*mask, va, pmap);
1212 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1213 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1216 pmap_invalidate_range_int(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1218 cpuset_t *mask, other_cpus;
1222 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1223 pmap_invalidate_all_int(pmap);
1228 if (pmap == kernel_pmap) {
1229 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1232 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1235 cpuid = PCPU_GET(cpuid);
1236 other_cpus = all_cpus;
1237 CPU_CLR(cpuid, &other_cpus);
1238 CPU_AND(&other_cpus, &pmap->pm_active);
1241 smp_masked_invlpg_range(*mask, sva, eva, pmap);
1246 pmap_invalidate_all_int(pmap_t pmap)
1248 cpuset_t *mask, other_cpus;
1252 if (pmap == kernel_pmap) {
1255 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1258 cpuid = PCPU_GET(cpuid);
1259 other_cpus = all_cpus;
1260 CPU_CLR(cpuid, &other_cpus);
1261 CPU_AND(&other_cpus, &pmap->pm_active);
1264 smp_masked_invltlb(*mask, pmap);
1269 __CONCAT(PMTYPE, invalidate_cache)(void)
1279 cpuset_t invalidate; /* processors that invalidate their TLB */
1283 u_int store; /* processor that updates the PDE */
1287 pmap_update_pde_kernel(void *arg)
1289 struct pde_action *act = arg;
1292 if (act->store == PCPU_GET(cpuid)) {
1293 pde = pmap_pde(kernel_pmap, act->va);
1294 pde_store(pde, act->newpde);
1299 pmap_update_pde_user(void *arg)
1301 struct pde_action *act = arg;
1303 if (act->store == PCPU_GET(cpuid))
1304 pde_store(act->pde, act->newpde);
1308 pmap_update_pde_teardown(void *arg)
1310 struct pde_action *act = arg;
1312 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1313 pmap_update_pde_invalidate(act->va, act->newpde);
1317 * Change the page size for the specified virtual address in a way that
1318 * prevents any possibility of the TLB ever having two entries that map the
1319 * same virtual address using different page sizes. This is the recommended
1320 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1321 * machine check exception for a TLB state that is improperly diagnosed as a
1325 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1327 struct pde_action act;
1328 cpuset_t active, other_cpus;
1332 cpuid = PCPU_GET(cpuid);
1333 other_cpus = all_cpus;
1334 CPU_CLR(cpuid, &other_cpus);
1335 if (pmap == kernel_pmap)
1338 active = pmap->pm_active;
1339 if (CPU_OVERLAP(&active, &other_cpus)) {
1341 act.invalidate = active;
1344 act.newpde = newpde;
1345 CPU_SET(cpuid, &active);
1346 smp_rendezvous_cpus(active,
1347 smp_no_rendezvous_barrier, pmap == kernel_pmap ?
1348 pmap_update_pde_kernel : pmap_update_pde_user,
1349 pmap_update_pde_teardown, &act);
1351 if (pmap == kernel_pmap)
1352 pmap_kenter_pde(va, newpde);
1354 pde_store(pde, newpde);
1355 if (CPU_ISSET(cpuid, &active))
1356 pmap_update_pde_invalidate(va, newpde);
1362 * Normal, non-SMP, 486+ invalidation functions.
1363 * We inline these within pmap.c for speed.
1366 pmap_invalidate_page_int(pmap_t pmap, vm_offset_t va)
1369 if (pmap == kernel_pmap)
1374 pmap_invalidate_range_int(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1378 if (pmap == kernel_pmap)
1379 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1384 pmap_invalidate_all_int(pmap_t pmap)
1387 if (pmap == kernel_pmap)
1392 __CONCAT(PMTYPE, invalidate_cache)(void)
1399 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1402 if (pmap == kernel_pmap)
1403 pmap_kenter_pde(va, newpde);
1405 pde_store(pde, newpde);
1406 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1407 pmap_update_pde_invalidate(va, newpde);
1412 __CONCAT(PMTYPE, invalidate_page)(pmap_t pmap, vm_offset_t va)
1415 pmap_invalidate_page_int(pmap, va);
1419 __CONCAT(PMTYPE, invalidate_range)(pmap_t pmap, vm_offset_t sva,
1423 pmap_invalidate_range_int(pmap, sva, eva);
1427 __CONCAT(PMTYPE, invalidate_all)(pmap_t pmap)
1430 pmap_invalidate_all_int(pmap);
1434 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1438 * When the PDE has PG_PROMOTED set, the 2- or 4MB page mapping was
1439 * created by a promotion that did not invalidate the 512 or 1024 4KB
1440 * page mappings that might exist in the TLB. Consequently, at this
1441 * point, the TLB may hold both 4KB and 2- or 4MB page mappings for
1442 * the address range [va, va + NBPDR). Therefore, the entire range
1443 * must be invalidated here. In contrast, when PG_PROMOTED is clear,
1444 * the TLB will not hold any 4KB page mappings for the address range
1445 * [va, va + NBPDR), and so a single INVLPG suffices to invalidate the
1446 * 2- or 4MB page mapping from the TLB.
1448 if ((pde & PG_PROMOTED) != 0)
1449 pmap_invalidate_range_int(pmap, va, va + NBPDR - 1);
1451 pmap_invalidate_page_int(pmap, va);
1455 * Are we current address space or kernel?
1458 pmap_is_current(pmap_t pmap)
1461 return (pmap == kernel_pmap);
1465 * If the given pmap is not the current or kernel pmap, the returned pte must
1466 * be released by passing it to pmap_pte_release().
1469 __CONCAT(PMTYPE, pte)(pmap_t pmap, vm_offset_t va)
1474 pde = pmap_pde(pmap, va);
1478 /* are we current address space or kernel? */
1479 if (pmap_is_current(pmap))
1480 return (vtopte(va));
1481 mtx_lock(&PMAP2mutex);
1482 newpf = *pde & PG_FRAME;
1483 if ((*PMAP2 & PG_FRAME) != newpf) {
1484 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1485 pmap_invalidate_page_int(kernel_pmap,
1486 (vm_offset_t)PADDR2);
1488 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1494 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1497 static __inline void
1498 pmap_pte_release(pt_entry_t *pte)
1501 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1502 mtx_unlock(&PMAP2mutex);
1506 * NB: The sequence of updating a page table followed by accesses to the
1507 * corresponding pages is subject to the situation described in the "AMD64
1508 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1509 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1510 * right after modifying the PTE bits is crucial.
1512 static __inline void
1513 invlcaddr(void *caddr)
1516 invlpg((u_int)caddr);
1520 * Super fast pmap_pte routine best used when scanning
1521 * the pv lists. This eliminates many coarse-grained
1522 * invltlb calls. Note that many of the pv list
1523 * scans are across different pmaps. It is very wasteful
1524 * to do an entire invltlb for checking a single mapping.
1526 * If the given pmap is not the current pmap, pvh_global_lock
1527 * must be held and curthread pinned to a CPU.
1530 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1535 pde = pmap_pde(pmap, va);
1539 /* are we current address space or kernel? */
1540 if (pmap_is_current(pmap))
1541 return (vtopte(va));
1542 rw_assert(&pvh_global_lock, RA_WLOCKED);
1543 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1544 newpf = *pde & PG_FRAME;
1545 if ((*PMAP1 & PG_FRAME) != newpf) {
1546 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1548 PMAP1cpu = PCPU_GET(cpuid);
1554 if (PMAP1cpu != PCPU_GET(cpuid)) {
1555 PMAP1cpu = PCPU_GET(cpuid);
1561 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1567 pmap_pte_quick3(pmap_t pmap, vm_offset_t va)
1572 pde = pmap_pde(pmap, va);
1576 rw_assert(&pvh_global_lock, RA_WLOCKED);
1577 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1578 newpf = *pde & PG_FRAME;
1579 if ((*PMAP3 & PG_FRAME) != newpf) {
1580 *PMAP3 = newpf | PG_RW | PG_V | PG_A | PG_M;
1582 PMAP3cpu = PCPU_GET(cpuid);
1588 if (PMAP3cpu != PCPU_GET(cpuid)) {
1589 PMAP3cpu = PCPU_GET(cpuid);
1595 return (PADDR3 + (i386_btop(va) & (NPTEPG - 1)));
1601 pmap_pte_ufast(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1603 pt_entry_t *eh_ptep, pte, *ptep;
1605 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1608 eh_ptep = (pt_entry_t *)PCPU_GET(pmap_eh_ptep);
1609 if ((*eh_ptep & PG_FRAME) != pde) {
1610 *eh_ptep = pde | PG_RW | PG_V | PG_A | PG_M;
1611 invlcaddr((void *)PCPU_GET(pmap_eh_va));
1613 ptep = (pt_entry_t *)PCPU_GET(pmap_eh_va) + (i386_btop(va) &
1621 * Extract from the kernel page table the physical address that is mapped by
1622 * the given virtual address "va".
1624 * This function may be used before pmap_bootstrap() is called.
1627 __CONCAT(PMTYPE, kextract)(vm_offset_t va)
1631 if ((pa = pte_load(&PTD[va >> PDRSHIFT])) & PG_PS) {
1632 pa = (pa & PG_PS_FRAME) | (va & PDRMASK);
1635 * Beware of a concurrent promotion that changes the PDE at
1636 * this point! For example, vtopte() must not be used to
1637 * access the PTE because it would use the new PDE. It is,
1638 * however, safe to use the old PDE because the page table
1639 * page is preserved by the promotion.
1641 pa = KPTmap[i386_btop(va)];
1642 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
1648 * Routine: pmap_extract
1650 * Extract the physical page address associated
1651 * with the given map/virtual_address pair.
1654 __CONCAT(PMTYPE, extract)(pmap_t pmap, vm_offset_t va)
1662 pde = pmap->pm_pdir[va >> PDRSHIFT];
1664 if ((pde & PG_PS) != 0)
1665 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1667 pte = pmap_pte_ufast(pmap, va, pde);
1668 rtval = (pte & PG_FRAME) | (va & PAGE_MASK);
1676 * Routine: pmap_extract_and_hold
1678 * Atomically extract and hold the physical page
1679 * with the given pmap and virtual address pair
1680 * if that mapping permits the given protection.
1683 __CONCAT(PMTYPE, extract_and_hold)(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1694 pde = *pmap_pde(pmap, va);
1697 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1698 if (vm_page_pa_tryrelock(pmap, (pde &
1699 PG_PS_FRAME) | (va & PDRMASK), &pa))
1701 m = PHYS_TO_VM_PAGE(pa);
1704 pte = pmap_pte_ufast(pmap, va, pde);
1706 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1707 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1710 m = PHYS_TO_VM_PAGE(pa);
1721 /***************************************************
1722 * Low level mapping routines.....
1723 ***************************************************/
1726 * Add a wired page to the kva.
1727 * Note: not SMP coherent.
1729 * This function may be used before pmap_bootstrap() is called.
1732 __CONCAT(PMTYPE, kenter)(vm_offset_t va, vm_paddr_t pa)
1737 pte_store(pte, pa | PG_RW | PG_V);
1740 static __inline void
1741 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1746 pte_store(pte, pa | PG_RW | PG_V | pmap_cache_bits(kernel_pmap,
1751 * Remove a page from the kernel pagetables.
1752 * Note: not SMP coherent.
1754 * This function may be used before pmap_bootstrap() is called.
1757 __CONCAT(PMTYPE, kremove)(vm_offset_t va)
1766 * Used to map a range of physical addresses into kernel
1767 * virtual address space.
1769 * The value passed in '*virt' is a suggested virtual address for
1770 * the mapping. Architectures which can support a direct-mapped
1771 * physical to virtual region can return the appropriate address
1772 * within that region, leaving '*virt' unchanged. Other
1773 * architectures should map the pages starting at '*virt' and
1774 * update '*virt' with the first usable address after the mapped
1778 __CONCAT(PMTYPE, map)(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end,
1781 vm_offset_t va, sva;
1782 vm_paddr_t superpage_offset;
1787 * Does the physical address range's size and alignment permit at
1788 * least one superpage mapping to be created?
1790 superpage_offset = start & PDRMASK;
1791 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1793 * Increase the starting virtual address so that its alignment
1794 * does not preclude the use of superpage mappings.
1796 if ((va & PDRMASK) < superpage_offset)
1797 va = (va & ~PDRMASK) + superpage_offset;
1798 else if ((va & PDRMASK) > superpage_offset)
1799 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1802 while (start < end) {
1803 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1805 KASSERT((va & PDRMASK) == 0,
1806 ("pmap_map: misaligned va %#x", va));
1807 newpde = start | PG_PS | PG_RW | PG_V;
1808 pmap_kenter_pde(va, newpde);
1812 pmap_kenter(va, start);
1817 pmap_invalidate_range_int(kernel_pmap, sva, va);
1824 * Add a list of wired pages to the kva
1825 * this routine is only used for temporary
1826 * kernel mappings that do not need to have
1827 * page modification or references recorded.
1828 * Note that old mappings are simply written
1829 * over. The page *must* be wired.
1830 * Note: SMP coherent. Uses a ranged shootdown IPI.
1833 __CONCAT(PMTYPE, qenter)(vm_offset_t sva, vm_page_t *ma, int count)
1835 pt_entry_t *endpte, oldpte, pa, *pte;
1840 endpte = pte + count;
1841 while (pte < endpte) {
1843 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(kernel_pmap,
1845 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1847 #ifdef PMAP_PAE_COMP
1848 pte_store(pte, pa | pg_nx | PG_RW | PG_V);
1850 pte_store(pte, pa | PG_RW | PG_V);
1855 if (__predict_false((oldpte & PG_V) != 0))
1856 pmap_invalidate_range_int(kernel_pmap, sva, sva + count *
1861 * This routine tears out page mappings from the
1862 * kernel -- it is meant only for temporary mappings.
1863 * Note: SMP coherent. Uses a ranged shootdown IPI.
1866 __CONCAT(PMTYPE, qremove)(vm_offset_t sva, int count)
1871 while (count-- > 0) {
1875 pmap_invalidate_range_int(kernel_pmap, sva, va);
1878 /***************************************************
1879 * Page table page management routines.....
1880 ***************************************************/
1882 * Schedule the specified unused page table page to be freed. Specifically,
1883 * add the page to the specified list of pages that will be released to the
1884 * physical memory manager after the TLB has been updated.
1886 static __inline void
1887 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1888 boolean_t set_PG_ZERO)
1892 m->flags |= PG_ZERO;
1894 m->flags &= ~PG_ZERO;
1895 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1899 * Inserts the specified page table page into the specified pmap's collection
1900 * of idle page table pages. Each of a pmap's page table pages is responsible
1901 * for mapping a distinct range of virtual addresses. The pmap's collection is
1902 * ordered by this virtual address range.
1905 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1908 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1909 return (vm_radix_insert(&pmap->pm_root, mpte));
1913 * Removes the page table page mapping the specified virtual address from the
1914 * specified pmap's collection of idle page table pages, and returns it.
1915 * Otherwise, returns NULL if there is no page table page corresponding to the
1916 * specified virtual address.
1918 static __inline vm_page_t
1919 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
1922 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1923 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT));
1927 * Decrements a page table page's wire count, which is used to record the
1928 * number of valid page table entries within the page. If the wire count
1929 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1930 * page table page was unmapped and FALSE otherwise.
1932 static inline boolean_t
1933 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1937 if (m->wire_count == 0) {
1938 _pmap_unwire_ptp(pmap, m, free);
1945 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1949 * unmap the page table page
1951 pmap->pm_pdir[m->pindex] = 0;
1952 --pmap->pm_stats.resident_count;
1955 * There is not need to invalidate the recursive mapping since
1956 * we never instantiate such mapping for the usermode pmaps,
1957 * and never remove page table pages from the kernel pmap.
1958 * Put page on a list so that it is released since all TLB
1959 * shootdown is done.
1961 MPASS(pmap != kernel_pmap);
1962 pmap_add_delayed_free_list(m, free, TRUE);
1966 * After removing a page table entry, this routine is used to
1967 * conditionally free the page, and manage the hold/wire counts.
1970 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1975 if (pmap == kernel_pmap)
1977 ptepde = *pmap_pde(pmap, va);
1978 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1979 return (pmap_unwire_ptp(pmap, mpte, free));
1983 * Initialize the pmap for the swapper process.
1986 __CONCAT(PMTYPE, pinit0)(pmap_t pmap)
1989 PMAP_LOCK_INIT(pmap);
1990 pmap->pm_pdir = IdlePTD;
1991 #ifdef PMAP_PAE_COMP
1992 pmap->pm_pdpt = IdlePDPT;
1994 pmap->pm_root.rt_root = 0;
1995 CPU_ZERO(&pmap->pm_active);
1996 TAILQ_INIT(&pmap->pm_pvchunk);
1997 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1998 pmap_activate_boot(pmap);
2002 * Initialize a preallocated and zeroed pmap structure,
2003 * such as one in a vmspace structure.
2006 __CONCAT(PMTYPE, pinit)(pmap_t pmap)
2012 * No need to allocate page table space yet but we do need a valid
2013 * page directory table.
2015 if (pmap->pm_pdir == NULL) {
2016 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
2017 if (pmap->pm_pdir == NULL)
2019 #ifdef PMAP_PAE_COMP
2020 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
2021 KASSERT(((vm_offset_t)pmap->pm_pdpt &
2022 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
2023 ("pmap_pinit: pdpt misaligned"));
2024 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
2025 ("pmap_pinit: pdpt above 4g"));
2027 pmap->pm_root.rt_root = 0;
2029 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2030 ("pmap_pinit: pmap has reserved page table page(s)"));
2033 * allocate the page directory page(s)
2035 for (i = 0; i < NPGPTD; i++) {
2036 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2037 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
2038 pmap->pm_ptdpg[i] = m;
2039 #ifdef PMAP_PAE_COMP
2040 pmap->pm_pdpt[i] = VM_PAGE_TO_PHYS(m) | PG_V;
2044 pmap_qenter((vm_offset_t)pmap->pm_pdir, pmap->pm_ptdpg, NPGPTD);
2045 #ifdef PMAP_PAE_COMP
2046 if ((cpu_feature & CPUID_PAT) == 0) {
2047 pmap_invalidate_cache_range(
2048 trunc_page((vm_offset_t)pmap->pm_pdpt),
2049 round_page((vm_offset_t)pmap->pm_pdpt +
2050 NPGPTD * sizeof(pdpt_entry_t)));
2054 for (i = 0; i < NPGPTD; i++)
2055 if ((pmap->pm_ptdpg[i]->flags & PG_ZERO) == 0)
2056 pagezero(pmap->pm_pdir + (i * NPDEPG));
2058 /* Install the trampoline mapping. */
2059 pmap->pm_pdir[TRPTDI] = PTD[TRPTDI];
2061 CPU_ZERO(&pmap->pm_active);
2062 TAILQ_INIT(&pmap->pm_pvchunk);
2063 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2069 * this routine is called if the page table page is not
2073 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
2079 * Allocate a page table page.
2081 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2082 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2083 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2085 rw_wunlock(&pvh_global_lock);
2087 rw_wlock(&pvh_global_lock);
2092 * Indicate the need to retry. While waiting, the page table
2093 * page may have been allocated.
2097 if ((m->flags & PG_ZERO) == 0)
2101 * Map the pagetable page into the process address space, if
2102 * it isn't already there.
2105 pmap->pm_stats.resident_count++;
2107 ptepa = VM_PAGE_TO_PHYS(m);
2108 pmap->pm_pdir[ptepindex] =
2109 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
2115 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
2122 * Calculate pagetable page index
2124 ptepindex = va >> PDRSHIFT;
2127 * Get the page directory entry
2129 ptepa = pmap->pm_pdir[ptepindex];
2132 * This supports switching from a 4MB page to a
2135 if (ptepa & PG_PS) {
2136 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
2137 ptepa = pmap->pm_pdir[ptepindex];
2141 * If the page table page is mapped, we just increment the
2142 * hold count, and activate it.
2145 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
2149 * Here if the pte page isn't mapped, or if it has
2152 m = _pmap_allocpte(pmap, ptepindex, flags);
2153 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2160 /***************************************************
2161 * Pmap allocation/deallocation routines.
2162 ***************************************************/
2165 * Release any resources held by the given physical map.
2166 * Called when a pmap initialized by pmap_pinit is being released.
2167 * Should only be called if the map contains no valid mappings.
2170 __CONCAT(PMTYPE, release)(pmap_t pmap)
2175 KASSERT(pmap->pm_stats.resident_count == 0,
2176 ("pmap_release: pmap resident count %ld != 0",
2177 pmap->pm_stats.resident_count));
2178 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2179 ("pmap_release: pmap has reserved page table page(s)"));
2180 KASSERT(CPU_EMPTY(&pmap->pm_active),
2181 ("releasing active pmap %p", pmap));
2183 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2185 for (i = 0; i < NPGPTD; i++) {
2186 m = pmap->pm_ptdpg[i];
2187 #ifdef PMAP_PAE_COMP
2188 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2189 ("pmap_release: got wrong ptd page"));
2191 vm_page_unwire_noq(m);
2197 * grow the number of kernel page table entries, if needed
2200 __CONCAT(PMTYPE, growkernel)(vm_offset_t addr)
2202 vm_paddr_t ptppaddr;
2206 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2207 addr = roundup2(addr, NBPDR);
2208 if (addr - 1 >= vm_map_max(kernel_map))
2209 addr = vm_map_max(kernel_map);
2210 while (kernel_vm_end < addr) {
2211 if (pdir_pde(PTD, kernel_vm_end)) {
2212 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2213 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2214 kernel_vm_end = vm_map_max(kernel_map);
2220 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2221 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2224 panic("pmap_growkernel: no memory to grow kernel");
2228 if ((nkpg->flags & PG_ZERO) == 0)
2229 pmap_zero_page(nkpg);
2230 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2231 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2232 pdir_pde(KPTD, kernel_vm_end) = newpdir;
2234 pmap_kenter_pde(kernel_vm_end, newpdir);
2235 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2236 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2237 kernel_vm_end = vm_map_max(kernel_map);
2244 /***************************************************
2245 * page management routines.
2246 ***************************************************/
2248 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2249 CTASSERT(_NPCM == 11);
2250 CTASSERT(_NPCPV == 336);
2252 static __inline struct pv_chunk *
2253 pv_to_chunk(pv_entry_t pv)
2256 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2259 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2261 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2262 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2264 static const uint32_t pc_freemask[_NPCM] = {
2265 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2266 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2267 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2268 PC_FREE0_9, PC_FREE10
2272 extern int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2273 extern long pv_entry_frees, pv_entry_allocs;
2274 extern int pv_entry_spare;
2278 * We are in a serious low memory condition. Resort to
2279 * drastic measures to free some pages so we can allocate
2280 * another pv entry chunk.
2283 pmap_pv_reclaim(pmap_t locked_pmap)
2286 struct pv_chunk *pc;
2287 struct md_page *pvh;
2290 pt_entry_t *pte, tpte;
2294 struct spglist free;
2296 int bit, field, freed;
2298 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2302 TAILQ_INIT(&newtail);
2303 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2304 SLIST_EMPTY(&free))) {
2305 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2306 if (pmap != pc->pc_pmap) {
2308 pmap_invalidate_all_int(pmap);
2309 if (pmap != locked_pmap)
2313 /* Avoid deadlock and lock recursion. */
2314 if (pmap > locked_pmap)
2316 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2318 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2324 * Destroy every non-wired, 4 KB page mapping in the chunk.
2327 for (field = 0; field < _NPCM; field++) {
2328 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2329 inuse != 0; inuse &= ~(1UL << bit)) {
2331 pv = &pc->pc_pventry[field * 32 + bit];
2333 pde = pmap_pde(pmap, va);
2334 if ((*pde & PG_PS) != 0)
2336 pte = __CONCAT(PMTYPE, pte)(pmap, va);
2338 if ((tpte & PG_W) == 0)
2339 tpte = pte_load_clear(pte);
2340 pmap_pte_release(pte);
2341 if ((tpte & PG_W) != 0)
2344 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2346 if ((tpte & PG_G) != 0)
2347 pmap_invalidate_page_int(pmap, va);
2348 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2349 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2351 if ((tpte & PG_A) != 0)
2352 vm_page_aflag_set(m, PGA_REFERENCED);
2353 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2354 if (TAILQ_EMPTY(&m->md.pv_list) &&
2355 (m->flags & PG_FICTITIOUS) == 0) {
2356 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2357 if (TAILQ_EMPTY(&pvh->pv_list)) {
2358 vm_page_aflag_clear(m,
2362 pc->pc_map[field] |= 1UL << bit;
2363 pmap_unuse_pt(pmap, va, &free);
2368 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2371 /* Every freed mapping is for a 4 KB page. */
2372 pmap->pm_stats.resident_count -= freed;
2373 PV_STAT(pv_entry_frees += freed);
2374 PV_STAT(pv_entry_spare += freed);
2375 pv_entry_count -= freed;
2376 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2377 for (field = 0; field < _NPCM; field++)
2378 if (pc->pc_map[field] != pc_freemask[field]) {
2379 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2381 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2384 * One freed pv entry in locked_pmap is
2387 if (pmap == locked_pmap)
2391 if (field == _NPCM) {
2392 PV_STAT(pv_entry_spare -= _NPCPV);
2393 PV_STAT(pc_chunk_count--);
2394 PV_STAT(pc_chunk_frees++);
2395 /* Entire chunk is free; return it. */
2396 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2397 pmap_qremove((vm_offset_t)pc, 1);
2398 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2403 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2405 pmap_invalidate_all_int(pmap);
2406 if (pmap != locked_pmap)
2409 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2410 m_pc = SLIST_FIRST(&free);
2411 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2412 /* Recycle a freed page table page. */
2413 m_pc->wire_count = 1;
2415 vm_page_free_pages_toq(&free, true);
2420 * free the pv_entry back to the free list
2423 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2425 struct pv_chunk *pc;
2426 int idx, field, bit;
2428 rw_assert(&pvh_global_lock, RA_WLOCKED);
2429 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2430 PV_STAT(pv_entry_frees++);
2431 PV_STAT(pv_entry_spare++);
2433 pc = pv_to_chunk(pv);
2434 idx = pv - &pc->pc_pventry[0];
2437 pc->pc_map[field] |= 1ul << bit;
2438 for (idx = 0; idx < _NPCM; idx++)
2439 if (pc->pc_map[idx] != pc_freemask[idx]) {
2441 * 98% of the time, pc is already at the head of the
2442 * list. If it isn't already, move it to the head.
2444 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2446 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2447 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2452 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2457 free_pv_chunk(struct pv_chunk *pc)
2461 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2462 PV_STAT(pv_entry_spare -= _NPCPV);
2463 PV_STAT(pc_chunk_count--);
2464 PV_STAT(pc_chunk_frees++);
2465 /* entire chunk is free, return it */
2466 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2467 pmap_qremove((vm_offset_t)pc, 1);
2468 vm_page_unwire(m, PQ_NONE);
2470 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2474 * get a new pv_entry, allocating a block from the system
2478 get_pv_entry(pmap_t pmap, boolean_t try)
2480 static const struct timeval printinterval = { 60, 0 };
2481 static struct timeval lastprint;
2484 struct pv_chunk *pc;
2487 rw_assert(&pvh_global_lock, RA_WLOCKED);
2488 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2489 PV_STAT(pv_entry_allocs++);
2491 if (pv_entry_count > pv_entry_high_water)
2492 if (ratecheck(&lastprint, &printinterval))
2493 printf("Approaching the limit on PV entries, consider "
2494 "increasing either the vm.pmap.shpgperproc or the "
2495 "vm.pmap.pv_entries tunable.\n");
2497 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2499 for (field = 0; field < _NPCM; field++) {
2500 if (pc->pc_map[field]) {
2501 bit = bsfl(pc->pc_map[field]);
2505 if (field < _NPCM) {
2506 pv = &pc->pc_pventry[field * 32 + bit];
2507 pc->pc_map[field] &= ~(1ul << bit);
2508 /* If this was the last item, move it to tail */
2509 for (field = 0; field < _NPCM; field++)
2510 if (pc->pc_map[field] != 0) {
2511 PV_STAT(pv_entry_spare--);
2512 return (pv); /* not full, return */
2514 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2515 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2516 PV_STAT(pv_entry_spare--);
2521 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2522 * global lock. If "pv_vafree" is currently non-empty, it will
2523 * remain non-empty until pmap_ptelist_alloc() completes.
2525 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2526 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2529 PV_STAT(pc_chunk_tryfail++);
2532 m = pmap_pv_reclaim(pmap);
2536 PV_STAT(pc_chunk_count++);
2537 PV_STAT(pc_chunk_allocs++);
2538 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2539 pmap_qenter((vm_offset_t)pc, &m, 1);
2541 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2542 for (field = 1; field < _NPCM; field++)
2543 pc->pc_map[field] = pc_freemask[field];
2544 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2545 pv = &pc->pc_pventry[0];
2546 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2547 PV_STAT(pv_entry_spare += _NPCPV - 1);
2551 static __inline pv_entry_t
2552 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2556 rw_assert(&pvh_global_lock, RA_WLOCKED);
2557 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2558 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2559 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2567 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2569 struct md_page *pvh;
2571 vm_offset_t va_last;
2574 rw_assert(&pvh_global_lock, RA_WLOCKED);
2575 KASSERT((pa & PDRMASK) == 0,
2576 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2579 * Transfer the 4mpage's pv entry for this mapping to the first
2582 pvh = pa_to_pvh(pa);
2583 va = trunc_4mpage(va);
2584 pv = pmap_pvh_remove(pvh, pmap, va);
2585 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2586 m = PHYS_TO_VM_PAGE(pa);
2587 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2588 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2589 va_last = va + NBPDR - PAGE_SIZE;
2592 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2593 ("pmap_pv_demote_pde: page %p is not managed", m));
2595 pmap_insert_entry(pmap, va, m);
2596 } while (va < va_last);
2599 #if VM_NRESERVLEVEL > 0
2601 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2603 struct md_page *pvh;
2605 vm_offset_t va_last;
2608 rw_assert(&pvh_global_lock, RA_WLOCKED);
2609 KASSERT((pa & PDRMASK) == 0,
2610 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2613 * Transfer the first page's pv entry for this mapping to the
2614 * 4mpage's pv list. Aside from avoiding the cost of a call
2615 * to get_pv_entry(), a transfer avoids the possibility that
2616 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2617 * removes one of the mappings that is being promoted.
2619 m = PHYS_TO_VM_PAGE(pa);
2620 va = trunc_4mpage(va);
2621 pv = pmap_pvh_remove(&m->md, pmap, va);
2622 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2623 pvh = pa_to_pvh(pa);
2624 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2625 /* Free the remaining NPTEPG - 1 pv entries. */
2626 va_last = va + NBPDR - PAGE_SIZE;
2630 pmap_pvh_free(&m->md, pmap, va);
2631 } while (va < va_last);
2633 #endif /* VM_NRESERVLEVEL > 0 */
2636 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2640 pv = pmap_pvh_remove(pvh, pmap, va);
2641 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2642 free_pv_entry(pmap, pv);
2646 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2648 struct md_page *pvh;
2650 rw_assert(&pvh_global_lock, RA_WLOCKED);
2651 pmap_pvh_free(&m->md, pmap, va);
2652 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2653 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2654 if (TAILQ_EMPTY(&pvh->pv_list))
2655 vm_page_aflag_clear(m, PGA_WRITEABLE);
2660 * Create a pv entry for page at pa for
2664 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2668 rw_assert(&pvh_global_lock, RA_WLOCKED);
2669 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2670 pv = get_pv_entry(pmap, FALSE);
2672 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2676 * Conditionally create a pv entry.
2679 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2683 rw_assert(&pvh_global_lock, RA_WLOCKED);
2684 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2685 if (pv_entry_count < pv_entry_high_water &&
2686 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2688 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2695 * Create the pv entries for each of the pages within a superpage.
2698 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags)
2700 struct md_page *pvh;
2704 rw_assert(&pvh_global_lock, RA_WLOCKED);
2705 noreclaim = (flags & PMAP_ENTER_NORECLAIM) != 0;
2706 if ((noreclaim && pv_entry_count >= pv_entry_high_water) ||
2707 (pv = get_pv_entry(pmap, noreclaim)) == NULL)
2710 pvh = pa_to_pvh(pde & PG_PS_FRAME);
2711 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2716 * Fills a page table page with mappings to consecutive physical pages.
2719 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2723 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2725 newpte += PAGE_SIZE;
2730 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2731 * 2- or 4MB page mapping is invalidated.
2734 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2736 pd_entry_t newpde, oldpde;
2737 pt_entry_t *firstpte, newpte;
2740 struct spglist free;
2743 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2745 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2746 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2747 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
2749 KASSERT((oldpde & PG_W) == 0,
2750 ("pmap_demote_pde: page table page for a wired mapping"
2754 * Invalidate the 2- or 4MB page mapping and return
2755 * "failure" if the mapping was never accessed or the
2756 * allocation of the new page table page fails.
2758 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2759 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2760 VM_ALLOC_WIRED)) == NULL) {
2762 sva = trunc_4mpage(va);
2763 pmap_remove_pde(pmap, pde, sva, &free);
2764 if ((oldpde & PG_G) == 0)
2765 pmap_invalidate_pde_page(pmap, sva, oldpde);
2766 vm_page_free_pages_toq(&free, true);
2767 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2768 " in pmap %p", va, pmap);
2771 if (pmap != kernel_pmap) {
2772 mpte->wire_count = NPTEPG;
2773 pmap->pm_stats.resident_count++;
2776 mptepa = VM_PAGE_TO_PHYS(mpte);
2779 * If the page mapping is in the kernel's address space, then the
2780 * KPTmap can provide access to the page table page. Otherwise,
2781 * temporarily map the page table page (mpte) into the kernel's
2782 * address space at either PADDR1 or PADDR2.
2784 if (pmap == kernel_pmap)
2785 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2786 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2787 if ((*PMAP1 & PG_FRAME) != mptepa) {
2788 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2790 PMAP1cpu = PCPU_GET(cpuid);
2796 if (PMAP1cpu != PCPU_GET(cpuid)) {
2797 PMAP1cpu = PCPU_GET(cpuid);
2805 mtx_lock(&PMAP2mutex);
2806 if ((*PMAP2 & PG_FRAME) != mptepa) {
2807 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2808 pmap_invalidate_page_int(kernel_pmap,
2809 (vm_offset_t)PADDR2);
2813 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2814 KASSERT((oldpde & PG_A) != 0,
2815 ("pmap_demote_pde: oldpde is missing PG_A"));
2816 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2817 ("pmap_demote_pde: oldpde is missing PG_M"));
2818 newpte = oldpde & ~PG_PS;
2819 if ((newpte & PG_PDE_PAT) != 0)
2820 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2823 * If the page table page is not leftover from an earlier promotion,
2826 if ((oldpde & PG_PROMOTED) == 0)
2827 pmap_fill_ptp(firstpte, newpte);
2829 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2830 ("pmap_demote_pde: firstpte and newpte map different physical"
2834 * If the mapping has changed attributes, update the page table
2837 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2838 pmap_fill_ptp(firstpte, newpte);
2841 * Demote the mapping. This pmap is locked. The old PDE has
2842 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2843 * set. Thus, there is no danger of a race with another
2844 * processor changing the setting of PG_A and/or PG_M between
2845 * the read above and the store below.
2847 if (workaround_erratum383)
2848 pmap_update_pde(pmap, va, pde, newpde);
2849 else if (pmap == kernel_pmap)
2850 pmap_kenter_pde(va, newpde);
2852 pde_store(pde, newpde);
2853 if (firstpte == PADDR2)
2854 mtx_unlock(&PMAP2mutex);
2857 * Invalidate the recursive mapping of the page table page.
2859 pmap_invalidate_page_int(pmap, (vm_offset_t)vtopte(va));
2862 * Demote the pv entry. This depends on the earlier demotion
2863 * of the mapping. Specifically, the (re)creation of a per-
2864 * page pv entry might trigger the execution of pmap_collect(),
2865 * which might reclaim a newly (re)created per-page pv entry
2866 * and destroy the associated mapping. In order to destroy
2867 * the mapping, the PDE must have already changed from mapping
2868 * the 2mpage to referencing the page table page.
2870 if ((oldpde & PG_MANAGED) != 0)
2871 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2873 pmap_pde_demotions++;
2874 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2875 " in pmap %p", va, pmap);
2880 * Removes a 2- or 4MB page mapping from the kernel pmap.
2883 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2889 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2890 mpte = pmap_remove_pt_page(pmap, va);
2892 panic("pmap_remove_kernel_pde: Missing pt page.");
2894 mptepa = VM_PAGE_TO_PHYS(mpte);
2895 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2898 * Initialize the page table page.
2900 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2903 * Remove the mapping.
2905 if (workaround_erratum383)
2906 pmap_update_pde(pmap, va, pde, newpde);
2908 pmap_kenter_pde(va, newpde);
2911 * Invalidate the recursive mapping of the page table page.
2913 pmap_invalidate_page_int(pmap, (vm_offset_t)vtopte(va));
2917 * pmap_remove_pde: do the things to unmap a superpage in a process
2920 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2921 struct spglist *free)
2923 struct md_page *pvh;
2925 vm_offset_t eva, va;
2928 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2929 KASSERT((sva & PDRMASK) == 0,
2930 ("pmap_remove_pde: sva is not 4mpage aligned"));
2931 oldpde = pte_load_clear(pdq);
2933 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2936 * Machines that don't support invlpg, also don't support
2939 if ((oldpde & PG_G) != 0)
2940 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
2942 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2943 if (oldpde & PG_MANAGED) {
2944 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2945 pmap_pvh_free(pvh, pmap, sva);
2947 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2948 va < eva; va += PAGE_SIZE, m++) {
2949 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2952 vm_page_aflag_set(m, PGA_REFERENCED);
2953 if (TAILQ_EMPTY(&m->md.pv_list) &&
2954 TAILQ_EMPTY(&pvh->pv_list))
2955 vm_page_aflag_clear(m, PGA_WRITEABLE);
2958 if (pmap == kernel_pmap) {
2959 pmap_remove_kernel_pde(pmap, pdq, sva);
2961 mpte = pmap_remove_pt_page(pmap, sva);
2963 pmap->pm_stats.resident_count--;
2964 KASSERT(mpte->wire_count == NPTEPG,
2965 ("pmap_remove_pde: pte page wire count error"));
2966 mpte->wire_count = 0;
2967 pmap_add_delayed_free_list(mpte, free, FALSE);
2973 * pmap_remove_pte: do the things to unmap a page in a process
2976 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
2977 struct spglist *free)
2982 rw_assert(&pvh_global_lock, RA_WLOCKED);
2983 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2984 oldpte = pte_load_clear(ptq);
2985 KASSERT(oldpte != 0,
2986 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
2988 pmap->pm_stats.wired_count -= 1;
2990 * Machines that don't support invlpg, also don't support
2994 pmap_invalidate_page_int(kernel_pmap, va);
2995 pmap->pm_stats.resident_count -= 1;
2996 if (oldpte & PG_MANAGED) {
2997 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2998 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3001 vm_page_aflag_set(m, PGA_REFERENCED);
3002 pmap_remove_entry(pmap, m, va);
3004 return (pmap_unuse_pt(pmap, va, free));
3008 * Remove a single page from a process address space
3011 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
3015 rw_assert(&pvh_global_lock, RA_WLOCKED);
3016 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3017 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3018 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
3020 pmap_remove_pte(pmap, pte, va, free);
3021 pmap_invalidate_page_int(pmap, va);
3025 * Removes the specified range of addresses from the page table page.
3028 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
3029 struct spglist *free)
3034 rw_assert(&pvh_global_lock, RA_WLOCKED);
3035 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3036 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3038 for (pte = pmap_pte_quick(pmap, sva); sva != eva; pte++,
3044 * The TLB entry for a PG_G mapping is invalidated by
3045 * pmap_remove_pte().
3047 if ((*pte & PG_G) == 0)
3050 if (pmap_remove_pte(pmap, pte, sva, free))
3057 * Remove the given range of addresses from the specified map.
3059 * It is assumed that the start and end are properly
3060 * rounded to the page size.
3063 __CONCAT(PMTYPE, remove)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3067 struct spglist free;
3071 * Perform an unsynchronized read. This is, however, safe.
3073 if (pmap->pm_stats.resident_count == 0)
3079 rw_wlock(&pvh_global_lock);
3084 * special handling of removing one page. a very
3085 * common operation and easy to short circuit some
3088 if ((sva + PAGE_SIZE == eva) &&
3089 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
3090 pmap_remove_page(pmap, sva, &free);
3094 for (; sva < eva; sva = pdnxt) {
3098 * Calculate index for next page table.
3100 pdnxt = (sva + NBPDR) & ~PDRMASK;
3103 if (pmap->pm_stats.resident_count == 0)
3106 pdirindex = sva >> PDRSHIFT;
3107 ptpaddr = pmap->pm_pdir[pdirindex];
3110 * Weed out invalid mappings. Note: we assume that the page
3111 * directory table is always allocated, and in kernel virtual.
3117 * Check for large page.
3119 if ((ptpaddr & PG_PS) != 0) {
3121 * Are we removing the entire large page? If not,
3122 * demote the mapping and fall through.
3124 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3126 * The TLB entry for a PG_G mapping is
3127 * invalidated by pmap_remove_pde().
3129 if ((ptpaddr & PG_G) == 0)
3131 pmap_remove_pde(pmap,
3132 &pmap->pm_pdir[pdirindex], sva, &free);
3134 } else if (!pmap_demote_pde(pmap,
3135 &pmap->pm_pdir[pdirindex], sva)) {
3136 /* The large page mapping was destroyed. */
3142 * Limit our scan to either the end of the va represented
3143 * by the current page table page, or to the end of the
3144 * range being removed.
3149 if (pmap_remove_ptes(pmap, sva, pdnxt, &free))
3155 pmap_invalidate_all_int(pmap);
3156 rw_wunlock(&pvh_global_lock);
3158 vm_page_free_pages_toq(&free, true);
3162 * Routine: pmap_remove_all
3164 * Removes this physical page from
3165 * all physical maps in which it resides.
3166 * Reflects back modify bits to the pager.
3169 * Original versions of this routine were very
3170 * inefficient because they iteratively called
3171 * pmap_remove (slow...)
3175 __CONCAT(PMTYPE, remove_all)(vm_page_t m)
3177 struct md_page *pvh;
3180 pt_entry_t *pte, tpte;
3183 struct spglist free;
3185 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3186 ("pmap_remove_all: page %p is not managed", m));
3188 rw_wlock(&pvh_global_lock);
3190 if ((m->flags & PG_FICTITIOUS) != 0)
3191 goto small_mappings;
3192 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3193 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3197 pde = pmap_pde(pmap, va);
3198 (void)pmap_demote_pde(pmap, pde, va);
3202 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3205 pmap->pm_stats.resident_count--;
3206 pde = pmap_pde(pmap, pv->pv_va);
3207 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3208 " a 4mpage in page %p's pv list", m));
3209 pte = pmap_pte_quick(pmap, pv->pv_va);
3210 tpte = pte_load_clear(pte);
3211 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3214 pmap->pm_stats.wired_count--;
3216 vm_page_aflag_set(m, PGA_REFERENCED);
3219 * Update the vm_page_t clean and reference bits.
3221 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3223 pmap_unuse_pt(pmap, pv->pv_va, &free);
3224 pmap_invalidate_page_int(pmap, pv->pv_va);
3225 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3226 free_pv_entry(pmap, pv);
3229 vm_page_aflag_clear(m, PGA_WRITEABLE);
3231 rw_wunlock(&pvh_global_lock);
3232 vm_page_free_pages_toq(&free, true);
3236 * pmap_protect_pde: do the things to protect a 4mpage in a process
3239 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3241 pd_entry_t newpde, oldpde;
3242 vm_offset_t eva, va;
3244 boolean_t anychanged;
3246 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3247 KASSERT((sva & PDRMASK) == 0,
3248 ("pmap_protect_pde: sva is not 4mpage aligned"));
3251 oldpde = newpde = *pde;
3252 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
3253 (PG_MANAGED | PG_M | PG_RW)) {
3255 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3256 va < eva; va += PAGE_SIZE, m++)
3259 if ((prot & VM_PROT_WRITE) == 0)
3260 newpde &= ~(PG_RW | PG_M);
3261 #ifdef PMAP_PAE_COMP
3262 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
3265 if (newpde != oldpde) {
3267 * As an optimization to future operations on this PDE, clear
3268 * PG_PROMOTED. The impending invalidation will remove any
3269 * lingering 4KB page mappings from the TLB.
3271 if (!pde_cmpset(pde, oldpde, newpde & ~PG_PROMOTED))
3273 if ((oldpde & PG_G) != 0)
3274 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
3278 return (anychanged);
3282 * Set the physical protection on the
3283 * specified range of this map as requested.
3286 __CONCAT(PMTYPE, protect)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
3292 boolean_t anychanged, pv_lists_locked;
3294 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3295 if (prot == VM_PROT_NONE) {
3296 pmap_remove(pmap, sva, eva);
3300 #ifdef PMAP_PAE_COMP
3301 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
3302 (VM_PROT_WRITE | VM_PROT_EXECUTE))
3305 if (prot & VM_PROT_WRITE)
3309 if (pmap_is_current(pmap))
3310 pv_lists_locked = FALSE;
3312 pv_lists_locked = TRUE;
3314 rw_wlock(&pvh_global_lock);
3320 for (; sva < eva; sva = pdnxt) {
3321 pt_entry_t obits, pbits;
3324 pdnxt = (sva + NBPDR) & ~PDRMASK;
3328 pdirindex = sva >> PDRSHIFT;
3329 ptpaddr = pmap->pm_pdir[pdirindex];
3332 * Weed out invalid mappings. Note: we assume that the page
3333 * directory table is always allocated, and in kernel virtual.
3339 * Check for large page.
3341 if ((ptpaddr & PG_PS) != 0) {
3343 * Are we protecting the entire large page? If not,
3344 * demote the mapping and fall through.
3346 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3348 * The TLB entry for a PG_G mapping is
3349 * invalidated by pmap_protect_pde().
3351 if (pmap_protect_pde(pmap,
3352 &pmap->pm_pdir[pdirindex], sva, prot))
3356 if (!pv_lists_locked) {
3357 pv_lists_locked = TRUE;
3358 if (!rw_try_wlock(&pvh_global_lock)) {
3360 pmap_invalidate_all_int(
3367 if (!pmap_demote_pde(pmap,
3368 &pmap->pm_pdir[pdirindex], sva)) {
3370 * The large page mapping was
3381 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3387 * Regardless of whether a pte is 32 or 64 bits in
3388 * size, PG_RW, PG_A, and PG_M are among the least
3389 * significant 32 bits.
3391 obits = pbits = *pte;
3392 if ((pbits & PG_V) == 0)
3395 if ((prot & VM_PROT_WRITE) == 0) {
3396 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3397 (PG_MANAGED | PG_M | PG_RW)) {
3398 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3401 pbits &= ~(PG_RW | PG_M);
3403 #ifdef PMAP_PAE_COMP
3404 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
3408 if (pbits != obits) {
3409 #ifdef PMAP_PAE_COMP
3410 if (!atomic_cmpset_64(pte, obits, pbits))
3413 if (!atomic_cmpset_int((u_int *)pte, obits,
3418 pmap_invalidate_page_int(pmap, sva);
3425 pmap_invalidate_all_int(pmap);
3426 if (pv_lists_locked) {
3428 rw_wunlock(&pvh_global_lock);
3433 #if VM_NRESERVLEVEL > 0
3435 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3436 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3437 * For promotion to occur, two conditions must be met: (1) the 4KB page
3438 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3439 * mappings must have identical characteristics.
3441 * Managed (PG_MANAGED) mappings within the kernel address space are not
3442 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3443 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3447 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3450 pt_entry_t *firstpte, oldpte, pa, *pte;
3451 vm_offset_t oldpteva;
3454 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3457 * Examine the first PTE in the specified PTP. Abort if this PTE is
3458 * either invalid, unused, or does not map the first 4KB physical page
3459 * within a 2- or 4MB page.
3461 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3464 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3465 pmap_pde_p_failures++;
3466 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3467 " in pmap %p", va, pmap);
3470 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3471 pmap_pde_p_failures++;
3472 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3473 " in pmap %p", va, pmap);
3476 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3478 * When PG_M is already clear, PG_RW can be cleared without
3479 * a TLB invalidation.
3481 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3488 * Examine each of the other PTEs in the specified PTP. Abort if this
3489 * PTE maps an unexpected 4KB physical page or does not have identical
3490 * characteristics to the first PTE.
3492 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3493 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3496 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3497 pmap_pde_p_failures++;
3498 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3499 " in pmap %p", va, pmap);
3502 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3504 * When PG_M is already clear, PG_RW can be cleared
3505 * without a TLB invalidation.
3507 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3511 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3513 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3514 " in pmap %p", oldpteva, pmap);
3516 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3517 pmap_pde_p_failures++;
3518 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3519 " in pmap %p", va, pmap);
3526 * Save the page table page in its current state until the PDE
3527 * mapping the superpage is demoted by pmap_demote_pde() or
3528 * destroyed by pmap_remove_pde().
3530 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3531 KASSERT(mpte >= vm_page_array &&
3532 mpte < &vm_page_array[vm_page_array_size],
3533 ("pmap_promote_pde: page table page is out of range"));
3534 KASSERT(mpte->pindex == va >> PDRSHIFT,
3535 ("pmap_promote_pde: page table page's pindex is wrong"));
3536 if (pmap_insert_pt_page(pmap, mpte)) {
3537 pmap_pde_p_failures++;
3539 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3545 * Promote the pv entries.
3547 if ((newpde & PG_MANAGED) != 0)
3548 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3551 * Propagate the PAT index to its proper position.
3553 if ((newpde & PG_PTE_PAT) != 0)
3554 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3557 * Map the superpage.
3559 if (workaround_erratum383)
3560 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3561 else if (pmap == kernel_pmap)
3562 pmap_kenter_pde(va, PG_PROMOTED | PG_PS | newpde);
3564 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
3566 pmap_pde_promotions++;
3567 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3568 " in pmap %p", va, pmap);
3570 #endif /* VM_NRESERVLEVEL > 0 */
3573 * Insert the given physical page (p) at
3574 * the specified virtual address (v) in the
3575 * target physical map with the protection requested.
3577 * If specified, the page will be wired down, meaning
3578 * that the related pte can not be reclaimed.
3580 * NB: This is the only routine which MAY NOT lazy-evaluate
3581 * or lose information. That is, this routine must actually
3582 * insert this page into the given map NOW.
3585 __CONCAT(PMTYPE, enter)(pmap_t pmap, vm_offset_t va, vm_page_t m,
3586 vm_prot_t prot, u_int flags, int8_t psind)
3590 pt_entry_t newpte, origpte;
3596 va = trunc_page(va);
3597 KASSERT((pmap == kernel_pmap && va < VM_MAX_KERNEL_ADDRESS) ||
3598 (pmap != kernel_pmap && va < VM_MAXUSER_ADDRESS),
3599 ("pmap_enter: toobig k%d %#x", pmap == kernel_pmap, va));
3600 KASSERT(va < PMAP_TRM_MIN_ADDRESS,
3601 ("pmap_enter: invalid to pmap_enter into trampoline (va: 0x%x)",
3603 KASSERT(pmap != kernel_pmap || (m->oflags & VPO_UNMANAGED) != 0 ||
3604 va < kmi.clean_sva || va >= kmi.clean_eva,
3605 ("pmap_enter: managed mapping within the clean submap"));
3606 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3607 VM_OBJECT_ASSERT_LOCKED(m->object);
3608 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
3609 ("pmap_enter: flags %u has reserved bits set", flags));
3610 pa = VM_PAGE_TO_PHYS(m);
3611 newpte = (pt_entry_t)(pa | PG_A | PG_V);
3612 if ((flags & VM_PROT_WRITE) != 0)
3614 if ((prot & VM_PROT_WRITE) != 0)
3616 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
3617 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
3618 #ifdef PMAP_PAE_COMP
3619 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
3622 if ((flags & PMAP_ENTER_WIRED) != 0)
3624 if (pmap != kernel_pmap)
3626 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
3627 if ((m->oflags & VPO_UNMANAGED) == 0)
3628 newpte |= PG_MANAGED;
3630 rw_wlock(&pvh_global_lock);
3634 /* Assert the required virtual and physical alignment. */
3635 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
3636 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3637 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m);
3641 pde = pmap_pde(pmap, va);
3642 if (pmap != kernel_pmap) {
3645 * In the case that a page table page is not resident,
3646 * we are creating it here. pmap_allocpte() handles
3649 mpte = pmap_allocpte(pmap, va, flags);
3651 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3652 ("pmap_allocpte failed with sleep allowed"));
3653 rv = KERN_RESOURCE_SHORTAGE;
3658 * va is for KVA, so pmap_demote_pde() will never fail
3659 * to install a page table page. PG_V is also
3660 * asserted by pmap_demote_pde().
3663 KASSERT(pde != NULL && (*pde & PG_V) != 0,
3664 ("KVA %#x invalid pde pdir %#jx", va,
3665 (uintmax_t)pmap->pm_pdir[PTDPTDI]));
3666 if ((*pde & PG_PS) != 0)
3667 pmap_demote_pde(pmap, pde, va);
3669 pte = pmap_pte_quick(pmap, va);
3672 * Page Directory table entry is not valid, which should not
3673 * happen. We should have either allocated the page table
3674 * page or demoted the existing mapping above.
3677 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3678 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3685 * Is the specified virtual address already mapped?
3687 if ((origpte & PG_V) != 0) {
3689 * Wiring change, just update stats. We don't worry about
3690 * wiring PT pages as they remain resident as long as there
3691 * are valid mappings in them. Hence, if a user page is wired,
3692 * the PT page will be also.
3694 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
3695 pmap->pm_stats.wired_count++;
3696 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
3697 pmap->pm_stats.wired_count--;
3700 * Remove the extra PT page reference.
3704 KASSERT(mpte->wire_count > 0,
3705 ("pmap_enter: missing reference to page table page,"
3710 * Has the physical page changed?
3712 opa = origpte & PG_FRAME;
3715 * No, might be a protection or wiring change.
3717 if ((origpte & PG_MANAGED) != 0 &&
3718 (newpte & PG_RW) != 0)
3719 vm_page_aflag_set(m, PGA_WRITEABLE);
3720 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
3726 * The physical page has changed. Temporarily invalidate
3727 * the mapping. This ensures that all threads sharing the
3728 * pmap keep a consistent view of the mapping, which is
3729 * necessary for the correct handling of COW faults. It
3730 * also permits reuse of the old mapping's PV entry,
3731 * avoiding an allocation.
3733 * For consistency, handle unmanaged mappings the same way.
3735 origpte = pte_load_clear(pte);
3736 KASSERT((origpte & PG_FRAME) == opa,
3737 ("pmap_enter: unexpected pa update for %#x", va));
3738 if ((origpte & PG_MANAGED) != 0) {
3739 om = PHYS_TO_VM_PAGE(opa);
3742 * The pmap lock is sufficient to synchronize with
3743 * concurrent calls to pmap_page_test_mappings() and
3744 * pmap_ts_referenced().
3746 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3748 if ((origpte & PG_A) != 0)
3749 vm_page_aflag_set(om, PGA_REFERENCED);
3750 pv = pmap_pvh_remove(&om->md, pmap, va);
3752 ("pmap_enter: no PV entry for %#x", va));
3753 if ((newpte & PG_MANAGED) == 0)
3754 free_pv_entry(pmap, pv);
3755 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3756 TAILQ_EMPTY(&om->md.pv_list) &&
3757 ((om->flags & PG_FICTITIOUS) != 0 ||
3758 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3759 vm_page_aflag_clear(om, PGA_WRITEABLE);
3761 if ((origpte & PG_A) != 0)
3762 pmap_invalidate_page_int(pmap, va);
3766 * Increment the counters.
3768 if ((newpte & PG_W) != 0)
3769 pmap->pm_stats.wired_count++;
3770 pmap->pm_stats.resident_count++;
3774 * Enter on the PV list if part of our managed memory.
3776 if ((newpte & PG_MANAGED) != 0) {
3778 pv = get_pv_entry(pmap, FALSE);
3781 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3782 if ((newpte & PG_RW) != 0)
3783 vm_page_aflag_set(m, PGA_WRITEABLE);
3789 if ((origpte & PG_V) != 0) {
3791 origpte = pte_load_store(pte, newpte);
3792 KASSERT((origpte & PG_FRAME) == pa,
3793 ("pmap_enter: unexpected pa update for %#x", va));
3794 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
3796 if ((origpte & PG_MANAGED) != 0)
3800 * Although the PTE may still have PG_RW set, TLB
3801 * invalidation may nonetheless be required because
3802 * the PTE no longer has PG_M set.
3805 #ifdef PMAP_PAE_COMP
3806 else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
3808 * This PTE change does not require TLB invalidation.
3813 if ((origpte & PG_A) != 0)
3814 pmap_invalidate_page_int(pmap, va);
3816 pte_store_zero(pte, newpte);
3820 #if VM_NRESERVLEVEL > 0
3822 * If both the page table page and the reservation are fully
3823 * populated, then attempt promotion.
3825 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3826 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3827 vm_reserv_level_iffullpop(m) == 0)
3828 pmap_promote_pde(pmap, pde, va);
3834 rw_wunlock(&pvh_global_lock);
3840 * Tries to create a read- and/or execute-only 2 or 4 MB page mapping. Returns
3841 * true if successful. Returns false if (1) a mapping already exists at the
3842 * specified virtual address or (2) a PV entry cannot be allocated without
3843 * reclaiming another PV entry.
3846 pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3850 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3851 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
3853 if ((m->oflags & VPO_UNMANAGED) == 0)
3854 newpde |= PG_MANAGED;
3855 #ifdef PMAP_PAE_COMP
3856 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
3859 if (pmap != kernel_pmap)
3861 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
3862 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL) ==
3867 * Tries to create the specified 2 or 4 MB page mapping. Returns KERN_SUCCESS
3868 * if the mapping was created, and either KERN_FAILURE or
3869 * KERN_RESOURCE_SHORTAGE otherwise. Returns KERN_FAILURE if
3870 * PMAP_ENTER_NOREPLACE was specified and a mapping already exists at the
3871 * specified virtual address. Returns KERN_RESOURCE_SHORTAGE if
3872 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3874 * The parameter "m" is only used when creating a managed, writeable mapping.
3877 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
3880 struct spglist free;
3881 pd_entry_t oldpde, *pde;
3884 rw_assert(&pvh_global_lock, RA_WLOCKED);
3885 KASSERT((newpde & (PG_M | PG_RW)) != PG_RW,
3886 ("pmap_enter_pde: newpde is missing PG_M"));
3887 KASSERT(pmap == kernel_pmap || (newpde & PG_W) == 0,
3888 ("pmap_enter_pde: cannot create wired user mapping"));
3889 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3890 pde = pmap_pde(pmap, va);
3892 if ((oldpde & PG_V) != 0) {
3893 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
3894 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3895 " in pmap %p", va, pmap);
3896 return (KERN_FAILURE);
3898 /* Break the existing mapping(s). */
3900 if ((oldpde & PG_PS) != 0) {
3902 * If the PDE resulted from a promotion, then a
3903 * reserved PT page could be freed.
3905 (void)pmap_remove_pde(pmap, pde, va, &free);
3906 if ((oldpde & PG_G) == 0)
3907 pmap_invalidate_pde_page(pmap, va, oldpde);
3909 if (pmap_remove_ptes(pmap, va, va + NBPDR, &free))
3910 pmap_invalidate_all_int(pmap);
3912 vm_page_free_pages_toq(&free, true);
3913 if (pmap == kernel_pmap) {
3914 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3915 if (pmap_insert_pt_page(pmap, mt)) {
3917 * XXX Currently, this can't happen because
3918 * we do not perform pmap_enter(psind == 1)
3919 * on the kernel pmap.
3921 panic("pmap_enter_pde: trie insert failed");
3924 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
3927 if ((newpde & PG_MANAGED) != 0) {
3929 * Abort this mapping if its PV entry could not be created.
3931 if (!pmap_pv_insert_pde(pmap, va, newpde, flags)) {
3932 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3933 " in pmap %p", va, pmap);
3934 return (KERN_RESOURCE_SHORTAGE);
3936 if ((newpde & PG_RW) != 0) {
3937 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
3938 vm_page_aflag_set(mt, PGA_WRITEABLE);
3943 * Increment counters.
3945 if ((newpde & PG_W) != 0)
3946 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
3947 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3950 * Map the superpage. (This is not a promoted mapping; there will not
3951 * be any lingering 4KB page mappings in the TLB.)
3953 pde_store(pde, newpde);
3955 pmap_pde_mappings++;
3956 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3957 " in pmap %p", va, pmap);
3958 return (KERN_SUCCESS);
3962 * Maps a sequence of resident pages belonging to the same object.
3963 * The sequence begins with the given page m_start. This page is
3964 * mapped at the given virtual address start. Each subsequent page is
3965 * mapped at a virtual address that is offset from start by the same
3966 * amount as the page is offset from m_start within the object. The
3967 * last page in the sequence is the page with the largest offset from
3968 * m_start that can be mapped at a virtual address less than the given
3969 * virtual address end. Not every virtual page between start and end
3970 * is mapped; only those for which a resident page exists with the
3971 * corresponding offset from m_start are mapped.
3974 __CONCAT(PMTYPE, enter_object)(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3975 vm_page_t m_start, vm_prot_t prot)
3979 vm_pindex_t diff, psize;
3981 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3983 psize = atop(end - start);
3986 rw_wlock(&pvh_global_lock);
3988 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3989 va = start + ptoa(diff);
3990 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3991 m->psind == 1 && pg_ps_enabled &&
3992 pmap_enter_4mpage(pmap, va, m, prot))
3993 m = &m[NBPDR / PAGE_SIZE - 1];
3995 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3997 m = TAILQ_NEXT(m, listq);
3999 rw_wunlock(&pvh_global_lock);
4004 * this code makes some *MAJOR* assumptions:
4005 * 1. Current pmap & pmap exists.
4008 * 4. No page table pages.
4009 * but is *MUCH* faster than pmap_enter...
4013 __CONCAT(PMTYPE, enter_quick)(pmap_t pmap, vm_offset_t va, vm_page_t m,
4017 rw_wlock(&pvh_global_lock);
4019 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
4020 rw_wunlock(&pvh_global_lock);
4025 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4026 vm_prot_t prot, vm_page_t mpte)
4028 pt_entry_t newpte, *pte;
4029 struct spglist free;
4031 KASSERT(pmap != kernel_pmap || va < kmi.clean_sva ||
4032 va >= kmi.clean_eva || (m->oflags & VPO_UNMANAGED) != 0,
4033 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4034 rw_assert(&pvh_global_lock, RA_WLOCKED);
4035 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4038 * In the case that a page table page is not
4039 * resident, we are creating it here.
4041 if (pmap != kernel_pmap) {
4046 * Calculate pagetable page index
4048 ptepindex = va >> PDRSHIFT;
4049 if (mpte && (mpte->pindex == ptepindex)) {
4053 * Get the page directory entry
4055 ptepa = pmap->pm_pdir[ptepindex];
4058 * If the page table page is mapped, we just increment
4059 * the hold count, and activate it.
4064 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
4067 mpte = _pmap_allocpte(pmap, ptepindex,
4068 PMAP_ENTER_NOSLEEP);
4078 pte = pmap_pte_quick(pmap, va);
4089 * Enter on the PV list if part of our managed memory.
4091 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4092 !pmap_try_insert_pv_entry(pmap, va, m)) {
4095 if (pmap_unwire_ptp(pmap, mpte, &free)) {
4096 pmap_invalidate_page_int(pmap, va);
4097 vm_page_free_pages_toq(&free, true);
4107 * Increment counters
4109 pmap->pm_stats.resident_count++;
4111 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
4112 pmap_cache_bits(pmap, m->md.pat_mode, 0);
4113 if ((m->oflags & VPO_UNMANAGED) == 0)
4114 newpte |= PG_MANAGED;
4115 #ifdef PMAP_PAE_COMP
4116 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
4119 if (pmap != kernel_pmap)
4121 pte_store_zero(pte, newpte);
4127 * Make a temporary mapping for a physical address. This is only intended
4128 * to be used for panic dumps.
4131 __CONCAT(PMTYPE, kenter_temporary)(vm_paddr_t pa, int i)
4135 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
4136 pmap_kenter(va, pa);
4138 return ((void *)crashdumpmap);
4142 * This code maps large physical mmap regions into the
4143 * processor address space. Note that some shortcuts
4144 * are taken, but the code works.
4147 __CONCAT(PMTYPE, object_init_pt)(pmap_t pmap, vm_offset_t addr,
4148 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
4151 vm_paddr_t pa, ptepa;
4155 VM_OBJECT_ASSERT_WLOCKED(object);
4156 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4157 ("pmap_object_init_pt: non-device object"));
4158 if (pg_ps_enabled &&
4159 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
4160 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4162 p = vm_page_lookup(object, pindex);
4163 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4164 ("pmap_object_init_pt: invalid page %p", p));
4165 pat_mode = p->md.pat_mode;
4168 * Abort the mapping if the first page is not physically
4169 * aligned to a 2/4MB page boundary.
4171 ptepa = VM_PAGE_TO_PHYS(p);
4172 if (ptepa & (NBPDR - 1))
4176 * Skip the first page. Abort the mapping if the rest of
4177 * the pages are not physically contiguous or have differing
4178 * memory attributes.
4180 p = TAILQ_NEXT(p, listq);
4181 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4183 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4184 ("pmap_object_init_pt: invalid page %p", p));
4185 if (pa != VM_PAGE_TO_PHYS(p) ||
4186 pat_mode != p->md.pat_mode)
4188 p = TAILQ_NEXT(p, listq);
4192 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
4193 * "size" is a multiple of 2/4M, adding the PAT setting to
4194 * "pa" will not affect the termination of this loop.
4197 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
4198 pa < ptepa + size; pa += NBPDR) {
4199 pde = pmap_pde(pmap, addr);
4201 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4202 PG_U | PG_RW | PG_V);
4203 pmap->pm_stats.resident_count += NBPDR /
4205 pmap_pde_mappings++;
4207 /* Else continue on if the PDE is already valid. */
4215 * Clear the wired attribute from the mappings for the specified range of
4216 * addresses in the given pmap. Every valid mapping within that range
4217 * must have the wired attribute set. In contrast, invalid mappings
4218 * cannot have the wired attribute set, so they are ignored.
4220 * The wired attribute of the page table entry is not a hardware feature,
4221 * so there is no need to invalidate any TLB entries.
4224 __CONCAT(PMTYPE, unwire)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4229 boolean_t pv_lists_locked;
4231 if (pmap_is_current(pmap))
4232 pv_lists_locked = FALSE;
4234 pv_lists_locked = TRUE;
4236 rw_wlock(&pvh_global_lock);
4240 for (; sva < eva; sva = pdnxt) {
4241 pdnxt = (sva + NBPDR) & ~PDRMASK;
4244 pde = pmap_pde(pmap, sva);
4245 if ((*pde & PG_V) == 0)
4247 if ((*pde & PG_PS) != 0) {
4248 if ((*pde & PG_W) == 0)
4249 panic("pmap_unwire: pde %#jx is missing PG_W",
4253 * Are we unwiring the entire large page? If not,
4254 * demote the mapping and fall through.
4256 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4258 * Regardless of whether a pde (or pte) is 32
4259 * or 64 bits in size, PG_W is among the least
4260 * significant 32 bits.
4262 atomic_clear_int((u_int *)pde, PG_W);
4263 pmap->pm_stats.wired_count -= NBPDR /
4267 if (!pv_lists_locked) {
4268 pv_lists_locked = TRUE;
4269 if (!rw_try_wlock(&pvh_global_lock)) {
4276 if (!pmap_demote_pde(pmap, pde, sva))
4277 panic("pmap_unwire: demotion failed");
4282 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4284 if ((*pte & PG_V) == 0)
4286 if ((*pte & PG_W) == 0)
4287 panic("pmap_unwire: pte %#jx is missing PG_W",
4291 * PG_W must be cleared atomically. Although the pmap
4292 * lock synchronizes access to PG_W, another processor
4293 * could be setting PG_M and/or PG_A concurrently.
4295 * PG_W is among the least significant 32 bits.
4297 atomic_clear_int((u_int *)pte, PG_W);
4298 pmap->pm_stats.wired_count--;
4301 if (pv_lists_locked) {
4303 rw_wunlock(&pvh_global_lock);
4310 * Copy the range specified by src_addr/len
4311 * from the source map to the range dst_addr/len
4312 * in the destination map.
4314 * This routine is only advisory and need not do anything. Since
4315 * current pmap is always the kernel pmap when executing in
4316 * kernel, and we do not copy from the kernel pmap to a user
4317 * pmap, this optimization is not usable in 4/4G full split i386
4322 __CONCAT(PMTYPE, copy)(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
4323 vm_size_t len, vm_offset_t src_addr)
4325 struct spglist free;
4326 pt_entry_t *src_pte, *dst_pte, ptetemp;
4327 pd_entry_t srcptepaddr;
4328 vm_page_t dstmpte, srcmpte;
4329 vm_offset_t addr, end_addr, pdnxt;
4332 if (dst_addr != src_addr)
4335 end_addr = src_addr + len;
4337 rw_wlock(&pvh_global_lock);
4338 if (dst_pmap < src_pmap) {
4339 PMAP_LOCK(dst_pmap);
4340 PMAP_LOCK(src_pmap);
4342 PMAP_LOCK(src_pmap);
4343 PMAP_LOCK(dst_pmap);
4346 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4347 KASSERT(addr < PMAP_TRM_MIN_ADDRESS,
4348 ("pmap_copy: invalid to pmap_copy the trampoline"));
4350 pdnxt = (addr + NBPDR) & ~PDRMASK;
4353 ptepindex = addr >> PDRSHIFT;
4355 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4356 if (srcptepaddr == 0)
4359 if (srcptepaddr & PG_PS) {
4360 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4362 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4363 ((srcptepaddr & PG_MANAGED) == 0 ||
4364 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
4365 PMAP_ENTER_NORECLAIM))) {
4366 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4368 dst_pmap->pm_stats.resident_count +=
4370 pmap_pde_mappings++;
4375 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4376 KASSERT(srcmpte->wire_count > 0,
4377 ("pmap_copy: source page table page is unused"));
4379 if (pdnxt > end_addr)
4382 src_pte = pmap_pte_quick3(src_pmap, addr);
4383 while (addr < pdnxt) {
4386 * we only virtual copy managed pages
4388 if ((ptetemp & PG_MANAGED) != 0) {
4389 dstmpte = pmap_allocpte(dst_pmap, addr,
4390 PMAP_ENTER_NOSLEEP);
4391 if (dstmpte == NULL)
4393 dst_pte = pmap_pte_quick(dst_pmap, addr);
4394 if (*dst_pte == 0 &&
4395 pmap_try_insert_pv_entry(dst_pmap, addr,
4396 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4398 * Clear the wired, modified, and
4399 * accessed (referenced) bits
4402 *dst_pte = ptetemp & ~(PG_W | PG_M |
4404 dst_pmap->pm_stats.resident_count++;
4407 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4409 pmap_invalidate_page_int(
4411 vm_page_free_pages_toq(&free,
4416 if (dstmpte->wire_count >= srcmpte->wire_count)
4425 rw_wunlock(&pvh_global_lock);
4426 PMAP_UNLOCK(src_pmap);
4427 PMAP_UNLOCK(dst_pmap);
4431 * Zero 1 page of virtual memory mapped from a hardware page by the caller.
4433 static __inline void
4434 pagezero(void *page)
4436 #if defined(I686_CPU)
4437 if (cpu_class == CPUCLASS_686) {
4438 if (cpu_feature & CPUID_SSE2)
4439 sse2_pagezero(page);
4441 i686_pagezero(page);
4444 bzero(page, PAGE_SIZE);
4448 * Zero the specified hardware page.
4451 __CONCAT(PMTYPE, zero_page)(vm_page_t m)
4453 pt_entry_t *cmap_pte2;
4458 cmap_pte2 = pc->pc_cmap_pte2;
4459 mtx_lock(&pc->pc_cmap_lock);
4461 panic("pmap_zero_page: CMAP2 busy");
4462 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4463 pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
4464 invlcaddr(pc->pc_cmap_addr2);
4465 pagezero(pc->pc_cmap_addr2);
4469 * Unpin the thread before releasing the lock. Otherwise the thread
4470 * could be rescheduled while still bound to the current CPU, only
4471 * to unpin itself immediately upon resuming execution.
4474 mtx_unlock(&pc->pc_cmap_lock);
4478 * Zero an an area within a single hardware page. off and size must not
4479 * cover an area beyond a single hardware page.
4482 __CONCAT(PMTYPE, zero_page_area)(vm_page_t m, int off, int size)
4484 pt_entry_t *cmap_pte2;
4489 cmap_pte2 = pc->pc_cmap_pte2;
4490 mtx_lock(&pc->pc_cmap_lock);
4492 panic("pmap_zero_page_area: CMAP2 busy");
4493 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4494 pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
4495 invlcaddr(pc->pc_cmap_addr2);
4496 if (off == 0 && size == PAGE_SIZE)
4497 pagezero(pc->pc_cmap_addr2);
4499 bzero(pc->pc_cmap_addr2 + off, size);
4502 mtx_unlock(&pc->pc_cmap_lock);
4506 * Copy 1 specified hardware page to another.
4509 __CONCAT(PMTYPE, copy_page)(vm_page_t src, vm_page_t dst)
4511 pt_entry_t *cmap_pte1, *cmap_pte2;
4516 cmap_pte1 = pc->pc_cmap_pte1;
4517 cmap_pte2 = pc->pc_cmap_pte2;
4518 mtx_lock(&pc->pc_cmap_lock);
4520 panic("pmap_copy_page: CMAP1 busy");
4522 panic("pmap_copy_page: CMAP2 busy");
4523 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4524 pmap_cache_bits(kernel_pmap, src->md.pat_mode, 0);
4525 invlcaddr(pc->pc_cmap_addr1);
4526 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4527 pmap_cache_bits(kernel_pmap, dst->md.pat_mode, 0);
4528 invlcaddr(pc->pc_cmap_addr2);
4529 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE);
4533 mtx_unlock(&pc->pc_cmap_lock);
4537 __CONCAT(PMTYPE, copy_pages)(vm_page_t ma[], vm_offset_t a_offset,
4538 vm_page_t mb[], vm_offset_t b_offset, int xfersize)
4540 vm_page_t a_pg, b_pg;
4542 vm_offset_t a_pg_offset, b_pg_offset;
4543 pt_entry_t *cmap_pte1, *cmap_pte2;
4549 cmap_pte1 = pc->pc_cmap_pte1;
4550 cmap_pte2 = pc->pc_cmap_pte2;
4551 mtx_lock(&pc->pc_cmap_lock);
4552 if (*cmap_pte1 != 0)
4553 panic("pmap_copy_pages: CMAP1 busy");
4554 if (*cmap_pte2 != 0)
4555 panic("pmap_copy_pages: CMAP2 busy");
4556 while (xfersize > 0) {
4557 a_pg = ma[a_offset >> PAGE_SHIFT];
4558 a_pg_offset = a_offset & PAGE_MASK;
4559 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4560 b_pg = mb[b_offset >> PAGE_SHIFT];
4561 b_pg_offset = b_offset & PAGE_MASK;
4562 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4563 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4564 pmap_cache_bits(kernel_pmap, a_pg->md.pat_mode, 0);
4565 invlcaddr(pc->pc_cmap_addr1);
4566 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4567 PG_M | pmap_cache_bits(kernel_pmap, b_pg->md.pat_mode, 0);
4568 invlcaddr(pc->pc_cmap_addr2);
4569 a_cp = pc->pc_cmap_addr1 + a_pg_offset;
4570 b_cp = pc->pc_cmap_addr2 + b_pg_offset;
4571 bcopy(a_cp, b_cp, cnt);
4579 mtx_unlock(&pc->pc_cmap_lock);
4583 * Returns true if the pmap's pv is one of the first
4584 * 16 pvs linked to from this page. This count may
4585 * be changed upwards or downwards in the future; it
4586 * is only necessary that true be returned for a small
4587 * subset of pmaps for proper page aging.
4590 __CONCAT(PMTYPE, page_exists_quick)(pmap_t pmap, vm_page_t m)
4592 struct md_page *pvh;
4597 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4598 ("pmap_page_exists_quick: page %p is not managed", m));
4600 rw_wlock(&pvh_global_lock);
4601 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4602 if (PV_PMAP(pv) == pmap) {
4610 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4611 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4612 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4613 if (PV_PMAP(pv) == pmap) {
4622 rw_wunlock(&pvh_global_lock);
4627 * pmap_page_wired_mappings:
4629 * Return the number of managed mappings to the given physical page
4633 __CONCAT(PMTYPE, page_wired_mappings)(vm_page_t m)
4638 if ((m->oflags & VPO_UNMANAGED) != 0)
4640 rw_wlock(&pvh_global_lock);
4641 count = pmap_pvh_wired_mappings(&m->md, count);
4642 if ((m->flags & PG_FICTITIOUS) == 0) {
4643 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4646 rw_wunlock(&pvh_global_lock);
4651 * pmap_pvh_wired_mappings:
4653 * Return the updated number "count" of managed mappings that are wired.
4656 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4662 rw_assert(&pvh_global_lock, RA_WLOCKED);
4664 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4667 pte = pmap_pte_quick(pmap, pv->pv_va);
4668 if ((*pte & PG_W) != 0)
4677 * Returns TRUE if the given page is mapped individually or as part of
4678 * a 4mpage. Otherwise, returns FALSE.
4681 __CONCAT(PMTYPE, page_is_mapped)(vm_page_t m)
4685 if ((m->oflags & VPO_UNMANAGED) != 0)
4687 rw_wlock(&pvh_global_lock);
4688 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4689 ((m->flags & PG_FICTITIOUS) == 0 &&
4690 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4691 rw_wunlock(&pvh_global_lock);
4696 * Remove all pages from specified address space
4697 * this aids process exit speeds. Also, this code
4698 * is special cased for current process only, but
4699 * can have the more generic (and slightly slower)
4700 * mode enabled. This is much faster than pmap_remove
4701 * in the case of running down an entire address space.
4704 __CONCAT(PMTYPE, remove_pages)(pmap_t pmap)
4706 pt_entry_t *pte, tpte;
4707 vm_page_t m, mpte, mt;
4709 struct md_page *pvh;
4710 struct pv_chunk *pc, *npc;
4711 struct spglist free;
4714 uint32_t inuse, bitmask;
4717 if (pmap != PCPU_GET(curpmap)) {
4718 printf("warning: pmap_remove_pages called with non-current pmap\n");
4722 rw_wlock(&pvh_global_lock);
4725 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4726 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4729 for (field = 0; field < _NPCM; field++) {
4730 inuse = ~pc->pc_map[field] & pc_freemask[field];
4731 while (inuse != 0) {
4733 bitmask = 1UL << bit;
4734 idx = field * 32 + bit;
4735 pv = &pc->pc_pventry[idx];
4738 pte = pmap_pde(pmap, pv->pv_va);
4740 if ((tpte & PG_PS) == 0) {
4741 pte = pmap_pte_quick(pmap, pv->pv_va);
4742 tpte = *pte & ~PG_PTE_PAT;
4747 "TPTE at %p IS ZERO @ VA %08x\n",
4753 * We cannot remove wired pages from a process' mapping at this time
4760 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4761 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4762 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4763 m, (uintmax_t)m->phys_addr,
4766 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4767 m < &vm_page_array[vm_page_array_size],
4768 ("pmap_remove_pages: bad tpte %#jx",
4774 * Update the vm_page_t clean/reference bits.
4776 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4777 if ((tpte & PG_PS) != 0) {
4778 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4785 PV_STAT(pv_entry_frees++);
4786 PV_STAT(pv_entry_spare++);
4788 pc->pc_map[field] |= bitmask;
4789 if ((tpte & PG_PS) != 0) {
4790 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4791 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4792 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4793 if (TAILQ_EMPTY(&pvh->pv_list)) {
4794 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4795 if (TAILQ_EMPTY(&mt->md.pv_list))
4796 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4798 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
4800 pmap->pm_stats.resident_count--;
4801 KASSERT(mpte->wire_count == NPTEPG,
4802 ("pmap_remove_pages: pte page wire count error"));
4803 mpte->wire_count = 0;
4804 pmap_add_delayed_free_list(mpte, &free, FALSE);
4807 pmap->pm_stats.resident_count--;
4808 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4809 if (TAILQ_EMPTY(&m->md.pv_list) &&
4810 (m->flags & PG_FICTITIOUS) == 0) {
4811 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4812 if (TAILQ_EMPTY(&pvh->pv_list))
4813 vm_page_aflag_clear(m, PGA_WRITEABLE);
4815 pmap_unuse_pt(pmap, pv->pv_va, &free);
4820 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4825 pmap_invalidate_all_int(pmap);
4826 rw_wunlock(&pvh_global_lock);
4828 vm_page_free_pages_toq(&free, true);
4834 * Return whether or not the specified physical page was modified
4835 * in any physical maps.
4838 __CONCAT(PMTYPE, is_modified)(vm_page_t m)
4842 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4843 ("pmap_is_modified: page %p is not managed", m));
4846 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4847 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4848 * is clear, no PTEs can have PG_M set.
4850 VM_OBJECT_ASSERT_WLOCKED(m->object);
4851 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4853 rw_wlock(&pvh_global_lock);
4854 rv = pmap_is_modified_pvh(&m->md) ||
4855 ((m->flags & PG_FICTITIOUS) == 0 &&
4856 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4857 rw_wunlock(&pvh_global_lock);
4862 * Returns TRUE if any of the given mappings were used to modify
4863 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4864 * mappings are supported.
4867 pmap_is_modified_pvh(struct md_page *pvh)
4874 rw_assert(&pvh_global_lock, RA_WLOCKED);
4877 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4880 pte = pmap_pte_quick(pmap, pv->pv_va);
4881 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4891 * pmap_is_prefaultable:
4893 * Return whether or not the specified virtual address is elgible
4897 __CONCAT(PMTYPE, is_prefaultable)(pmap_t pmap, vm_offset_t addr)
4904 pde = *pmap_pde(pmap, addr);
4905 if (pde != 0 && (pde & PG_PS) == 0)
4906 rv = pmap_pte_ufast(pmap, addr, pde) == 0;
4912 * pmap_is_referenced:
4914 * Return whether or not the specified physical page was referenced
4915 * in any physical maps.
4918 __CONCAT(PMTYPE, is_referenced)(vm_page_t m)
4922 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4923 ("pmap_is_referenced: page %p is not managed", m));
4924 rw_wlock(&pvh_global_lock);
4925 rv = pmap_is_referenced_pvh(&m->md) ||
4926 ((m->flags & PG_FICTITIOUS) == 0 &&
4927 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4928 rw_wunlock(&pvh_global_lock);
4933 * Returns TRUE if any of the given mappings were referenced and FALSE
4934 * otherwise. Both page and 4mpage mappings are supported.
4937 pmap_is_referenced_pvh(struct md_page *pvh)
4944 rw_assert(&pvh_global_lock, RA_WLOCKED);
4947 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4950 pte = pmap_pte_quick(pmap, pv->pv_va);
4951 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4961 * Clear the write and modified bits in each of the given page's mappings.
4964 __CONCAT(PMTYPE, remove_write)(vm_page_t m)
4966 struct md_page *pvh;
4967 pv_entry_t next_pv, pv;
4970 pt_entry_t oldpte, *pte;
4973 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4974 ("pmap_remove_write: page %p is not managed", m));
4977 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4978 * set by another thread while the object is locked. Thus,
4979 * if PGA_WRITEABLE is clear, no page table entries need updating.
4981 VM_OBJECT_ASSERT_WLOCKED(m->object);
4982 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4984 rw_wlock(&pvh_global_lock);
4986 if ((m->flags & PG_FICTITIOUS) != 0)
4987 goto small_mappings;
4988 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4989 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4993 pde = pmap_pde(pmap, va);
4994 if ((*pde & PG_RW) != 0)
4995 (void)pmap_demote_pde(pmap, pde, va);
4999 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5002 pde = pmap_pde(pmap, pv->pv_va);
5003 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
5004 " a 4mpage in page %p's pv list", m));
5005 pte = pmap_pte_quick(pmap, pv->pv_va);
5008 if ((oldpte & PG_RW) != 0) {
5010 * Regardless of whether a pte is 32 or 64 bits
5011 * in size, PG_RW and PG_M are among the least
5012 * significant 32 bits.
5014 if (!atomic_cmpset_int((u_int *)pte, oldpte,
5015 oldpte & ~(PG_RW | PG_M)))
5017 if ((oldpte & PG_M) != 0)
5019 pmap_invalidate_page_int(pmap, pv->pv_va);
5023 vm_page_aflag_clear(m, PGA_WRITEABLE);
5025 rw_wunlock(&pvh_global_lock);
5029 * pmap_ts_referenced:
5031 * Return a count of reference bits for a page, clearing those bits.
5032 * It is not necessary for every reference bit to be cleared, but it
5033 * is necessary that 0 only be returned when there are truly no
5034 * reference bits set.
5036 * As an optimization, update the page's dirty field if a modified bit is
5037 * found while counting reference bits. This opportunistic update can be
5038 * performed at low cost and can eliminate the need for some future calls
5039 * to pmap_is_modified(). However, since this function stops after
5040 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5041 * dirty pages. Those dirty pages will only be detected by a future call
5042 * to pmap_is_modified().
5045 __CONCAT(PMTYPE, ts_referenced)(vm_page_t m)
5047 struct md_page *pvh;
5055 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5056 ("pmap_ts_referenced: page %p is not managed", m));
5057 pa = VM_PAGE_TO_PHYS(m);
5058 pvh = pa_to_pvh(pa);
5059 rw_wlock(&pvh_global_lock);
5061 if ((m->flags & PG_FICTITIOUS) != 0 ||
5062 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5063 goto small_mappings;
5068 pde = pmap_pde(pmap, pv->pv_va);
5069 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5071 * Although "*pde" is mapping a 2/4MB page, because
5072 * this function is called at a 4KB page granularity,
5073 * we only update the 4KB page under test.
5077 if ((*pde & PG_A) != 0) {
5079 * Since this reference bit is shared by either 1024
5080 * or 512 4KB pages, it should not be cleared every
5081 * time it is tested. Apply a simple "hash" function
5082 * on the physical page number, the virtual superpage
5083 * number, and the pmap address to select one 4KB page
5084 * out of the 1024 or 512 on which testing the
5085 * reference bit will result in clearing that bit.
5086 * This function is designed to avoid the selection of
5087 * the same 4KB page for every 2- or 4MB page mapping.
5089 * On demotion, a mapping that hasn't been referenced
5090 * is simply destroyed. To avoid the possibility of a
5091 * subsequent page fault on a demoted wired mapping,
5092 * always leave its reference bit set. Moreover,
5093 * since the superpage is wired, the current state of
5094 * its reference bit won't affect page replacement.
5096 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
5097 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
5098 (*pde & PG_W) == 0) {
5099 atomic_clear_int((u_int *)pde, PG_A);
5100 pmap_invalidate_page_int(pmap, pv->pv_va);
5105 /* Rotate the PV list if it has more than one entry. */
5106 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5107 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5108 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5110 if (rtval >= PMAP_TS_REFERENCED_MAX)
5112 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5114 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5120 pde = pmap_pde(pmap, pv->pv_va);
5121 KASSERT((*pde & PG_PS) == 0,
5122 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
5124 pte = pmap_pte_quick(pmap, pv->pv_va);
5125 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5127 if ((*pte & PG_A) != 0) {
5128 atomic_clear_int((u_int *)pte, PG_A);
5129 pmap_invalidate_page_int(pmap, pv->pv_va);
5133 /* Rotate the PV list if it has more than one entry. */
5134 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5135 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5136 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5138 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
5139 PMAP_TS_REFERENCED_MAX);
5142 rw_wunlock(&pvh_global_lock);
5147 * Apply the given advice to the specified range of addresses within the
5148 * given pmap. Depending on the advice, clear the referenced and/or
5149 * modified flags in each mapping and set the mapped page's dirty field.
5152 __CONCAT(PMTYPE, advise)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
5155 pd_entry_t oldpde, *pde;
5157 vm_offset_t va, pdnxt;
5159 boolean_t anychanged, pv_lists_locked;
5161 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5163 if (pmap_is_current(pmap))
5164 pv_lists_locked = FALSE;
5166 pv_lists_locked = TRUE;
5168 rw_wlock(&pvh_global_lock);
5173 for (; sva < eva; sva = pdnxt) {
5174 pdnxt = (sva + NBPDR) & ~PDRMASK;
5177 pde = pmap_pde(pmap, sva);
5179 if ((oldpde & PG_V) == 0)
5181 else if ((oldpde & PG_PS) != 0) {
5182 if ((oldpde & PG_MANAGED) == 0)
5184 if (!pv_lists_locked) {
5185 pv_lists_locked = TRUE;
5186 if (!rw_try_wlock(&pvh_global_lock)) {
5188 pmap_invalidate_all_int(pmap);
5194 if (!pmap_demote_pde(pmap, pde, sva)) {
5196 * The large page mapping was destroyed.
5202 * Unless the page mappings are wired, remove the
5203 * mapping to a single page so that a subsequent
5204 * access may repromote. Since the underlying page
5205 * table page is fully populated, this removal never
5206 * frees a page table page.
5208 if ((oldpde & PG_W) == 0) {
5209 pte = pmap_pte_quick(pmap, sva);
5210 KASSERT((*pte & PG_V) != 0,
5211 ("pmap_advise: invalid PTE"));
5212 pmap_remove_pte(pmap, pte, sva, NULL);
5219 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
5221 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
5223 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5224 if (advice == MADV_DONTNEED) {
5226 * Future calls to pmap_is_modified()
5227 * can be avoided by making the page
5230 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
5233 atomic_clear_int((u_int *)pte, PG_M | PG_A);
5234 } else if ((*pte & PG_A) != 0)
5235 atomic_clear_int((u_int *)pte, PG_A);
5238 if ((*pte & PG_G) != 0) {
5246 pmap_invalidate_range_int(pmap, va, sva);
5251 pmap_invalidate_range_int(pmap, va, sva);
5254 pmap_invalidate_all_int(pmap);
5255 if (pv_lists_locked) {
5257 rw_wunlock(&pvh_global_lock);
5263 * Clear the modify bits on the specified physical page.
5266 __CONCAT(PMTYPE, clear_modify)(vm_page_t m)
5268 struct md_page *pvh;
5269 pv_entry_t next_pv, pv;
5271 pd_entry_t oldpde, *pde;
5272 pt_entry_t oldpte, *pte;
5275 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5276 ("pmap_clear_modify: page %p is not managed", m));
5277 VM_OBJECT_ASSERT_WLOCKED(m->object);
5278 KASSERT(!vm_page_xbusied(m),
5279 ("pmap_clear_modify: page %p is exclusive busied", m));
5282 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5283 * If the object containing the page is locked and the page is not
5284 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5286 if ((m->aflags & PGA_WRITEABLE) == 0)
5288 rw_wlock(&pvh_global_lock);
5290 if ((m->flags & PG_FICTITIOUS) != 0)
5291 goto small_mappings;
5292 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5293 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5297 pde = pmap_pde(pmap, va);
5299 if ((oldpde & PG_RW) != 0) {
5300 if (pmap_demote_pde(pmap, pde, va)) {
5301 if ((oldpde & PG_W) == 0) {
5303 * Write protect the mapping to a
5304 * single page so that a subsequent
5305 * write access may repromote.
5307 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5309 pte = pmap_pte_quick(pmap, va);
5311 if ((oldpte & PG_V) != 0) {
5313 * Regardless of whether a pte is 32 or 64 bits
5314 * in size, PG_RW and PG_M are among the least
5315 * significant 32 bits.
5317 while (!atomic_cmpset_int((u_int *)pte,
5319 oldpte & ~(PG_M | PG_RW)))
5322 pmap_invalidate_page_int(pmap,
5331 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5334 pde = pmap_pde(pmap, pv->pv_va);
5335 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5336 " a 4mpage in page %p's pv list", m));
5337 pte = pmap_pte_quick(pmap, pv->pv_va);
5338 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5340 * Regardless of whether a pte is 32 or 64 bits
5341 * in size, PG_M is among the least significant
5344 atomic_clear_int((u_int *)pte, PG_M);
5345 pmap_invalidate_page_int(pmap, pv->pv_va);
5350 rw_wunlock(&pvh_global_lock);
5354 * Miscellaneous support routines follow
5357 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5358 static __inline void
5359 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5364 * The cache mode bits are all in the low 32-bits of the
5365 * PTE, so we can just spin on updating the low 32-bits.
5368 opte = *(u_int *)pte;
5369 npte = opte & ~PG_PTE_CACHE;
5371 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5374 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5375 static __inline void
5376 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5381 * The cache mode bits are all in the low 32-bits of the
5382 * PDE, so we can just spin on updating the low 32-bits.
5385 opde = *(u_int *)pde;
5386 npde = opde & ~PG_PDE_CACHE;
5388 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5392 * Map a set of physical memory pages into the kernel virtual
5393 * address space. Return a pointer to where it is mapped. This
5394 * routine is intended to be used for mapping device memory,
5398 __CONCAT(PMTYPE, mapdev_attr)(vm_paddr_t pa, vm_size_t size, int mode)
5400 struct pmap_preinit_mapping *ppim;
5401 vm_offset_t va, offset;
5405 offset = pa & PAGE_MASK;
5406 size = round_page(offset + size);
5409 if (pa < PMAP_MAP_LOW && pa + size <= PMAP_MAP_LOW)
5410 va = pa + PMAP_MAP_LOW;
5411 else if (!pmap_initialized) {
5413 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5414 ppim = pmap_preinit_mapping + i;
5415 if (ppim->va == 0) {
5419 ppim->va = virtual_avail;
5420 virtual_avail += size;
5426 panic("%s: too many preinit mappings", __func__);
5429 * If we have a preinit mapping, re-use it.
5431 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5432 ppim = pmap_preinit_mapping + i;
5433 if (ppim->pa == pa && ppim->sz == size &&
5435 return ((void *)(ppim->va + offset));
5437 va = kva_alloc(size);
5439 panic("%s: Couldn't allocate KVA", __func__);
5441 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5442 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5443 pmap_invalidate_range_int(kernel_pmap, va, va + tmpsize);
5444 pmap_invalidate_cache_range(va, va + size);
5445 return ((void *)(va + offset));
5449 __CONCAT(PMTYPE, unmapdev)(vm_offset_t va, vm_size_t size)
5451 struct pmap_preinit_mapping *ppim;
5455 if (va >= PMAP_MAP_LOW && va <= KERNBASE && va + size <= KERNBASE)
5457 offset = va & PAGE_MASK;
5458 size = round_page(offset + size);
5459 va = trunc_page(va);
5460 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5461 ppim = pmap_preinit_mapping + i;
5462 if (ppim->va == va && ppim->sz == size) {
5463 if (pmap_initialized)
5469 if (va + size == virtual_avail)
5474 if (pmap_initialized)
5479 * Sets the memory attribute for the specified page.
5482 __CONCAT(PMTYPE, page_set_memattr)(vm_page_t m, vm_memattr_t ma)
5485 m->md.pat_mode = ma;
5486 if ((m->flags & PG_FICTITIOUS) != 0)
5490 * If "m" is a normal page, flush it from the cache.
5491 * See pmap_invalidate_cache_range().
5493 * First, try to find an existing mapping of the page by sf
5494 * buffer. sf_buf_invalidate_cache() modifies mapping and
5495 * flushes the cache.
5497 if (sf_buf_invalidate_cache(m))
5501 * If page is not mapped by sf buffer, but CPU does not
5502 * support self snoop, map the page transient and do
5503 * invalidation. In the worst case, whole cache is flushed by
5504 * pmap_invalidate_cache_range().
5506 if ((cpu_feature & CPUID_SS) == 0)
5511 __CONCAT(PMTYPE, flush_page)(vm_page_t m)
5513 pt_entry_t *cmap_pte2;
5515 vm_offset_t sva, eva;
5518 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5519 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5522 cmap_pte2 = pc->pc_cmap_pte2;
5523 mtx_lock(&pc->pc_cmap_lock);
5525 panic("pmap_flush_page: CMAP2 busy");
5526 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5527 PG_A | PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode,
5529 invlcaddr(pc->pc_cmap_addr2);
5530 sva = (vm_offset_t)pc->pc_cmap_addr2;
5531 eva = sva + PAGE_SIZE;
5534 * Use mfence or sfence despite the ordering implied by
5535 * mtx_{un,}lock() because clflush on non-Intel CPUs
5536 * and clflushopt are not guaranteed to be ordered by
5537 * any other instruction.
5541 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5543 for (; sva < eva; sva += cpu_clflush_line_size) {
5551 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5555 mtx_unlock(&pc->pc_cmap_lock);
5557 pmap_invalidate_cache();
5561 * Changes the specified virtual address range's memory type to that given by
5562 * the parameter "mode". The specified virtual address range must be
5563 * completely contained within either the kernel map.
5565 * Returns zero if the change completed successfully, and either EINVAL or
5566 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5567 * of the virtual address range was not mapped, and ENOMEM is returned if
5568 * there was insufficient memory available to complete the change.
5571 __CONCAT(PMTYPE, change_attr)(vm_offset_t va, vm_size_t size, int mode)
5573 vm_offset_t base, offset, tmpva;
5576 int cache_bits_pte, cache_bits_pde;
5579 base = trunc_page(va);
5580 offset = va & PAGE_MASK;
5581 size = round_page(offset + size);
5584 * Only supported on kernel virtual addresses above the recursive map.
5586 if (base < VM_MIN_KERNEL_ADDRESS)
5589 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
5590 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
5594 * Pages that aren't mapped aren't supported. Also break down
5595 * 2/4MB pages into 4KB pages if required.
5597 PMAP_LOCK(kernel_pmap);
5598 for (tmpva = base; tmpva < base + size; ) {
5599 pde = pmap_pde(kernel_pmap, tmpva);
5601 PMAP_UNLOCK(kernel_pmap);
5606 * If the current 2/4MB page already has
5607 * the required memory type, then we need not
5608 * demote this page. Just increment tmpva to
5609 * the next 2/4MB page frame.
5611 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5612 tmpva = trunc_4mpage(tmpva) + NBPDR;
5617 * If the current offset aligns with a 2/4MB
5618 * page frame and there is at least 2/4MB left
5619 * within the range, then we need not break
5620 * down this page into 4KB pages.
5622 if ((tmpva & PDRMASK) == 0 &&
5623 tmpva + PDRMASK < base + size) {
5627 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5628 PMAP_UNLOCK(kernel_pmap);
5632 pte = vtopte(tmpva);
5634 PMAP_UNLOCK(kernel_pmap);
5639 PMAP_UNLOCK(kernel_pmap);
5642 * Ok, all the pages exist, so run through them updating their
5643 * cache mode if required.
5645 for (tmpva = base; tmpva < base + size; ) {
5646 pde = pmap_pde(kernel_pmap, tmpva);
5648 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5649 pmap_pde_attr(pde, cache_bits_pde);
5652 tmpva = trunc_4mpage(tmpva) + NBPDR;
5654 pte = vtopte(tmpva);
5655 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5656 pmap_pte_attr(pte, cache_bits_pte);
5664 * Flush CPU caches to make sure any data isn't cached that
5665 * shouldn't be, etc.
5668 pmap_invalidate_range_int(kernel_pmap, base, tmpva);
5669 pmap_invalidate_cache_range(base, tmpva);
5675 * perform the pmap work for mincore
5678 __CONCAT(PMTYPE, mincore)(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5687 pde = *pmap_pde(pmap, addr);
5689 if ((pde & PG_PS) != 0) {
5691 /* Compute the physical address of the 4KB page. */
5692 pa = ((pde & PG_PS_FRAME) | (addr & PDRMASK)) &
5694 val = MINCORE_SUPER;
5696 pte = pmap_pte_ufast(pmap, addr, pde);
5697 pa = pte & PG_FRAME;
5705 if ((pte & PG_V) != 0) {
5706 val |= MINCORE_INCORE;
5707 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5708 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5709 if ((pte & PG_A) != 0)
5710 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5712 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5713 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5714 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5715 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5716 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5719 PA_UNLOCK_COND(*locked_pa);
5725 __CONCAT(PMTYPE, activate)(struct thread *td)
5727 pmap_t pmap, oldpmap;
5732 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5733 oldpmap = PCPU_GET(curpmap);
5734 cpuid = PCPU_GET(cpuid);
5736 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5737 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5739 CPU_CLR(cpuid, &oldpmap->pm_active);
5740 CPU_SET(cpuid, &pmap->pm_active);
5742 #ifdef PMAP_PAE_COMP
5743 cr3 = vtophys(pmap->pm_pdpt);
5745 cr3 = vtophys(pmap->pm_pdir);
5748 * pmap_activate is for the current thread on the current cpu
5750 td->td_pcb->pcb_cr3 = cr3;
5751 PCPU_SET(curpmap, pmap);
5756 __CONCAT(PMTYPE, activate_boot)(pmap_t pmap)
5760 cpuid = PCPU_GET(cpuid);
5762 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5764 CPU_SET(cpuid, &pmap->pm_active);
5766 PCPU_SET(curpmap, pmap);
5770 * Increase the starting virtual address of the given mapping if a
5771 * different alignment might result in more superpage mappings.
5774 __CONCAT(PMTYPE, align_superpage)(vm_object_t object, vm_ooffset_t offset,
5775 vm_offset_t *addr, vm_size_t size)
5777 vm_offset_t superpage_offset;
5781 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5782 offset += ptoa(object->pg_color);
5783 superpage_offset = offset & PDRMASK;
5784 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5785 (*addr & PDRMASK) == superpage_offset)
5787 if ((*addr & PDRMASK) < superpage_offset)
5788 *addr = (*addr & ~PDRMASK) + superpage_offset;
5790 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5794 __CONCAT(PMTYPE, quick_enter_page)(vm_page_t m)
5800 qaddr = PCPU_GET(qmap_addr);
5801 pte = vtopte(qaddr);
5804 ("pmap_quick_enter_page: PTE busy %#jx", (uintmax_t)*pte));
5805 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5806 pmap_cache_bits(kernel_pmap, pmap_page_get_memattr(m), 0);
5813 __CONCAT(PMTYPE, quick_remove_page)(vm_offset_t addr)
5818 qaddr = PCPU_GET(qmap_addr);
5819 pte = vtopte(qaddr);
5821 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5822 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5828 static vmem_t *pmap_trm_arena;
5829 static vmem_addr_t pmap_trm_arena_last = PMAP_TRM_MIN_ADDRESS;
5830 static int trm_guard = PAGE_SIZE;
5833 pmap_trm_import(void *unused __unused, vmem_size_t size, int flags,
5837 vmem_addr_t af, addr, prev_addr;
5838 pt_entry_t *trm_pte;
5840 prev_addr = atomic_load_long(&pmap_trm_arena_last);
5841 size = round_page(size) + trm_guard;
5843 if (prev_addr + size < prev_addr || prev_addr + size < size ||
5844 prev_addr + size > PMAP_TRM_MAX_ADDRESS)
5846 addr = prev_addr + size;
5847 if (atomic_fcmpset_int(&pmap_trm_arena_last, &prev_addr, addr))
5850 prev_addr += trm_guard;
5851 trm_pte = PTmap + atop(prev_addr);
5852 for (af = prev_addr; af < addr; af += PAGE_SIZE) {
5853 m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5854 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
5855 pte_store(&trm_pte[atop(af - prev_addr)], VM_PAGE_TO_PHYS(m) |
5856 PG_M | PG_A | PG_RW | PG_V | pgeflag |
5857 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE));
5868 TUNABLE_INT_FETCH("machdep.trm_guard", &trm_guard);
5869 if ((trm_guard & PAGE_MASK) != 0)
5871 pmap_trm_arena = vmem_create("i386trampoline", 0, 0, 1, 0, M_WAITOK);
5872 vmem_set_import(pmap_trm_arena, pmap_trm_import, NULL, NULL, PAGE_SIZE);
5873 pd_m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5874 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK | VM_ALLOC_ZERO);
5875 if ((pd_m->flags & PG_ZERO) == 0)
5876 pmap_zero_page(pd_m);
5877 PTD[TRPTDI] = VM_PAGE_TO_PHYS(pd_m) | PG_M | PG_A | PG_RW | PG_V |
5878 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, TRUE);
5882 __CONCAT(PMTYPE, trm_alloc)(size_t size, int flags)
5887 MPASS((flags & ~(M_WAITOK | M_NOWAIT | M_ZERO)) == 0);
5888 error = vmem_xalloc(pmap_trm_arena, roundup2(size, 4), sizeof(int),
5889 0, 0, VMEM_ADDR_MIN, VMEM_ADDR_MAX, flags | M_FIRSTFIT, &res);
5892 if ((flags & M_ZERO) != 0)
5893 bzero((void *)res, size);
5894 return ((void *)res);
5898 __CONCAT(PMTYPE, trm_free)(void *addr, size_t size)
5901 vmem_free(pmap_trm_arena, (uintptr_t)addr, roundup2(size, 4));
5905 __CONCAT(PMTYPE, ksetrw)(vm_offset_t va)
5908 *vtopte(va) |= PG_RW;
5912 __CONCAT(PMTYPE, remap_lowptdi)(bool enable)
5915 PTD[KPTDI] = enable ? PTD[LOWPTDI] : 0;
5920 __CONCAT(PMTYPE, get_map_low)(void)
5923 return (PMAP_MAP_LOW);
5927 __CONCAT(PMTYPE, get_vm_maxuser_address)(void)
5930 return (VM_MAXUSER_ADDRESS);
5934 __CONCAT(PMTYPE, pg_frame)(vm_paddr_t pa)
5937 return (pa & PG_FRAME);
5941 __CONCAT(PMTYPE, sf_buf_map)(struct sf_buf *sf)
5943 pt_entry_t opte, *ptep;
5946 * Update the sf_buf's virtual-to-physical mapping, flushing the
5947 * virtual address from the TLB. Since the reference count for
5948 * the sf_buf's old mapping was zero, that mapping is not
5949 * currently in use. Consequently, there is no need to exchange
5950 * the old and new PTEs atomically, even under PAE.
5952 ptep = vtopte(sf->kva);
5954 *ptep = VM_PAGE_TO_PHYS(sf->m) | PG_RW | PG_V |
5955 pmap_cache_bits(kernel_pmap, sf->m->md.pat_mode, 0);
5958 * Avoid unnecessary TLB invalidations: If the sf_buf's old
5959 * virtual-to-physical mapping was not used, then any processor
5960 * that has invalidated the sf_buf's virtual address from its TLB
5961 * since the last used mapping need not invalidate again.
5964 if ((opte & (PG_V | PG_A)) == (PG_V | PG_A))
5965 CPU_ZERO(&sf->cpumask);
5967 if ((opte & (PG_V | PG_A)) == (PG_V | PG_A))
5968 pmap_invalidate_page_int(kernel_pmap, sf->kva);
5973 __CONCAT(PMTYPE, cp_slow0_map)(vm_offset_t kaddr, int plen, vm_page_t *ma)
5978 for (i = 0, pte = vtopte(kaddr); i < plen; i++, pte++) {
5979 *pte = PG_V | PG_RW | PG_A | PG_M | VM_PAGE_TO_PHYS(ma[i]) |
5980 pmap_cache_bits(kernel_pmap, pmap_page_get_memattr(ma[i]),
5982 invlpg(kaddr + ptoa(i));
5987 __CONCAT(PMTYPE, get_kcr3)(void)
5990 #ifdef PMAP_PAE_COMP
5991 return ((u_int)IdlePDPT);
5993 return ((u_int)IdlePTD);
5998 __CONCAT(PMTYPE, get_cr3)(pmap_t pmap)
6001 #ifdef PMAP_PAE_COMP
6002 return ((u_int)vtophys(pmap->pm_pdpt));
6004 return ((u_int)vtophys(pmap->pm_pdir));
6009 __CONCAT(PMTYPE, cmap3)(vm_paddr_t pa, u_int pte_bits)
6014 *pte = pa | pte_bits;
6020 __CONCAT(PMTYPE, basemem_setup)(u_int basemem)
6026 * Map pages between basemem and ISA_HOLE_START, if any, r/w into
6027 * the vm86 page table so that vm86 can scribble on them using
6028 * the vm86 map too. XXX: why 2 ways for this and only 1 way for
6029 * page 0, at least as initialized here?
6031 pte = (pt_entry_t *)vm86paddr;
6032 for (i = basemem / 4; i < 160; i++)
6033 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
6036 struct bios16_pmap_handle {
6039 pt_entry_t orig_ptd;
6043 __CONCAT(PMTYPE, bios16_enter)(void)
6045 struct bios16_pmap_handle *h;
6048 * no page table, so create one and install it.
6050 h = malloc(sizeof(struct bios16_pmap_handle), M_TEMP, M_WAITOK);
6051 h->pte = (pt_entry_t *)malloc(PAGE_SIZE, M_TEMP, M_WAITOK);
6053 *h->pte = vm86phystk | PG_RW | PG_V;
6054 h->orig_ptd = *h->ptd;
6055 *h->ptd = vtophys(h->pte) | PG_RW | PG_V;
6056 pmap_invalidate_all_int(kernel_pmap); /* XXX insurance for now */
6061 __CONCAT(PMTYPE, bios16_leave)(void *arg)
6063 struct bios16_pmap_handle *h;
6066 *h->ptd = h->orig_ptd; /* remove page table */
6068 * XXX only needs to be invlpg(0) but that doesn't work on the 386
6070 pmap_invalidate_all_int(kernel_pmap);
6071 free(h->pte, M_TEMP); /* ... and free it */
6075 .pm_##a = __CONCAT(PMTYPE, a),
6077 struct pmap_methods __CONCAT(PMTYPE, methods) = {
6081 PMM(align_superpage)
6082 PMM(quick_enter_page)
6083 PMM(quick_remove_page)
6087 PMM(get_vm_maxuser_address)
6100 PMM(is_valid_memattr)
6119 PMM(kenter_temporary)
6122 PMM(page_exists_quick)
6123 PMM(page_wired_mappings)
6127 PMM(is_prefaultable)
6133 PMM(page_set_memattr)
6135 PMM(extract_and_hold)
6146 PMM(invalidate_page)
6147 PMM(invalidate_range)
6149 PMM(invalidate_cache)