2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
50 * Copyright (c) 2018 The FreeBSD Foundation
51 * All rights reserved.
53 * This software was developed for the FreeBSD Project by Jake Burkholder,
54 * Safeport Network Services, and Network Associates Laboratories, the
55 * Security Research Division of Network Associates, Inc. under
56 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
57 * CHATS research program.
59 * Portions of this software were developed by
60 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
61 * the FreeBSD Foundation.
63 * Redistribution and use in source and binary forms, with or without
64 * modification, are permitted provided that the following conditions
66 * 1. Redistributions of source code must retain the above copyright
67 * notice, this list of conditions and the following disclaimer.
68 * 2. Redistributions in binary form must reproduce the above copyright
69 * notice, this list of conditions and the following disclaimer in the
70 * documentation and/or other materials provided with the distribution.
72 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
73 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
75 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
78 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
79 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
80 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
81 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
85 #include <sys/cdefs.h>
86 __FBSDID("$FreeBSD$");
89 * Manages physical address maps.
91 * Since the information managed by this module is
92 * also stored by the logical address mapping module,
93 * this module may throw away valid virtual-to-physical
94 * mappings at almost any time. However, invalidations
95 * of virtual-to-physical mappings must be done as
98 * In order to cope with hardware architectures which
99 * make virtual-to-physical map invalidates expensive,
100 * this module may delay invalidate or reduced protection
101 * operations until such time as they are actually
102 * necessary. This module is given full information as
103 * to which processors are currently using which maps,
104 * and to when physical maps must be made correct.
107 #include "opt_apic.h"
109 #include "opt_pmap.h"
113 #include <sys/param.h>
114 #include <sys/systm.h>
115 #include <sys/kernel.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/proc.h>
123 #include <sys/rwlock.h>
124 #include <sys/sf_buf.h>
126 #include <sys/vmmeter.h>
127 #include <sys/sched.h>
128 #include <sys/sysctl.h>
130 #include <sys/vmem.h>
133 #include <vm/vm_param.h>
134 #include <vm/vm_kern.h>
135 #include <vm/vm_page.h>
136 #include <vm/vm_map.h>
137 #include <vm/vm_object.h>
138 #include <vm/vm_extern.h>
139 #include <vm/vm_pageout.h>
140 #include <vm/vm_pager.h>
141 #include <vm/vm_phys.h>
142 #include <vm/vm_radix.h>
143 #include <vm/vm_reserv.h>
148 #include <machine/intr_machdep.h>
149 #include <x86/apicvar.h>
151 #include <x86/ifunc.h>
152 #include <machine/bootinfo.h>
153 #include <machine/cpu.h>
154 #include <machine/cputypes.h>
155 #include <machine/md_var.h>
156 #include <machine/pcb.h>
157 #include <machine/specialreg.h>
159 #include <machine/smp.h>
162 #ifndef PMAP_SHPGPERPROC
163 #define PMAP_SHPGPERPROC 200
166 #if !defined(DIAGNOSTIC)
167 #ifdef __GNUC_GNU_INLINE__
168 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
170 #define PMAP_INLINE extern inline
177 #define PV_STAT(x) do { x ; } while (0)
179 #define PV_STAT(x) do { } while (0)
182 #define pa_index(pa) ((pa) >> PDRSHIFT)
183 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
186 * Get PDEs and PTEs for user/kernel address space
188 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
189 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
191 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
192 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
193 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
194 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
195 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
197 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
198 atomic_clear_int((u_int *)(pte), PG_W))
199 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
201 struct pmap kernel_pmap_store;
203 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
204 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
205 static int pgeflag = 0; /* PG_G or-in */
206 static int pseflag = 0; /* PG_PS or-in */
208 static int nkpt = NKPT;
209 vm_offset_t kernel_vm_end = /* 0 + */ NKPT * NBPDR;
211 #if defined(PAE) || defined(PAE_TABLES)
213 static uma_zone_t pdptzone;
216 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
218 static int pat_works = 1;
219 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 0,
220 "Is page attribute table fully functional?");
222 static int pg_ps_enabled = 1;
223 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
224 &pg_ps_enabled, 0, "Are large page mappings enabled?");
226 #define PAT_INDEX_SIZE 8
227 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
230 * pmap_mapdev support pre initialization (i.e. console)
232 #define PMAP_PREINIT_MAPPING_COUNT 8
233 static struct pmap_preinit_mapping {
238 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
239 static int pmap_initialized;
241 static struct rwlock_padalign pvh_global_lock;
244 * Data for the pv entry allocation mechanism
246 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
247 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
248 static struct md_page *pv_table;
249 static int shpgperproc = PMAP_SHPGPERPROC;
251 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
252 int pv_maxchunks; /* How many chunks we have KVA for */
253 vm_offset_t pv_vafree; /* freelist stored in the PTE */
256 * All those kernel PT submaps that BSD is so fond of
259 static pd_entry_t *KPTD;
266 static caddr_t crashdumpmap;
268 static pt_entry_t *PMAP1 = NULL, *PMAP2, *PMAP3;
269 static pt_entry_t *PADDR1 = NULL, *PADDR2, *PADDR3;
271 static int PMAP1cpu, PMAP3cpu;
272 static int PMAP1changedcpu;
273 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
275 "Number of times pmap_pte_quick changed CPU with same PMAP1");
277 static int PMAP1changed;
278 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
280 "Number of times pmap_pte_quick changed PMAP1");
281 static int PMAP1unchanged;
282 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
284 "Number of times pmap_pte_quick didn't change PMAP1");
285 static struct mtx PMAP2mutex;
290 * Internal flags for pmap_enter()'s helper functions.
292 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
293 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
295 static void free_pv_chunk(struct pv_chunk *pc);
296 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
297 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
298 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
299 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
301 #if VM_NRESERVLEVEL > 0
302 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
304 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
305 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
307 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
309 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
310 static bool pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
312 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
313 u_int flags, vm_page_t m);
314 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
315 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
316 static void pmap_flush_page(vm_page_t m);
317 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
318 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
320 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
322 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
324 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
325 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
326 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
327 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
328 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
329 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
330 #if VM_NRESERVLEVEL > 0
331 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
333 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
335 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
336 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
337 struct spglist *free);
338 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
339 struct spglist *free);
340 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
341 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
342 struct spglist *free);
343 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
344 struct spglist *free);
345 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
347 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
348 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
350 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
352 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
354 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
356 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
357 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
358 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
359 static void pmap_pte_release(pt_entry_t *pte);
360 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
361 #if defined(PAE) || defined(PAE_TABLES)
362 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain,
363 uint8_t *flags, int wait);
365 static void pmap_init_trm(void);
367 static __inline void pagezero(void *page);
369 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
370 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
372 void pmap_cold(void);
374 u_long physfree; /* phys addr of next free page */
375 u_long vm86phystk; /* PA of vm86/bios stack */
376 u_long vm86paddr; /* address of vm86 region */
377 int vm86pa; /* phys addr of vm86 region */
378 u_long KERNend; /* phys addr end of kernel (just after bss) */
379 pd_entry_t *IdlePTD; /* phys addr of kernel PTD */
380 #if defined(PAE) || defined(PAE_TABLES)
381 pdpt_entry_t *IdlePDPT; /* phys addr of kernel PDPT */
383 pt_entry_t *KPTmap; /* address of kernel page tables */
384 u_long KPTphys; /* phys addr of kernel page tables */
385 extern u_long tramp_idleptd;
388 allocpages(u_int cnt, u_long *physfree)
393 *physfree += PAGE_SIZE * cnt;
394 bzero((void *)res, PAGE_SIZE * cnt);
399 pmap_cold_map(u_long pa, u_long va, u_long cnt)
403 for (pt = (pt_entry_t *)KPTphys + atop(va); cnt > 0;
404 cnt--, pt++, va += PAGE_SIZE, pa += PAGE_SIZE)
405 *pt = pa | PG_V | PG_RW | PG_A | PG_M;
409 pmap_cold_mapident(u_long pa, u_long cnt)
412 pmap_cold_map(pa, pa, cnt);
415 _Static_assert(2 * NBPDR == KERNBASE, "Broken double-map of zero PTD");
418 * Called from locore.s before paging is enabled. Sets up the first
419 * kernel page table. Since kernel is mapped with PA == VA, this code
420 * does not require relocations.
429 physfree = (u_long)&_end;
430 if (bootinfo.bi_esymtab != 0)
431 physfree = bootinfo.bi_esymtab;
432 if (bootinfo.bi_kernend != 0)
433 physfree = bootinfo.bi_kernend;
434 physfree = roundup2(physfree, NBPDR);
437 /* Allocate Kernel Page Tables */
438 KPTphys = allocpages(NKPT, &physfree);
439 KPTmap = (pt_entry_t *)KPTphys;
441 /* Allocate Page Table Directory */
442 #if defined(PAE) || defined(PAE_TABLES)
443 /* XXX only need 32 bytes (easier for now) */
444 IdlePDPT = (pdpt_entry_t *)allocpages(1, &physfree);
446 IdlePTD = (pd_entry_t *)allocpages(NPGPTD, &physfree);
449 * Allocate KSTACK. Leave a guard page between IdlePTD and
450 * proc0kstack, to control stack overflow for thread0 and
451 * prevent corruption of the page table. We leak the guard
452 * physical memory due to 1:1 mappings.
454 allocpages(1, &physfree);
455 proc0kstack = allocpages(TD0_KSTACK_PAGES, &physfree);
457 /* vm86/bios stack */
458 vm86phystk = allocpages(1, &physfree);
460 /* pgtable + ext + IOPAGES */
461 vm86paddr = vm86pa = allocpages(3, &physfree);
463 /* Install page tables into PTD. Page table page 1 is wasted. */
464 for (a = 0; a < NKPT; a++)
465 IdlePTD[a] = (KPTphys + ptoa(a)) | PG_V | PG_RW | PG_A | PG_M;
467 #if defined(PAE) || defined(PAE_TABLES)
468 /* PAE install PTD pointers into PDPT */
469 for (a = 0; a < NPGPTD; a++)
470 IdlePDPT[a] = ((u_int)IdlePTD + ptoa(a)) | PG_V;
474 * Install recursive mapping for kernel page tables into
477 for (a = 0; a < NPGPTD; a++)
478 IdlePTD[PTDPTDI + a] = ((u_int)IdlePTD + ptoa(a)) | PG_V |
482 * Initialize page table pages mapping physical address zero
483 * through the (physical) end of the kernel. Many of these
484 * pages must be reserved, and we reserve them all and map
485 * them linearly for convenience. We do this even if we've
486 * enabled PSE above; we'll just switch the corresponding
487 * kernel PDEs before we turn on paging.
489 * This and all other page table entries allow read and write
490 * access for various reasons. Kernel mappings never have any
491 * access restrictions.
493 pmap_cold_mapident(0, atop(NBPDR));
494 pmap_cold_map(0, NBPDR, atop(NBPDR));
495 pmap_cold_mapident(KERNBASE, atop(KERNend - KERNBASE));
497 /* Map page table directory */
498 #if defined(PAE) || defined(PAE_TABLES)
499 pmap_cold_mapident((u_long)IdlePDPT, 1);
501 pmap_cold_mapident((u_long)IdlePTD, NPGPTD);
503 /* Map early KPTmap. It is really pmap_cold_mapident. */
504 pmap_cold_map(KPTphys, (u_long)KPTmap, NKPT);
506 /* Map proc0kstack */
507 pmap_cold_mapident(proc0kstack, TD0_KSTACK_PAGES);
508 /* ISA hole already mapped */
510 pmap_cold_mapident(vm86phystk, 1);
511 pmap_cold_mapident(vm86pa, 3);
513 /* Map page 0 into the vm86 page table */
514 *(pt_entry_t *)vm86pa = 0 | PG_RW | PG_U | PG_A | PG_M | PG_V;
516 /* ...likewise for the ISA hole for vm86 */
517 for (pt = (pt_entry_t *)vm86pa + atop(ISA_HOLE_START), a = 0;
518 a < atop(ISA_HOLE_LENGTH); a++, pt++)
519 *pt = (ISA_HOLE_START + ptoa(a)) | PG_RW | PG_U | PG_A |
522 /* Enable PSE, PGE, VME, and PAE if configured. */
524 if ((cpu_feature & CPUID_PSE) != 0) {
528 * Superpage mapping of the kernel text. Existing 4k
529 * page table pages are wasted.
531 for (a = KERNBASE; a < KERNend; a += NBPDR)
532 IdlePTD[a >> PDRSHIFT] = a | PG_PS | PG_A | PG_M |
535 if ((cpu_feature & CPUID_PGE) != 0) {
539 ncr4 |= (cpu_feature & CPUID_VME) != 0 ? CR4_VME : 0;
540 #if defined(PAE) || defined(PAE_TABLES)
544 load_cr4(rcr4() | ncr4);
546 /* Now enable paging */
547 #if defined(PAE) || defined(PAE_TABLES)
548 cr3 = (u_int)IdlePDPT;
550 cr3 = (u_int)IdlePTD;
554 load_cr0(rcr0() | CR0_PG);
557 * Now running relocated at KERNBASE where the system is
562 * Remove the lowest part of the double mapping of low memory
563 * to get some null pointer checks.
566 load_cr3(cr3); /* invalidate TLB */
570 * Bootstrap the system enough to run with virtual memory.
572 * On the i386 this is called after pmap_cold() created initial
573 * kernel page table and enabled paging, and just syncs the pmap
574 * module with what has already been done.
577 pmap_bootstrap(vm_paddr_t firstaddr)
580 pt_entry_t *pte, *unused;
585 res = atop(firstaddr - (vm_paddr_t)KERNLOAD);
588 * Add a physical memory segment (vm_phys_seg) corresponding to the
589 * preallocated kernel page table pages so that vm_page structures
590 * representing these pages will be created. The vm_page structures
591 * are required for promotion of the corresponding kernel virtual
592 * addresses to superpage mappings.
594 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
597 * Initialize the first available kernel virtual address.
598 * However, using "firstaddr" may waste a few pages of the
599 * kernel virtual address space, because pmap_cold() may not
600 * have mapped every physical page that it allocated.
601 * Preferably, pmap_cold() would provide a first unused
602 * virtual address in addition to "firstaddr".
604 virtual_avail = (vm_offset_t)firstaddr;
605 virtual_end = VM_MAX_KERNEL_ADDRESS;
608 * Initialize the kernel pmap (which is statically allocated).
609 * Count bootstrap data as being resident in case any of this data is
610 * later unmapped (using pmap_remove()) and freed.
612 PMAP_LOCK_INIT(kernel_pmap);
613 kernel_pmap->pm_pdir = IdlePTD;
614 #if defined(PAE) || defined(PAE_TABLES)
615 kernel_pmap->pm_pdpt = IdlePDPT;
617 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
618 kernel_pmap->pm_stats.resident_count = res;
619 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
622 * Initialize the global pv list lock.
624 rw_init(&pvh_global_lock, "pmap pv global");
627 * Reserve some special page table entries/VA space for temporary
630 #define SYSMAP(c, p, v, n) \
631 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
638 * Initialize temporary map objects on the current CPU for use
640 * CMAP1/CMAP2 are used for zeroing and copying pages.
641 * CMAP3 is used for the boot-time memory test.
644 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
645 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1)
646 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1)
647 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1)
649 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
654 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
657 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
659 SYSMAP(caddr_t, unused, ptvmmap, 1)
662 * msgbufp is used to map the system message buffer.
664 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
667 * KPTmap is used by pmap_kextract().
669 * KPTmap is first initialized by pmap_cold(). However, that initial
670 * KPTmap can only support NKPT page table pages. Here, a larger
671 * KPTmap is created that can support KVA_PAGES page table pages.
673 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
675 for (i = 0; i < NKPT; i++)
676 KPTD[i] = (KPTphys + ptoa(i)) | PG_RW | PG_V;
679 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
682 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
683 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
684 SYSMAP(pt_entry_t *, PMAP3, PADDR3, 1)
686 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
691 * Initialize the PAT MSR if present.
692 * pmap_init_pat() clears and sets CR4_PGE, which, as a
693 * side-effect, invalidates stale PG_G TLB entries that might
694 * have been created in our pre-boot environment. We assume
695 * that PAT support implies PGE and in reverse, PGE presence
696 * comes with PAT. Both features were added for Pentium Pro.
702 pmap_init_reserved_pages(void)
710 mtx_init(&pc->pc_copyout_mlock, "cpmlk", NULL, MTX_DEF |
712 pc->pc_copyout_maddr = kva_alloc(ptoa(2));
713 if (pc->pc_copyout_maddr == 0)
714 panic("unable to allocate non-sleepable copyout KVA");
715 sx_init(&pc->pc_copyout_slock, "cpslk");
716 pc->pc_copyout_saddr = kva_alloc(ptoa(2));
717 if (pc->pc_copyout_saddr == 0)
718 panic("unable to allocate sleepable copyout KVA");
719 pc->pc_pmap_eh_va = kva_alloc(ptoa(1));
720 if (pc->pc_pmap_eh_va == 0)
721 panic("unable to allocate pmap_extract_and_hold KVA");
722 pc->pc_pmap_eh_ptep = (char *)vtopte(pc->pc_pmap_eh_va);
725 * Skip if the mappings have already been initialized,
726 * i.e. this is the BSP.
728 if (pc->pc_cmap_addr1 != 0)
731 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
732 pages = kva_alloc(PAGE_SIZE * 3);
734 panic("unable to allocate CMAP KVA");
735 pc->pc_cmap_pte1 = vtopte(pages);
736 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE);
737 pc->pc_cmap_addr1 = (caddr_t)pages;
738 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE);
739 pc->pc_qmap_addr = pages + ptoa(2);
743 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
751 int pat_table[PAT_INDEX_SIZE];
756 /* Set default PAT index table. */
757 for (i = 0; i < PAT_INDEX_SIZE; i++)
759 pat_table[PAT_WRITE_BACK] = 0;
760 pat_table[PAT_WRITE_THROUGH] = 1;
761 pat_table[PAT_UNCACHEABLE] = 3;
762 pat_table[PAT_WRITE_COMBINING] = 3;
763 pat_table[PAT_WRITE_PROTECTED] = 3;
764 pat_table[PAT_UNCACHED] = 3;
767 * Bail if this CPU doesn't implement PAT.
768 * We assume that PAT support implies PGE.
770 if ((cpu_feature & CPUID_PAT) == 0) {
771 for (i = 0; i < PAT_INDEX_SIZE; i++)
772 pat_index[i] = pat_table[i];
778 * Due to some Intel errata, we can only safely use the lower 4
781 * Intel Pentium III Processor Specification Update
782 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
785 * Intel Pentium IV Processor Specification Update
786 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
788 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
789 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
792 /* Initialize default PAT entries. */
793 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
794 PAT_VALUE(1, PAT_WRITE_THROUGH) |
795 PAT_VALUE(2, PAT_UNCACHED) |
796 PAT_VALUE(3, PAT_UNCACHEABLE) |
797 PAT_VALUE(4, PAT_WRITE_BACK) |
798 PAT_VALUE(5, PAT_WRITE_THROUGH) |
799 PAT_VALUE(6, PAT_UNCACHED) |
800 PAT_VALUE(7, PAT_UNCACHEABLE);
804 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
805 * Program 5 and 6 as WP and WC.
806 * Leave 4 and 7 as WB and UC.
808 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
809 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
810 PAT_VALUE(6, PAT_WRITE_COMBINING);
811 pat_table[PAT_UNCACHED] = 2;
812 pat_table[PAT_WRITE_PROTECTED] = 5;
813 pat_table[PAT_WRITE_COMBINING] = 6;
816 * Just replace PAT Index 2 with WC instead of UC-.
818 pat_msr &= ~PAT_MASK(2);
819 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
820 pat_table[PAT_WRITE_COMBINING] = 2;
825 load_cr4(cr4 & ~CR4_PGE);
827 /* Disable caches (CD = 1, NW = 0). */
829 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
831 /* Flushes caches and TLBs. */
835 /* Update PAT and index table. */
836 wrmsr(MSR_PAT, pat_msr);
837 for (i = 0; i < PAT_INDEX_SIZE; i++)
838 pat_index[i] = pat_table[i];
840 /* Flush caches and TLBs again. */
844 /* Restore caches and PGE. */
850 * Initialize a vm_page's machine-dependent fields.
853 pmap_page_init(vm_page_t m)
856 TAILQ_INIT(&m->md.pv_list);
857 m->md.pat_mode = PAT_WRITE_BACK;
860 #if defined(PAE) || defined(PAE_TABLES)
862 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain, uint8_t *flags,
866 /* Inform UMA that this allocator uses kernel_map/object. */
867 *flags = UMA_SLAB_KERNEL;
868 return ((void *)kmem_alloc_contig_domainset(DOMAINSET_FIXED(domain),
869 bytes, wait, 0x0ULL, 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
874 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
876 * - Must deal with pages in order to ensure that none of the PG_* bits
877 * are ever set, PG_V in particular.
878 * - Assumes we can write to ptes without pte_store() atomic ops, even
879 * on PAE systems. This should be ok.
880 * - Assumes nothing will ever test these addresses for 0 to indicate
881 * no mapping instead of correctly checking PG_V.
882 * - Assumes a vm_offset_t will fit in a pte (true for i386).
883 * Because PG_V is never set, there can be no mappings to invalidate.
886 pmap_ptelist_alloc(vm_offset_t *head)
893 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
897 panic("pmap_ptelist_alloc: va with PG_V set!");
903 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
908 panic("pmap_ptelist_free: freeing va with PG_V set!");
910 *pte = *head; /* virtual! PG_V is 0 though */
915 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
921 for (i = npages - 1; i >= 0; i--) {
922 va = (vm_offset_t)base + i * PAGE_SIZE;
923 pmap_ptelist_free(head, va);
929 * Initialize the pmap module.
930 * Called by vm_init, to initialize any structures that the pmap
931 * system needs to map virtual memory.
936 struct pmap_preinit_mapping *ppim;
942 * Initialize the vm page array entries for the kernel pmap's
945 PMAP_LOCK(kernel_pmap);
946 for (i = 0; i < NKPT; i++) {
947 mpte = PHYS_TO_VM_PAGE(KPTphys + ptoa(i));
948 KASSERT(mpte >= vm_page_array &&
949 mpte < &vm_page_array[vm_page_array_size],
950 ("pmap_init: page table page is out of range"));
951 mpte->pindex = i + KPTDI;
952 mpte->phys_addr = KPTphys + ptoa(i);
953 mpte->wire_count = 1;
955 KERNBASE <= i << PDRSHIFT && i << PDRSHIFT < KERNend &&
956 pmap_insert_pt_page(kernel_pmap, mpte))
957 panic("pmap_init: pmap_insert_pt_page failed");
959 PMAP_UNLOCK(kernel_pmap);
963 * Initialize the address space (zone) for the pv entries. Set a
964 * high water mark so that the system can recover from excessive
965 * numbers of pv entries.
967 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
968 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
969 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
970 pv_entry_max = roundup(pv_entry_max, _NPCPV);
971 pv_entry_high_water = 9 * (pv_entry_max / 10);
974 * If the kernel is running on a virtual machine, then it must assume
975 * that MCA is enabled by the hypervisor. Moreover, the kernel must
976 * be prepared for the hypervisor changing the vendor and family that
977 * are reported by CPUID. Consequently, the workaround for AMD Family
978 * 10h Erratum 383 is enabled if the processor's feature set does not
979 * include at least one feature that is only supported by older Intel
980 * or newer AMD processors.
982 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
983 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
984 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
986 workaround_erratum383 = 1;
989 * Are large page mappings supported and enabled?
991 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
994 else if (pg_ps_enabled) {
995 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
996 ("pmap_init: can't assign to pagesizes[1]"));
997 pagesizes[1] = NBPDR;
1001 * Calculate the size of the pv head table for superpages.
1002 * Handle the possibility that "vm_phys_segs[...].end" is zero.
1004 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
1005 PAGE_SIZE) / NBPDR + 1;
1008 * Allocate memory for the pv head table for superpages.
1010 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1012 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1013 for (i = 0; i < pv_npg; i++)
1014 TAILQ_INIT(&pv_table[i].pv_list);
1016 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
1017 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
1018 if (pv_chunkbase == NULL)
1019 panic("pmap_init: not enough kvm for pv chunks");
1020 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
1021 #if defined(PAE) || defined(PAE_TABLES)
1022 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
1023 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
1024 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1025 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
1028 pmap_initialized = 1;
1033 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1034 ppim = pmap_preinit_mapping + i;
1037 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
1038 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
1044 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
1045 "Max number of PV entries");
1046 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
1047 "Page share factor per proc");
1049 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1050 "2/4MB page mapping counters");
1052 static u_long pmap_pde_demotions;
1053 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1054 &pmap_pde_demotions, 0, "2/4MB page demotions");
1056 static u_long pmap_pde_mappings;
1057 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1058 &pmap_pde_mappings, 0, "2/4MB page mappings");
1060 static u_long pmap_pde_p_failures;
1061 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1062 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
1064 static u_long pmap_pde_promotions;
1065 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1066 &pmap_pde_promotions, 0, "2/4MB page promotions");
1068 /***************************************************
1069 * Low level helper routines.....
1070 ***************************************************/
1073 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
1076 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
1077 pat_index[(int)mode] >= 0);
1081 * Determine the appropriate bits to set in a PTE or PDE for a specified
1085 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
1087 int cache_bits, pat_flag, pat_idx;
1089 if (!pmap_is_valid_memattr(pmap, mode))
1090 panic("Unknown caching mode %d\n", mode);
1092 /* The PAT bit is different for PTE's and PDE's. */
1093 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
1095 /* Map the caching mode to a PAT index. */
1096 pat_idx = pat_index[mode];
1098 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1101 cache_bits |= pat_flag;
1103 cache_bits |= PG_NC_PCD;
1105 cache_bits |= PG_NC_PWT;
1106 return (cache_bits);
1110 pmap_ps_enabled(pmap_t pmap __unused)
1113 return (pg_ps_enabled);
1117 * The caller is responsible for maintaining TLB consistency.
1120 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
1124 pde = pmap_pde(kernel_pmap, va);
1125 pde_store(pde, newpde);
1129 * After changing the page size for the specified virtual address in the page
1130 * table, flush the corresponding entries from the processor's TLB. Only the
1131 * calling processor's TLB is affected.
1133 * The calling thread must be pinned to a processor.
1136 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
1139 if ((newpde & PG_PS) == 0)
1140 /* Demotion: flush a specific 2MB page mapping. */
1142 else /* if ((newpde & PG_G) == 0) */
1144 * Promotion: flush every 4KB page mapping from the TLB
1145 * because there are too many to flush individually.
1160 * For SMP, these functions have to use the IPI mechanism for coherence.
1162 * N.B.: Before calling any of the following TLB invalidation functions,
1163 * the calling processor must ensure that all stores updating a non-
1164 * kernel page table are globally performed. Otherwise, another
1165 * processor could cache an old, pre-update entry without being
1166 * invalidated. This can happen one of two ways: (1) The pmap becomes
1167 * active on another processor after its pm_active field is checked by
1168 * one of the following functions but before a store updating the page
1169 * table is globally performed. (2) The pmap becomes active on another
1170 * processor before its pm_active field is checked but due to
1171 * speculative loads one of the following functions stills reads the
1172 * pmap as inactive on the other processor.
1174 * The kernel page table is exempt because its pm_active field is
1175 * immutable. The kernel page table is always active on every
1179 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1181 cpuset_t *mask, other_cpus;
1185 if (pmap == kernel_pmap) {
1188 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1191 cpuid = PCPU_GET(cpuid);
1192 other_cpus = all_cpus;
1193 CPU_CLR(cpuid, &other_cpus);
1194 CPU_AND(&other_cpus, &pmap->pm_active);
1197 smp_masked_invlpg(*mask, va, pmap);
1201 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1202 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1205 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1207 cpuset_t *mask, other_cpus;
1211 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1212 pmap_invalidate_all(pmap);
1217 if (pmap == kernel_pmap) {
1218 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1221 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1224 cpuid = PCPU_GET(cpuid);
1225 other_cpus = all_cpus;
1226 CPU_CLR(cpuid, &other_cpus);
1227 CPU_AND(&other_cpus, &pmap->pm_active);
1230 smp_masked_invlpg_range(*mask, sva, eva, pmap);
1235 pmap_invalidate_all(pmap_t pmap)
1237 cpuset_t *mask, other_cpus;
1241 if (pmap == kernel_pmap) {
1244 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1247 cpuid = PCPU_GET(cpuid);
1248 other_cpus = all_cpus;
1249 CPU_CLR(cpuid, &other_cpus);
1250 CPU_AND(&other_cpus, &pmap->pm_active);
1253 smp_masked_invltlb(*mask, pmap);
1258 pmap_invalidate_cache(void)
1268 cpuset_t invalidate; /* processors that invalidate their TLB */
1272 u_int store; /* processor that updates the PDE */
1276 pmap_update_pde_kernel(void *arg)
1278 struct pde_action *act = arg;
1281 if (act->store == PCPU_GET(cpuid)) {
1282 pde = pmap_pde(kernel_pmap, act->va);
1283 pde_store(pde, act->newpde);
1288 pmap_update_pde_user(void *arg)
1290 struct pde_action *act = arg;
1292 if (act->store == PCPU_GET(cpuid))
1293 pde_store(act->pde, act->newpde);
1297 pmap_update_pde_teardown(void *arg)
1299 struct pde_action *act = arg;
1301 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1302 pmap_update_pde_invalidate(act->va, act->newpde);
1306 * Change the page size for the specified virtual address in a way that
1307 * prevents any possibility of the TLB ever having two entries that map the
1308 * same virtual address using different page sizes. This is the recommended
1309 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1310 * machine check exception for a TLB state that is improperly diagnosed as a
1314 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1316 struct pde_action act;
1317 cpuset_t active, other_cpus;
1321 cpuid = PCPU_GET(cpuid);
1322 other_cpus = all_cpus;
1323 CPU_CLR(cpuid, &other_cpus);
1324 if (pmap == kernel_pmap)
1327 active = pmap->pm_active;
1328 if (CPU_OVERLAP(&active, &other_cpus)) {
1330 act.invalidate = active;
1333 act.newpde = newpde;
1334 CPU_SET(cpuid, &active);
1335 smp_rendezvous_cpus(active,
1336 smp_no_rendezvous_barrier, pmap == kernel_pmap ?
1337 pmap_update_pde_kernel : pmap_update_pde_user,
1338 pmap_update_pde_teardown, &act);
1340 if (pmap == kernel_pmap)
1341 pmap_kenter_pde(va, newpde);
1343 pde_store(pde, newpde);
1344 if (CPU_ISSET(cpuid, &active))
1345 pmap_update_pde_invalidate(va, newpde);
1351 * Normal, non-SMP, 486+ invalidation functions.
1352 * We inline these within pmap.c for speed.
1355 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1358 if (pmap == kernel_pmap)
1363 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1367 if (pmap == kernel_pmap)
1368 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1373 pmap_invalidate_all(pmap_t pmap)
1376 if (pmap == kernel_pmap)
1381 pmap_invalidate_cache(void)
1388 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1391 if (pmap == kernel_pmap)
1392 pmap_kenter_pde(va, newpde);
1394 pde_store(pde, newpde);
1395 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1396 pmap_update_pde_invalidate(va, newpde);
1401 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1405 * When the PDE has PG_PROMOTED set, the 2- or 4MB page mapping was
1406 * created by a promotion that did not invalidate the 512 or 1024 4KB
1407 * page mappings that might exist in the TLB. Consequently, at this
1408 * point, the TLB may hold both 4KB and 2- or 4MB page mappings for
1409 * the address range [va, va + NBPDR). Therefore, the entire range
1410 * must be invalidated here. In contrast, when PG_PROMOTED is clear,
1411 * the TLB will not hold any 4KB page mappings for the address range
1412 * [va, va + NBPDR), and so a single INVLPG suffices to invalidate the
1413 * 2- or 4MB page mapping from the TLB.
1415 if ((pde & PG_PROMOTED) != 0)
1416 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
1418 pmap_invalidate_page(pmap, va);
1421 DEFINE_IFUNC(, void, pmap_invalidate_cache_range, (vm_offset_t, vm_offset_t),
1425 if ((cpu_feature & CPUID_SS) != 0)
1426 return (pmap_invalidate_cache_range_selfsnoop);
1427 if ((cpu_feature & CPUID_CLFSH) != 0)
1428 return (pmap_force_invalidate_cache_range);
1429 return (pmap_invalidate_cache_range_all);
1432 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1435 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
1438 KASSERT((sva & PAGE_MASK) == 0,
1439 ("pmap_invalidate_cache_range: sva not page-aligned"));
1440 KASSERT((eva & PAGE_MASK) == 0,
1441 ("pmap_invalidate_cache_range: eva not page-aligned"));
1445 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
1448 pmap_invalidate_cache_range_check_align(sva, eva);
1452 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
1455 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
1456 if (eva - sva >= PMAP_CLFLUSH_THRESHOLD) {
1458 * The supplied range is bigger than 2MB.
1459 * Globally invalidate cache.
1461 pmap_invalidate_cache();
1467 * XXX: Some CPUs fault, hang, or trash the local APIC
1468 * registers if we use CLFLUSH on the local APIC
1469 * range. The local APIC is always uncached, so we
1470 * don't need to flush for that range anyway.
1472 if (pmap_kextract(sva) == lapic_paddr)
1476 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
1478 * Do per-cache line flush. Use the sfence
1479 * instruction to insure that previous stores are
1480 * included in the write-back. The processor
1481 * propagates flush to other processors in the cache
1485 for (; sva < eva; sva += cpu_clflush_line_size)
1490 * Writes are ordered by CLFLUSH on Intel CPUs.
1492 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1494 for (; sva < eva; sva += cpu_clflush_line_size)
1496 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1502 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
1505 pmap_invalidate_cache_range_check_align(sva, eva);
1506 pmap_invalidate_cache();
1510 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1514 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1515 (cpu_feature & CPUID_CLFSH) == 0) {
1516 pmap_invalidate_cache();
1518 for (i = 0; i < count; i++)
1519 pmap_flush_page(pages[i]);
1524 * Are we current address space or kernel?
1527 pmap_is_current(pmap_t pmap)
1530 return (pmap == kernel_pmap);
1534 * If the given pmap is not the current or kernel pmap, the returned pte must
1535 * be released by passing it to pmap_pte_release().
1538 pmap_pte(pmap_t pmap, vm_offset_t va)
1543 pde = pmap_pde(pmap, va);
1547 /* are we current address space or kernel? */
1548 if (pmap_is_current(pmap))
1549 return (vtopte(va));
1550 mtx_lock(&PMAP2mutex);
1551 newpf = *pde & PG_FRAME;
1552 if ((*PMAP2 & PG_FRAME) != newpf) {
1553 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1554 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1556 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1562 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1565 static __inline void
1566 pmap_pte_release(pt_entry_t *pte)
1569 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1570 mtx_unlock(&PMAP2mutex);
1574 * NB: The sequence of updating a page table followed by accesses to the
1575 * corresponding pages is subject to the situation described in the "AMD64
1576 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1577 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1578 * right after modifying the PTE bits is crucial.
1580 static __inline void
1581 invlcaddr(void *caddr)
1584 invlpg((u_int)caddr);
1588 * Super fast pmap_pte routine best used when scanning
1589 * the pv lists. This eliminates many coarse-grained
1590 * invltlb calls. Note that many of the pv list
1591 * scans are across different pmaps. It is very wasteful
1592 * to do an entire invltlb for checking a single mapping.
1594 * If the given pmap is not the current pmap, pvh_global_lock
1595 * must be held and curthread pinned to a CPU.
1598 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1603 pde = pmap_pde(pmap, va);
1607 /* are we current address space or kernel? */
1608 if (pmap_is_current(pmap))
1609 return (vtopte(va));
1610 rw_assert(&pvh_global_lock, RA_WLOCKED);
1611 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1612 newpf = *pde & PG_FRAME;
1613 if ((*PMAP1 & PG_FRAME) != newpf) {
1614 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1616 PMAP1cpu = PCPU_GET(cpuid);
1622 if (PMAP1cpu != PCPU_GET(cpuid)) {
1623 PMAP1cpu = PCPU_GET(cpuid);
1629 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1635 pmap_pte_quick3(pmap_t pmap, vm_offset_t va)
1640 pde = pmap_pde(pmap, va);
1644 rw_assert(&pvh_global_lock, RA_WLOCKED);
1645 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1646 newpf = *pde & PG_FRAME;
1647 if ((*PMAP3 & PG_FRAME) != newpf) {
1648 *PMAP3 = newpf | PG_RW | PG_V | PG_A | PG_M;
1650 PMAP3cpu = PCPU_GET(cpuid);
1656 if (PMAP3cpu != PCPU_GET(cpuid)) {
1657 PMAP3cpu = PCPU_GET(cpuid);
1663 return (PADDR3 + (i386_btop(va) & (NPTEPG - 1)));
1669 pmap_pte_ufast(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1671 pt_entry_t *eh_ptep, pte, *ptep;
1673 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1676 eh_ptep = (pt_entry_t *)PCPU_GET(pmap_eh_ptep);
1677 if ((*eh_ptep & PG_FRAME) != pde) {
1678 *eh_ptep = pde | PG_RW | PG_V | PG_A | PG_M;
1679 invlcaddr((void *)PCPU_GET(pmap_eh_va));
1681 ptep = (pt_entry_t *)PCPU_GET(pmap_eh_va) + (i386_btop(va) &
1689 * Routine: pmap_extract
1691 * Extract the physical page address associated
1692 * with the given map/virtual_address pair.
1695 pmap_extract(pmap_t pmap, vm_offset_t va)
1703 pde = pmap->pm_pdir[va >> PDRSHIFT];
1705 if ((pde & PG_PS) != 0)
1706 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1708 pte = pmap_pte_ufast(pmap, va, pde);
1709 rtval = (pte & PG_FRAME) | (va & PAGE_MASK);
1717 * Routine: pmap_extract_and_hold
1719 * Atomically extract and hold the physical page
1720 * with the given pmap and virtual address pair
1721 * if that mapping permits the given protection.
1724 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1735 pde = *pmap_pde(pmap, va);
1738 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1739 if (vm_page_pa_tryrelock(pmap, (pde &
1740 PG_PS_FRAME) | (va & PDRMASK), &pa))
1742 m = PHYS_TO_VM_PAGE(pa);
1745 pte = pmap_pte_ufast(pmap, va, pde);
1747 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1748 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1751 m = PHYS_TO_VM_PAGE(pa);
1762 /***************************************************
1763 * Low level mapping routines.....
1764 ***************************************************/
1767 * Add a wired page to the kva.
1768 * Note: not SMP coherent.
1770 * This function may be used before pmap_bootstrap() is called.
1773 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1778 pte_store(pte, pa | PG_RW | PG_V);
1781 static __inline void
1782 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1787 pte_store(pte, pa | PG_RW | PG_V | pmap_cache_bits(kernel_pmap,
1792 * Remove a page from the kernel pagetables.
1793 * Note: not SMP coherent.
1795 * This function may be used before pmap_bootstrap() is called.
1798 pmap_kremove(vm_offset_t va)
1807 * Used to map a range of physical addresses into kernel
1808 * virtual address space.
1810 * The value passed in '*virt' is a suggested virtual address for
1811 * the mapping. Architectures which can support a direct-mapped
1812 * physical to virtual region can return the appropriate address
1813 * within that region, leaving '*virt' unchanged. Other
1814 * architectures should map the pages starting at '*virt' and
1815 * update '*virt' with the first usable address after the mapped
1819 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1821 vm_offset_t va, sva;
1822 vm_paddr_t superpage_offset;
1827 * Does the physical address range's size and alignment permit at
1828 * least one superpage mapping to be created?
1830 superpage_offset = start & PDRMASK;
1831 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1833 * Increase the starting virtual address so that its alignment
1834 * does not preclude the use of superpage mappings.
1836 if ((va & PDRMASK) < superpage_offset)
1837 va = (va & ~PDRMASK) + superpage_offset;
1838 else if ((va & PDRMASK) > superpage_offset)
1839 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1842 while (start < end) {
1843 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1845 KASSERT((va & PDRMASK) == 0,
1846 ("pmap_map: misaligned va %#x", va));
1847 newpde = start | PG_PS | PG_RW | PG_V;
1848 pmap_kenter_pde(va, newpde);
1852 pmap_kenter(va, start);
1857 pmap_invalidate_range(kernel_pmap, sva, va);
1864 * Add a list of wired pages to the kva
1865 * this routine is only used for temporary
1866 * kernel mappings that do not need to have
1867 * page modification or references recorded.
1868 * Note that old mappings are simply written
1869 * over. The page *must* be wired.
1870 * Note: SMP coherent. Uses a ranged shootdown IPI.
1873 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1875 pt_entry_t *endpte, oldpte, pa, *pte;
1880 endpte = pte + count;
1881 while (pte < endpte) {
1883 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(kernel_pmap,
1885 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1887 #if defined(PAE) || defined(PAE_TABLES)
1888 pte_store(pte, pa | pg_nx | PG_RW | PG_V);
1890 pte_store(pte, pa | PG_RW | PG_V);
1895 if (__predict_false((oldpte & PG_V) != 0))
1896 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1901 * This routine tears out page mappings from the
1902 * kernel -- it is meant only for temporary mappings.
1903 * Note: SMP coherent. Uses a ranged shootdown IPI.
1906 pmap_qremove(vm_offset_t sva, int count)
1911 while (count-- > 0) {
1915 pmap_invalidate_range(kernel_pmap, sva, va);
1918 /***************************************************
1919 * Page table page management routines.....
1920 ***************************************************/
1922 * Schedule the specified unused page table page to be freed. Specifically,
1923 * add the page to the specified list of pages that will be released to the
1924 * physical memory manager after the TLB has been updated.
1926 static __inline void
1927 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1928 boolean_t set_PG_ZERO)
1932 m->flags |= PG_ZERO;
1934 m->flags &= ~PG_ZERO;
1935 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1939 * Inserts the specified page table page into the specified pmap's collection
1940 * of idle page table pages. Each of a pmap's page table pages is responsible
1941 * for mapping a distinct range of virtual addresses. The pmap's collection is
1942 * ordered by this virtual address range.
1945 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1948 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1949 return (vm_radix_insert(&pmap->pm_root, mpte));
1953 * Removes the page table page mapping the specified virtual address from the
1954 * specified pmap's collection of idle page table pages, and returns it.
1955 * Otherwise, returns NULL if there is no page table page corresponding to the
1956 * specified virtual address.
1958 static __inline vm_page_t
1959 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
1962 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1963 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT));
1967 * Decrements a page table page's wire count, which is used to record the
1968 * number of valid page table entries within the page. If the wire count
1969 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1970 * page table page was unmapped and FALSE otherwise.
1972 static inline boolean_t
1973 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1977 if (m->wire_count == 0) {
1978 _pmap_unwire_ptp(pmap, m, free);
1985 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1989 * unmap the page table page
1991 pmap->pm_pdir[m->pindex] = 0;
1992 --pmap->pm_stats.resident_count;
1995 * There is not need to invalidate the recursive mapping since
1996 * we never instantiate such mapping for the usermode pmaps,
1997 * and never remove page table pages from the kernel pmap.
1998 * Put page on a list so that it is released since all TLB
1999 * shootdown is done.
2001 MPASS(pmap != kernel_pmap);
2002 pmap_add_delayed_free_list(m, free, TRUE);
2006 * After removing a page table entry, this routine is used to
2007 * conditionally free the page, and manage the hold/wire counts.
2010 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
2015 if (pmap == kernel_pmap)
2017 ptepde = *pmap_pde(pmap, va);
2018 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
2019 return (pmap_unwire_ptp(pmap, mpte, free));
2023 * Initialize the pmap for the swapper process.
2026 pmap_pinit0(pmap_t pmap)
2029 PMAP_LOCK_INIT(pmap);
2030 pmap->pm_pdir = IdlePTD;
2031 #if defined(PAE) || defined(PAE_TABLES)
2032 pmap->pm_pdpt = IdlePDPT;
2034 pmap->pm_root.rt_root = 0;
2035 CPU_ZERO(&pmap->pm_active);
2036 TAILQ_INIT(&pmap->pm_pvchunk);
2037 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2038 pmap_activate_boot(pmap);
2042 * Initialize a preallocated and zeroed pmap structure,
2043 * such as one in a vmspace structure.
2046 pmap_pinit(pmap_t pmap)
2052 * No need to allocate page table space yet but we do need a valid
2053 * page directory table.
2055 if (pmap->pm_pdir == NULL) {
2056 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
2057 if (pmap->pm_pdir == NULL)
2059 #if defined(PAE) || defined(PAE_TABLES)
2060 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
2061 KASSERT(((vm_offset_t)pmap->pm_pdpt &
2062 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
2063 ("pmap_pinit: pdpt misaligned"));
2064 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
2065 ("pmap_pinit: pdpt above 4g"));
2067 pmap->pm_root.rt_root = 0;
2069 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2070 ("pmap_pinit: pmap has reserved page table page(s)"));
2073 * allocate the page directory page(s)
2075 for (i = 0; i < NPGPTD;) {
2076 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2077 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2081 pmap->pm_ptdpg[i] = m;
2082 #if defined(PAE) || defined(PAE_TABLES)
2083 pmap->pm_pdpt[i] = VM_PAGE_TO_PHYS(m) | PG_V;
2089 pmap_qenter((vm_offset_t)pmap->pm_pdir, pmap->pm_ptdpg, NPGPTD);
2091 for (i = 0; i < NPGPTD; i++)
2092 if ((pmap->pm_ptdpg[i]->flags & PG_ZERO) == 0)
2093 pagezero(pmap->pm_pdir + (i * NPDEPG));
2095 /* Install the trampoline mapping. */
2096 pmap->pm_pdir[TRPTDI] = PTD[TRPTDI];
2098 CPU_ZERO(&pmap->pm_active);
2099 TAILQ_INIT(&pmap->pm_pvchunk);
2100 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2106 * this routine is called if the page table page is not
2110 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
2116 * Allocate a page table page.
2118 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2119 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2120 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2122 rw_wunlock(&pvh_global_lock);
2124 rw_wlock(&pvh_global_lock);
2129 * Indicate the need to retry. While waiting, the page table
2130 * page may have been allocated.
2134 if ((m->flags & PG_ZERO) == 0)
2138 * Map the pagetable page into the process address space, if
2139 * it isn't already there.
2142 pmap->pm_stats.resident_count++;
2144 ptepa = VM_PAGE_TO_PHYS(m);
2145 pmap->pm_pdir[ptepindex] =
2146 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
2152 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
2159 * Calculate pagetable page index
2161 ptepindex = va >> PDRSHIFT;
2164 * Get the page directory entry
2166 ptepa = pmap->pm_pdir[ptepindex];
2169 * This supports switching from a 4MB page to a
2172 if (ptepa & PG_PS) {
2173 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
2174 ptepa = pmap->pm_pdir[ptepindex];
2178 * If the page table page is mapped, we just increment the
2179 * hold count, and activate it.
2182 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
2186 * Here if the pte page isn't mapped, or if it has
2189 m = _pmap_allocpte(pmap, ptepindex, flags);
2190 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2197 /***************************************************
2198 * Pmap allocation/deallocation routines.
2199 ***************************************************/
2202 * Release any resources held by the given physical map.
2203 * Called when a pmap initialized by pmap_pinit is being released.
2204 * Should only be called if the map contains no valid mappings.
2207 pmap_release(pmap_t pmap)
2212 KASSERT(pmap->pm_stats.resident_count == 0,
2213 ("pmap_release: pmap resident count %ld != 0",
2214 pmap->pm_stats.resident_count));
2215 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2216 ("pmap_release: pmap has reserved page table page(s)"));
2217 KASSERT(CPU_EMPTY(&pmap->pm_active),
2218 ("releasing active pmap %p", pmap));
2220 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2222 for (i = 0; i < NPGPTD; i++) {
2223 m = pmap->pm_ptdpg[i];
2224 #if defined(PAE) || defined(PAE_TABLES)
2225 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2226 ("pmap_release: got wrong ptd page"));
2228 vm_page_unwire_noq(m);
2234 kvm_size(SYSCTL_HANDLER_ARGS)
2236 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2238 return (sysctl_handle_long(oidp, &ksize, 0, req));
2240 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2241 0, 0, kvm_size, "IU", "Size of KVM");
2244 kvm_free(SYSCTL_HANDLER_ARGS)
2246 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2248 return (sysctl_handle_long(oidp, &kfree, 0, req));
2250 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2251 0, 0, kvm_free, "IU", "Amount of KVM free");
2254 * grow the number of kernel page table entries, if needed
2257 pmap_growkernel(vm_offset_t addr)
2259 vm_paddr_t ptppaddr;
2263 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2264 addr = roundup2(addr, NBPDR);
2265 if (addr - 1 >= vm_map_max(kernel_map))
2266 addr = vm_map_max(kernel_map);
2267 while (kernel_vm_end < addr) {
2268 if (pdir_pde(PTD, kernel_vm_end)) {
2269 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2270 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2271 kernel_vm_end = vm_map_max(kernel_map);
2277 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2278 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2281 panic("pmap_growkernel: no memory to grow kernel");
2285 if ((nkpg->flags & PG_ZERO) == 0)
2286 pmap_zero_page(nkpg);
2287 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2288 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2289 pdir_pde(KPTD, kernel_vm_end) = newpdir;
2291 pmap_kenter_pde(kernel_vm_end, newpdir);
2292 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2293 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2294 kernel_vm_end = vm_map_max(kernel_map);
2301 /***************************************************
2302 * page management routines.
2303 ***************************************************/
2305 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2306 CTASSERT(_NPCM == 11);
2307 CTASSERT(_NPCPV == 336);
2309 static __inline struct pv_chunk *
2310 pv_to_chunk(pv_entry_t pv)
2313 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2316 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2318 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2319 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2321 static const uint32_t pc_freemask[_NPCM] = {
2322 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2323 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2324 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2325 PC_FREE0_9, PC_FREE10
2328 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2329 "Current number of pv entries");
2332 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2334 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2335 "Current number of pv entry chunks");
2336 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2337 "Current number of pv entry chunks allocated");
2338 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2339 "Current number of pv entry chunks frees");
2340 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2341 "Number of times tried to get a chunk page but failed.");
2343 static long pv_entry_frees, pv_entry_allocs;
2344 static int pv_entry_spare;
2346 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2347 "Current number of pv entry frees");
2348 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2349 "Current number of pv entry allocs");
2350 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2351 "Current number of spare pv entries");
2355 * We are in a serious low memory condition. Resort to
2356 * drastic measures to free some pages so we can allocate
2357 * another pv entry chunk.
2360 pmap_pv_reclaim(pmap_t locked_pmap)
2363 struct pv_chunk *pc;
2364 struct md_page *pvh;
2367 pt_entry_t *pte, tpte;
2371 struct spglist free;
2373 int bit, field, freed;
2375 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2379 TAILQ_INIT(&newtail);
2380 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2381 SLIST_EMPTY(&free))) {
2382 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2383 if (pmap != pc->pc_pmap) {
2385 pmap_invalidate_all(pmap);
2386 if (pmap != locked_pmap)
2390 /* Avoid deadlock and lock recursion. */
2391 if (pmap > locked_pmap)
2393 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2395 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2401 * Destroy every non-wired, 4 KB page mapping in the chunk.
2404 for (field = 0; field < _NPCM; field++) {
2405 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2406 inuse != 0; inuse &= ~(1UL << bit)) {
2408 pv = &pc->pc_pventry[field * 32 + bit];
2410 pde = pmap_pde(pmap, va);
2411 if ((*pde & PG_PS) != 0)
2413 pte = pmap_pte(pmap, va);
2415 if ((tpte & PG_W) == 0)
2416 tpte = pte_load_clear(pte);
2417 pmap_pte_release(pte);
2418 if ((tpte & PG_W) != 0)
2421 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2423 if ((tpte & PG_G) != 0)
2424 pmap_invalidate_page(pmap, va);
2425 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2426 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2428 if ((tpte & PG_A) != 0)
2429 vm_page_aflag_set(m, PGA_REFERENCED);
2430 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2431 if (TAILQ_EMPTY(&m->md.pv_list) &&
2432 (m->flags & PG_FICTITIOUS) == 0) {
2433 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2434 if (TAILQ_EMPTY(&pvh->pv_list)) {
2435 vm_page_aflag_clear(m,
2439 pc->pc_map[field] |= 1UL << bit;
2440 pmap_unuse_pt(pmap, va, &free);
2445 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2448 /* Every freed mapping is for a 4 KB page. */
2449 pmap->pm_stats.resident_count -= freed;
2450 PV_STAT(pv_entry_frees += freed);
2451 PV_STAT(pv_entry_spare += freed);
2452 pv_entry_count -= freed;
2453 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2454 for (field = 0; field < _NPCM; field++)
2455 if (pc->pc_map[field] != pc_freemask[field]) {
2456 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2458 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2461 * One freed pv entry in locked_pmap is
2464 if (pmap == locked_pmap)
2468 if (field == _NPCM) {
2469 PV_STAT(pv_entry_spare -= _NPCPV);
2470 PV_STAT(pc_chunk_count--);
2471 PV_STAT(pc_chunk_frees++);
2472 /* Entire chunk is free; return it. */
2473 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2474 pmap_qremove((vm_offset_t)pc, 1);
2475 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2480 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2482 pmap_invalidate_all(pmap);
2483 if (pmap != locked_pmap)
2486 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2487 m_pc = SLIST_FIRST(&free);
2488 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2489 /* Recycle a freed page table page. */
2490 m_pc->wire_count = 1;
2492 vm_page_free_pages_toq(&free, true);
2497 * free the pv_entry back to the free list
2500 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2502 struct pv_chunk *pc;
2503 int idx, field, bit;
2505 rw_assert(&pvh_global_lock, RA_WLOCKED);
2506 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2507 PV_STAT(pv_entry_frees++);
2508 PV_STAT(pv_entry_spare++);
2510 pc = pv_to_chunk(pv);
2511 idx = pv - &pc->pc_pventry[0];
2514 pc->pc_map[field] |= 1ul << bit;
2515 for (idx = 0; idx < _NPCM; idx++)
2516 if (pc->pc_map[idx] != pc_freemask[idx]) {
2518 * 98% of the time, pc is already at the head of the
2519 * list. If it isn't already, move it to the head.
2521 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2523 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2524 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2529 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2534 free_pv_chunk(struct pv_chunk *pc)
2538 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2539 PV_STAT(pv_entry_spare -= _NPCPV);
2540 PV_STAT(pc_chunk_count--);
2541 PV_STAT(pc_chunk_frees++);
2542 /* entire chunk is free, return it */
2543 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2544 pmap_qremove((vm_offset_t)pc, 1);
2545 vm_page_unwire(m, PQ_NONE);
2547 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2551 * get a new pv_entry, allocating a block from the system
2555 get_pv_entry(pmap_t pmap, boolean_t try)
2557 static const struct timeval printinterval = { 60, 0 };
2558 static struct timeval lastprint;
2561 struct pv_chunk *pc;
2564 rw_assert(&pvh_global_lock, RA_WLOCKED);
2565 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2566 PV_STAT(pv_entry_allocs++);
2568 if (pv_entry_count > pv_entry_high_water)
2569 if (ratecheck(&lastprint, &printinterval))
2570 printf("Approaching the limit on PV entries, consider "
2571 "increasing either the vm.pmap.shpgperproc or the "
2572 "vm.pmap.pv_entries tunable.\n");
2574 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2576 for (field = 0; field < _NPCM; field++) {
2577 if (pc->pc_map[field]) {
2578 bit = bsfl(pc->pc_map[field]);
2582 if (field < _NPCM) {
2583 pv = &pc->pc_pventry[field * 32 + bit];
2584 pc->pc_map[field] &= ~(1ul << bit);
2585 /* If this was the last item, move it to tail */
2586 for (field = 0; field < _NPCM; field++)
2587 if (pc->pc_map[field] != 0) {
2588 PV_STAT(pv_entry_spare--);
2589 return (pv); /* not full, return */
2591 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2592 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2593 PV_STAT(pv_entry_spare--);
2598 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2599 * global lock. If "pv_vafree" is currently non-empty, it will
2600 * remain non-empty until pmap_ptelist_alloc() completes.
2602 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2603 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2606 PV_STAT(pc_chunk_tryfail++);
2609 m = pmap_pv_reclaim(pmap);
2613 PV_STAT(pc_chunk_count++);
2614 PV_STAT(pc_chunk_allocs++);
2615 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2616 pmap_qenter((vm_offset_t)pc, &m, 1);
2618 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2619 for (field = 1; field < _NPCM; field++)
2620 pc->pc_map[field] = pc_freemask[field];
2621 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2622 pv = &pc->pc_pventry[0];
2623 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2624 PV_STAT(pv_entry_spare += _NPCPV - 1);
2628 static __inline pv_entry_t
2629 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2633 rw_assert(&pvh_global_lock, RA_WLOCKED);
2634 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2635 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2636 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2644 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2646 struct md_page *pvh;
2648 vm_offset_t va_last;
2651 rw_assert(&pvh_global_lock, RA_WLOCKED);
2652 KASSERT((pa & PDRMASK) == 0,
2653 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2656 * Transfer the 4mpage's pv entry for this mapping to the first
2659 pvh = pa_to_pvh(pa);
2660 va = trunc_4mpage(va);
2661 pv = pmap_pvh_remove(pvh, pmap, va);
2662 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2663 m = PHYS_TO_VM_PAGE(pa);
2664 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2665 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2666 va_last = va + NBPDR - PAGE_SIZE;
2669 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2670 ("pmap_pv_demote_pde: page %p is not managed", m));
2672 pmap_insert_entry(pmap, va, m);
2673 } while (va < va_last);
2676 #if VM_NRESERVLEVEL > 0
2678 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2680 struct md_page *pvh;
2682 vm_offset_t va_last;
2685 rw_assert(&pvh_global_lock, RA_WLOCKED);
2686 KASSERT((pa & PDRMASK) == 0,
2687 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2690 * Transfer the first page's pv entry for this mapping to the
2691 * 4mpage's pv list. Aside from avoiding the cost of a call
2692 * to get_pv_entry(), a transfer avoids the possibility that
2693 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2694 * removes one of the mappings that is being promoted.
2696 m = PHYS_TO_VM_PAGE(pa);
2697 va = trunc_4mpage(va);
2698 pv = pmap_pvh_remove(&m->md, pmap, va);
2699 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2700 pvh = pa_to_pvh(pa);
2701 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2702 /* Free the remaining NPTEPG - 1 pv entries. */
2703 va_last = va + NBPDR - PAGE_SIZE;
2707 pmap_pvh_free(&m->md, pmap, va);
2708 } while (va < va_last);
2710 #endif /* VM_NRESERVLEVEL > 0 */
2713 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2717 pv = pmap_pvh_remove(pvh, pmap, va);
2718 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2719 free_pv_entry(pmap, pv);
2723 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2725 struct md_page *pvh;
2727 rw_assert(&pvh_global_lock, RA_WLOCKED);
2728 pmap_pvh_free(&m->md, pmap, va);
2729 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2730 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2731 if (TAILQ_EMPTY(&pvh->pv_list))
2732 vm_page_aflag_clear(m, PGA_WRITEABLE);
2737 * Create a pv entry for page at pa for
2741 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2745 rw_assert(&pvh_global_lock, RA_WLOCKED);
2746 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2747 pv = get_pv_entry(pmap, FALSE);
2749 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2753 * Conditionally create a pv entry.
2756 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2760 rw_assert(&pvh_global_lock, RA_WLOCKED);
2761 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2762 if (pv_entry_count < pv_entry_high_water &&
2763 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2765 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2772 * Create the pv entries for each of the pages within a superpage.
2775 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags)
2777 struct md_page *pvh;
2781 rw_assert(&pvh_global_lock, RA_WLOCKED);
2782 noreclaim = (flags & PMAP_ENTER_NORECLAIM) != 0;
2783 if ((noreclaim && pv_entry_count >= pv_entry_high_water) ||
2784 (pv = get_pv_entry(pmap, noreclaim)) == NULL)
2787 pvh = pa_to_pvh(pde & PG_PS_FRAME);
2788 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2793 * Fills a page table page with mappings to consecutive physical pages.
2796 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2800 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2802 newpte += PAGE_SIZE;
2807 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2808 * 2- or 4MB page mapping is invalidated.
2811 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2813 pd_entry_t newpde, oldpde;
2814 pt_entry_t *firstpte, newpte;
2817 struct spglist free;
2820 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2822 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2823 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2824 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
2826 KASSERT((oldpde & PG_W) == 0,
2827 ("pmap_demote_pde: page table page for a wired mapping"
2831 * Invalidate the 2- or 4MB page mapping and return
2832 * "failure" if the mapping was never accessed or the
2833 * allocation of the new page table page fails.
2835 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2836 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2837 VM_ALLOC_WIRED)) == NULL) {
2839 sva = trunc_4mpage(va);
2840 pmap_remove_pde(pmap, pde, sva, &free);
2841 if ((oldpde & PG_G) == 0)
2842 pmap_invalidate_pde_page(pmap, sva, oldpde);
2843 vm_page_free_pages_toq(&free, true);
2844 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2845 " in pmap %p", va, pmap);
2848 if (pmap != kernel_pmap) {
2849 mpte->wire_count = NPTEPG;
2850 pmap->pm_stats.resident_count++;
2853 mptepa = VM_PAGE_TO_PHYS(mpte);
2856 * If the page mapping is in the kernel's address space, then the
2857 * KPTmap can provide access to the page table page. Otherwise,
2858 * temporarily map the page table page (mpte) into the kernel's
2859 * address space at either PADDR1 or PADDR2.
2861 if (pmap == kernel_pmap)
2862 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2863 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2864 if ((*PMAP1 & PG_FRAME) != mptepa) {
2865 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2867 PMAP1cpu = PCPU_GET(cpuid);
2873 if (PMAP1cpu != PCPU_GET(cpuid)) {
2874 PMAP1cpu = PCPU_GET(cpuid);
2882 mtx_lock(&PMAP2mutex);
2883 if ((*PMAP2 & PG_FRAME) != mptepa) {
2884 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2885 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2889 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2890 KASSERT((oldpde & PG_A) != 0,
2891 ("pmap_demote_pde: oldpde is missing PG_A"));
2892 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2893 ("pmap_demote_pde: oldpde is missing PG_M"));
2894 newpte = oldpde & ~PG_PS;
2895 if ((newpte & PG_PDE_PAT) != 0)
2896 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2899 * If the page table page is not leftover from an earlier promotion,
2902 if ((oldpde & PG_PROMOTED) == 0)
2903 pmap_fill_ptp(firstpte, newpte);
2905 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2906 ("pmap_demote_pde: firstpte and newpte map different physical"
2910 * If the mapping has changed attributes, update the page table
2913 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2914 pmap_fill_ptp(firstpte, newpte);
2917 * Demote the mapping. This pmap is locked. The old PDE has
2918 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2919 * set. Thus, there is no danger of a race with another
2920 * processor changing the setting of PG_A and/or PG_M between
2921 * the read above and the store below.
2923 if (workaround_erratum383)
2924 pmap_update_pde(pmap, va, pde, newpde);
2925 else if (pmap == kernel_pmap)
2926 pmap_kenter_pde(va, newpde);
2928 pde_store(pde, newpde);
2929 if (firstpte == PADDR2)
2930 mtx_unlock(&PMAP2mutex);
2933 * Invalidate the recursive mapping of the page table page.
2935 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2938 * Demote the pv entry. This depends on the earlier demotion
2939 * of the mapping. Specifically, the (re)creation of a per-
2940 * page pv entry might trigger the execution of pmap_collect(),
2941 * which might reclaim a newly (re)created per-page pv entry
2942 * and destroy the associated mapping. In order to destroy
2943 * the mapping, the PDE must have already changed from mapping
2944 * the 2mpage to referencing the page table page.
2946 if ((oldpde & PG_MANAGED) != 0)
2947 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2949 pmap_pde_demotions++;
2950 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2951 " in pmap %p", va, pmap);
2956 * Removes a 2- or 4MB page mapping from the kernel pmap.
2959 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2965 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2966 mpte = pmap_remove_pt_page(pmap, va);
2968 panic("pmap_remove_kernel_pde: Missing pt page.");
2970 mptepa = VM_PAGE_TO_PHYS(mpte);
2971 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2974 * Initialize the page table page.
2976 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2979 * Remove the mapping.
2981 if (workaround_erratum383)
2982 pmap_update_pde(pmap, va, pde, newpde);
2984 pmap_kenter_pde(va, newpde);
2987 * Invalidate the recursive mapping of the page table page.
2989 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2993 * pmap_remove_pde: do the things to unmap a superpage in a process
2996 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2997 struct spglist *free)
2999 struct md_page *pvh;
3001 vm_offset_t eva, va;
3004 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3005 KASSERT((sva & PDRMASK) == 0,
3006 ("pmap_remove_pde: sva is not 4mpage aligned"));
3007 oldpde = pte_load_clear(pdq);
3009 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
3012 * Machines that don't support invlpg, also don't support
3015 if ((oldpde & PG_G) != 0)
3016 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
3018 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
3019 if (oldpde & PG_MANAGED) {
3020 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
3021 pmap_pvh_free(pvh, pmap, sva);
3023 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3024 va < eva; va += PAGE_SIZE, m++) {
3025 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3028 vm_page_aflag_set(m, PGA_REFERENCED);
3029 if (TAILQ_EMPTY(&m->md.pv_list) &&
3030 TAILQ_EMPTY(&pvh->pv_list))
3031 vm_page_aflag_clear(m, PGA_WRITEABLE);
3034 if (pmap == kernel_pmap) {
3035 pmap_remove_kernel_pde(pmap, pdq, sva);
3037 mpte = pmap_remove_pt_page(pmap, sva);
3039 pmap->pm_stats.resident_count--;
3040 KASSERT(mpte->wire_count == NPTEPG,
3041 ("pmap_remove_pde: pte page wire count error"));
3042 mpte->wire_count = 0;
3043 pmap_add_delayed_free_list(mpte, free, FALSE);
3049 * pmap_remove_pte: do the things to unmap a page in a process
3052 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
3053 struct spglist *free)
3058 rw_assert(&pvh_global_lock, RA_WLOCKED);
3059 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3060 oldpte = pte_load_clear(ptq);
3061 KASSERT(oldpte != 0,
3062 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
3064 pmap->pm_stats.wired_count -= 1;
3066 * Machines that don't support invlpg, also don't support
3070 pmap_invalidate_page(kernel_pmap, va);
3071 pmap->pm_stats.resident_count -= 1;
3072 if (oldpte & PG_MANAGED) {
3073 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
3074 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3077 vm_page_aflag_set(m, PGA_REFERENCED);
3078 pmap_remove_entry(pmap, m, va);
3080 return (pmap_unuse_pt(pmap, va, free));
3084 * Remove a single page from a process address space
3087 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
3091 rw_assert(&pvh_global_lock, RA_WLOCKED);
3092 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3093 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3094 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
3096 pmap_remove_pte(pmap, pte, va, free);
3097 pmap_invalidate_page(pmap, va);
3101 * Removes the specified range of addresses from the page table page.
3104 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
3105 struct spglist *free)
3110 rw_assert(&pvh_global_lock, RA_WLOCKED);
3111 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3112 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3114 for (pte = pmap_pte_quick(pmap, sva); sva != eva; pte++,
3120 * The TLB entry for a PG_G mapping is invalidated by
3121 * pmap_remove_pte().
3123 if ((*pte & PG_G) == 0)
3126 if (pmap_remove_pte(pmap, pte, sva, free))
3133 * Remove the given range of addresses from the specified map.
3135 * It is assumed that the start and end are properly
3136 * rounded to the page size.
3139 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3143 struct spglist free;
3147 * Perform an unsynchronized read. This is, however, safe.
3149 if (pmap->pm_stats.resident_count == 0)
3155 rw_wlock(&pvh_global_lock);
3160 * special handling of removing one page. a very
3161 * common operation and easy to short circuit some
3164 if ((sva + PAGE_SIZE == eva) &&
3165 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
3166 pmap_remove_page(pmap, sva, &free);
3170 for (; sva < eva; sva = pdnxt) {
3174 * Calculate index for next page table.
3176 pdnxt = (sva + NBPDR) & ~PDRMASK;
3179 if (pmap->pm_stats.resident_count == 0)
3182 pdirindex = sva >> PDRSHIFT;
3183 ptpaddr = pmap->pm_pdir[pdirindex];
3186 * Weed out invalid mappings. Note: we assume that the page
3187 * directory table is always allocated, and in kernel virtual.
3193 * Check for large page.
3195 if ((ptpaddr & PG_PS) != 0) {
3197 * Are we removing the entire large page? If not,
3198 * demote the mapping and fall through.
3200 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3202 * The TLB entry for a PG_G mapping is
3203 * invalidated by pmap_remove_pde().
3205 if ((ptpaddr & PG_G) == 0)
3207 pmap_remove_pde(pmap,
3208 &pmap->pm_pdir[pdirindex], sva, &free);
3210 } else if (!pmap_demote_pde(pmap,
3211 &pmap->pm_pdir[pdirindex], sva)) {
3212 /* The large page mapping was destroyed. */
3218 * Limit our scan to either the end of the va represented
3219 * by the current page table page, or to the end of the
3220 * range being removed.
3225 if (pmap_remove_ptes(pmap, sva, pdnxt, &free))
3231 pmap_invalidate_all(pmap);
3232 rw_wunlock(&pvh_global_lock);
3234 vm_page_free_pages_toq(&free, true);
3238 * Routine: pmap_remove_all
3240 * Removes this physical page from
3241 * all physical maps in which it resides.
3242 * Reflects back modify bits to the pager.
3245 * Original versions of this routine were very
3246 * inefficient because they iteratively called
3247 * pmap_remove (slow...)
3251 pmap_remove_all(vm_page_t m)
3253 struct md_page *pvh;
3256 pt_entry_t *pte, tpte;
3259 struct spglist free;
3261 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3262 ("pmap_remove_all: page %p is not managed", m));
3264 rw_wlock(&pvh_global_lock);
3266 if ((m->flags & PG_FICTITIOUS) != 0)
3267 goto small_mappings;
3268 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3269 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3273 pde = pmap_pde(pmap, va);
3274 (void)pmap_demote_pde(pmap, pde, va);
3278 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3281 pmap->pm_stats.resident_count--;
3282 pde = pmap_pde(pmap, pv->pv_va);
3283 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3284 " a 4mpage in page %p's pv list", m));
3285 pte = pmap_pte_quick(pmap, pv->pv_va);
3286 tpte = pte_load_clear(pte);
3287 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3290 pmap->pm_stats.wired_count--;
3292 vm_page_aflag_set(m, PGA_REFERENCED);
3295 * Update the vm_page_t clean and reference bits.
3297 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3299 pmap_unuse_pt(pmap, pv->pv_va, &free);
3300 pmap_invalidate_page(pmap, pv->pv_va);
3301 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3302 free_pv_entry(pmap, pv);
3305 vm_page_aflag_clear(m, PGA_WRITEABLE);
3307 rw_wunlock(&pvh_global_lock);
3308 vm_page_free_pages_toq(&free, true);
3312 * pmap_protect_pde: do the things to protect a 4mpage in a process
3315 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3317 pd_entry_t newpde, oldpde;
3318 vm_offset_t eva, va;
3320 boolean_t anychanged;
3322 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3323 KASSERT((sva & PDRMASK) == 0,
3324 ("pmap_protect_pde: sva is not 4mpage aligned"));
3327 oldpde = newpde = *pde;
3328 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
3329 (PG_MANAGED | PG_M | PG_RW)) {
3331 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3332 va < eva; va += PAGE_SIZE, m++)
3335 if ((prot & VM_PROT_WRITE) == 0)
3336 newpde &= ~(PG_RW | PG_M);
3337 #if defined(PAE) || defined(PAE_TABLES)
3338 if ((prot & VM_PROT_EXECUTE) == 0)
3341 if (newpde != oldpde) {
3343 * As an optimization to future operations on this PDE, clear
3344 * PG_PROMOTED. The impending invalidation will remove any
3345 * lingering 4KB page mappings from the TLB.
3347 if (!pde_cmpset(pde, oldpde, newpde & ~PG_PROMOTED))
3349 if ((oldpde & PG_G) != 0)
3350 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
3354 return (anychanged);
3358 * Set the physical protection on the
3359 * specified range of this map as requested.
3362 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3367 boolean_t anychanged, pv_lists_locked;
3369 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3370 if (prot == VM_PROT_NONE) {
3371 pmap_remove(pmap, sva, eva);
3375 #if defined(PAE) || defined(PAE_TABLES)
3376 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3377 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3380 if (prot & VM_PROT_WRITE)
3384 if (pmap_is_current(pmap))
3385 pv_lists_locked = FALSE;
3387 pv_lists_locked = TRUE;
3389 rw_wlock(&pvh_global_lock);
3395 for (; sva < eva; sva = pdnxt) {
3396 pt_entry_t obits, pbits;
3399 pdnxt = (sva + NBPDR) & ~PDRMASK;
3403 pdirindex = sva >> PDRSHIFT;
3404 ptpaddr = pmap->pm_pdir[pdirindex];
3407 * Weed out invalid mappings. Note: we assume that the page
3408 * directory table is always allocated, and in kernel virtual.
3414 * Check for large page.
3416 if ((ptpaddr & PG_PS) != 0) {
3418 * Are we protecting the entire large page? If not,
3419 * demote the mapping and fall through.
3421 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3423 * The TLB entry for a PG_G mapping is
3424 * invalidated by pmap_protect_pde().
3426 if (pmap_protect_pde(pmap,
3427 &pmap->pm_pdir[pdirindex], sva, prot))
3431 if (!pv_lists_locked) {
3432 pv_lists_locked = TRUE;
3433 if (!rw_try_wlock(&pvh_global_lock)) {
3435 pmap_invalidate_all(
3442 if (!pmap_demote_pde(pmap,
3443 &pmap->pm_pdir[pdirindex], sva)) {
3445 * The large page mapping was
3456 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3462 * Regardless of whether a pte is 32 or 64 bits in
3463 * size, PG_RW, PG_A, and PG_M are among the least
3464 * significant 32 bits.
3466 obits = pbits = *pte;
3467 if ((pbits & PG_V) == 0)
3470 if ((prot & VM_PROT_WRITE) == 0) {
3471 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3472 (PG_MANAGED | PG_M | PG_RW)) {
3473 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3476 pbits &= ~(PG_RW | PG_M);
3478 #if defined(PAE) || defined(PAE_TABLES)
3479 if ((prot & VM_PROT_EXECUTE) == 0)
3483 if (pbits != obits) {
3484 #if defined(PAE) || defined(PAE_TABLES)
3485 if (!atomic_cmpset_64(pte, obits, pbits))
3488 if (!atomic_cmpset_int((u_int *)pte, obits,
3493 pmap_invalidate_page(pmap, sva);
3500 pmap_invalidate_all(pmap);
3501 if (pv_lists_locked) {
3503 rw_wunlock(&pvh_global_lock);
3508 #if VM_NRESERVLEVEL > 0
3510 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3511 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3512 * For promotion to occur, two conditions must be met: (1) the 4KB page
3513 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3514 * mappings must have identical characteristics.
3516 * Managed (PG_MANAGED) mappings within the kernel address space are not
3517 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3518 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3522 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3525 pt_entry_t *firstpte, oldpte, pa, *pte;
3526 vm_offset_t oldpteva;
3529 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3532 * Examine the first PTE in the specified PTP. Abort if this PTE is
3533 * either invalid, unused, or does not map the first 4KB physical page
3534 * within a 2- or 4MB page.
3536 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3539 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3540 pmap_pde_p_failures++;
3541 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3542 " in pmap %p", va, pmap);
3545 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3546 pmap_pde_p_failures++;
3547 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3548 " in pmap %p", va, pmap);
3551 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3553 * When PG_M is already clear, PG_RW can be cleared without
3554 * a TLB invalidation.
3556 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3563 * Examine each of the other PTEs in the specified PTP. Abort if this
3564 * PTE maps an unexpected 4KB physical page or does not have identical
3565 * characteristics to the first PTE.
3567 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3568 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3571 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3572 pmap_pde_p_failures++;
3573 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3574 " in pmap %p", va, pmap);
3577 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3579 * When PG_M is already clear, PG_RW can be cleared
3580 * without a TLB invalidation.
3582 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3586 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3588 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3589 " in pmap %p", oldpteva, pmap);
3591 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3592 pmap_pde_p_failures++;
3593 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3594 " in pmap %p", va, pmap);
3601 * Save the page table page in its current state until the PDE
3602 * mapping the superpage is demoted by pmap_demote_pde() or
3603 * destroyed by pmap_remove_pde().
3605 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3606 KASSERT(mpte >= vm_page_array &&
3607 mpte < &vm_page_array[vm_page_array_size],
3608 ("pmap_promote_pde: page table page is out of range"));
3609 KASSERT(mpte->pindex == va >> PDRSHIFT,
3610 ("pmap_promote_pde: page table page's pindex is wrong"));
3611 if (pmap_insert_pt_page(pmap, mpte)) {
3612 pmap_pde_p_failures++;
3614 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3620 * Promote the pv entries.
3622 if ((newpde & PG_MANAGED) != 0)
3623 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3626 * Propagate the PAT index to its proper position.
3628 if ((newpde & PG_PTE_PAT) != 0)
3629 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3632 * Map the superpage.
3634 if (workaround_erratum383)
3635 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3636 else if (pmap == kernel_pmap)
3637 pmap_kenter_pde(va, PG_PROMOTED | PG_PS | newpde);
3639 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
3641 pmap_pde_promotions++;
3642 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3643 " in pmap %p", va, pmap);
3645 #endif /* VM_NRESERVLEVEL > 0 */
3648 * Insert the given physical page (p) at
3649 * the specified virtual address (v) in the
3650 * target physical map with the protection requested.
3652 * If specified, the page will be wired down, meaning
3653 * that the related pte can not be reclaimed.
3655 * NB: This is the only routine which MAY NOT lazy-evaluate
3656 * or lose information. That is, this routine must actually
3657 * insert this page into the given map NOW.
3660 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3661 u_int flags, int8_t psind)
3665 pt_entry_t newpte, origpte;
3671 va = trunc_page(va);
3672 KASSERT((pmap == kernel_pmap && va < VM_MAX_KERNEL_ADDRESS) ||
3673 (pmap != kernel_pmap && va < VM_MAXUSER_ADDRESS),
3674 ("pmap_enter: toobig k%d %#x", pmap == kernel_pmap, va));
3675 KASSERT(va < PMAP_TRM_MIN_ADDRESS,
3676 ("pmap_enter: invalid to pmap_enter into trampoline (va: 0x%x)",
3678 KASSERT(pmap != kernel_pmap || (m->oflags & VPO_UNMANAGED) != 0 ||
3679 va < kmi.clean_sva || va >= kmi.clean_eva,
3680 ("pmap_enter: managed mapping within the clean submap"));
3681 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3682 VM_OBJECT_ASSERT_LOCKED(m->object);
3683 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
3684 ("pmap_enter: flags %u has reserved bits set", flags));
3685 pa = VM_PAGE_TO_PHYS(m);
3686 newpte = (pt_entry_t)(pa | PG_A | PG_V);
3687 if ((flags & VM_PROT_WRITE) != 0)
3689 if ((prot & VM_PROT_WRITE) != 0)
3691 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
3692 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
3693 #if defined(PAE) || defined(PAE_TABLES)
3694 if ((prot & VM_PROT_EXECUTE) == 0)
3697 if ((flags & PMAP_ENTER_WIRED) != 0)
3699 if (pmap != kernel_pmap)
3701 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
3702 if ((m->oflags & VPO_UNMANAGED) == 0)
3703 newpte |= PG_MANAGED;
3705 rw_wlock(&pvh_global_lock);
3709 /* Assert the required virtual and physical alignment. */
3710 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
3711 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3712 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m);
3716 pde = pmap_pde(pmap, va);
3717 if (pmap != kernel_pmap) {
3720 * In the case that a page table page is not resident,
3721 * we are creating it here. pmap_allocpte() handles
3724 mpte = pmap_allocpte(pmap, va, flags);
3726 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3727 ("pmap_allocpte failed with sleep allowed"));
3728 rv = KERN_RESOURCE_SHORTAGE;
3733 * va is for KVA, so pmap_demote_pde() will never fail
3734 * to install a page table page. PG_V is also
3735 * asserted by pmap_demote_pde().
3738 KASSERT(pde != NULL && (*pde & PG_V) != 0,
3739 ("KVA %#x invalid pde pdir %#jx", va,
3740 (uintmax_t)pmap->pm_pdir[PTDPTDI]));
3741 if ((*pde & PG_PS) != 0)
3742 pmap_demote_pde(pmap, pde, va);
3744 pte = pmap_pte_quick(pmap, va);
3747 * Page Directory table entry is not valid, which should not
3748 * happen. We should have either allocated the page table
3749 * page or demoted the existing mapping above.
3752 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3753 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3760 * Is the specified virtual address already mapped?
3762 if ((origpte & PG_V) != 0) {
3764 * Wiring change, just update stats. We don't worry about
3765 * wiring PT pages as they remain resident as long as there
3766 * are valid mappings in them. Hence, if a user page is wired,
3767 * the PT page will be also.
3769 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
3770 pmap->pm_stats.wired_count++;
3771 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
3772 pmap->pm_stats.wired_count--;
3775 * Remove the extra PT page reference.
3779 KASSERT(mpte->wire_count > 0,
3780 ("pmap_enter: missing reference to page table page,"
3785 * Has the physical page changed?
3787 opa = origpte & PG_FRAME;
3790 * No, might be a protection or wiring change.
3792 if ((origpte & PG_MANAGED) != 0 &&
3793 (newpte & PG_RW) != 0)
3794 vm_page_aflag_set(m, PGA_WRITEABLE);
3795 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
3801 * The physical page has changed. Temporarily invalidate
3802 * the mapping. This ensures that all threads sharing the
3803 * pmap keep a consistent view of the mapping, which is
3804 * necessary for the correct handling of COW faults. It
3805 * also permits reuse of the old mapping's PV entry,
3806 * avoiding an allocation.
3808 * For consistency, handle unmanaged mappings the same way.
3810 origpte = pte_load_clear(pte);
3811 KASSERT((origpte & PG_FRAME) == opa,
3812 ("pmap_enter: unexpected pa update for %#x", va));
3813 if ((origpte & PG_MANAGED) != 0) {
3814 om = PHYS_TO_VM_PAGE(opa);
3817 * The pmap lock is sufficient to synchronize with
3818 * concurrent calls to pmap_page_test_mappings() and
3819 * pmap_ts_referenced().
3821 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3823 if ((origpte & PG_A) != 0)
3824 vm_page_aflag_set(om, PGA_REFERENCED);
3825 pv = pmap_pvh_remove(&om->md, pmap, va);
3827 ("pmap_enter: no PV entry for %#x", va));
3828 if ((newpte & PG_MANAGED) == 0)
3829 free_pv_entry(pmap, pv);
3830 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3831 TAILQ_EMPTY(&om->md.pv_list) &&
3832 ((om->flags & PG_FICTITIOUS) != 0 ||
3833 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3834 vm_page_aflag_clear(om, PGA_WRITEABLE);
3836 if ((origpte & PG_A) != 0)
3837 pmap_invalidate_page(pmap, va);
3841 * Increment the counters.
3843 if ((newpte & PG_W) != 0)
3844 pmap->pm_stats.wired_count++;
3845 pmap->pm_stats.resident_count++;
3849 * Enter on the PV list if part of our managed memory.
3851 if ((newpte & PG_MANAGED) != 0) {
3853 pv = get_pv_entry(pmap, FALSE);
3856 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3857 if ((newpte & PG_RW) != 0)
3858 vm_page_aflag_set(m, PGA_WRITEABLE);
3864 if ((origpte & PG_V) != 0) {
3866 origpte = pte_load_store(pte, newpte);
3867 KASSERT((origpte & PG_FRAME) == pa,
3868 ("pmap_enter: unexpected pa update for %#x", va));
3869 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
3871 if ((origpte & PG_MANAGED) != 0)
3875 * Although the PTE may still have PG_RW set, TLB
3876 * invalidation may nonetheless be required because
3877 * the PTE no longer has PG_M set.
3880 #if defined(PAE) || defined(PAE_TABLES)
3881 else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
3883 * This PTE change does not require TLB invalidation.
3888 if ((origpte & PG_A) != 0)
3889 pmap_invalidate_page(pmap, va);
3891 pte_store(pte, newpte);
3895 #if VM_NRESERVLEVEL > 0
3897 * If both the page table page and the reservation are fully
3898 * populated, then attempt promotion.
3900 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3901 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3902 vm_reserv_level_iffullpop(m) == 0)
3903 pmap_promote_pde(pmap, pde, va);
3909 rw_wunlock(&pvh_global_lock);
3915 * Tries to create a read- and/or execute-only 2 or 4 MB page mapping. Returns
3916 * true if successful. Returns false if (1) a mapping already exists at the
3917 * specified virtual address or (2) a PV entry cannot be allocated without
3918 * reclaiming another PV entry.
3921 pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3925 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3926 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
3928 if ((m->oflags & VPO_UNMANAGED) == 0)
3929 newpde |= PG_MANAGED;
3930 #if defined(PAE) || defined(PAE_TABLES)
3931 if ((prot & VM_PROT_EXECUTE) == 0)
3934 if (pmap != kernel_pmap)
3936 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
3937 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL) ==
3942 * Tries to create the specified 2 or 4 MB page mapping. Returns KERN_SUCCESS
3943 * if the mapping was created, and either KERN_FAILURE or
3944 * KERN_RESOURCE_SHORTAGE otherwise. Returns KERN_FAILURE if
3945 * PMAP_ENTER_NOREPLACE was specified and a mapping already exists at the
3946 * specified virtual address. Returns KERN_RESOURCE_SHORTAGE if
3947 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3949 * The parameter "m" is only used when creating a managed, writeable mapping.
3952 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
3955 struct spglist free;
3956 pd_entry_t oldpde, *pde;
3959 rw_assert(&pvh_global_lock, RA_WLOCKED);
3960 KASSERT((newpde & (PG_M | PG_RW)) != PG_RW,
3961 ("pmap_enter_pde: newpde is missing PG_M"));
3962 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3963 pde = pmap_pde(pmap, va);
3965 if ((oldpde & PG_V) != 0) {
3966 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
3967 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3968 " in pmap %p", va, pmap);
3969 return (KERN_FAILURE);
3971 /* Break the existing mapping(s). */
3973 if ((oldpde & PG_PS) != 0) {
3975 * If the PDE resulted from a promotion, then a
3976 * reserved PT page could be freed.
3978 (void)pmap_remove_pde(pmap, pde, va, &free);
3979 if ((oldpde & PG_G) == 0)
3980 pmap_invalidate_pde_page(pmap, va, oldpde);
3982 if (pmap_remove_ptes(pmap, va, va + NBPDR, &free))
3983 pmap_invalidate_all(pmap);
3985 vm_page_free_pages_toq(&free, true);
3986 if (pmap == kernel_pmap) {
3987 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3988 if (pmap_insert_pt_page(pmap, mt)) {
3990 * XXX Currently, this can't happen because
3991 * we do not perform pmap_enter(psind == 1)
3992 * on the kernel pmap.
3994 panic("pmap_enter_pde: trie insert failed");
3997 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
4000 if ((newpde & PG_MANAGED) != 0) {
4002 * Abort this mapping if its PV entry could not be created.
4004 if (!pmap_pv_insert_pde(pmap, va, newpde, flags)) {
4005 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4006 " in pmap %p", va, pmap);
4007 return (KERN_RESOURCE_SHORTAGE);
4009 if ((newpde & PG_RW) != 0) {
4010 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4011 vm_page_aflag_set(mt, PGA_WRITEABLE);
4016 * Increment counters.
4018 if ((newpde & PG_W) != 0)
4019 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
4020 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
4023 * Map the superpage. (This is not a promoted mapping; there will not
4024 * be any lingering 4KB page mappings in the TLB.)
4026 pde_store(pde, newpde);
4028 pmap_pde_mappings++;
4029 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
4030 " in pmap %p", va, pmap);
4031 return (KERN_SUCCESS);
4035 * Maps a sequence of resident pages belonging to the same object.
4036 * The sequence begins with the given page m_start. This page is
4037 * mapped at the given virtual address start. Each subsequent page is
4038 * mapped at a virtual address that is offset from start by the same
4039 * amount as the page is offset from m_start within the object. The
4040 * last page in the sequence is the page with the largest offset from
4041 * m_start that can be mapped at a virtual address less than the given
4042 * virtual address end. Not every virtual page between start and end
4043 * is mapped; only those for which a resident page exists with the
4044 * corresponding offset from m_start are mapped.
4047 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4048 vm_page_t m_start, vm_prot_t prot)
4052 vm_pindex_t diff, psize;
4054 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4056 psize = atop(end - start);
4059 rw_wlock(&pvh_global_lock);
4061 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4062 va = start + ptoa(diff);
4063 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
4064 m->psind == 1 && pg_ps_enabled &&
4065 pmap_enter_4mpage(pmap, va, m, prot))
4066 m = &m[NBPDR / PAGE_SIZE - 1];
4068 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
4070 m = TAILQ_NEXT(m, listq);
4072 rw_wunlock(&pvh_global_lock);
4077 * this code makes some *MAJOR* assumptions:
4078 * 1. Current pmap & pmap exists.
4081 * 4. No page table pages.
4082 * but is *MUCH* faster than pmap_enter...
4086 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4089 rw_wlock(&pvh_global_lock);
4091 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
4092 rw_wunlock(&pvh_global_lock);
4097 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4098 vm_prot_t prot, vm_page_t mpte)
4100 pt_entry_t newpte, *pte;
4101 struct spglist free;
4103 KASSERT(pmap != kernel_pmap || va < kmi.clean_sva ||
4104 va >= kmi.clean_eva || (m->oflags & VPO_UNMANAGED) != 0,
4105 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4106 rw_assert(&pvh_global_lock, RA_WLOCKED);
4107 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4110 * In the case that a page table page is not
4111 * resident, we are creating it here.
4113 if (pmap != kernel_pmap) {
4118 * Calculate pagetable page index
4120 ptepindex = va >> PDRSHIFT;
4121 if (mpte && (mpte->pindex == ptepindex)) {
4125 * Get the page directory entry
4127 ptepa = pmap->pm_pdir[ptepindex];
4130 * If the page table page is mapped, we just increment
4131 * the hold count, and activate it.
4136 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
4139 mpte = _pmap_allocpte(pmap, ptepindex,
4140 PMAP_ENTER_NOSLEEP);
4150 pte = pmap_pte_quick(pmap, va);
4161 * Enter on the PV list if part of our managed memory.
4163 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4164 !pmap_try_insert_pv_entry(pmap, va, m)) {
4167 if (pmap_unwire_ptp(pmap, mpte, &free)) {
4168 pmap_invalidate_page(pmap, va);
4169 vm_page_free_pages_toq(&free, true);
4179 * Increment counters
4181 pmap->pm_stats.resident_count++;
4183 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
4184 pmap_cache_bits(pmap, m->md.pat_mode, 0);
4185 if ((m->oflags & VPO_UNMANAGED) == 0)
4186 newpte |= PG_MANAGED;
4187 #if defined(PAE) || defined(PAE_TABLES)
4188 if ((prot & VM_PROT_EXECUTE) == 0)
4191 if (pmap != kernel_pmap)
4193 pte_store(pte, newpte);
4199 * Make a temporary mapping for a physical address. This is only intended
4200 * to be used for panic dumps.
4203 pmap_kenter_temporary(vm_paddr_t pa, int i)
4207 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
4208 pmap_kenter(va, pa);
4210 return ((void *)crashdumpmap);
4214 * This code maps large physical mmap regions into the
4215 * processor address space. Note that some shortcuts
4216 * are taken, but the code works.
4219 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4220 vm_pindex_t pindex, vm_size_t size)
4223 vm_paddr_t pa, ptepa;
4227 VM_OBJECT_ASSERT_WLOCKED(object);
4228 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4229 ("pmap_object_init_pt: non-device object"));
4230 if (pg_ps_enabled &&
4231 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
4232 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4234 p = vm_page_lookup(object, pindex);
4235 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4236 ("pmap_object_init_pt: invalid page %p", p));
4237 pat_mode = p->md.pat_mode;
4240 * Abort the mapping if the first page is not physically
4241 * aligned to a 2/4MB page boundary.
4243 ptepa = VM_PAGE_TO_PHYS(p);
4244 if (ptepa & (NBPDR - 1))
4248 * Skip the first page. Abort the mapping if the rest of
4249 * the pages are not physically contiguous or have differing
4250 * memory attributes.
4252 p = TAILQ_NEXT(p, listq);
4253 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4255 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4256 ("pmap_object_init_pt: invalid page %p", p));
4257 if (pa != VM_PAGE_TO_PHYS(p) ||
4258 pat_mode != p->md.pat_mode)
4260 p = TAILQ_NEXT(p, listq);
4264 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
4265 * "size" is a multiple of 2/4M, adding the PAT setting to
4266 * "pa" will not affect the termination of this loop.
4269 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
4270 pa < ptepa + size; pa += NBPDR) {
4271 pde = pmap_pde(pmap, addr);
4273 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4274 PG_U | PG_RW | PG_V);
4275 pmap->pm_stats.resident_count += NBPDR /
4277 pmap_pde_mappings++;
4279 /* Else continue on if the PDE is already valid. */
4287 * Clear the wired attribute from the mappings for the specified range of
4288 * addresses in the given pmap. Every valid mapping within that range
4289 * must have the wired attribute set. In contrast, invalid mappings
4290 * cannot have the wired attribute set, so they are ignored.
4292 * The wired attribute of the page table entry is not a hardware feature,
4293 * so there is no need to invalidate any TLB entries.
4296 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4301 boolean_t pv_lists_locked;
4303 if (pmap_is_current(pmap))
4304 pv_lists_locked = FALSE;
4306 pv_lists_locked = TRUE;
4308 rw_wlock(&pvh_global_lock);
4312 for (; sva < eva; sva = pdnxt) {
4313 pdnxt = (sva + NBPDR) & ~PDRMASK;
4316 pde = pmap_pde(pmap, sva);
4317 if ((*pde & PG_V) == 0)
4319 if ((*pde & PG_PS) != 0) {
4320 if ((*pde & PG_W) == 0)
4321 panic("pmap_unwire: pde %#jx is missing PG_W",
4325 * Are we unwiring the entire large page? If not,
4326 * demote the mapping and fall through.
4328 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4330 * Regardless of whether a pde (or pte) is 32
4331 * or 64 bits in size, PG_W is among the least
4332 * significant 32 bits.
4334 atomic_clear_int((u_int *)pde, PG_W);
4335 pmap->pm_stats.wired_count -= NBPDR /
4339 if (!pv_lists_locked) {
4340 pv_lists_locked = TRUE;
4341 if (!rw_try_wlock(&pvh_global_lock)) {
4348 if (!pmap_demote_pde(pmap, pde, sva))
4349 panic("pmap_unwire: demotion failed");
4354 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4356 if ((*pte & PG_V) == 0)
4358 if ((*pte & PG_W) == 0)
4359 panic("pmap_unwire: pte %#jx is missing PG_W",
4363 * PG_W must be cleared atomically. Although the pmap
4364 * lock synchronizes access to PG_W, another processor
4365 * could be setting PG_M and/or PG_A concurrently.
4367 * PG_W is among the least significant 32 bits.
4369 atomic_clear_int((u_int *)pte, PG_W);
4370 pmap->pm_stats.wired_count--;
4373 if (pv_lists_locked) {
4375 rw_wunlock(&pvh_global_lock);
4382 * Copy the range specified by src_addr/len
4383 * from the source map to the range dst_addr/len
4384 * in the destination map.
4386 * This routine is only advisory and need not do anything. Since
4387 * current pmap is always the kernel pmap when executing in
4388 * kernel, and we do not copy from the kernel pmap to a user
4389 * pmap, this optimization is not usable in 4/4G full split i386
4394 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4395 vm_offset_t src_addr)
4397 struct spglist free;
4398 pt_entry_t *src_pte, *dst_pte, ptetemp;
4399 pd_entry_t srcptepaddr;
4400 vm_page_t dstmpte, srcmpte;
4401 vm_offset_t addr, end_addr, pdnxt;
4404 if (dst_addr != src_addr)
4407 end_addr = src_addr + len;
4409 rw_wlock(&pvh_global_lock);
4410 if (dst_pmap < src_pmap) {
4411 PMAP_LOCK(dst_pmap);
4412 PMAP_LOCK(src_pmap);
4414 PMAP_LOCK(src_pmap);
4415 PMAP_LOCK(dst_pmap);
4418 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4419 KASSERT(addr < PMAP_TRM_MIN_ADDRESS,
4420 ("pmap_copy: invalid to pmap_copy the trampoline"));
4422 pdnxt = (addr + NBPDR) & ~PDRMASK;
4425 ptepindex = addr >> PDRSHIFT;
4427 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4428 if (srcptepaddr == 0)
4431 if (srcptepaddr & PG_PS) {
4432 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4434 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4435 ((srcptepaddr & PG_MANAGED) == 0 ||
4436 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
4437 PMAP_ENTER_NORECLAIM))) {
4438 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4440 dst_pmap->pm_stats.resident_count +=
4442 pmap_pde_mappings++;
4447 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4448 KASSERT(srcmpte->wire_count > 0,
4449 ("pmap_copy: source page table page is unused"));
4451 if (pdnxt > end_addr)
4454 src_pte = pmap_pte_quick3(src_pmap, addr);
4455 while (addr < pdnxt) {
4458 * we only virtual copy managed pages
4460 if ((ptetemp & PG_MANAGED) != 0) {
4461 dstmpte = pmap_allocpte(dst_pmap, addr,
4462 PMAP_ENTER_NOSLEEP);
4463 if (dstmpte == NULL)
4465 dst_pte = pmap_pte_quick(dst_pmap, addr);
4466 if (*dst_pte == 0 &&
4467 pmap_try_insert_pv_entry(dst_pmap, addr,
4468 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4470 * Clear the wired, modified, and
4471 * accessed (referenced) bits
4474 *dst_pte = ptetemp & ~(PG_W | PG_M |
4476 dst_pmap->pm_stats.resident_count++;
4479 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4481 pmap_invalidate_page(dst_pmap,
4483 vm_page_free_pages_toq(&free,
4488 if (dstmpte->wire_count >= srcmpte->wire_count)
4497 rw_wunlock(&pvh_global_lock);
4498 PMAP_UNLOCK(src_pmap);
4499 PMAP_UNLOCK(dst_pmap);
4503 * Zero 1 page of virtual memory mapped from a hardware page by the caller.
4505 static __inline void
4506 pagezero(void *page)
4508 #if defined(I686_CPU)
4509 if (cpu_class == CPUCLASS_686) {
4510 if (cpu_feature & CPUID_SSE2)
4511 sse2_pagezero(page);
4513 i686_pagezero(page);
4516 bzero(page, PAGE_SIZE);
4520 * Zero the specified hardware page.
4523 pmap_zero_page(vm_page_t m)
4525 pt_entry_t *cmap_pte2;
4530 cmap_pte2 = pc->pc_cmap_pte2;
4531 mtx_lock(&pc->pc_cmap_lock);
4533 panic("pmap_zero_page: CMAP2 busy");
4534 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4535 pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
4536 invlcaddr(pc->pc_cmap_addr2);
4537 pagezero(pc->pc_cmap_addr2);
4541 * Unpin the thread before releasing the lock. Otherwise the thread
4542 * could be rescheduled while still bound to the current CPU, only
4543 * to unpin itself immediately upon resuming execution.
4546 mtx_unlock(&pc->pc_cmap_lock);
4550 * Zero an an area within a single hardware page. off and size must not
4551 * cover an area beyond a single hardware page.
4554 pmap_zero_page_area(vm_page_t m, int off, int size)
4556 pt_entry_t *cmap_pte2;
4561 cmap_pte2 = pc->pc_cmap_pte2;
4562 mtx_lock(&pc->pc_cmap_lock);
4564 panic("pmap_zero_page_area: CMAP2 busy");
4565 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4566 pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
4567 invlcaddr(pc->pc_cmap_addr2);
4568 if (off == 0 && size == PAGE_SIZE)
4569 pagezero(pc->pc_cmap_addr2);
4571 bzero(pc->pc_cmap_addr2 + off, size);
4574 mtx_unlock(&pc->pc_cmap_lock);
4578 * Copy 1 specified hardware page to another.
4581 pmap_copy_page(vm_page_t src, vm_page_t dst)
4583 pt_entry_t *cmap_pte1, *cmap_pte2;
4588 cmap_pte1 = pc->pc_cmap_pte1;
4589 cmap_pte2 = pc->pc_cmap_pte2;
4590 mtx_lock(&pc->pc_cmap_lock);
4592 panic("pmap_copy_page: CMAP1 busy");
4594 panic("pmap_copy_page: CMAP2 busy");
4595 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4596 pmap_cache_bits(kernel_pmap, src->md.pat_mode, 0);
4597 invlcaddr(pc->pc_cmap_addr1);
4598 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4599 pmap_cache_bits(kernel_pmap, dst->md.pat_mode, 0);
4600 invlcaddr(pc->pc_cmap_addr2);
4601 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE);
4605 mtx_unlock(&pc->pc_cmap_lock);
4608 int unmapped_buf_allowed = 1;
4611 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4612 vm_offset_t b_offset, int xfersize)
4614 vm_page_t a_pg, b_pg;
4616 vm_offset_t a_pg_offset, b_pg_offset;
4617 pt_entry_t *cmap_pte1, *cmap_pte2;
4623 cmap_pte1 = pc->pc_cmap_pte1;
4624 cmap_pte2 = pc->pc_cmap_pte2;
4625 mtx_lock(&pc->pc_cmap_lock);
4626 if (*cmap_pte1 != 0)
4627 panic("pmap_copy_pages: CMAP1 busy");
4628 if (*cmap_pte2 != 0)
4629 panic("pmap_copy_pages: CMAP2 busy");
4630 while (xfersize > 0) {
4631 a_pg = ma[a_offset >> PAGE_SHIFT];
4632 a_pg_offset = a_offset & PAGE_MASK;
4633 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4634 b_pg = mb[b_offset >> PAGE_SHIFT];
4635 b_pg_offset = b_offset & PAGE_MASK;
4636 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4637 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4638 pmap_cache_bits(kernel_pmap, a_pg->md.pat_mode, 0);
4639 invlcaddr(pc->pc_cmap_addr1);
4640 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4641 PG_M | pmap_cache_bits(kernel_pmap, b_pg->md.pat_mode, 0);
4642 invlcaddr(pc->pc_cmap_addr2);
4643 a_cp = pc->pc_cmap_addr1 + a_pg_offset;
4644 b_cp = pc->pc_cmap_addr2 + b_pg_offset;
4645 bcopy(a_cp, b_cp, cnt);
4653 mtx_unlock(&pc->pc_cmap_lock);
4657 * Returns true if the pmap's pv is one of the first
4658 * 16 pvs linked to from this page. This count may
4659 * be changed upwards or downwards in the future; it
4660 * is only necessary that true be returned for a small
4661 * subset of pmaps for proper page aging.
4664 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4666 struct md_page *pvh;
4671 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4672 ("pmap_page_exists_quick: page %p is not managed", m));
4674 rw_wlock(&pvh_global_lock);
4675 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4676 if (PV_PMAP(pv) == pmap) {
4684 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4685 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4686 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4687 if (PV_PMAP(pv) == pmap) {
4696 rw_wunlock(&pvh_global_lock);
4701 * pmap_page_wired_mappings:
4703 * Return the number of managed mappings to the given physical page
4707 pmap_page_wired_mappings(vm_page_t m)
4712 if ((m->oflags & VPO_UNMANAGED) != 0)
4714 rw_wlock(&pvh_global_lock);
4715 count = pmap_pvh_wired_mappings(&m->md, count);
4716 if ((m->flags & PG_FICTITIOUS) == 0) {
4717 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4720 rw_wunlock(&pvh_global_lock);
4725 * pmap_pvh_wired_mappings:
4727 * Return the updated number "count" of managed mappings that are wired.
4730 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4736 rw_assert(&pvh_global_lock, RA_WLOCKED);
4738 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4741 pte = pmap_pte_quick(pmap, pv->pv_va);
4742 if ((*pte & PG_W) != 0)
4751 * Returns TRUE if the given page is mapped individually or as part of
4752 * a 4mpage. Otherwise, returns FALSE.
4755 pmap_page_is_mapped(vm_page_t m)
4759 if ((m->oflags & VPO_UNMANAGED) != 0)
4761 rw_wlock(&pvh_global_lock);
4762 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4763 ((m->flags & PG_FICTITIOUS) == 0 &&
4764 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4765 rw_wunlock(&pvh_global_lock);
4770 * Remove all pages from specified address space
4771 * this aids process exit speeds. Also, this code
4772 * is special cased for current process only, but
4773 * can have the more generic (and slightly slower)
4774 * mode enabled. This is much faster than pmap_remove
4775 * in the case of running down an entire address space.
4778 pmap_remove_pages(pmap_t pmap)
4780 pt_entry_t *pte, tpte;
4781 vm_page_t m, mpte, mt;
4783 struct md_page *pvh;
4784 struct pv_chunk *pc, *npc;
4785 struct spglist free;
4788 uint32_t inuse, bitmask;
4791 if (pmap != PCPU_GET(curpmap)) {
4792 printf("warning: pmap_remove_pages called with non-current pmap\n");
4796 rw_wlock(&pvh_global_lock);
4799 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4800 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4803 for (field = 0; field < _NPCM; field++) {
4804 inuse = ~pc->pc_map[field] & pc_freemask[field];
4805 while (inuse != 0) {
4807 bitmask = 1UL << bit;
4808 idx = field * 32 + bit;
4809 pv = &pc->pc_pventry[idx];
4812 pte = pmap_pde(pmap, pv->pv_va);
4814 if ((tpte & PG_PS) == 0) {
4815 pte = pmap_pte_quick(pmap, pv->pv_va);
4816 tpte = *pte & ~PG_PTE_PAT;
4821 "TPTE at %p IS ZERO @ VA %08x\n",
4827 * We cannot remove wired pages from a process' mapping at this time
4834 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4835 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4836 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4837 m, (uintmax_t)m->phys_addr,
4840 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4841 m < &vm_page_array[vm_page_array_size],
4842 ("pmap_remove_pages: bad tpte %#jx",
4848 * Update the vm_page_t clean/reference bits.
4850 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4851 if ((tpte & PG_PS) != 0) {
4852 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4859 PV_STAT(pv_entry_frees++);
4860 PV_STAT(pv_entry_spare++);
4862 pc->pc_map[field] |= bitmask;
4863 if ((tpte & PG_PS) != 0) {
4864 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4865 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4866 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4867 if (TAILQ_EMPTY(&pvh->pv_list)) {
4868 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4869 if (TAILQ_EMPTY(&mt->md.pv_list))
4870 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4872 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
4874 pmap->pm_stats.resident_count--;
4875 KASSERT(mpte->wire_count == NPTEPG,
4876 ("pmap_remove_pages: pte page wire count error"));
4877 mpte->wire_count = 0;
4878 pmap_add_delayed_free_list(mpte, &free, FALSE);
4881 pmap->pm_stats.resident_count--;
4882 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4883 if (TAILQ_EMPTY(&m->md.pv_list) &&
4884 (m->flags & PG_FICTITIOUS) == 0) {
4885 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4886 if (TAILQ_EMPTY(&pvh->pv_list))
4887 vm_page_aflag_clear(m, PGA_WRITEABLE);
4889 pmap_unuse_pt(pmap, pv->pv_va, &free);
4894 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4899 pmap_invalidate_all(pmap);
4900 rw_wunlock(&pvh_global_lock);
4902 vm_page_free_pages_toq(&free, true);
4908 * Return whether or not the specified physical page was modified
4909 * in any physical maps.
4912 pmap_is_modified(vm_page_t m)
4916 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4917 ("pmap_is_modified: page %p is not managed", m));
4920 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4921 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4922 * is clear, no PTEs can have PG_M set.
4924 VM_OBJECT_ASSERT_WLOCKED(m->object);
4925 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4927 rw_wlock(&pvh_global_lock);
4928 rv = pmap_is_modified_pvh(&m->md) ||
4929 ((m->flags & PG_FICTITIOUS) == 0 &&
4930 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4931 rw_wunlock(&pvh_global_lock);
4936 * Returns TRUE if any of the given mappings were used to modify
4937 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4938 * mappings are supported.
4941 pmap_is_modified_pvh(struct md_page *pvh)
4948 rw_assert(&pvh_global_lock, RA_WLOCKED);
4951 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4954 pte = pmap_pte_quick(pmap, pv->pv_va);
4955 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4965 * pmap_is_prefaultable:
4967 * Return whether or not the specified virtual address is elgible
4971 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4978 pde = *pmap_pde(pmap, addr);
4979 if (pde != 0 && (pde & PG_PS) == 0)
4980 rv = pmap_pte_ufast(pmap, addr, pde) == 0;
4986 * pmap_is_referenced:
4988 * Return whether or not the specified physical page was referenced
4989 * in any physical maps.
4992 pmap_is_referenced(vm_page_t m)
4996 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4997 ("pmap_is_referenced: page %p is not managed", m));
4998 rw_wlock(&pvh_global_lock);
4999 rv = pmap_is_referenced_pvh(&m->md) ||
5000 ((m->flags & PG_FICTITIOUS) == 0 &&
5001 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
5002 rw_wunlock(&pvh_global_lock);
5007 * Returns TRUE if any of the given mappings were referenced and FALSE
5008 * otherwise. Both page and 4mpage mappings are supported.
5011 pmap_is_referenced_pvh(struct md_page *pvh)
5018 rw_assert(&pvh_global_lock, RA_WLOCKED);
5021 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5024 pte = pmap_pte_quick(pmap, pv->pv_va);
5025 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
5035 * Clear the write and modified bits in each of the given page's mappings.
5038 pmap_remove_write(vm_page_t m)
5040 struct md_page *pvh;
5041 pv_entry_t next_pv, pv;
5044 pt_entry_t oldpte, *pte;
5047 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5048 ("pmap_remove_write: page %p is not managed", m));
5051 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5052 * set by another thread while the object is locked. Thus,
5053 * if PGA_WRITEABLE is clear, no page table entries need updating.
5055 VM_OBJECT_ASSERT_WLOCKED(m->object);
5056 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5058 rw_wlock(&pvh_global_lock);
5060 if ((m->flags & PG_FICTITIOUS) != 0)
5061 goto small_mappings;
5062 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5063 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5067 pde = pmap_pde(pmap, va);
5068 if ((*pde & PG_RW) != 0)
5069 (void)pmap_demote_pde(pmap, pde, va);
5073 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5076 pde = pmap_pde(pmap, pv->pv_va);
5077 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
5078 " a 4mpage in page %p's pv list", m));
5079 pte = pmap_pte_quick(pmap, pv->pv_va);
5082 if ((oldpte & PG_RW) != 0) {
5084 * Regardless of whether a pte is 32 or 64 bits
5085 * in size, PG_RW and PG_M are among the least
5086 * significant 32 bits.
5088 if (!atomic_cmpset_int((u_int *)pte, oldpte,
5089 oldpte & ~(PG_RW | PG_M)))
5091 if ((oldpte & PG_M) != 0)
5093 pmap_invalidate_page(pmap, pv->pv_va);
5097 vm_page_aflag_clear(m, PGA_WRITEABLE);
5099 rw_wunlock(&pvh_global_lock);
5103 * pmap_ts_referenced:
5105 * Return a count of reference bits for a page, clearing those bits.
5106 * It is not necessary for every reference bit to be cleared, but it
5107 * is necessary that 0 only be returned when there are truly no
5108 * reference bits set.
5110 * As an optimization, update the page's dirty field if a modified bit is
5111 * found while counting reference bits. This opportunistic update can be
5112 * performed at low cost and can eliminate the need for some future calls
5113 * to pmap_is_modified(). However, since this function stops after
5114 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5115 * dirty pages. Those dirty pages will only be detected by a future call
5116 * to pmap_is_modified().
5119 pmap_ts_referenced(vm_page_t m)
5121 struct md_page *pvh;
5129 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5130 ("pmap_ts_referenced: page %p is not managed", m));
5131 pa = VM_PAGE_TO_PHYS(m);
5132 pvh = pa_to_pvh(pa);
5133 rw_wlock(&pvh_global_lock);
5135 if ((m->flags & PG_FICTITIOUS) != 0 ||
5136 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5137 goto small_mappings;
5142 pde = pmap_pde(pmap, pv->pv_va);
5143 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5145 * Although "*pde" is mapping a 2/4MB page, because
5146 * this function is called at a 4KB page granularity,
5147 * we only update the 4KB page under test.
5151 if ((*pde & PG_A) != 0) {
5153 * Since this reference bit is shared by either 1024
5154 * or 512 4KB pages, it should not be cleared every
5155 * time it is tested. Apply a simple "hash" function
5156 * on the physical page number, the virtual superpage
5157 * number, and the pmap address to select one 4KB page
5158 * out of the 1024 or 512 on which testing the
5159 * reference bit will result in clearing that bit.
5160 * This function is designed to avoid the selection of
5161 * the same 4KB page for every 2- or 4MB page mapping.
5163 * On demotion, a mapping that hasn't been referenced
5164 * is simply destroyed. To avoid the possibility of a
5165 * subsequent page fault on a demoted wired mapping,
5166 * always leave its reference bit set. Moreover,
5167 * since the superpage is wired, the current state of
5168 * its reference bit won't affect page replacement.
5170 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
5171 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
5172 (*pde & PG_W) == 0) {
5173 atomic_clear_int((u_int *)pde, PG_A);
5174 pmap_invalidate_page(pmap, pv->pv_va);
5179 /* Rotate the PV list if it has more than one entry. */
5180 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5181 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5182 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5184 if (rtval >= PMAP_TS_REFERENCED_MAX)
5186 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5188 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5194 pde = pmap_pde(pmap, pv->pv_va);
5195 KASSERT((*pde & PG_PS) == 0,
5196 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
5198 pte = pmap_pte_quick(pmap, pv->pv_va);
5199 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5201 if ((*pte & PG_A) != 0) {
5202 atomic_clear_int((u_int *)pte, PG_A);
5203 pmap_invalidate_page(pmap, pv->pv_va);
5207 /* Rotate the PV list if it has more than one entry. */
5208 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5209 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5210 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5212 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
5213 PMAP_TS_REFERENCED_MAX);
5216 rw_wunlock(&pvh_global_lock);
5221 * Apply the given advice to the specified range of addresses within the
5222 * given pmap. Depending on the advice, clear the referenced and/or
5223 * modified flags in each mapping and set the mapped page's dirty field.
5226 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5228 pd_entry_t oldpde, *pde;
5230 vm_offset_t va, pdnxt;
5232 boolean_t anychanged, pv_lists_locked;
5234 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5236 if (pmap_is_current(pmap))
5237 pv_lists_locked = FALSE;
5239 pv_lists_locked = TRUE;
5241 rw_wlock(&pvh_global_lock);
5246 for (; sva < eva; sva = pdnxt) {
5247 pdnxt = (sva + NBPDR) & ~PDRMASK;
5250 pde = pmap_pde(pmap, sva);
5252 if ((oldpde & PG_V) == 0)
5254 else if ((oldpde & PG_PS) != 0) {
5255 if ((oldpde & PG_MANAGED) == 0)
5257 if (!pv_lists_locked) {
5258 pv_lists_locked = TRUE;
5259 if (!rw_try_wlock(&pvh_global_lock)) {
5261 pmap_invalidate_all(pmap);
5267 if (!pmap_demote_pde(pmap, pde, sva)) {
5269 * The large page mapping was destroyed.
5275 * Unless the page mappings are wired, remove the
5276 * mapping to a single page so that a subsequent
5277 * access may repromote. Since the underlying page
5278 * table page is fully populated, this removal never
5279 * frees a page table page.
5281 if ((oldpde & PG_W) == 0) {
5282 pte = pmap_pte_quick(pmap, sva);
5283 KASSERT((*pte & PG_V) != 0,
5284 ("pmap_advise: invalid PTE"));
5285 pmap_remove_pte(pmap, pte, sva, NULL);
5292 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
5294 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
5296 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5297 if (advice == MADV_DONTNEED) {
5299 * Future calls to pmap_is_modified()
5300 * can be avoided by making the page
5303 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
5306 atomic_clear_int((u_int *)pte, PG_M | PG_A);
5307 } else if ((*pte & PG_A) != 0)
5308 atomic_clear_int((u_int *)pte, PG_A);
5311 if ((*pte & PG_G) != 0) {
5319 pmap_invalidate_range(pmap, va, sva);
5324 pmap_invalidate_range(pmap, va, sva);
5327 pmap_invalidate_all(pmap);
5328 if (pv_lists_locked) {
5330 rw_wunlock(&pvh_global_lock);
5336 * Clear the modify bits on the specified physical page.
5339 pmap_clear_modify(vm_page_t m)
5341 struct md_page *pvh;
5342 pv_entry_t next_pv, pv;
5344 pd_entry_t oldpde, *pde;
5345 pt_entry_t oldpte, *pte;
5348 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5349 ("pmap_clear_modify: page %p is not managed", m));
5350 VM_OBJECT_ASSERT_WLOCKED(m->object);
5351 KASSERT(!vm_page_xbusied(m),
5352 ("pmap_clear_modify: page %p is exclusive busied", m));
5355 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5356 * If the object containing the page is locked and the page is not
5357 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5359 if ((m->aflags & PGA_WRITEABLE) == 0)
5361 rw_wlock(&pvh_global_lock);
5363 if ((m->flags & PG_FICTITIOUS) != 0)
5364 goto small_mappings;
5365 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5366 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5370 pde = pmap_pde(pmap, va);
5372 if ((oldpde & PG_RW) != 0) {
5373 if (pmap_demote_pde(pmap, pde, va)) {
5374 if ((oldpde & PG_W) == 0) {
5376 * Write protect the mapping to a
5377 * single page so that a subsequent
5378 * write access may repromote.
5380 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5382 pte = pmap_pte_quick(pmap, va);
5384 if ((oldpte & PG_V) != 0) {
5386 * Regardless of whether a pte is 32 or 64 bits
5387 * in size, PG_RW and PG_M are among the least
5388 * significant 32 bits.
5390 while (!atomic_cmpset_int((u_int *)pte,
5392 oldpte & ~(PG_M | PG_RW)))
5395 pmap_invalidate_page(pmap, va);
5403 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5406 pde = pmap_pde(pmap, pv->pv_va);
5407 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5408 " a 4mpage in page %p's pv list", m));
5409 pte = pmap_pte_quick(pmap, pv->pv_va);
5410 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5412 * Regardless of whether a pte is 32 or 64 bits
5413 * in size, PG_M is among the least significant
5416 atomic_clear_int((u_int *)pte, PG_M);
5417 pmap_invalidate_page(pmap, pv->pv_va);
5422 rw_wunlock(&pvh_global_lock);
5426 * Miscellaneous support routines follow
5429 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5430 static __inline void
5431 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5436 * The cache mode bits are all in the low 32-bits of the
5437 * PTE, so we can just spin on updating the low 32-bits.
5440 opte = *(u_int *)pte;
5441 npte = opte & ~PG_PTE_CACHE;
5443 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5446 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5447 static __inline void
5448 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5453 * The cache mode bits are all in the low 32-bits of the
5454 * PDE, so we can just spin on updating the low 32-bits.
5457 opde = *(u_int *)pde;
5458 npde = opde & ~PG_PDE_CACHE;
5460 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5464 * Map a set of physical memory pages into the kernel virtual
5465 * address space. Return a pointer to where it is mapped. This
5466 * routine is intended to be used for mapping device memory,
5470 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5472 struct pmap_preinit_mapping *ppim;
5473 vm_offset_t va, offset;
5477 offset = pa & PAGE_MASK;
5478 size = round_page(offset + size);
5481 if (pa < PMAP_MAP_LOW && pa + size <= PMAP_MAP_LOW)
5482 va = pa + PMAP_MAP_LOW;
5483 else if (!pmap_initialized) {
5485 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5486 ppim = pmap_preinit_mapping + i;
5487 if (ppim->va == 0) {
5491 ppim->va = virtual_avail;
5492 virtual_avail += size;
5498 panic("%s: too many preinit mappings", __func__);
5501 * If we have a preinit mapping, re-use it.
5503 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5504 ppim = pmap_preinit_mapping + i;
5505 if (ppim->pa == pa && ppim->sz == size &&
5507 return ((void *)(ppim->va + offset));
5509 va = kva_alloc(size);
5511 panic("%s: Couldn't allocate KVA", __func__);
5513 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5514 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5515 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5516 pmap_invalidate_cache_range(va, va + size);
5517 return ((void *)(va + offset));
5521 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5524 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5528 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5531 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5535 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5537 struct pmap_preinit_mapping *ppim;
5541 if (va >= PMAP_MAP_LOW && va <= KERNBASE && va + size <= KERNBASE)
5543 offset = va & PAGE_MASK;
5544 size = round_page(offset + size);
5545 va = trunc_page(va);
5546 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5547 ppim = pmap_preinit_mapping + i;
5548 if (ppim->va == va && ppim->sz == size) {
5549 if (pmap_initialized)
5555 if (va + size == virtual_avail)
5560 if (pmap_initialized)
5565 * Sets the memory attribute for the specified page.
5568 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5571 m->md.pat_mode = ma;
5572 if ((m->flags & PG_FICTITIOUS) != 0)
5576 * If "m" is a normal page, flush it from the cache.
5577 * See pmap_invalidate_cache_range().
5579 * First, try to find an existing mapping of the page by sf
5580 * buffer. sf_buf_invalidate_cache() modifies mapping and
5581 * flushes the cache.
5583 if (sf_buf_invalidate_cache(m))
5587 * If page is not mapped by sf buffer, but CPU does not
5588 * support self snoop, map the page transient and do
5589 * invalidation. In the worst case, whole cache is flushed by
5590 * pmap_invalidate_cache_range().
5592 if ((cpu_feature & CPUID_SS) == 0)
5597 pmap_flush_page(vm_page_t m)
5599 pt_entry_t *cmap_pte2;
5601 vm_offset_t sva, eva;
5604 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5605 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5608 cmap_pte2 = pc->pc_cmap_pte2;
5609 mtx_lock(&pc->pc_cmap_lock);
5611 panic("pmap_flush_page: CMAP2 busy");
5612 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5613 PG_A | PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode,
5615 invlcaddr(pc->pc_cmap_addr2);
5616 sva = (vm_offset_t)pc->pc_cmap_addr2;
5617 eva = sva + PAGE_SIZE;
5620 * Use mfence or sfence despite the ordering implied by
5621 * mtx_{un,}lock() because clflush on non-Intel CPUs
5622 * and clflushopt are not guaranteed to be ordered by
5623 * any other instruction.
5627 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5629 for (; sva < eva; sva += cpu_clflush_line_size) {
5637 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5641 mtx_unlock(&pc->pc_cmap_lock);
5643 pmap_invalidate_cache();
5647 * Changes the specified virtual address range's memory type to that given by
5648 * the parameter "mode". The specified virtual address range must be
5649 * completely contained within either the kernel map.
5651 * Returns zero if the change completed successfully, and either EINVAL or
5652 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5653 * of the virtual address range was not mapped, and ENOMEM is returned if
5654 * there was insufficient memory available to complete the change.
5657 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5659 vm_offset_t base, offset, tmpva;
5662 int cache_bits_pte, cache_bits_pde;
5665 base = trunc_page(va);
5666 offset = va & PAGE_MASK;
5667 size = round_page(offset + size);
5670 * Only supported on kernel virtual addresses above the recursive map.
5672 if (base < VM_MIN_KERNEL_ADDRESS)
5675 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
5676 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
5680 * Pages that aren't mapped aren't supported. Also break down
5681 * 2/4MB pages into 4KB pages if required.
5683 PMAP_LOCK(kernel_pmap);
5684 for (tmpva = base; tmpva < base + size; ) {
5685 pde = pmap_pde(kernel_pmap, tmpva);
5687 PMAP_UNLOCK(kernel_pmap);
5692 * If the current 2/4MB page already has
5693 * the required memory type, then we need not
5694 * demote this page. Just increment tmpva to
5695 * the next 2/4MB page frame.
5697 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5698 tmpva = trunc_4mpage(tmpva) + NBPDR;
5703 * If the current offset aligns with a 2/4MB
5704 * page frame and there is at least 2/4MB left
5705 * within the range, then we need not break
5706 * down this page into 4KB pages.
5708 if ((tmpva & PDRMASK) == 0 &&
5709 tmpva + PDRMASK < base + size) {
5713 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5714 PMAP_UNLOCK(kernel_pmap);
5718 pte = vtopte(tmpva);
5720 PMAP_UNLOCK(kernel_pmap);
5725 PMAP_UNLOCK(kernel_pmap);
5728 * Ok, all the pages exist, so run through them updating their
5729 * cache mode if required.
5731 for (tmpva = base; tmpva < base + size; ) {
5732 pde = pmap_pde(kernel_pmap, tmpva);
5734 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5735 pmap_pde_attr(pde, cache_bits_pde);
5738 tmpva = trunc_4mpage(tmpva) + NBPDR;
5740 pte = vtopte(tmpva);
5741 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5742 pmap_pte_attr(pte, cache_bits_pte);
5750 * Flush CPU caches to make sure any data isn't cached that
5751 * shouldn't be, etc.
5754 pmap_invalidate_range(kernel_pmap, base, tmpva);
5755 pmap_invalidate_cache_range(base, tmpva);
5761 * perform the pmap work for mincore
5764 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5773 pde = *pmap_pde(pmap, addr);
5775 if ((pde & PG_PS) != 0) {
5777 /* Compute the physical address of the 4KB page. */
5778 pa = ((pde & PG_PS_FRAME) | (addr & PDRMASK)) &
5780 val = MINCORE_SUPER;
5782 pte = pmap_pte_ufast(pmap, addr, pde);
5783 pa = pte & PG_FRAME;
5791 if ((pte & PG_V) != 0) {
5792 val |= MINCORE_INCORE;
5793 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5794 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5795 if ((pte & PG_A) != 0)
5796 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5798 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5799 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5800 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5801 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5802 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5805 PA_UNLOCK_COND(*locked_pa);
5811 pmap_activate(struct thread *td)
5813 pmap_t pmap, oldpmap;
5818 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5819 oldpmap = PCPU_GET(curpmap);
5820 cpuid = PCPU_GET(cpuid);
5822 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5823 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5825 CPU_CLR(cpuid, &oldpmap->pm_active);
5826 CPU_SET(cpuid, &pmap->pm_active);
5828 #if defined(PAE) || defined(PAE_TABLES)
5829 cr3 = vtophys(pmap->pm_pdpt);
5831 cr3 = vtophys(pmap->pm_pdir);
5834 * pmap_activate is for the current thread on the current cpu
5836 td->td_pcb->pcb_cr3 = cr3;
5837 PCPU_SET(curpmap, pmap);
5842 pmap_activate_boot(pmap_t pmap)
5846 cpuid = PCPU_GET(cpuid);
5848 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5850 CPU_SET(cpuid, &pmap->pm_active);
5852 PCPU_SET(curpmap, pmap);
5856 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5861 * Increase the starting virtual address of the given mapping if a
5862 * different alignment might result in more superpage mappings.
5865 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5866 vm_offset_t *addr, vm_size_t size)
5868 vm_offset_t superpage_offset;
5872 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5873 offset += ptoa(object->pg_color);
5874 superpage_offset = offset & PDRMASK;
5875 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5876 (*addr & PDRMASK) == superpage_offset)
5878 if ((*addr & PDRMASK) < superpage_offset)
5879 *addr = (*addr & ~PDRMASK) + superpage_offset;
5881 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5885 pmap_quick_enter_page(vm_page_t m)
5891 qaddr = PCPU_GET(qmap_addr);
5892 pte = vtopte(qaddr);
5894 KASSERT(*pte == 0, ("pmap_quick_enter_page: PTE busy"));
5895 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5896 pmap_cache_bits(kernel_pmap, pmap_page_get_memattr(m), 0);
5903 pmap_quick_remove_page(vm_offset_t addr)
5908 qaddr = PCPU_GET(qmap_addr);
5909 pte = vtopte(qaddr);
5911 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5912 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5918 static vmem_t *pmap_trm_arena;
5919 static vmem_addr_t pmap_trm_arena_last = PMAP_TRM_MIN_ADDRESS;
5920 static int trm_guard = PAGE_SIZE;
5923 pmap_trm_import(void *unused __unused, vmem_size_t size, int flags,
5927 vmem_addr_t af, addr, prev_addr;
5928 pt_entry_t *trm_pte;
5930 prev_addr = atomic_load_long(&pmap_trm_arena_last);
5931 size = round_page(size) + trm_guard;
5933 if (prev_addr + size < prev_addr || prev_addr + size < size ||
5934 prev_addr + size > PMAP_TRM_MAX_ADDRESS)
5936 addr = prev_addr + size;
5937 if (atomic_fcmpset_int(&pmap_trm_arena_last, &prev_addr, addr))
5940 prev_addr += trm_guard;
5941 trm_pte = PTmap + atop(prev_addr);
5942 for (af = prev_addr; af < addr; af += PAGE_SIZE) {
5943 m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5944 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
5945 pte_store(&trm_pte[atop(af - prev_addr)], VM_PAGE_TO_PHYS(m) |
5946 PG_M | PG_A | PG_RW | PG_V | pgeflag |
5947 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE));
5954 void pmap_init_trm(void)
5958 TUNABLE_INT_FETCH("machdep.trm_guard", &trm_guard);
5959 if ((trm_guard & PAGE_MASK) != 0)
5961 pmap_trm_arena = vmem_create("i386trampoline", 0, 0, 1, 0, M_WAITOK);
5962 vmem_set_import(pmap_trm_arena, pmap_trm_import, NULL, NULL, PAGE_SIZE);
5963 pd_m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5964 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK | VM_ALLOC_ZERO);
5965 if ((pd_m->flags & PG_ZERO) == 0)
5966 pmap_zero_page(pd_m);
5967 PTD[TRPTDI] = VM_PAGE_TO_PHYS(pd_m) | PG_M | PG_A | PG_RW | PG_V |
5968 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, TRUE);
5972 pmap_trm_alloc(size_t size, int flags)
5977 MPASS((flags & ~(M_WAITOK | M_NOWAIT | M_ZERO)) == 0);
5978 error = vmem_xalloc(pmap_trm_arena, roundup2(size, 4), sizeof(int),
5979 0, 0, VMEM_ADDR_MIN, VMEM_ADDR_MAX, flags | M_FIRSTFIT, &res);
5982 if ((flags & M_ZERO) != 0)
5983 bzero((void *)res, size);
5984 return ((void *)res);
5988 pmap_trm_free(void *addr, size_t size)
5991 vmem_free(pmap_trm_arena, (uintptr_t)addr, roundup2(size, 4));
5994 #if defined(PMAP_DEBUG)
5995 pmap_pid_dump(int pid)
6002 sx_slock(&allproc_lock);
6003 FOREACH_PROC_IN_SYSTEM(p) {
6004 if (p->p_pid != pid)
6010 pmap = vmspace_pmap(p->p_vmspace);
6011 for (i = 0; i < NPDEPTD; i++) {
6014 vm_offset_t base = i << PDRSHIFT;
6016 pde = &pmap->pm_pdir[i];
6017 if (pde && pmap_pde_v(pde)) {
6018 for (j = 0; j < NPTEPG; j++) {
6019 vm_offset_t va = base + (j << PAGE_SHIFT);
6020 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
6025 sx_sunlock(&allproc_lock);
6028 pte = pmap_pte(pmap, va);
6029 if (pte && pmap_pte_v(pte)) {
6033 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
6034 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
6035 va, pa, m->hold_count, m->wire_count, m->flags);
6050 sx_sunlock(&allproc_lock);