2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
50 * Copyright (c) 2018 The FreeBSD Foundation
51 * All rights reserved.
53 * This software was developed for the FreeBSD Project by Jake Burkholder,
54 * Safeport Network Services, and Network Associates Laboratories, the
55 * Security Research Division of Network Associates, Inc. under
56 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
57 * CHATS research program.
59 * Portions of this software were developed by
60 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
61 * the FreeBSD Foundation.
63 * Redistribution and use in source and binary forms, with or without
64 * modification, are permitted provided that the following conditions
66 * 1. Redistributions of source code must retain the above copyright
67 * notice, this list of conditions and the following disclaimer.
68 * 2. Redistributions in binary form must reproduce the above copyright
69 * notice, this list of conditions and the following disclaimer in the
70 * documentation and/or other materials provided with the distribution.
72 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
73 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
75 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
78 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
79 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
80 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
81 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
85 #include <sys/cdefs.h>
86 __FBSDID("$FreeBSD$");
89 * Manages physical address maps.
91 * Since the information managed by this module is
92 * also stored by the logical address mapping module,
93 * this module may throw away valid virtual-to-physical
94 * mappings at almost any time. However, invalidations
95 * of virtual-to-physical mappings must be done as
98 * In order to cope with hardware architectures which
99 * make virtual-to-physical map invalidates expensive,
100 * this module may delay invalidate or reduced protection
101 * operations until such time as they are actually
102 * necessary. This module is given full information as
103 * to which processors are currently using which maps,
104 * and to when physical maps must be made correct.
107 #include "opt_apic.h"
109 #include "opt_pmap.h"
113 #include <sys/param.h>
114 #include <sys/systm.h>
115 #include <sys/kernel.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/proc.h>
123 #include <sys/rwlock.h>
124 #include <sys/sf_buf.h>
126 #include <sys/vmmeter.h>
127 #include <sys/sched.h>
128 #include <sys/sysctl.h>
130 #include <sys/vmem.h>
133 #include <vm/vm_param.h>
134 #include <vm/vm_kern.h>
135 #include <vm/vm_page.h>
136 #include <vm/vm_map.h>
137 #include <vm/vm_object.h>
138 #include <vm/vm_extern.h>
139 #include <vm/vm_pageout.h>
140 #include <vm/vm_pager.h>
141 #include <vm/vm_phys.h>
142 #include <vm/vm_radix.h>
143 #include <vm/vm_reserv.h>
148 #include <machine/intr_machdep.h>
149 #include <x86/apicvar.h>
151 #include <x86/ifunc.h>
152 #include <machine/bootinfo.h>
153 #include <machine/cpu.h>
154 #include <machine/cputypes.h>
155 #include <machine/md_var.h>
156 #include <machine/pcb.h>
157 #include <machine/specialreg.h>
159 #include <machine/smp.h>
162 #ifndef PMAP_SHPGPERPROC
163 #define PMAP_SHPGPERPROC 200
166 #if !defined(DIAGNOSTIC)
167 #ifdef __GNUC_GNU_INLINE__
168 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
170 #define PMAP_INLINE extern inline
177 #define PV_STAT(x) do { x ; } while (0)
179 #define PV_STAT(x) do { } while (0)
182 #define pa_index(pa) ((pa) >> PDRSHIFT)
183 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
186 * Get PDEs and PTEs for user/kernel address space
188 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
189 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
191 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
192 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
193 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
194 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
195 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
197 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
198 atomic_clear_int((u_int *)(pte), PG_W))
199 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
201 struct pmap kernel_pmap_store;
203 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
204 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
205 static int pgeflag = 0; /* PG_G or-in */
206 static int pseflag = 0; /* PG_PS or-in */
208 static int nkpt = NKPT;
209 vm_offset_t kernel_vm_end = /* 0 + */ NKPT * NBPDR;
211 #if defined(PAE) || defined(PAE_TABLES)
213 static uma_zone_t pdptzone;
216 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
218 static int pat_works = 1;
219 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
220 "Is page attribute table fully functional?");
222 static int pg_ps_enabled = 1;
223 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
224 &pg_ps_enabled, 0, "Are large page mappings enabled?");
226 #define PAT_INDEX_SIZE 8
227 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
230 * pmap_mapdev support pre initialization (i.e. console)
232 #define PMAP_PREINIT_MAPPING_COUNT 8
233 static struct pmap_preinit_mapping {
238 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
239 static int pmap_initialized;
241 static struct rwlock_padalign pvh_global_lock;
244 * Data for the pv entry allocation mechanism
246 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
247 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
248 static struct md_page *pv_table;
249 static int shpgperproc = PMAP_SHPGPERPROC;
251 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
252 int pv_maxchunks; /* How many chunks we have KVA for */
253 vm_offset_t pv_vafree; /* freelist stored in the PTE */
256 * All those kernel PT submaps that BSD is so fond of
259 static pd_entry_t *KPTD;
266 static caddr_t crashdumpmap;
268 static pt_entry_t *PMAP1 = NULL, *PMAP2, *PMAP3;
269 static pt_entry_t *PADDR1 = NULL, *PADDR2, *PADDR3;
271 static int PMAP1cpu, PMAP3cpu;
272 static int PMAP1changedcpu;
273 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
275 "Number of times pmap_pte_quick changed CPU with same PMAP1");
277 static int PMAP1changed;
278 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
280 "Number of times pmap_pte_quick changed PMAP1");
281 static int PMAP1unchanged;
282 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
284 "Number of times pmap_pte_quick didn't change PMAP1");
285 static struct mtx PMAP2mutex;
290 * Internal flags for pmap_enter()'s helper functions.
292 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
293 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
295 static void free_pv_chunk(struct pv_chunk *pc);
296 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
297 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
298 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
299 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
301 #if VM_NRESERVLEVEL > 0
302 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
304 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
305 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
307 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
309 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
310 static bool pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
312 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
313 u_int flags, vm_page_t m);
314 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
315 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
316 static void pmap_flush_page(vm_page_t m);
317 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
318 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
320 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
322 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
324 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
325 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
326 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
327 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
328 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
329 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
330 #if VM_NRESERVLEVEL > 0
331 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
333 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
335 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
336 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
337 struct spglist *free);
338 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
339 struct spglist *free);
340 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
341 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
342 struct spglist *free);
343 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
344 struct spglist *free);
345 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
347 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
348 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
350 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
352 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
354 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
356 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
357 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
358 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
359 static void pmap_pte_release(pt_entry_t *pte);
360 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
361 #if defined(PAE) || defined(PAE_TABLES)
362 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain,
363 uint8_t *flags, int wait);
365 static void pmap_init_trm(void);
367 static __inline void pagezero(void *page);
369 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
370 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
372 void pmap_cold(void);
374 u_long physfree; /* phys addr of next free page */
375 u_long vm86phystk; /* PA of vm86/bios stack */
376 u_long vm86paddr; /* address of vm86 region */
377 int vm86pa; /* phys addr of vm86 region */
378 u_long KERNend; /* phys addr end of kernel (just after bss) */
379 pd_entry_t *IdlePTD; /* phys addr of kernel PTD */
380 #if defined(PAE) || defined(PAE_TABLES)
381 pdpt_entry_t *IdlePDPT; /* phys addr of kernel PDPT */
383 pt_entry_t *KPTmap; /* address of kernel page tables */
384 u_long KPTphys; /* phys addr of kernel page tables */
385 extern u_long tramp_idleptd;
388 allocpages(u_int cnt, u_long *physfree)
393 *physfree += PAGE_SIZE * cnt;
394 bzero((void *)res, PAGE_SIZE * cnt);
399 pmap_cold_map(u_long pa, u_long va, u_long cnt)
403 for (pt = (pt_entry_t *)KPTphys + atop(va); cnt > 0;
404 cnt--, pt++, va += PAGE_SIZE, pa += PAGE_SIZE)
405 *pt = pa | PG_V | PG_RW | PG_A | PG_M;
409 pmap_cold_mapident(u_long pa, u_long cnt)
412 pmap_cold_map(pa, pa, cnt);
415 _Static_assert(2 * NBPDR == KERNBASE, "Broken double-map of zero PTD");
418 * Called from locore.s before paging is enabled. Sets up the first
419 * kernel page table. Since kernel is mapped with PA == VA, this code
420 * does not require relocations.
429 physfree = (u_long)&_end;
430 if (bootinfo.bi_esymtab != 0)
431 physfree = bootinfo.bi_esymtab;
432 if (bootinfo.bi_kernend != 0)
433 physfree = bootinfo.bi_kernend;
434 physfree = roundup2(physfree, NBPDR);
437 /* Allocate Kernel Page Tables */
438 KPTphys = allocpages(NKPT, &physfree);
439 KPTmap = (pt_entry_t *)KPTphys;
441 /* Allocate Page Table Directory */
442 #if defined(PAE) || defined(PAE_TABLES)
443 /* XXX only need 32 bytes (easier for now) */
444 IdlePDPT = (pdpt_entry_t *)allocpages(1, &physfree);
446 IdlePTD = (pd_entry_t *)allocpages(NPGPTD, &physfree);
449 * Allocate KSTACK. Leave a guard page between IdlePTD and
450 * proc0kstack, to control stack overflow for thread0 and
451 * prevent corruption of the page table. We leak the guard
452 * physical memory due to 1:1 mappings.
454 allocpages(1, &physfree);
455 proc0kstack = allocpages(TD0_KSTACK_PAGES, &physfree);
457 /* vm86/bios stack */
458 vm86phystk = allocpages(1, &physfree);
460 /* pgtable + ext + IOPAGES */
461 vm86paddr = vm86pa = allocpages(3, &physfree);
463 /* Install page tables into PTD. Page table page 1 is wasted. */
464 for (a = 0; a < NKPT; a++)
465 IdlePTD[a] = (KPTphys + ptoa(a)) | PG_V | PG_RW | PG_A | PG_M;
467 #if defined(PAE) || defined(PAE_TABLES)
468 /* PAE install PTD pointers into PDPT */
469 for (a = 0; a < NPGPTD; a++)
470 IdlePDPT[a] = ((u_int)IdlePTD + ptoa(a)) | PG_V;
474 * Install recursive mapping for kernel page tables into
477 for (a = 0; a < NPGPTD; a++)
478 IdlePTD[PTDPTDI + a] = ((u_int)IdlePTD + ptoa(a)) | PG_V |
482 * Initialize page table pages mapping physical address zero
483 * through the (physical) end of the kernel. Many of these
484 * pages must be reserved, and we reserve them all and map
485 * them linearly for convenience. We do this even if we've
486 * enabled PSE above; we'll just switch the corresponding
487 * kernel PDEs before we turn on paging.
489 * This and all other page table entries allow read and write
490 * access for various reasons. Kernel mappings never have any
491 * access restrictions.
493 pmap_cold_mapident(0, atop(NBPDR));
494 pmap_cold_map(0, NBPDR, atop(NBPDR));
495 pmap_cold_mapident(KERNBASE, atop(KERNend - KERNBASE));
497 /* Map page table directory */
498 #if defined(PAE) || defined(PAE_TABLES)
499 pmap_cold_mapident((u_long)IdlePDPT, 1);
501 pmap_cold_mapident((u_long)IdlePTD, NPGPTD);
503 /* Map early KPTmap. It is really pmap_cold_mapident. */
504 pmap_cold_map(KPTphys, (u_long)KPTmap, NKPT);
506 /* Map proc0kstack */
507 pmap_cold_mapident(proc0kstack, TD0_KSTACK_PAGES);
508 /* ISA hole already mapped */
510 pmap_cold_mapident(vm86phystk, 1);
511 pmap_cold_mapident(vm86pa, 3);
513 /* Map page 0 into the vm86 page table */
514 *(pt_entry_t *)vm86pa = 0 | PG_RW | PG_U | PG_A | PG_M | PG_V;
516 /* ...likewise for the ISA hole for vm86 */
517 for (pt = (pt_entry_t *)vm86pa + atop(ISA_HOLE_START), a = 0;
518 a < atop(ISA_HOLE_LENGTH); a++, pt++)
519 *pt = (ISA_HOLE_START + ptoa(a)) | PG_RW | PG_U | PG_A |
522 /* Enable PSE, PGE, VME, and PAE if configured. */
524 if ((cpu_feature & CPUID_PSE) != 0) {
528 * Superpage mapping of the kernel text. Existing 4k
529 * page table pages are wasted.
531 for (a = KERNBASE; a < KERNend; a += NBPDR)
532 IdlePTD[a >> PDRSHIFT] = a | PG_PS | PG_A | PG_M |
535 if ((cpu_feature & CPUID_PGE) != 0) {
539 ncr4 |= (cpu_feature & CPUID_VME) != 0 ? CR4_VME : 0;
540 #if defined(PAE) || defined(PAE_TABLES)
544 load_cr4(rcr4() | ncr4);
546 /* Now enable paging */
547 #if defined(PAE) || defined(PAE_TABLES)
548 cr3 = (u_int)IdlePDPT;
550 cr3 = (u_int)IdlePTD;
554 load_cr0(rcr0() | CR0_PG);
557 * Now running relocated at KERNBASE where the system is
562 * Remove the lowest part of the double mapping of low memory
563 * to get some null pointer checks.
566 load_cr3(cr3); /* invalidate TLB */
570 * Bootstrap the system enough to run with virtual memory.
572 * On the i386 this is called after mapping has already been enabled
573 * in locore.s with the page table created in pmap_cold(),
574 * and just syncs the pmap module with what has already been done.
577 pmap_bootstrap(vm_paddr_t firstaddr)
580 pt_entry_t *pte, *unused;
585 * Add a physical memory segment (vm_phys_seg) corresponding to the
586 * preallocated kernel page table pages so that vm_page structures
587 * representing these pages will be created. The vm_page structures
588 * are required for promotion of the corresponding kernel virtual
589 * addresses to superpage mappings.
591 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
594 * Initialize the first available kernel virtual address. However,
595 * using "firstaddr" may waste a few pages of the kernel virtual
596 * address space, because locore may not have mapped every physical
597 * page that it allocated. Preferably, locore would provide a first
598 * unused virtual address in addition to "firstaddr".
600 virtual_avail = (vm_offset_t)firstaddr;
602 virtual_end = VM_MAX_KERNEL_ADDRESS;
605 * Initialize the kernel pmap (which is statically allocated).
607 PMAP_LOCK_INIT(kernel_pmap);
608 kernel_pmap->pm_pdir = IdlePTD;
609 #if defined(PAE) || defined(PAE_TABLES)
610 kernel_pmap->pm_pdpt = IdlePDPT;
612 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
613 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
616 * Initialize the global pv list lock.
618 rw_init(&pvh_global_lock, "pmap pv global");
621 * Reserve some special page table entries/VA space for temporary
624 #define SYSMAP(c, p, v, n) \
625 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
632 * Initialize temporary map objects on the current CPU for use
634 * CMAP1/CMAP2 are used for zeroing and copying pages.
635 * CMAP3 is used for the boot-time memory test.
638 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
639 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1)
640 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1)
641 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1)
643 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
648 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
651 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
653 SYSMAP(caddr_t, unused, ptvmmap, 1)
656 * msgbufp is used to map the system message buffer.
658 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
661 * KPTmap is used by pmap_kextract().
663 * KPTmap is first initialized by locore. However, that initial
664 * KPTmap can only support NKPT page table pages. Here, a larger
665 * KPTmap is created that can support KVA_PAGES page table pages.
667 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
669 for (i = 0; i < NKPT; i++)
670 KPTD[i] = (KPTphys + ptoa(i)) | PG_RW | PG_V;
673 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
676 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
677 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
678 SYSMAP(pt_entry_t *, PMAP3, PADDR3, 1)
680 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
685 * Initialize the PAT MSR if present.
686 * pmap_init_pat() clears and sets CR4_PGE, which, as a
687 * side-effect, invalidates stale PG_G TLB entries that might
688 * have been created in our pre-boot environment. We assume
689 * that PAT support implies PGE and in reverse, PGE presence
690 * comes with PAT. Both features were added for Pentium Pro.
696 pmap_init_reserved_pages(void)
704 mtx_init(&pc->pc_copyout_mlock, "cpmlk", NULL, MTX_DEF |
706 pc->pc_copyout_maddr = kva_alloc(ptoa(2));
707 if (pc->pc_copyout_maddr == 0)
708 panic("unable to allocate non-sleepable copyout KVA");
709 sx_init(&pc->pc_copyout_slock, "cpslk");
710 pc->pc_copyout_saddr = kva_alloc(ptoa(2));
711 if (pc->pc_copyout_saddr == 0)
712 panic("unable to allocate sleepable copyout KVA");
713 pc->pc_pmap_eh_va = kva_alloc(ptoa(1));
714 if (pc->pc_pmap_eh_va == 0)
715 panic("unable to allocate pmap_extract_and_hold KVA");
716 pc->pc_pmap_eh_ptep = (char *)vtopte(pc->pc_pmap_eh_va);
719 * Skip if the mappings have already been initialized,
720 * i.e. this is the BSP.
722 if (pc->pc_cmap_addr1 != 0)
725 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
726 pages = kva_alloc(PAGE_SIZE * 3);
728 panic("unable to allocate CMAP KVA");
729 pc->pc_cmap_pte1 = vtopte(pages);
730 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE);
731 pc->pc_cmap_addr1 = (caddr_t)pages;
732 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE);
733 pc->pc_qmap_addr = pages + atop(2);
737 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
745 int pat_table[PAT_INDEX_SIZE];
750 /* Set default PAT index table. */
751 for (i = 0; i < PAT_INDEX_SIZE; i++)
753 pat_table[PAT_WRITE_BACK] = 0;
754 pat_table[PAT_WRITE_THROUGH] = 1;
755 pat_table[PAT_UNCACHEABLE] = 3;
756 pat_table[PAT_WRITE_COMBINING] = 3;
757 pat_table[PAT_WRITE_PROTECTED] = 3;
758 pat_table[PAT_UNCACHED] = 3;
761 * Bail if this CPU doesn't implement PAT.
762 * We assume that PAT support implies PGE.
764 if ((cpu_feature & CPUID_PAT) == 0) {
765 for (i = 0; i < PAT_INDEX_SIZE; i++)
766 pat_index[i] = pat_table[i];
772 * Due to some Intel errata, we can only safely use the lower 4
775 * Intel Pentium III Processor Specification Update
776 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
779 * Intel Pentium IV Processor Specification Update
780 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
782 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
783 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
786 /* Initialize default PAT entries. */
787 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
788 PAT_VALUE(1, PAT_WRITE_THROUGH) |
789 PAT_VALUE(2, PAT_UNCACHED) |
790 PAT_VALUE(3, PAT_UNCACHEABLE) |
791 PAT_VALUE(4, PAT_WRITE_BACK) |
792 PAT_VALUE(5, PAT_WRITE_THROUGH) |
793 PAT_VALUE(6, PAT_UNCACHED) |
794 PAT_VALUE(7, PAT_UNCACHEABLE);
798 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
799 * Program 5 and 6 as WP and WC.
800 * Leave 4 and 7 as WB and UC.
802 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
803 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
804 PAT_VALUE(6, PAT_WRITE_COMBINING);
805 pat_table[PAT_UNCACHED] = 2;
806 pat_table[PAT_WRITE_PROTECTED] = 5;
807 pat_table[PAT_WRITE_COMBINING] = 6;
810 * Just replace PAT Index 2 with WC instead of UC-.
812 pat_msr &= ~PAT_MASK(2);
813 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
814 pat_table[PAT_WRITE_COMBINING] = 2;
819 load_cr4(cr4 & ~CR4_PGE);
821 /* Disable caches (CD = 1, NW = 0). */
823 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
825 /* Flushes caches and TLBs. */
829 /* Update PAT and index table. */
830 wrmsr(MSR_PAT, pat_msr);
831 for (i = 0; i < PAT_INDEX_SIZE; i++)
832 pat_index[i] = pat_table[i];
834 /* Flush caches and TLBs again. */
838 /* Restore caches and PGE. */
844 * Initialize a vm_page's machine-dependent fields.
847 pmap_page_init(vm_page_t m)
850 TAILQ_INIT(&m->md.pv_list);
851 m->md.pat_mode = PAT_WRITE_BACK;
854 #if defined(PAE) || defined(PAE_TABLES)
856 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain, uint8_t *flags,
860 /* Inform UMA that this allocator uses kernel_map/object. */
861 *flags = UMA_SLAB_KERNEL;
862 return ((void *)kmem_alloc_contig_domain(domain, bytes, wait, 0x0ULL,
863 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
868 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
870 * - Must deal with pages in order to ensure that none of the PG_* bits
871 * are ever set, PG_V in particular.
872 * - Assumes we can write to ptes without pte_store() atomic ops, even
873 * on PAE systems. This should be ok.
874 * - Assumes nothing will ever test these addresses for 0 to indicate
875 * no mapping instead of correctly checking PG_V.
876 * - Assumes a vm_offset_t will fit in a pte (true for i386).
877 * Because PG_V is never set, there can be no mappings to invalidate.
880 pmap_ptelist_alloc(vm_offset_t *head)
887 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
891 panic("pmap_ptelist_alloc: va with PG_V set!");
897 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
902 panic("pmap_ptelist_free: freeing va with PG_V set!");
904 *pte = *head; /* virtual! PG_V is 0 though */
909 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
915 for (i = npages - 1; i >= 0; i--) {
916 va = (vm_offset_t)base + i * PAGE_SIZE;
917 pmap_ptelist_free(head, va);
923 * Initialize the pmap module.
924 * Called by vm_init, to initialize any structures that the pmap
925 * system needs to map virtual memory.
930 struct pmap_preinit_mapping *ppim;
936 * Initialize the vm page array entries for the kernel pmap's
939 PMAP_LOCK(kernel_pmap);
940 for (i = 0; i < NKPT; i++) {
941 mpte = PHYS_TO_VM_PAGE(KPTphys + ptoa(i));
942 KASSERT(mpte >= vm_page_array &&
943 mpte < &vm_page_array[vm_page_array_size],
944 ("pmap_init: page table page is out of range"));
945 mpte->pindex = i + KPTDI;
946 mpte->phys_addr = KPTphys + ptoa(i);
947 mpte->wire_count = 1;
949 KERNBASE <= i << PDRSHIFT && i << PDRSHIFT < KERNend &&
950 pmap_insert_pt_page(kernel_pmap, mpte))
951 panic("pmap_init: pmap_insert_pt_page failed");
953 PMAP_UNLOCK(kernel_pmap);
957 * Initialize the address space (zone) for the pv entries. Set a
958 * high water mark so that the system can recover from excessive
959 * numbers of pv entries.
961 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
962 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
963 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
964 pv_entry_max = roundup(pv_entry_max, _NPCPV);
965 pv_entry_high_water = 9 * (pv_entry_max / 10);
968 * If the kernel is running on a virtual machine, then it must assume
969 * that MCA is enabled by the hypervisor. Moreover, the kernel must
970 * be prepared for the hypervisor changing the vendor and family that
971 * are reported by CPUID. Consequently, the workaround for AMD Family
972 * 10h Erratum 383 is enabled if the processor's feature set does not
973 * include at least one feature that is only supported by older Intel
974 * or newer AMD processors.
976 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
977 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
978 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
980 workaround_erratum383 = 1;
983 * Are large page mappings supported and enabled?
985 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
988 else if (pg_ps_enabled) {
989 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
990 ("pmap_init: can't assign to pagesizes[1]"));
991 pagesizes[1] = NBPDR;
995 * Calculate the size of the pv head table for superpages.
996 * Handle the possibility that "vm_phys_segs[...].end" is zero.
998 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
999 PAGE_SIZE) / NBPDR + 1;
1002 * Allocate memory for the pv head table for superpages.
1004 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1006 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1007 for (i = 0; i < pv_npg; i++)
1008 TAILQ_INIT(&pv_table[i].pv_list);
1010 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
1011 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
1012 if (pv_chunkbase == NULL)
1013 panic("pmap_init: not enough kvm for pv chunks");
1014 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
1015 #if defined(PAE) || defined(PAE_TABLES)
1016 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
1017 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
1018 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1019 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
1022 pmap_initialized = 1;
1027 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1028 ppim = pmap_preinit_mapping + i;
1031 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
1032 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
1038 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
1039 "Max number of PV entries");
1040 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
1041 "Page share factor per proc");
1043 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1044 "2/4MB page mapping counters");
1046 static u_long pmap_pde_demotions;
1047 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1048 &pmap_pde_demotions, 0, "2/4MB page demotions");
1050 static u_long pmap_pde_mappings;
1051 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1052 &pmap_pde_mappings, 0, "2/4MB page mappings");
1054 static u_long pmap_pde_p_failures;
1055 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1056 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
1058 static u_long pmap_pde_promotions;
1059 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1060 &pmap_pde_promotions, 0, "2/4MB page promotions");
1062 /***************************************************
1063 * Low level helper routines.....
1064 ***************************************************/
1067 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
1070 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
1071 pat_index[(int)mode] >= 0);
1075 * Determine the appropriate bits to set in a PTE or PDE for a specified
1079 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
1081 int cache_bits, pat_flag, pat_idx;
1083 if (!pmap_is_valid_memattr(pmap, mode))
1084 panic("Unknown caching mode %d\n", mode);
1086 /* The PAT bit is different for PTE's and PDE's. */
1087 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
1089 /* Map the caching mode to a PAT index. */
1090 pat_idx = pat_index[mode];
1092 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1095 cache_bits |= pat_flag;
1097 cache_bits |= PG_NC_PCD;
1099 cache_bits |= PG_NC_PWT;
1100 return (cache_bits);
1104 pmap_ps_enabled(pmap_t pmap __unused)
1107 return (pg_ps_enabled);
1111 * The caller is responsible for maintaining TLB consistency.
1114 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
1118 pde = pmap_pde(kernel_pmap, va);
1119 pde_store(pde, newpde);
1123 * After changing the page size for the specified virtual address in the page
1124 * table, flush the corresponding entries from the processor's TLB. Only the
1125 * calling processor's TLB is affected.
1127 * The calling thread must be pinned to a processor.
1130 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
1133 if ((newpde & PG_PS) == 0)
1134 /* Demotion: flush a specific 2MB page mapping. */
1136 else /* if ((newpde & PG_G) == 0) */
1138 * Promotion: flush every 4KB page mapping from the TLB
1139 * because there are too many to flush individually.
1154 * For SMP, these functions have to use the IPI mechanism for coherence.
1156 * N.B.: Before calling any of the following TLB invalidation functions,
1157 * the calling processor must ensure that all stores updating a non-
1158 * kernel page table are globally performed. Otherwise, another
1159 * processor could cache an old, pre-update entry without being
1160 * invalidated. This can happen one of two ways: (1) The pmap becomes
1161 * active on another processor after its pm_active field is checked by
1162 * one of the following functions but before a store updating the page
1163 * table is globally performed. (2) The pmap becomes active on another
1164 * processor before its pm_active field is checked but due to
1165 * speculative loads one of the following functions stills reads the
1166 * pmap as inactive on the other processor.
1168 * The kernel page table is exempt because its pm_active field is
1169 * immutable. The kernel page table is always active on every
1173 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1175 cpuset_t *mask, other_cpus;
1179 if (pmap == kernel_pmap) {
1182 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1185 cpuid = PCPU_GET(cpuid);
1186 other_cpus = all_cpus;
1187 CPU_CLR(cpuid, &other_cpus);
1188 CPU_AND(&other_cpus, &pmap->pm_active);
1191 smp_masked_invlpg(*mask, va, pmap);
1195 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1196 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1199 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1201 cpuset_t *mask, other_cpus;
1205 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1206 pmap_invalidate_all(pmap);
1211 if (pmap == kernel_pmap) {
1212 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1215 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1218 cpuid = PCPU_GET(cpuid);
1219 other_cpus = all_cpus;
1220 CPU_CLR(cpuid, &other_cpus);
1221 CPU_AND(&other_cpus, &pmap->pm_active);
1224 smp_masked_invlpg_range(*mask, sva, eva, pmap);
1229 pmap_invalidate_all(pmap_t pmap)
1231 cpuset_t *mask, other_cpus;
1235 if (pmap == kernel_pmap) {
1238 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1241 cpuid = PCPU_GET(cpuid);
1242 other_cpus = all_cpus;
1243 CPU_CLR(cpuid, &other_cpus);
1244 CPU_AND(&other_cpus, &pmap->pm_active);
1247 smp_masked_invltlb(*mask, pmap);
1252 pmap_invalidate_cache(void)
1262 cpuset_t invalidate; /* processors that invalidate their TLB */
1266 u_int store; /* processor that updates the PDE */
1270 pmap_update_pde_kernel(void *arg)
1272 struct pde_action *act = arg;
1275 if (act->store == PCPU_GET(cpuid)) {
1276 pde = pmap_pde(kernel_pmap, act->va);
1277 pde_store(pde, act->newpde);
1282 pmap_update_pde_user(void *arg)
1284 struct pde_action *act = arg;
1286 if (act->store == PCPU_GET(cpuid))
1287 pde_store(act->pde, act->newpde);
1291 pmap_update_pde_teardown(void *arg)
1293 struct pde_action *act = arg;
1295 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1296 pmap_update_pde_invalidate(act->va, act->newpde);
1300 * Change the page size for the specified virtual address in a way that
1301 * prevents any possibility of the TLB ever having two entries that map the
1302 * same virtual address using different page sizes. This is the recommended
1303 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1304 * machine check exception for a TLB state that is improperly diagnosed as a
1308 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1310 struct pde_action act;
1311 cpuset_t active, other_cpus;
1315 cpuid = PCPU_GET(cpuid);
1316 other_cpus = all_cpus;
1317 CPU_CLR(cpuid, &other_cpus);
1318 if (pmap == kernel_pmap)
1321 active = pmap->pm_active;
1322 if (CPU_OVERLAP(&active, &other_cpus)) {
1324 act.invalidate = active;
1327 act.newpde = newpde;
1328 CPU_SET(cpuid, &active);
1329 smp_rendezvous_cpus(active,
1330 smp_no_rendezvous_barrier, pmap == kernel_pmap ?
1331 pmap_update_pde_kernel : pmap_update_pde_user,
1332 pmap_update_pde_teardown, &act);
1334 if (pmap == kernel_pmap)
1335 pmap_kenter_pde(va, newpde);
1337 pde_store(pde, newpde);
1338 if (CPU_ISSET(cpuid, &active))
1339 pmap_update_pde_invalidate(va, newpde);
1345 * Normal, non-SMP, 486+ invalidation functions.
1346 * We inline these within pmap.c for speed.
1349 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1352 if (pmap == kernel_pmap)
1357 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1361 if (pmap == kernel_pmap)
1362 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1367 pmap_invalidate_all(pmap_t pmap)
1370 if (pmap == kernel_pmap)
1375 pmap_invalidate_cache(void)
1382 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1385 if (pmap == kernel_pmap)
1386 pmap_kenter_pde(va, newpde);
1388 pde_store(pde, newpde);
1389 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1390 pmap_update_pde_invalidate(va, newpde);
1395 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1399 * When the PDE has PG_PROMOTED set, the 2- or 4MB page mapping was
1400 * created by a promotion that did not invalidate the 512 or 1024 4KB
1401 * page mappings that might exist in the TLB. Consequently, at this
1402 * point, the TLB may hold both 4KB and 2- or 4MB page mappings for
1403 * the address range [va, va + NBPDR). Therefore, the entire range
1404 * must be invalidated here. In contrast, when PG_PROMOTED is clear,
1405 * the TLB will not hold any 4KB page mappings for the address range
1406 * [va, va + NBPDR), and so a single INVLPG suffices to invalidate the
1407 * 2- or 4MB page mapping from the TLB.
1409 if ((pde & PG_PROMOTED) != 0)
1410 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
1412 pmap_invalidate_page(pmap, va);
1415 DEFINE_IFUNC(, void, pmap_invalidate_cache_range, (vm_offset_t, vm_offset_t),
1419 if ((cpu_feature & CPUID_SS) != 0)
1420 return (pmap_invalidate_cache_range_selfsnoop);
1421 if ((cpu_feature & CPUID_CLFSH) != 0)
1422 return (pmap_force_invalidate_cache_range);
1423 return (pmap_invalidate_cache_range_all);
1426 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1429 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
1432 KASSERT((sva & PAGE_MASK) == 0,
1433 ("pmap_invalidate_cache_range: sva not page-aligned"));
1434 KASSERT((eva & PAGE_MASK) == 0,
1435 ("pmap_invalidate_cache_range: eva not page-aligned"));
1439 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
1442 pmap_invalidate_cache_range_check_align(sva, eva);
1446 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
1449 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
1450 if (eva - sva >= PMAP_CLFLUSH_THRESHOLD) {
1452 * The supplied range is bigger than 2MB.
1453 * Globally invalidate cache.
1455 pmap_invalidate_cache();
1460 * XXX: Some CPUs fault, hang, or trash the local APIC
1461 * registers if we use CLFLUSH on the local APIC
1462 * range. The local APIC is always uncached, so we
1463 * don't need to flush for that range anyway.
1465 if (pmap_kextract(sva) == lapic_paddr)
1468 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
1470 * Do per-cache line flush. Use the sfence
1471 * instruction to insure that previous stores are
1472 * included in the write-back. The processor
1473 * propagates flush to other processors in the cache
1477 for (; sva < eva; sva += cpu_clflush_line_size)
1482 * Writes are ordered by CLFLUSH on Intel CPUs.
1484 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1486 for (; sva < eva; sva += cpu_clflush_line_size)
1488 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1494 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
1497 pmap_invalidate_cache_range_check_align(sva, eva);
1498 pmap_invalidate_cache();
1502 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1506 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1507 (cpu_feature & CPUID_CLFSH) == 0) {
1508 pmap_invalidate_cache();
1510 for (i = 0; i < count; i++)
1511 pmap_flush_page(pages[i]);
1516 * Are we current address space or kernel?
1519 pmap_is_current(pmap_t pmap)
1522 return (pmap == kernel_pmap);
1526 * If the given pmap is not the current or kernel pmap, the returned pte must
1527 * be released by passing it to pmap_pte_release().
1530 pmap_pte(pmap_t pmap, vm_offset_t va)
1535 pde = pmap_pde(pmap, va);
1539 /* are we current address space or kernel? */
1540 if (pmap_is_current(pmap))
1541 return (vtopte(va));
1542 mtx_lock(&PMAP2mutex);
1543 newpf = *pde & PG_FRAME;
1544 if ((*PMAP2 & PG_FRAME) != newpf) {
1545 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1546 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1548 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1554 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1557 static __inline void
1558 pmap_pte_release(pt_entry_t *pte)
1561 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1562 mtx_unlock(&PMAP2mutex);
1566 * NB: The sequence of updating a page table followed by accesses to the
1567 * corresponding pages is subject to the situation described in the "AMD64
1568 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1569 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1570 * right after modifying the PTE bits is crucial.
1572 static __inline void
1573 invlcaddr(void *caddr)
1576 invlpg((u_int)caddr);
1580 * Super fast pmap_pte routine best used when scanning
1581 * the pv lists. This eliminates many coarse-grained
1582 * invltlb calls. Note that many of the pv list
1583 * scans are across different pmaps. It is very wasteful
1584 * to do an entire invltlb for checking a single mapping.
1586 * If the given pmap is not the current pmap, pvh_global_lock
1587 * must be held and curthread pinned to a CPU.
1590 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1595 pde = pmap_pde(pmap, va);
1599 /* are we current address space or kernel? */
1600 if (pmap_is_current(pmap))
1601 return (vtopte(va));
1602 rw_assert(&pvh_global_lock, RA_WLOCKED);
1603 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1604 newpf = *pde & PG_FRAME;
1605 if ((*PMAP1 & PG_FRAME) != newpf) {
1606 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1608 PMAP1cpu = PCPU_GET(cpuid);
1614 if (PMAP1cpu != PCPU_GET(cpuid)) {
1615 PMAP1cpu = PCPU_GET(cpuid);
1621 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1627 pmap_pte_quick3(pmap_t pmap, vm_offset_t va)
1632 pde = pmap_pde(pmap, va);
1636 rw_assert(&pvh_global_lock, RA_WLOCKED);
1637 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1638 newpf = *pde & PG_FRAME;
1639 if ((*PMAP3 & PG_FRAME) != newpf) {
1640 *PMAP3 = newpf | PG_RW | PG_V | PG_A | PG_M;
1642 PMAP3cpu = PCPU_GET(cpuid);
1648 if (PMAP3cpu != PCPU_GET(cpuid)) {
1649 PMAP3cpu = PCPU_GET(cpuid);
1655 return (PADDR3 + (i386_btop(va) & (NPTEPG - 1)));
1661 pmap_pte_ufast(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1663 pt_entry_t *eh_ptep, pte, *ptep;
1665 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1668 eh_ptep = (pt_entry_t *)PCPU_GET(pmap_eh_ptep);
1669 if ((*eh_ptep & PG_FRAME) != pde) {
1670 *eh_ptep = pde | PG_RW | PG_V | PG_A | PG_M;
1671 invlcaddr((void *)PCPU_GET(pmap_eh_va));
1673 ptep = (pt_entry_t *)PCPU_GET(pmap_eh_va) + (i386_btop(va) &
1681 * Routine: pmap_extract
1683 * Extract the physical page address associated
1684 * with the given map/virtual_address pair.
1687 pmap_extract(pmap_t pmap, vm_offset_t va)
1695 pde = pmap->pm_pdir[va >> PDRSHIFT];
1697 if ((pde & PG_PS) != 0)
1698 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1700 pte = pmap_pte_ufast(pmap, va, pde);
1701 rtval = (pte & PG_FRAME) | (va & PAGE_MASK);
1709 * Routine: pmap_extract_and_hold
1711 * Atomically extract and hold the physical page
1712 * with the given pmap and virtual address pair
1713 * if that mapping permits the given protection.
1716 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1727 pde = *pmap_pde(pmap, va);
1730 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1731 if (vm_page_pa_tryrelock(pmap, (pde &
1732 PG_PS_FRAME) | (va & PDRMASK), &pa))
1734 m = PHYS_TO_VM_PAGE(pa);
1737 pte = pmap_pte_ufast(pmap, va, pde);
1739 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1740 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1743 m = PHYS_TO_VM_PAGE(pa);
1754 /***************************************************
1755 * Low level mapping routines.....
1756 ***************************************************/
1759 * Add a wired page to the kva.
1760 * Note: not SMP coherent.
1762 * This function may be used before pmap_bootstrap() is called.
1765 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1770 pte_store(pte, pa | PG_RW | PG_V);
1773 static __inline void
1774 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1779 pte_store(pte, pa | PG_RW | PG_V | pmap_cache_bits(kernel_pmap,
1784 * Remove a page from the kernel pagetables.
1785 * Note: not SMP coherent.
1787 * This function may be used before pmap_bootstrap() is called.
1790 pmap_kremove(vm_offset_t va)
1799 * Used to map a range of physical addresses into kernel
1800 * virtual address space.
1802 * The value passed in '*virt' is a suggested virtual address for
1803 * the mapping. Architectures which can support a direct-mapped
1804 * physical to virtual region can return the appropriate address
1805 * within that region, leaving '*virt' unchanged. Other
1806 * architectures should map the pages starting at '*virt' and
1807 * update '*virt' with the first usable address after the mapped
1811 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1813 vm_offset_t va, sva;
1814 vm_paddr_t superpage_offset;
1819 * Does the physical address range's size and alignment permit at
1820 * least one superpage mapping to be created?
1822 superpage_offset = start & PDRMASK;
1823 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1825 * Increase the starting virtual address so that its alignment
1826 * does not preclude the use of superpage mappings.
1828 if ((va & PDRMASK) < superpage_offset)
1829 va = (va & ~PDRMASK) + superpage_offset;
1830 else if ((va & PDRMASK) > superpage_offset)
1831 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1834 while (start < end) {
1835 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1837 KASSERT((va & PDRMASK) == 0,
1838 ("pmap_map: misaligned va %#x", va));
1839 newpde = start | PG_PS | PG_RW | PG_V;
1840 pmap_kenter_pde(va, newpde);
1844 pmap_kenter(va, start);
1849 pmap_invalidate_range(kernel_pmap, sva, va);
1856 * Add a list of wired pages to the kva
1857 * this routine is only used for temporary
1858 * kernel mappings that do not need to have
1859 * page modification or references recorded.
1860 * Note that old mappings are simply written
1861 * over. The page *must* be wired.
1862 * Note: SMP coherent. Uses a ranged shootdown IPI.
1865 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1867 pt_entry_t *endpte, oldpte, pa, *pte;
1872 endpte = pte + count;
1873 while (pte < endpte) {
1875 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(kernel_pmap,
1877 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1879 #if defined(PAE) || defined(PAE_TABLES)
1880 pte_store(pte, pa | pg_nx | PG_RW | PG_V);
1882 pte_store(pte, pa | PG_RW | PG_V);
1887 if (__predict_false((oldpte & PG_V) != 0))
1888 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1893 * This routine tears out page mappings from the
1894 * kernel -- it is meant only for temporary mappings.
1895 * Note: SMP coherent. Uses a ranged shootdown IPI.
1898 pmap_qremove(vm_offset_t sva, int count)
1903 while (count-- > 0) {
1907 pmap_invalidate_range(kernel_pmap, sva, va);
1910 /***************************************************
1911 * Page table page management routines.....
1912 ***************************************************/
1914 * Schedule the specified unused page table page to be freed. Specifically,
1915 * add the page to the specified list of pages that will be released to the
1916 * physical memory manager after the TLB has been updated.
1918 static __inline void
1919 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1920 boolean_t set_PG_ZERO)
1924 m->flags |= PG_ZERO;
1926 m->flags &= ~PG_ZERO;
1927 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1931 * Inserts the specified page table page into the specified pmap's collection
1932 * of idle page table pages. Each of a pmap's page table pages is responsible
1933 * for mapping a distinct range of virtual addresses. The pmap's collection is
1934 * ordered by this virtual address range.
1937 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1940 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1941 return (vm_radix_insert(&pmap->pm_root, mpte));
1945 * Removes the page table page mapping the specified virtual address from the
1946 * specified pmap's collection of idle page table pages, and returns it.
1947 * Otherwise, returns NULL if there is no page table page corresponding to the
1948 * specified virtual address.
1950 static __inline vm_page_t
1951 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
1954 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1955 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT));
1959 * Decrements a page table page's wire count, which is used to record the
1960 * number of valid page table entries within the page. If the wire count
1961 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1962 * page table page was unmapped and FALSE otherwise.
1964 static inline boolean_t
1965 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1969 if (m->wire_count == 0) {
1970 _pmap_unwire_ptp(pmap, m, free);
1977 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1981 * unmap the page table page
1983 pmap->pm_pdir[m->pindex] = 0;
1984 --pmap->pm_stats.resident_count;
1987 * There is not need to invalidate the recursive mapping since
1988 * we never instantiate such mapping for the usermode pmaps,
1989 * and never remove page table pages from the kernel pmap.
1990 * Put page on a list so that it is released since all TLB
1991 * shootdown is done.
1993 MPASS(pmap != kernel_pmap);
1994 pmap_add_delayed_free_list(m, free, TRUE);
1998 * After removing a page table entry, this routine is used to
1999 * conditionally free the page, and manage the hold/wire counts.
2002 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
2007 if (pmap == kernel_pmap)
2009 ptepde = *pmap_pde(pmap, va);
2010 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
2011 return (pmap_unwire_ptp(pmap, mpte, free));
2015 * Initialize the pmap for the swapper process.
2018 pmap_pinit0(pmap_t pmap)
2021 PMAP_LOCK_INIT(pmap);
2022 pmap->pm_pdir = IdlePTD;
2023 #if defined(PAE) || defined(PAE_TABLES)
2024 pmap->pm_pdpt = IdlePDPT;
2026 pmap->pm_root.rt_root = 0;
2027 CPU_ZERO(&pmap->pm_active);
2028 TAILQ_INIT(&pmap->pm_pvchunk);
2029 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2030 pmap_activate_boot(pmap);
2034 * Initialize a preallocated and zeroed pmap structure,
2035 * such as one in a vmspace structure.
2038 pmap_pinit(pmap_t pmap)
2044 * No need to allocate page table space yet but we do need a valid
2045 * page directory table.
2047 if (pmap->pm_pdir == NULL) {
2048 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
2049 if (pmap->pm_pdir == NULL)
2051 #if defined(PAE) || defined(PAE_TABLES)
2052 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
2053 KASSERT(((vm_offset_t)pmap->pm_pdpt &
2054 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
2055 ("pmap_pinit: pdpt misaligned"));
2056 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
2057 ("pmap_pinit: pdpt above 4g"));
2059 pmap->pm_root.rt_root = 0;
2061 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2062 ("pmap_pinit: pmap has reserved page table page(s)"));
2065 * allocate the page directory page(s)
2067 for (i = 0; i < NPGPTD;) {
2068 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2069 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2073 pmap->pm_ptdpg[i] = m;
2074 #if defined(PAE) || defined(PAE_TABLES)
2075 pmap->pm_pdpt[i] = VM_PAGE_TO_PHYS(m) | PG_V;
2081 pmap_qenter((vm_offset_t)pmap->pm_pdir, pmap->pm_ptdpg, NPGPTD);
2083 for (i = 0; i < NPGPTD; i++)
2084 if ((pmap->pm_ptdpg[i]->flags & PG_ZERO) == 0)
2085 pagezero(pmap->pm_pdir + (i * NPDEPG));
2087 /* Install the trampoline mapping. */
2088 pmap->pm_pdir[TRPTDI] = PTD[TRPTDI];
2090 CPU_ZERO(&pmap->pm_active);
2091 TAILQ_INIT(&pmap->pm_pvchunk);
2092 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2098 * this routine is called if the page table page is not
2102 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
2108 * Allocate a page table page.
2110 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2111 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2112 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2114 rw_wunlock(&pvh_global_lock);
2116 rw_wlock(&pvh_global_lock);
2121 * Indicate the need to retry. While waiting, the page table
2122 * page may have been allocated.
2126 if ((m->flags & PG_ZERO) == 0)
2130 * Map the pagetable page into the process address space, if
2131 * it isn't already there.
2134 pmap->pm_stats.resident_count++;
2136 ptepa = VM_PAGE_TO_PHYS(m);
2137 pmap->pm_pdir[ptepindex] =
2138 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
2144 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
2151 * Calculate pagetable page index
2153 ptepindex = va >> PDRSHIFT;
2156 * Get the page directory entry
2158 ptepa = pmap->pm_pdir[ptepindex];
2161 * This supports switching from a 4MB page to a
2164 if (ptepa & PG_PS) {
2165 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
2166 ptepa = pmap->pm_pdir[ptepindex];
2170 * If the page table page is mapped, we just increment the
2171 * hold count, and activate it.
2174 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
2178 * Here if the pte page isn't mapped, or if it has
2181 m = _pmap_allocpte(pmap, ptepindex, flags);
2182 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2189 /***************************************************
2190 * Pmap allocation/deallocation routines.
2191 ***************************************************/
2194 * Release any resources held by the given physical map.
2195 * Called when a pmap initialized by pmap_pinit is being released.
2196 * Should only be called if the map contains no valid mappings.
2199 pmap_release(pmap_t pmap)
2204 KASSERT(pmap->pm_stats.resident_count == 0,
2205 ("pmap_release: pmap resident count %ld != 0",
2206 pmap->pm_stats.resident_count));
2207 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2208 ("pmap_release: pmap has reserved page table page(s)"));
2209 KASSERT(CPU_EMPTY(&pmap->pm_active),
2210 ("releasing active pmap %p", pmap));
2212 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2214 for (i = 0; i < NPGPTD; i++) {
2215 m = pmap->pm_ptdpg[i];
2216 #if defined(PAE) || defined(PAE_TABLES)
2217 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2218 ("pmap_release: got wrong ptd page"));
2220 vm_page_unwire_noq(m);
2226 kvm_size(SYSCTL_HANDLER_ARGS)
2228 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2230 return (sysctl_handle_long(oidp, &ksize, 0, req));
2232 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2233 0, 0, kvm_size, "IU", "Size of KVM");
2236 kvm_free(SYSCTL_HANDLER_ARGS)
2238 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2240 return (sysctl_handle_long(oidp, &kfree, 0, req));
2242 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2243 0, 0, kvm_free, "IU", "Amount of KVM free");
2246 * grow the number of kernel page table entries, if needed
2249 pmap_growkernel(vm_offset_t addr)
2251 vm_paddr_t ptppaddr;
2255 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2256 addr = roundup2(addr, NBPDR);
2257 if (addr - 1 >= vm_map_max(kernel_map))
2258 addr = vm_map_max(kernel_map);
2259 while (kernel_vm_end < addr) {
2260 if (pdir_pde(PTD, kernel_vm_end)) {
2261 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2262 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2263 kernel_vm_end = vm_map_max(kernel_map);
2269 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2270 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2273 panic("pmap_growkernel: no memory to grow kernel");
2277 if ((nkpg->flags & PG_ZERO) == 0)
2278 pmap_zero_page(nkpg);
2279 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2280 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2281 pdir_pde(KPTD, kernel_vm_end) = newpdir;
2283 pmap_kenter_pde(kernel_vm_end, newpdir);
2284 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2285 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2286 kernel_vm_end = vm_map_max(kernel_map);
2293 /***************************************************
2294 * page management routines.
2295 ***************************************************/
2297 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2298 CTASSERT(_NPCM == 11);
2299 CTASSERT(_NPCPV == 336);
2301 static __inline struct pv_chunk *
2302 pv_to_chunk(pv_entry_t pv)
2305 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2308 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2310 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2311 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2313 static const uint32_t pc_freemask[_NPCM] = {
2314 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2315 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2316 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2317 PC_FREE0_9, PC_FREE10
2320 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2321 "Current number of pv entries");
2324 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2326 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2327 "Current number of pv entry chunks");
2328 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2329 "Current number of pv entry chunks allocated");
2330 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2331 "Current number of pv entry chunks frees");
2332 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2333 "Number of times tried to get a chunk page but failed.");
2335 static long pv_entry_frees, pv_entry_allocs;
2336 static int pv_entry_spare;
2338 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2339 "Current number of pv entry frees");
2340 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2341 "Current number of pv entry allocs");
2342 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2343 "Current number of spare pv entries");
2347 * We are in a serious low memory condition. Resort to
2348 * drastic measures to free some pages so we can allocate
2349 * another pv entry chunk.
2352 pmap_pv_reclaim(pmap_t locked_pmap)
2355 struct pv_chunk *pc;
2356 struct md_page *pvh;
2359 pt_entry_t *pte, tpte;
2363 struct spglist free;
2365 int bit, field, freed;
2367 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2371 TAILQ_INIT(&newtail);
2372 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2373 SLIST_EMPTY(&free))) {
2374 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2375 if (pmap != pc->pc_pmap) {
2377 pmap_invalidate_all(pmap);
2378 if (pmap != locked_pmap)
2382 /* Avoid deadlock and lock recursion. */
2383 if (pmap > locked_pmap)
2385 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2387 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2393 * Destroy every non-wired, 4 KB page mapping in the chunk.
2396 for (field = 0; field < _NPCM; field++) {
2397 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2398 inuse != 0; inuse &= ~(1UL << bit)) {
2400 pv = &pc->pc_pventry[field * 32 + bit];
2402 pde = pmap_pde(pmap, va);
2403 if ((*pde & PG_PS) != 0)
2405 pte = pmap_pte(pmap, va);
2407 if ((tpte & PG_W) == 0)
2408 tpte = pte_load_clear(pte);
2409 pmap_pte_release(pte);
2410 if ((tpte & PG_W) != 0)
2413 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2415 if ((tpte & PG_G) != 0)
2416 pmap_invalidate_page(pmap, va);
2417 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2418 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2420 if ((tpte & PG_A) != 0)
2421 vm_page_aflag_set(m, PGA_REFERENCED);
2422 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2423 if (TAILQ_EMPTY(&m->md.pv_list) &&
2424 (m->flags & PG_FICTITIOUS) == 0) {
2425 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2426 if (TAILQ_EMPTY(&pvh->pv_list)) {
2427 vm_page_aflag_clear(m,
2431 pc->pc_map[field] |= 1UL << bit;
2432 pmap_unuse_pt(pmap, va, &free);
2437 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2440 /* Every freed mapping is for a 4 KB page. */
2441 pmap->pm_stats.resident_count -= freed;
2442 PV_STAT(pv_entry_frees += freed);
2443 PV_STAT(pv_entry_spare += freed);
2444 pv_entry_count -= freed;
2445 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2446 for (field = 0; field < _NPCM; field++)
2447 if (pc->pc_map[field] != pc_freemask[field]) {
2448 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2450 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2453 * One freed pv entry in locked_pmap is
2456 if (pmap == locked_pmap)
2460 if (field == _NPCM) {
2461 PV_STAT(pv_entry_spare -= _NPCPV);
2462 PV_STAT(pc_chunk_count--);
2463 PV_STAT(pc_chunk_frees++);
2464 /* Entire chunk is free; return it. */
2465 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2466 pmap_qremove((vm_offset_t)pc, 1);
2467 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2472 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2474 pmap_invalidate_all(pmap);
2475 if (pmap != locked_pmap)
2478 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2479 m_pc = SLIST_FIRST(&free);
2480 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2481 /* Recycle a freed page table page. */
2482 m_pc->wire_count = 1;
2484 vm_page_free_pages_toq(&free, true);
2489 * free the pv_entry back to the free list
2492 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2494 struct pv_chunk *pc;
2495 int idx, field, bit;
2497 rw_assert(&pvh_global_lock, RA_WLOCKED);
2498 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2499 PV_STAT(pv_entry_frees++);
2500 PV_STAT(pv_entry_spare++);
2502 pc = pv_to_chunk(pv);
2503 idx = pv - &pc->pc_pventry[0];
2506 pc->pc_map[field] |= 1ul << bit;
2507 for (idx = 0; idx < _NPCM; idx++)
2508 if (pc->pc_map[idx] != pc_freemask[idx]) {
2510 * 98% of the time, pc is already at the head of the
2511 * list. If it isn't already, move it to the head.
2513 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2515 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2516 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2521 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2526 free_pv_chunk(struct pv_chunk *pc)
2530 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2531 PV_STAT(pv_entry_spare -= _NPCPV);
2532 PV_STAT(pc_chunk_count--);
2533 PV_STAT(pc_chunk_frees++);
2534 /* entire chunk is free, return it */
2535 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2536 pmap_qremove((vm_offset_t)pc, 1);
2537 vm_page_unwire(m, PQ_NONE);
2539 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2543 * get a new pv_entry, allocating a block from the system
2547 get_pv_entry(pmap_t pmap, boolean_t try)
2549 static const struct timeval printinterval = { 60, 0 };
2550 static struct timeval lastprint;
2553 struct pv_chunk *pc;
2556 rw_assert(&pvh_global_lock, RA_WLOCKED);
2557 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2558 PV_STAT(pv_entry_allocs++);
2560 if (pv_entry_count > pv_entry_high_water)
2561 if (ratecheck(&lastprint, &printinterval))
2562 printf("Approaching the limit on PV entries, consider "
2563 "increasing either the vm.pmap.shpgperproc or the "
2564 "vm.pmap.pv_entry_max tunable.\n");
2566 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2568 for (field = 0; field < _NPCM; field++) {
2569 if (pc->pc_map[field]) {
2570 bit = bsfl(pc->pc_map[field]);
2574 if (field < _NPCM) {
2575 pv = &pc->pc_pventry[field * 32 + bit];
2576 pc->pc_map[field] &= ~(1ul << bit);
2577 /* If this was the last item, move it to tail */
2578 for (field = 0; field < _NPCM; field++)
2579 if (pc->pc_map[field] != 0) {
2580 PV_STAT(pv_entry_spare--);
2581 return (pv); /* not full, return */
2583 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2584 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2585 PV_STAT(pv_entry_spare--);
2590 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2591 * global lock. If "pv_vafree" is currently non-empty, it will
2592 * remain non-empty until pmap_ptelist_alloc() completes.
2594 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2595 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2598 PV_STAT(pc_chunk_tryfail++);
2601 m = pmap_pv_reclaim(pmap);
2605 PV_STAT(pc_chunk_count++);
2606 PV_STAT(pc_chunk_allocs++);
2607 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2608 pmap_qenter((vm_offset_t)pc, &m, 1);
2610 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2611 for (field = 1; field < _NPCM; field++)
2612 pc->pc_map[field] = pc_freemask[field];
2613 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2614 pv = &pc->pc_pventry[0];
2615 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2616 PV_STAT(pv_entry_spare += _NPCPV - 1);
2620 static __inline pv_entry_t
2621 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2625 rw_assert(&pvh_global_lock, RA_WLOCKED);
2626 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2627 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2628 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2636 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2638 struct md_page *pvh;
2640 vm_offset_t va_last;
2643 rw_assert(&pvh_global_lock, RA_WLOCKED);
2644 KASSERT((pa & PDRMASK) == 0,
2645 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2648 * Transfer the 4mpage's pv entry for this mapping to the first
2651 pvh = pa_to_pvh(pa);
2652 va = trunc_4mpage(va);
2653 pv = pmap_pvh_remove(pvh, pmap, va);
2654 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2655 m = PHYS_TO_VM_PAGE(pa);
2656 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2657 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2658 va_last = va + NBPDR - PAGE_SIZE;
2661 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2662 ("pmap_pv_demote_pde: page %p is not managed", m));
2664 pmap_insert_entry(pmap, va, m);
2665 } while (va < va_last);
2668 #if VM_NRESERVLEVEL > 0
2670 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2672 struct md_page *pvh;
2674 vm_offset_t va_last;
2677 rw_assert(&pvh_global_lock, RA_WLOCKED);
2678 KASSERT((pa & PDRMASK) == 0,
2679 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2682 * Transfer the first page's pv entry for this mapping to the
2683 * 4mpage's pv list. Aside from avoiding the cost of a call
2684 * to get_pv_entry(), a transfer avoids the possibility that
2685 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2686 * removes one of the mappings that is being promoted.
2688 m = PHYS_TO_VM_PAGE(pa);
2689 va = trunc_4mpage(va);
2690 pv = pmap_pvh_remove(&m->md, pmap, va);
2691 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2692 pvh = pa_to_pvh(pa);
2693 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2694 /* Free the remaining NPTEPG - 1 pv entries. */
2695 va_last = va + NBPDR - PAGE_SIZE;
2699 pmap_pvh_free(&m->md, pmap, va);
2700 } while (va < va_last);
2702 #endif /* VM_NRESERVLEVEL > 0 */
2705 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2709 pv = pmap_pvh_remove(pvh, pmap, va);
2710 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2711 free_pv_entry(pmap, pv);
2715 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2717 struct md_page *pvh;
2719 rw_assert(&pvh_global_lock, RA_WLOCKED);
2720 pmap_pvh_free(&m->md, pmap, va);
2721 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2722 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2723 if (TAILQ_EMPTY(&pvh->pv_list))
2724 vm_page_aflag_clear(m, PGA_WRITEABLE);
2729 * Create a pv entry for page at pa for
2733 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2737 rw_assert(&pvh_global_lock, RA_WLOCKED);
2738 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2739 pv = get_pv_entry(pmap, FALSE);
2741 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2745 * Conditionally create a pv entry.
2748 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2752 rw_assert(&pvh_global_lock, RA_WLOCKED);
2753 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2754 if (pv_entry_count < pv_entry_high_water &&
2755 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2757 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2764 * Create the pv entries for each of the pages within a superpage.
2767 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags)
2769 struct md_page *pvh;
2773 rw_assert(&pvh_global_lock, RA_WLOCKED);
2774 noreclaim = (flags & PMAP_ENTER_NORECLAIM) != 0;
2775 if ((noreclaim && pv_entry_count >= pv_entry_high_water) ||
2776 (pv = get_pv_entry(pmap, noreclaim)) == NULL)
2779 pvh = pa_to_pvh(pde & PG_PS_FRAME);
2780 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2785 * Fills a page table page with mappings to consecutive physical pages.
2788 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2792 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2794 newpte += PAGE_SIZE;
2799 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2800 * 2- or 4MB page mapping is invalidated.
2803 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2805 pd_entry_t newpde, oldpde;
2806 pt_entry_t *firstpte, newpte;
2809 struct spglist free;
2812 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2814 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2815 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2816 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
2818 KASSERT((oldpde & PG_W) == 0,
2819 ("pmap_demote_pde: page table page for a wired mapping"
2823 * Invalidate the 2- or 4MB page mapping and return
2824 * "failure" if the mapping was never accessed or the
2825 * allocation of the new page table page fails.
2827 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2828 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2829 VM_ALLOC_WIRED)) == NULL) {
2831 sva = trunc_4mpage(va);
2832 pmap_remove_pde(pmap, pde, sva, &free);
2833 if ((oldpde & PG_G) == 0)
2834 pmap_invalidate_pde_page(pmap, sva, oldpde);
2835 vm_page_free_pages_toq(&free, true);
2836 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2837 " in pmap %p", va, pmap);
2840 if (pmap != kernel_pmap)
2841 pmap->pm_stats.resident_count++;
2843 mptepa = VM_PAGE_TO_PHYS(mpte);
2846 * If the page mapping is in the kernel's address space, then the
2847 * KPTmap can provide access to the page table page. Otherwise,
2848 * temporarily map the page table page (mpte) into the kernel's
2849 * address space at either PADDR1 or PADDR2.
2851 if (pmap == kernel_pmap)
2852 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2853 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2854 if ((*PMAP1 & PG_FRAME) != mptepa) {
2855 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2857 PMAP1cpu = PCPU_GET(cpuid);
2863 if (PMAP1cpu != PCPU_GET(cpuid)) {
2864 PMAP1cpu = PCPU_GET(cpuid);
2872 mtx_lock(&PMAP2mutex);
2873 if ((*PMAP2 & PG_FRAME) != mptepa) {
2874 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2875 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2879 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2880 KASSERT((oldpde & PG_A) != 0,
2881 ("pmap_demote_pde: oldpde is missing PG_A"));
2882 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2883 ("pmap_demote_pde: oldpde is missing PG_M"));
2884 newpte = oldpde & ~PG_PS;
2885 if ((newpte & PG_PDE_PAT) != 0)
2886 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2889 * If the page table page is new, initialize it.
2891 if (mpte->wire_count == 1) {
2892 mpte->wire_count = NPTEPG;
2893 pmap_fill_ptp(firstpte, newpte);
2895 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2896 ("pmap_demote_pde: firstpte and newpte map different physical"
2900 * If the mapping has changed attributes, update the page table
2903 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2904 pmap_fill_ptp(firstpte, newpte);
2907 * Demote the mapping. This pmap is locked. The old PDE has
2908 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2909 * set. Thus, there is no danger of a race with another
2910 * processor changing the setting of PG_A and/or PG_M between
2911 * the read above and the store below.
2913 if (workaround_erratum383)
2914 pmap_update_pde(pmap, va, pde, newpde);
2915 else if (pmap == kernel_pmap)
2916 pmap_kenter_pde(va, newpde);
2918 pde_store(pde, newpde);
2919 if (firstpte == PADDR2)
2920 mtx_unlock(&PMAP2mutex);
2923 * Invalidate the recursive mapping of the page table page.
2925 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2928 * Demote the pv entry. This depends on the earlier demotion
2929 * of the mapping. Specifically, the (re)creation of a per-
2930 * page pv entry might trigger the execution of pmap_collect(),
2931 * which might reclaim a newly (re)created per-page pv entry
2932 * and destroy the associated mapping. In order to destroy
2933 * the mapping, the PDE must have already changed from mapping
2934 * the 2mpage to referencing the page table page.
2936 if ((oldpde & PG_MANAGED) != 0)
2937 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2939 pmap_pde_demotions++;
2940 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2941 " in pmap %p", va, pmap);
2946 * Removes a 2- or 4MB page mapping from the kernel pmap.
2949 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2955 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2956 mpte = pmap_remove_pt_page(pmap, va);
2958 panic("pmap_remove_kernel_pde: Missing pt page.");
2960 mptepa = VM_PAGE_TO_PHYS(mpte);
2961 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2964 * Initialize the page table page.
2966 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2969 * Remove the mapping.
2971 if (workaround_erratum383)
2972 pmap_update_pde(pmap, va, pde, newpde);
2974 pmap_kenter_pde(va, newpde);
2977 * Invalidate the recursive mapping of the page table page.
2979 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2983 * pmap_remove_pde: do the things to unmap a superpage in a process
2986 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2987 struct spglist *free)
2989 struct md_page *pvh;
2991 vm_offset_t eva, va;
2994 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2995 KASSERT((sva & PDRMASK) == 0,
2996 ("pmap_remove_pde: sva is not 4mpage aligned"));
2997 oldpde = pte_load_clear(pdq);
2999 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
3002 * Machines that don't support invlpg, also don't support
3005 if ((oldpde & PG_G) != 0)
3006 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
3008 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
3009 if (oldpde & PG_MANAGED) {
3010 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
3011 pmap_pvh_free(pvh, pmap, sva);
3013 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3014 va < eva; va += PAGE_SIZE, m++) {
3015 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3018 vm_page_aflag_set(m, PGA_REFERENCED);
3019 if (TAILQ_EMPTY(&m->md.pv_list) &&
3020 TAILQ_EMPTY(&pvh->pv_list))
3021 vm_page_aflag_clear(m, PGA_WRITEABLE);
3024 if (pmap == kernel_pmap) {
3025 pmap_remove_kernel_pde(pmap, pdq, sva);
3027 mpte = pmap_remove_pt_page(pmap, sva);
3029 pmap->pm_stats.resident_count--;
3030 KASSERT(mpte->wire_count == NPTEPG,
3031 ("pmap_remove_pde: pte page wire count error"));
3032 mpte->wire_count = 0;
3033 pmap_add_delayed_free_list(mpte, free, FALSE);
3039 * pmap_remove_pte: do the things to unmap a page in a process
3042 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
3043 struct spglist *free)
3048 rw_assert(&pvh_global_lock, RA_WLOCKED);
3049 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3050 oldpte = pte_load_clear(ptq);
3051 KASSERT(oldpte != 0,
3052 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
3054 pmap->pm_stats.wired_count -= 1;
3056 * Machines that don't support invlpg, also don't support
3060 pmap_invalidate_page(kernel_pmap, va);
3061 pmap->pm_stats.resident_count -= 1;
3062 if (oldpte & PG_MANAGED) {
3063 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
3064 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3067 vm_page_aflag_set(m, PGA_REFERENCED);
3068 pmap_remove_entry(pmap, m, va);
3070 return (pmap_unuse_pt(pmap, va, free));
3074 * Remove a single page from a process address space
3077 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
3081 rw_assert(&pvh_global_lock, RA_WLOCKED);
3082 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3083 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3084 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
3086 pmap_remove_pte(pmap, pte, va, free);
3087 pmap_invalidate_page(pmap, va);
3091 * Removes the specified range of addresses from the page table page.
3094 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
3095 struct spglist *free)
3100 rw_assert(&pvh_global_lock, RA_WLOCKED);
3101 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3102 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3104 for (pte = pmap_pte_quick(pmap, sva); sva != eva; pte++,
3110 * The TLB entry for a PG_G mapping is invalidated by
3111 * pmap_remove_pte().
3113 if ((*pte & PG_G) == 0)
3116 if (pmap_remove_pte(pmap, pte, sva, free))
3123 * Remove the given range of addresses from the specified map.
3125 * It is assumed that the start and end are properly
3126 * rounded to the page size.
3129 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3133 struct spglist free;
3137 * Perform an unsynchronized read. This is, however, safe.
3139 if (pmap->pm_stats.resident_count == 0)
3145 rw_wlock(&pvh_global_lock);
3150 * special handling of removing one page. a very
3151 * common operation and easy to short circuit some
3154 if ((sva + PAGE_SIZE == eva) &&
3155 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
3156 pmap_remove_page(pmap, sva, &free);
3160 for (; sva < eva; sva = pdnxt) {
3164 * Calculate index for next page table.
3166 pdnxt = (sva + NBPDR) & ~PDRMASK;
3169 if (pmap->pm_stats.resident_count == 0)
3172 pdirindex = sva >> PDRSHIFT;
3173 ptpaddr = pmap->pm_pdir[pdirindex];
3176 * Weed out invalid mappings. Note: we assume that the page
3177 * directory table is always allocated, and in kernel virtual.
3183 * Check for large page.
3185 if ((ptpaddr & PG_PS) != 0) {
3187 * Are we removing the entire large page? If not,
3188 * demote the mapping and fall through.
3190 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3192 * The TLB entry for a PG_G mapping is
3193 * invalidated by pmap_remove_pde().
3195 if ((ptpaddr & PG_G) == 0)
3197 pmap_remove_pde(pmap,
3198 &pmap->pm_pdir[pdirindex], sva, &free);
3200 } else if (!pmap_demote_pde(pmap,
3201 &pmap->pm_pdir[pdirindex], sva)) {
3202 /* The large page mapping was destroyed. */
3208 * Limit our scan to either the end of the va represented
3209 * by the current page table page, or to the end of the
3210 * range being removed.
3215 if (pmap_remove_ptes(pmap, sva, pdnxt, &free))
3221 pmap_invalidate_all(pmap);
3222 rw_wunlock(&pvh_global_lock);
3224 vm_page_free_pages_toq(&free, true);
3228 * Routine: pmap_remove_all
3230 * Removes this physical page from
3231 * all physical maps in which it resides.
3232 * Reflects back modify bits to the pager.
3235 * Original versions of this routine were very
3236 * inefficient because they iteratively called
3237 * pmap_remove (slow...)
3241 pmap_remove_all(vm_page_t m)
3243 struct md_page *pvh;
3246 pt_entry_t *pte, tpte;
3249 struct spglist free;
3251 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3252 ("pmap_remove_all: page %p is not managed", m));
3254 rw_wlock(&pvh_global_lock);
3256 if ((m->flags & PG_FICTITIOUS) != 0)
3257 goto small_mappings;
3258 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3259 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3263 pde = pmap_pde(pmap, va);
3264 (void)pmap_demote_pde(pmap, pde, va);
3268 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3271 pmap->pm_stats.resident_count--;
3272 pde = pmap_pde(pmap, pv->pv_va);
3273 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3274 " a 4mpage in page %p's pv list", m));
3275 pte = pmap_pte_quick(pmap, pv->pv_va);
3276 tpte = pte_load_clear(pte);
3277 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3280 pmap->pm_stats.wired_count--;
3282 vm_page_aflag_set(m, PGA_REFERENCED);
3285 * Update the vm_page_t clean and reference bits.
3287 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3289 pmap_unuse_pt(pmap, pv->pv_va, &free);
3290 pmap_invalidate_page(pmap, pv->pv_va);
3291 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3292 free_pv_entry(pmap, pv);
3295 vm_page_aflag_clear(m, PGA_WRITEABLE);
3297 rw_wunlock(&pvh_global_lock);
3298 vm_page_free_pages_toq(&free, true);
3302 * pmap_protect_pde: do the things to protect a 4mpage in a process
3305 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3307 pd_entry_t newpde, oldpde;
3308 vm_offset_t eva, va;
3310 boolean_t anychanged;
3312 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3313 KASSERT((sva & PDRMASK) == 0,
3314 ("pmap_protect_pde: sva is not 4mpage aligned"));
3317 oldpde = newpde = *pde;
3318 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
3319 (PG_MANAGED | PG_M | PG_RW)) {
3321 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3322 va < eva; va += PAGE_SIZE, m++)
3325 if ((prot & VM_PROT_WRITE) == 0)
3326 newpde &= ~(PG_RW | PG_M);
3327 #if defined(PAE) || defined(PAE_TABLES)
3328 if ((prot & VM_PROT_EXECUTE) == 0)
3331 if (newpde != oldpde) {
3333 * As an optimization to future operations on this PDE, clear
3334 * PG_PROMOTED. The impending invalidation will remove any
3335 * lingering 4KB page mappings from the TLB.
3337 if (!pde_cmpset(pde, oldpde, newpde & ~PG_PROMOTED))
3339 if ((oldpde & PG_G) != 0)
3340 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
3344 return (anychanged);
3348 * Set the physical protection on the
3349 * specified range of this map as requested.
3352 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3357 boolean_t anychanged, pv_lists_locked;
3359 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3360 if (prot == VM_PROT_NONE) {
3361 pmap_remove(pmap, sva, eva);
3365 #if defined(PAE) || defined(PAE_TABLES)
3366 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3367 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3370 if (prot & VM_PROT_WRITE)
3374 if (pmap_is_current(pmap))
3375 pv_lists_locked = FALSE;
3377 pv_lists_locked = TRUE;
3379 rw_wlock(&pvh_global_lock);
3385 for (; sva < eva; sva = pdnxt) {
3386 pt_entry_t obits, pbits;
3389 pdnxt = (sva + NBPDR) & ~PDRMASK;
3393 pdirindex = sva >> PDRSHIFT;
3394 ptpaddr = pmap->pm_pdir[pdirindex];
3397 * Weed out invalid mappings. Note: we assume that the page
3398 * directory table is always allocated, and in kernel virtual.
3404 * Check for large page.
3406 if ((ptpaddr & PG_PS) != 0) {
3408 * Are we protecting the entire large page? If not,
3409 * demote the mapping and fall through.
3411 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3413 * The TLB entry for a PG_G mapping is
3414 * invalidated by pmap_protect_pde().
3416 if (pmap_protect_pde(pmap,
3417 &pmap->pm_pdir[pdirindex], sva, prot))
3421 if (!pv_lists_locked) {
3422 pv_lists_locked = TRUE;
3423 if (!rw_try_wlock(&pvh_global_lock)) {
3425 pmap_invalidate_all(
3432 if (!pmap_demote_pde(pmap,
3433 &pmap->pm_pdir[pdirindex], sva)) {
3435 * The large page mapping was
3446 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3452 * Regardless of whether a pte is 32 or 64 bits in
3453 * size, PG_RW, PG_A, and PG_M are among the least
3454 * significant 32 bits.
3456 obits = pbits = *pte;
3457 if ((pbits & PG_V) == 0)
3460 if ((prot & VM_PROT_WRITE) == 0) {
3461 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3462 (PG_MANAGED | PG_M | PG_RW)) {
3463 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3466 pbits &= ~(PG_RW | PG_M);
3468 #if defined(PAE) || defined(PAE_TABLES)
3469 if ((prot & VM_PROT_EXECUTE) == 0)
3473 if (pbits != obits) {
3474 #if defined(PAE) || defined(PAE_TABLES)
3475 if (!atomic_cmpset_64(pte, obits, pbits))
3478 if (!atomic_cmpset_int((u_int *)pte, obits,
3483 pmap_invalidate_page(pmap, sva);
3490 pmap_invalidate_all(pmap);
3491 if (pv_lists_locked) {
3493 rw_wunlock(&pvh_global_lock);
3498 #if VM_NRESERVLEVEL > 0
3500 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3501 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3502 * For promotion to occur, two conditions must be met: (1) the 4KB page
3503 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3504 * mappings must have identical characteristics.
3506 * Managed (PG_MANAGED) mappings within the kernel address space are not
3507 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3508 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3512 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3515 pt_entry_t *firstpte, oldpte, pa, *pte;
3516 vm_offset_t oldpteva;
3519 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3522 * Examine the first PTE in the specified PTP. Abort if this PTE is
3523 * either invalid, unused, or does not map the first 4KB physical page
3524 * within a 2- or 4MB page.
3526 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3529 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3530 pmap_pde_p_failures++;
3531 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3532 " in pmap %p", va, pmap);
3535 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3536 pmap_pde_p_failures++;
3537 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3538 " in pmap %p", va, pmap);
3541 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3543 * When PG_M is already clear, PG_RW can be cleared without
3544 * a TLB invalidation.
3546 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3553 * Examine each of the other PTEs in the specified PTP. Abort if this
3554 * PTE maps an unexpected 4KB physical page or does not have identical
3555 * characteristics to the first PTE.
3557 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3558 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3561 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3562 pmap_pde_p_failures++;
3563 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3564 " in pmap %p", va, pmap);
3567 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3569 * When PG_M is already clear, PG_RW can be cleared
3570 * without a TLB invalidation.
3572 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3576 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3578 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3579 " in pmap %p", oldpteva, pmap);
3581 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3582 pmap_pde_p_failures++;
3583 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3584 " in pmap %p", va, pmap);
3591 * Save the page table page in its current state until the PDE
3592 * mapping the superpage is demoted by pmap_demote_pde() or
3593 * destroyed by pmap_remove_pde().
3595 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3596 KASSERT(mpte >= vm_page_array &&
3597 mpte < &vm_page_array[vm_page_array_size],
3598 ("pmap_promote_pde: page table page is out of range"));
3599 KASSERT(mpte->pindex == va >> PDRSHIFT,
3600 ("pmap_promote_pde: page table page's pindex is wrong"));
3601 if (pmap_insert_pt_page(pmap, mpte)) {
3602 pmap_pde_p_failures++;
3604 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3610 * Promote the pv entries.
3612 if ((newpde & PG_MANAGED) != 0)
3613 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3616 * Propagate the PAT index to its proper position.
3618 if ((newpde & PG_PTE_PAT) != 0)
3619 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3622 * Map the superpage.
3624 if (workaround_erratum383)
3625 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3626 else if (pmap == kernel_pmap)
3627 pmap_kenter_pde(va, PG_PROMOTED | PG_PS | newpde);
3629 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
3631 pmap_pde_promotions++;
3632 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3633 " in pmap %p", va, pmap);
3635 #endif /* VM_NRESERVLEVEL > 0 */
3638 * Insert the given physical page (p) at
3639 * the specified virtual address (v) in the
3640 * target physical map with the protection requested.
3642 * If specified, the page will be wired down, meaning
3643 * that the related pte can not be reclaimed.
3645 * NB: This is the only routine which MAY NOT lazy-evaluate
3646 * or lose information. That is, this routine must actually
3647 * insert this page into the given map NOW.
3650 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3651 u_int flags, int8_t psind)
3655 pt_entry_t newpte, origpte;
3661 va = trunc_page(va);
3662 KASSERT((pmap == kernel_pmap && va < VM_MAX_KERNEL_ADDRESS) ||
3663 (pmap != kernel_pmap && va < VM_MAXUSER_ADDRESS),
3664 ("pmap_enter: toobig k%d %#x", pmap == kernel_pmap, va));
3665 KASSERT(va < PMAP_TRM_MIN_ADDRESS,
3666 ("pmap_enter: invalid to pmap_enter into trampoline (va: 0x%x)",
3668 KASSERT(pmap != kernel_pmap || (m->oflags & VPO_UNMANAGED) != 0 ||
3669 va < kmi.clean_sva || va >= kmi.clean_eva,
3670 ("pmap_enter: managed mapping within the clean submap"));
3671 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3672 VM_OBJECT_ASSERT_LOCKED(m->object);
3673 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
3674 ("pmap_enter: flags %u has reserved bits set", flags));
3675 pa = VM_PAGE_TO_PHYS(m);
3676 newpte = (pt_entry_t)(pa | PG_A | PG_V);
3677 if ((flags & VM_PROT_WRITE) != 0)
3679 if ((prot & VM_PROT_WRITE) != 0)
3681 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
3682 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
3683 #if defined(PAE) || defined(PAE_TABLES)
3684 if ((prot & VM_PROT_EXECUTE) == 0)
3687 if ((flags & PMAP_ENTER_WIRED) != 0)
3689 if (pmap != kernel_pmap)
3691 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
3692 if ((m->oflags & VPO_UNMANAGED) == 0)
3693 newpte |= PG_MANAGED;
3695 rw_wlock(&pvh_global_lock);
3699 /* Assert the required virtual and physical alignment. */
3700 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
3701 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3702 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m);
3706 pde = pmap_pde(pmap, va);
3707 if (pmap != kernel_pmap) {
3710 * In the case that a page table page is not resident,
3711 * we are creating it here. pmap_allocpte() handles
3714 mpte = pmap_allocpte(pmap, va, flags);
3716 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3717 ("pmap_allocpte failed with sleep allowed"));
3718 rv = KERN_RESOURCE_SHORTAGE;
3723 * va is for KVA, so pmap_demote_pde() will never fail
3724 * to install a page table page. PG_V is also
3725 * asserted by pmap_demote_pde().
3728 KASSERT(pde != NULL && (*pde & PG_V) != 0,
3729 ("KVA %#x invalid pde pdir %#jx", va,
3730 (uintmax_t)pmap->pm_pdir[PTDPTDI]));
3731 if ((*pde & PG_PS) != 0)
3732 pmap_demote_pde(pmap, pde, va);
3734 pte = pmap_pte_quick(pmap, va);
3737 * Page Directory table entry is not valid, which should not
3738 * happen. We should have either allocated the page table
3739 * page or demoted the existing mapping above.
3742 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3743 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3750 * Is the specified virtual address already mapped?
3752 if ((origpte & PG_V) != 0) {
3754 * Wiring change, just update stats. We don't worry about
3755 * wiring PT pages as they remain resident as long as there
3756 * are valid mappings in them. Hence, if a user page is wired,
3757 * the PT page will be also.
3759 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
3760 pmap->pm_stats.wired_count++;
3761 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
3762 pmap->pm_stats.wired_count--;
3765 * Remove the extra PT page reference.
3769 KASSERT(mpte->wire_count > 0,
3770 ("pmap_enter: missing reference to page table page,"
3775 * Has the physical page changed?
3777 opa = origpte & PG_FRAME;
3780 * No, might be a protection or wiring change.
3782 if ((origpte & PG_MANAGED) != 0 &&
3783 (newpte & PG_RW) != 0)
3784 vm_page_aflag_set(m, PGA_WRITEABLE);
3785 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
3791 * The physical page has changed. Temporarily invalidate
3792 * the mapping. This ensures that all threads sharing the
3793 * pmap keep a consistent view of the mapping, which is
3794 * necessary for the correct handling of COW faults. It
3795 * also permits reuse of the old mapping's PV entry,
3796 * avoiding an allocation.
3798 * For consistency, handle unmanaged mappings the same way.
3800 origpte = pte_load_clear(pte);
3801 KASSERT((origpte & PG_FRAME) == opa,
3802 ("pmap_enter: unexpected pa update for %#x", va));
3803 if ((origpte & PG_MANAGED) != 0) {
3804 om = PHYS_TO_VM_PAGE(opa);
3807 * The pmap lock is sufficient to synchronize with
3808 * concurrent calls to pmap_page_test_mappings() and
3809 * pmap_ts_referenced().
3811 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3813 if ((origpte & PG_A) != 0)
3814 vm_page_aflag_set(om, PGA_REFERENCED);
3815 pv = pmap_pvh_remove(&om->md, pmap, va);
3816 if ((newpte & PG_MANAGED) == 0)
3817 free_pv_entry(pmap, pv);
3818 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3819 TAILQ_EMPTY(&om->md.pv_list) &&
3820 ((om->flags & PG_FICTITIOUS) != 0 ||
3821 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3822 vm_page_aflag_clear(om, PGA_WRITEABLE);
3824 if ((origpte & PG_A) != 0)
3825 pmap_invalidate_page(pmap, va);
3829 * Increment the counters.
3831 if ((newpte & PG_W) != 0)
3832 pmap->pm_stats.wired_count++;
3833 pmap->pm_stats.resident_count++;
3837 * Enter on the PV list if part of our managed memory.
3839 if ((newpte & PG_MANAGED) != 0) {
3841 pv = get_pv_entry(pmap, FALSE);
3844 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3845 if ((newpte & PG_RW) != 0)
3846 vm_page_aflag_set(m, PGA_WRITEABLE);
3852 if ((origpte & PG_V) != 0) {
3854 origpte = pte_load_store(pte, newpte);
3855 KASSERT((origpte & PG_FRAME) == pa,
3856 ("pmap_enter: unexpected pa update for %#x", va));
3857 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
3859 if ((origpte & PG_MANAGED) != 0)
3863 * Although the PTE may still have PG_RW set, TLB
3864 * invalidation may nonetheless be required because
3865 * the PTE no longer has PG_M set.
3868 #if defined(PAE) || defined(PAE_TABLES)
3869 else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
3871 * This PTE change does not require TLB invalidation.
3876 if ((origpte & PG_A) != 0)
3877 pmap_invalidate_page(pmap, va);
3879 pte_store(pte, newpte);
3883 #if VM_NRESERVLEVEL > 0
3885 * If both the page table page and the reservation are fully
3886 * populated, then attempt promotion.
3888 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3889 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3890 vm_reserv_level_iffullpop(m) == 0)
3891 pmap_promote_pde(pmap, pde, va);
3897 rw_wunlock(&pvh_global_lock);
3903 * Tries to create a read- and/or execute-only 2 or 4 MB page mapping. Returns
3904 * true if successful. Returns false if (1) a mapping already exists at the
3905 * specified virtual address or (2) a PV entry cannot be allocated without
3906 * reclaiming another PV entry.
3909 pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3913 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3914 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
3916 if ((m->oflags & VPO_UNMANAGED) == 0)
3917 newpde |= PG_MANAGED;
3918 #if defined(PAE) || defined(PAE_TABLES)
3919 if ((prot & VM_PROT_EXECUTE) == 0)
3922 if (pmap != kernel_pmap)
3924 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
3925 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL) ==
3930 * Tries to create the specified 2 or 4 MB page mapping. Returns KERN_SUCCESS
3931 * if the mapping was created, and either KERN_FAILURE or
3932 * KERN_RESOURCE_SHORTAGE otherwise. Returns KERN_FAILURE if
3933 * PMAP_ENTER_NOREPLACE was specified and a mapping already exists at the
3934 * specified virtual address. Returns KERN_RESOURCE_SHORTAGE if
3935 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3937 * The parameter "m" is only used when creating a managed, writeable mapping.
3940 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
3943 struct spglist free;
3944 pd_entry_t oldpde, *pde;
3947 rw_assert(&pvh_global_lock, RA_WLOCKED);
3948 KASSERT((newpde & (PG_M | PG_RW)) != PG_RW,
3949 ("pmap_enter_pde: newpde is missing PG_M"));
3950 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3951 pde = pmap_pde(pmap, va);
3953 if ((oldpde & PG_V) != 0) {
3954 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
3955 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3956 " in pmap %p", va, pmap);
3957 return (KERN_FAILURE);
3959 /* Break the existing mapping(s). */
3961 if ((oldpde & PG_PS) != 0) {
3963 * If the PDE resulted from a promotion, then a
3964 * reserved PT page could be freed.
3966 (void)pmap_remove_pde(pmap, pde, va, &free);
3967 if ((oldpde & PG_G) == 0)
3968 pmap_invalidate_pde_page(pmap, va, oldpde);
3970 if (pmap_remove_ptes(pmap, va, va + NBPDR, &free))
3971 pmap_invalidate_all(pmap);
3973 vm_page_free_pages_toq(&free, true);
3974 if (pmap == kernel_pmap) {
3975 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3976 if (pmap_insert_pt_page(pmap, mt)) {
3978 * XXX Currently, this can't happen because
3979 * we do not perform pmap_enter(psind == 1)
3980 * on the kernel pmap.
3982 panic("pmap_enter_pde: trie insert failed");
3985 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
3988 if ((newpde & PG_MANAGED) != 0) {
3990 * Abort this mapping if its PV entry could not be created.
3992 if (!pmap_pv_insert_pde(pmap, va, newpde, flags)) {
3993 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3994 " in pmap %p", va, pmap);
3995 return (KERN_RESOURCE_SHORTAGE);
3997 if ((newpde & PG_RW) != 0) {
3998 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
3999 vm_page_aflag_set(mt, PGA_WRITEABLE);
4004 * Increment counters.
4006 if ((newpde & PG_W) != 0)
4007 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
4008 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
4011 * Map the superpage. (This is not a promoted mapping; there will not
4012 * be any lingering 4KB page mappings in the TLB.)
4014 pde_store(pde, newpde);
4016 pmap_pde_mappings++;
4017 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
4018 " in pmap %p", va, pmap);
4019 return (KERN_SUCCESS);
4023 * Maps a sequence of resident pages belonging to the same object.
4024 * The sequence begins with the given page m_start. This page is
4025 * mapped at the given virtual address start. Each subsequent page is
4026 * mapped at a virtual address that is offset from start by the same
4027 * amount as the page is offset from m_start within the object. The
4028 * last page in the sequence is the page with the largest offset from
4029 * m_start that can be mapped at a virtual address less than the given
4030 * virtual address end. Not every virtual page between start and end
4031 * is mapped; only those for which a resident page exists with the
4032 * corresponding offset from m_start are mapped.
4035 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4036 vm_page_t m_start, vm_prot_t prot)
4040 vm_pindex_t diff, psize;
4042 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4044 psize = atop(end - start);
4047 rw_wlock(&pvh_global_lock);
4049 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4050 va = start + ptoa(diff);
4051 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
4052 m->psind == 1 && pg_ps_enabled &&
4053 pmap_enter_4mpage(pmap, va, m, prot))
4054 m = &m[NBPDR / PAGE_SIZE - 1];
4056 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
4058 m = TAILQ_NEXT(m, listq);
4060 rw_wunlock(&pvh_global_lock);
4065 * this code makes some *MAJOR* assumptions:
4066 * 1. Current pmap & pmap exists.
4069 * 4. No page table pages.
4070 * but is *MUCH* faster than pmap_enter...
4074 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4077 rw_wlock(&pvh_global_lock);
4079 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
4080 rw_wunlock(&pvh_global_lock);
4085 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4086 vm_prot_t prot, vm_page_t mpte)
4090 struct spglist free;
4092 KASSERT(pmap != kernel_pmap || va < kmi.clean_sva ||
4093 va >= kmi.clean_eva || (m->oflags & VPO_UNMANAGED) != 0,
4094 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4095 rw_assert(&pvh_global_lock, RA_WLOCKED);
4096 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4099 * In the case that a page table page is not
4100 * resident, we are creating it here.
4102 if (pmap != kernel_pmap) {
4107 * Calculate pagetable page index
4109 ptepindex = va >> PDRSHIFT;
4110 if (mpte && (mpte->pindex == ptepindex)) {
4114 * Get the page directory entry
4116 ptepa = pmap->pm_pdir[ptepindex];
4119 * If the page table page is mapped, we just increment
4120 * the hold count, and activate it.
4125 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
4128 mpte = _pmap_allocpte(pmap, ptepindex,
4129 PMAP_ENTER_NOSLEEP);
4139 pte = pmap_pte_quick(pmap, va);
4150 * Enter on the PV list if part of our managed memory.
4152 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4153 !pmap_try_insert_pv_entry(pmap, va, m)) {
4156 if (pmap_unwire_ptp(pmap, mpte, &free)) {
4157 pmap_invalidate_page(pmap, va);
4158 vm_page_free_pages_toq(&free, true);
4168 * Increment counters
4170 pmap->pm_stats.resident_count++;
4172 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 0);
4173 #if defined(PAE) || defined(PAE_TABLES)
4174 if ((prot & VM_PROT_EXECUTE) == 0)
4179 * Now validate mapping with RO protection
4181 if ((m->oflags & VPO_UNMANAGED) != 0)
4182 pte_store(pte, pa | PG_V | PG_U);
4184 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
4190 * Make a temporary mapping for a physical address. This is only intended
4191 * to be used for panic dumps.
4194 pmap_kenter_temporary(vm_paddr_t pa, int i)
4198 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
4199 pmap_kenter(va, pa);
4201 return ((void *)crashdumpmap);
4205 * This code maps large physical mmap regions into the
4206 * processor address space. Note that some shortcuts
4207 * are taken, but the code works.
4210 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4211 vm_pindex_t pindex, vm_size_t size)
4214 vm_paddr_t pa, ptepa;
4218 VM_OBJECT_ASSERT_WLOCKED(object);
4219 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4220 ("pmap_object_init_pt: non-device object"));
4221 if (pg_ps_enabled &&
4222 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
4223 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4225 p = vm_page_lookup(object, pindex);
4226 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4227 ("pmap_object_init_pt: invalid page %p", p));
4228 pat_mode = p->md.pat_mode;
4231 * Abort the mapping if the first page is not physically
4232 * aligned to a 2/4MB page boundary.
4234 ptepa = VM_PAGE_TO_PHYS(p);
4235 if (ptepa & (NBPDR - 1))
4239 * Skip the first page. Abort the mapping if the rest of
4240 * the pages are not physically contiguous or have differing
4241 * memory attributes.
4243 p = TAILQ_NEXT(p, listq);
4244 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4246 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4247 ("pmap_object_init_pt: invalid page %p", p));
4248 if (pa != VM_PAGE_TO_PHYS(p) ||
4249 pat_mode != p->md.pat_mode)
4251 p = TAILQ_NEXT(p, listq);
4255 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
4256 * "size" is a multiple of 2/4M, adding the PAT setting to
4257 * "pa" will not affect the termination of this loop.
4260 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
4261 pa < ptepa + size; pa += NBPDR) {
4262 pde = pmap_pde(pmap, addr);
4264 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4265 PG_U | PG_RW | PG_V);
4266 pmap->pm_stats.resident_count += NBPDR /
4268 pmap_pde_mappings++;
4270 /* Else continue on if the PDE is already valid. */
4278 * Clear the wired attribute from the mappings for the specified range of
4279 * addresses in the given pmap. Every valid mapping within that range
4280 * must have the wired attribute set. In contrast, invalid mappings
4281 * cannot have the wired attribute set, so they are ignored.
4283 * The wired attribute of the page table entry is not a hardware feature,
4284 * so there is no need to invalidate any TLB entries.
4287 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4292 boolean_t pv_lists_locked;
4294 if (pmap_is_current(pmap))
4295 pv_lists_locked = FALSE;
4297 pv_lists_locked = TRUE;
4299 rw_wlock(&pvh_global_lock);
4303 for (; sva < eva; sva = pdnxt) {
4304 pdnxt = (sva + NBPDR) & ~PDRMASK;
4307 pde = pmap_pde(pmap, sva);
4308 if ((*pde & PG_V) == 0)
4310 if ((*pde & PG_PS) != 0) {
4311 if ((*pde & PG_W) == 0)
4312 panic("pmap_unwire: pde %#jx is missing PG_W",
4316 * Are we unwiring the entire large page? If not,
4317 * demote the mapping and fall through.
4319 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4321 * Regardless of whether a pde (or pte) is 32
4322 * or 64 bits in size, PG_W is among the least
4323 * significant 32 bits.
4325 atomic_clear_int((u_int *)pde, PG_W);
4326 pmap->pm_stats.wired_count -= NBPDR /
4330 if (!pv_lists_locked) {
4331 pv_lists_locked = TRUE;
4332 if (!rw_try_wlock(&pvh_global_lock)) {
4339 if (!pmap_demote_pde(pmap, pde, sva))
4340 panic("pmap_unwire: demotion failed");
4345 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4347 if ((*pte & PG_V) == 0)
4349 if ((*pte & PG_W) == 0)
4350 panic("pmap_unwire: pte %#jx is missing PG_W",
4354 * PG_W must be cleared atomically. Although the pmap
4355 * lock synchronizes access to PG_W, another processor
4356 * could be setting PG_M and/or PG_A concurrently.
4358 * PG_W is among the least significant 32 bits.
4360 atomic_clear_int((u_int *)pte, PG_W);
4361 pmap->pm_stats.wired_count--;
4364 if (pv_lists_locked) {
4366 rw_wunlock(&pvh_global_lock);
4373 * Copy the range specified by src_addr/len
4374 * from the source map to the range dst_addr/len
4375 * in the destination map.
4377 * This routine is only advisory and need not do anything. Since
4378 * current pmap is always the kernel pmap when executing in
4379 * kernel, and we do not copy from the kernel pmap to a user
4380 * pmap, this optimization is not usable in 4/4G full split i386
4385 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4386 vm_offset_t src_addr)
4388 struct spglist free;
4389 pt_entry_t *src_pte, *dst_pte, ptetemp;
4390 pd_entry_t srcptepaddr;
4391 vm_page_t dstmpte, srcmpte;
4392 vm_offset_t addr, end_addr, pdnxt;
4395 if (dst_addr != src_addr)
4398 end_addr = src_addr + len;
4400 rw_wlock(&pvh_global_lock);
4401 if (dst_pmap < src_pmap) {
4402 PMAP_LOCK(dst_pmap);
4403 PMAP_LOCK(src_pmap);
4405 PMAP_LOCK(src_pmap);
4406 PMAP_LOCK(dst_pmap);
4409 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4410 KASSERT(addr < PMAP_TRM_MIN_ADDRESS,
4411 ("pmap_copy: invalid to pmap_copy the trampoline"));
4413 pdnxt = (addr + NBPDR) & ~PDRMASK;
4416 ptepindex = addr >> PDRSHIFT;
4418 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4419 if (srcptepaddr == 0)
4422 if (srcptepaddr & PG_PS) {
4423 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4425 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4426 ((srcptepaddr & PG_MANAGED) == 0 ||
4427 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
4428 PMAP_ENTER_NORECLAIM))) {
4429 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4431 dst_pmap->pm_stats.resident_count +=
4433 pmap_pde_mappings++;
4438 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4439 KASSERT(srcmpte->wire_count > 0,
4440 ("pmap_copy: source page table page is unused"));
4442 if (pdnxt > end_addr)
4445 src_pte = pmap_pte_quick3(src_pmap, addr);
4446 while (addr < pdnxt) {
4449 * we only virtual copy managed pages
4451 if ((ptetemp & PG_MANAGED) != 0) {
4452 dstmpte = pmap_allocpte(dst_pmap, addr,
4453 PMAP_ENTER_NOSLEEP);
4454 if (dstmpte == NULL)
4456 dst_pte = pmap_pte_quick(dst_pmap, addr);
4457 if (*dst_pte == 0 &&
4458 pmap_try_insert_pv_entry(dst_pmap, addr,
4459 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4461 * Clear the wired, modified, and
4462 * accessed (referenced) bits
4465 *dst_pte = ptetemp & ~(PG_W | PG_M |
4467 dst_pmap->pm_stats.resident_count++;
4470 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4472 pmap_invalidate_page(dst_pmap,
4474 vm_page_free_pages_toq(&free,
4479 if (dstmpte->wire_count >= srcmpte->wire_count)
4488 rw_wunlock(&pvh_global_lock);
4489 PMAP_UNLOCK(src_pmap);
4490 PMAP_UNLOCK(dst_pmap);
4494 * Zero 1 page of virtual memory mapped from a hardware page by the caller.
4496 static __inline void
4497 pagezero(void *page)
4499 #if defined(I686_CPU)
4500 if (cpu_class == CPUCLASS_686) {
4501 if (cpu_feature & CPUID_SSE2)
4502 sse2_pagezero(page);
4504 i686_pagezero(page);
4507 bzero(page, PAGE_SIZE);
4511 * Zero the specified hardware page.
4514 pmap_zero_page(vm_page_t m)
4516 pt_entry_t *cmap_pte2;
4521 cmap_pte2 = pc->pc_cmap_pte2;
4522 mtx_lock(&pc->pc_cmap_lock);
4524 panic("pmap_zero_page: CMAP2 busy");
4525 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4526 pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
4527 invlcaddr(pc->pc_cmap_addr2);
4528 pagezero(pc->pc_cmap_addr2);
4532 * Unpin the thread before releasing the lock. Otherwise the thread
4533 * could be rescheduled while still bound to the current CPU, only
4534 * to unpin itself immediately upon resuming execution.
4537 mtx_unlock(&pc->pc_cmap_lock);
4541 * Zero an an area within a single hardware page. off and size must not
4542 * cover an area beyond a single hardware page.
4545 pmap_zero_page_area(vm_page_t m, int off, int size)
4547 pt_entry_t *cmap_pte2;
4552 cmap_pte2 = pc->pc_cmap_pte2;
4553 mtx_lock(&pc->pc_cmap_lock);
4555 panic("pmap_zero_page_area: CMAP2 busy");
4556 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4557 pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
4558 invlcaddr(pc->pc_cmap_addr2);
4559 if (off == 0 && size == PAGE_SIZE)
4560 pagezero(pc->pc_cmap_addr2);
4562 bzero(pc->pc_cmap_addr2 + off, size);
4565 mtx_unlock(&pc->pc_cmap_lock);
4569 * Copy 1 specified hardware page to another.
4572 pmap_copy_page(vm_page_t src, vm_page_t dst)
4574 pt_entry_t *cmap_pte1, *cmap_pte2;
4579 cmap_pte1 = pc->pc_cmap_pte1;
4580 cmap_pte2 = pc->pc_cmap_pte2;
4581 mtx_lock(&pc->pc_cmap_lock);
4583 panic("pmap_copy_page: CMAP1 busy");
4585 panic("pmap_copy_page: CMAP2 busy");
4586 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4587 pmap_cache_bits(kernel_pmap, src->md.pat_mode, 0);
4588 invlcaddr(pc->pc_cmap_addr1);
4589 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4590 pmap_cache_bits(kernel_pmap, dst->md.pat_mode, 0);
4591 invlcaddr(pc->pc_cmap_addr2);
4592 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE);
4596 mtx_unlock(&pc->pc_cmap_lock);
4599 int unmapped_buf_allowed = 1;
4602 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4603 vm_offset_t b_offset, int xfersize)
4605 vm_page_t a_pg, b_pg;
4607 vm_offset_t a_pg_offset, b_pg_offset;
4608 pt_entry_t *cmap_pte1, *cmap_pte2;
4614 cmap_pte1 = pc->pc_cmap_pte1;
4615 cmap_pte2 = pc->pc_cmap_pte2;
4616 mtx_lock(&pc->pc_cmap_lock);
4617 if (*cmap_pte1 != 0)
4618 panic("pmap_copy_pages: CMAP1 busy");
4619 if (*cmap_pte2 != 0)
4620 panic("pmap_copy_pages: CMAP2 busy");
4621 while (xfersize > 0) {
4622 a_pg = ma[a_offset >> PAGE_SHIFT];
4623 a_pg_offset = a_offset & PAGE_MASK;
4624 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4625 b_pg = mb[b_offset >> PAGE_SHIFT];
4626 b_pg_offset = b_offset & PAGE_MASK;
4627 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4628 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4629 pmap_cache_bits(kernel_pmap, a_pg->md.pat_mode, 0);
4630 invlcaddr(pc->pc_cmap_addr1);
4631 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4632 PG_M | pmap_cache_bits(kernel_pmap, b_pg->md.pat_mode, 0);
4633 invlcaddr(pc->pc_cmap_addr2);
4634 a_cp = pc->pc_cmap_addr1 + a_pg_offset;
4635 b_cp = pc->pc_cmap_addr2 + b_pg_offset;
4636 bcopy(a_cp, b_cp, cnt);
4644 mtx_unlock(&pc->pc_cmap_lock);
4648 * Returns true if the pmap's pv is one of the first
4649 * 16 pvs linked to from this page. This count may
4650 * be changed upwards or downwards in the future; it
4651 * is only necessary that true be returned for a small
4652 * subset of pmaps for proper page aging.
4655 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4657 struct md_page *pvh;
4662 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4663 ("pmap_page_exists_quick: page %p is not managed", m));
4665 rw_wlock(&pvh_global_lock);
4666 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4667 if (PV_PMAP(pv) == pmap) {
4675 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4676 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4677 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4678 if (PV_PMAP(pv) == pmap) {
4687 rw_wunlock(&pvh_global_lock);
4692 * pmap_page_wired_mappings:
4694 * Return the number of managed mappings to the given physical page
4698 pmap_page_wired_mappings(vm_page_t m)
4703 if ((m->oflags & VPO_UNMANAGED) != 0)
4705 rw_wlock(&pvh_global_lock);
4706 count = pmap_pvh_wired_mappings(&m->md, count);
4707 if ((m->flags & PG_FICTITIOUS) == 0) {
4708 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4711 rw_wunlock(&pvh_global_lock);
4716 * pmap_pvh_wired_mappings:
4718 * Return the updated number "count" of managed mappings that are wired.
4721 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4727 rw_assert(&pvh_global_lock, RA_WLOCKED);
4729 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4732 pte = pmap_pte_quick(pmap, pv->pv_va);
4733 if ((*pte & PG_W) != 0)
4742 * Returns TRUE if the given page is mapped individually or as part of
4743 * a 4mpage. Otherwise, returns FALSE.
4746 pmap_page_is_mapped(vm_page_t m)
4750 if ((m->oflags & VPO_UNMANAGED) != 0)
4752 rw_wlock(&pvh_global_lock);
4753 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4754 ((m->flags & PG_FICTITIOUS) == 0 &&
4755 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4756 rw_wunlock(&pvh_global_lock);
4761 * Remove all pages from specified address space
4762 * this aids process exit speeds. Also, this code
4763 * is special cased for current process only, but
4764 * can have the more generic (and slightly slower)
4765 * mode enabled. This is much faster than pmap_remove
4766 * in the case of running down an entire address space.
4769 pmap_remove_pages(pmap_t pmap)
4771 pt_entry_t *pte, tpte;
4772 vm_page_t m, mpte, mt;
4774 struct md_page *pvh;
4775 struct pv_chunk *pc, *npc;
4776 struct spglist free;
4779 uint32_t inuse, bitmask;
4782 if (pmap != PCPU_GET(curpmap)) {
4783 printf("warning: pmap_remove_pages called with non-current pmap\n");
4787 rw_wlock(&pvh_global_lock);
4790 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4791 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4794 for (field = 0; field < _NPCM; field++) {
4795 inuse = ~pc->pc_map[field] & pc_freemask[field];
4796 while (inuse != 0) {
4798 bitmask = 1UL << bit;
4799 idx = field * 32 + bit;
4800 pv = &pc->pc_pventry[idx];
4803 pte = pmap_pde(pmap, pv->pv_va);
4805 if ((tpte & PG_PS) == 0) {
4806 pte = pmap_pte_quick(pmap, pv->pv_va);
4807 tpte = *pte & ~PG_PTE_PAT;
4812 "TPTE at %p IS ZERO @ VA %08x\n",
4818 * We cannot remove wired pages from a process' mapping at this time
4825 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4826 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4827 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4828 m, (uintmax_t)m->phys_addr,
4831 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4832 m < &vm_page_array[vm_page_array_size],
4833 ("pmap_remove_pages: bad tpte %#jx",
4839 * Update the vm_page_t clean/reference bits.
4841 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4842 if ((tpte & PG_PS) != 0) {
4843 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4850 PV_STAT(pv_entry_frees++);
4851 PV_STAT(pv_entry_spare++);
4853 pc->pc_map[field] |= bitmask;
4854 if ((tpte & PG_PS) != 0) {
4855 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4856 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4857 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4858 if (TAILQ_EMPTY(&pvh->pv_list)) {
4859 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4860 if (TAILQ_EMPTY(&mt->md.pv_list))
4861 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4863 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
4865 pmap->pm_stats.resident_count--;
4866 KASSERT(mpte->wire_count == NPTEPG,
4867 ("pmap_remove_pages: pte page wire count error"));
4868 mpte->wire_count = 0;
4869 pmap_add_delayed_free_list(mpte, &free, FALSE);
4872 pmap->pm_stats.resident_count--;
4873 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4874 if (TAILQ_EMPTY(&m->md.pv_list) &&
4875 (m->flags & PG_FICTITIOUS) == 0) {
4876 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4877 if (TAILQ_EMPTY(&pvh->pv_list))
4878 vm_page_aflag_clear(m, PGA_WRITEABLE);
4880 pmap_unuse_pt(pmap, pv->pv_va, &free);
4885 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4890 pmap_invalidate_all(pmap);
4891 rw_wunlock(&pvh_global_lock);
4893 vm_page_free_pages_toq(&free, true);
4899 * Return whether or not the specified physical page was modified
4900 * in any physical maps.
4903 pmap_is_modified(vm_page_t m)
4907 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4908 ("pmap_is_modified: page %p is not managed", m));
4911 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4912 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4913 * is clear, no PTEs can have PG_M set.
4915 VM_OBJECT_ASSERT_WLOCKED(m->object);
4916 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4918 rw_wlock(&pvh_global_lock);
4919 rv = pmap_is_modified_pvh(&m->md) ||
4920 ((m->flags & PG_FICTITIOUS) == 0 &&
4921 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4922 rw_wunlock(&pvh_global_lock);
4927 * Returns TRUE if any of the given mappings were used to modify
4928 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4929 * mappings are supported.
4932 pmap_is_modified_pvh(struct md_page *pvh)
4939 rw_assert(&pvh_global_lock, RA_WLOCKED);
4942 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4945 pte = pmap_pte_quick(pmap, pv->pv_va);
4946 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4956 * pmap_is_prefaultable:
4958 * Return whether or not the specified virtual address is elgible
4962 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4969 pde = *pmap_pde(pmap, addr);
4970 if (pde != 0 && (pde & PG_PS) == 0)
4971 rv = pmap_pte_ufast(pmap, addr, pde) == 0;
4977 * pmap_is_referenced:
4979 * Return whether or not the specified physical page was referenced
4980 * in any physical maps.
4983 pmap_is_referenced(vm_page_t m)
4987 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4988 ("pmap_is_referenced: page %p is not managed", m));
4989 rw_wlock(&pvh_global_lock);
4990 rv = pmap_is_referenced_pvh(&m->md) ||
4991 ((m->flags & PG_FICTITIOUS) == 0 &&
4992 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4993 rw_wunlock(&pvh_global_lock);
4998 * Returns TRUE if any of the given mappings were referenced and FALSE
4999 * otherwise. Both page and 4mpage mappings are supported.
5002 pmap_is_referenced_pvh(struct md_page *pvh)
5009 rw_assert(&pvh_global_lock, RA_WLOCKED);
5012 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5015 pte = pmap_pte_quick(pmap, pv->pv_va);
5016 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
5026 * Clear the write and modified bits in each of the given page's mappings.
5029 pmap_remove_write(vm_page_t m)
5031 struct md_page *pvh;
5032 pv_entry_t next_pv, pv;
5035 pt_entry_t oldpte, *pte;
5038 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5039 ("pmap_remove_write: page %p is not managed", m));
5042 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5043 * set by another thread while the object is locked. Thus,
5044 * if PGA_WRITEABLE is clear, no page table entries need updating.
5046 VM_OBJECT_ASSERT_WLOCKED(m->object);
5047 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5049 rw_wlock(&pvh_global_lock);
5051 if ((m->flags & PG_FICTITIOUS) != 0)
5052 goto small_mappings;
5053 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5054 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5058 pde = pmap_pde(pmap, va);
5059 if ((*pde & PG_RW) != 0)
5060 (void)pmap_demote_pde(pmap, pde, va);
5064 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5067 pde = pmap_pde(pmap, pv->pv_va);
5068 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
5069 " a 4mpage in page %p's pv list", m));
5070 pte = pmap_pte_quick(pmap, pv->pv_va);
5073 if ((oldpte & PG_RW) != 0) {
5075 * Regardless of whether a pte is 32 or 64 bits
5076 * in size, PG_RW and PG_M are among the least
5077 * significant 32 bits.
5079 if (!atomic_cmpset_int((u_int *)pte, oldpte,
5080 oldpte & ~(PG_RW | PG_M)))
5082 if ((oldpte & PG_M) != 0)
5084 pmap_invalidate_page(pmap, pv->pv_va);
5088 vm_page_aflag_clear(m, PGA_WRITEABLE);
5090 rw_wunlock(&pvh_global_lock);
5094 * pmap_ts_referenced:
5096 * Return a count of reference bits for a page, clearing those bits.
5097 * It is not necessary for every reference bit to be cleared, but it
5098 * is necessary that 0 only be returned when there are truly no
5099 * reference bits set.
5101 * As an optimization, update the page's dirty field if a modified bit is
5102 * found while counting reference bits. This opportunistic update can be
5103 * performed at low cost and can eliminate the need for some future calls
5104 * to pmap_is_modified(). However, since this function stops after
5105 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5106 * dirty pages. Those dirty pages will only be detected by a future call
5107 * to pmap_is_modified().
5110 pmap_ts_referenced(vm_page_t m)
5112 struct md_page *pvh;
5120 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5121 ("pmap_ts_referenced: page %p is not managed", m));
5122 pa = VM_PAGE_TO_PHYS(m);
5123 pvh = pa_to_pvh(pa);
5124 rw_wlock(&pvh_global_lock);
5126 if ((m->flags & PG_FICTITIOUS) != 0 ||
5127 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5128 goto small_mappings;
5133 pde = pmap_pde(pmap, pv->pv_va);
5134 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5136 * Although "*pde" is mapping a 2/4MB page, because
5137 * this function is called at a 4KB page granularity,
5138 * we only update the 4KB page under test.
5142 if ((*pde & PG_A) != 0) {
5144 * Since this reference bit is shared by either 1024
5145 * or 512 4KB pages, it should not be cleared every
5146 * time it is tested. Apply a simple "hash" function
5147 * on the physical page number, the virtual superpage
5148 * number, and the pmap address to select one 4KB page
5149 * out of the 1024 or 512 on which testing the
5150 * reference bit will result in clearing that bit.
5151 * This function is designed to avoid the selection of
5152 * the same 4KB page for every 2- or 4MB page mapping.
5154 * On demotion, a mapping that hasn't been referenced
5155 * is simply destroyed. To avoid the possibility of a
5156 * subsequent page fault on a demoted wired mapping,
5157 * always leave its reference bit set. Moreover,
5158 * since the superpage is wired, the current state of
5159 * its reference bit won't affect page replacement.
5161 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
5162 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
5163 (*pde & PG_W) == 0) {
5164 atomic_clear_int((u_int *)pde, PG_A);
5165 pmap_invalidate_page(pmap, pv->pv_va);
5170 /* Rotate the PV list if it has more than one entry. */
5171 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5172 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5173 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5175 if (rtval >= PMAP_TS_REFERENCED_MAX)
5177 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5179 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5185 pde = pmap_pde(pmap, pv->pv_va);
5186 KASSERT((*pde & PG_PS) == 0,
5187 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
5189 pte = pmap_pte_quick(pmap, pv->pv_va);
5190 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5192 if ((*pte & PG_A) != 0) {
5193 atomic_clear_int((u_int *)pte, PG_A);
5194 pmap_invalidate_page(pmap, pv->pv_va);
5198 /* Rotate the PV list if it has more than one entry. */
5199 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5200 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5201 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5203 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
5204 PMAP_TS_REFERENCED_MAX);
5207 rw_wunlock(&pvh_global_lock);
5212 * Apply the given advice to the specified range of addresses within the
5213 * given pmap. Depending on the advice, clear the referenced and/or
5214 * modified flags in each mapping and set the mapped page's dirty field.
5217 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5219 pd_entry_t oldpde, *pde;
5221 vm_offset_t va, pdnxt;
5223 boolean_t anychanged, pv_lists_locked;
5225 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5227 if (pmap_is_current(pmap))
5228 pv_lists_locked = FALSE;
5230 pv_lists_locked = TRUE;
5232 rw_wlock(&pvh_global_lock);
5237 for (; sva < eva; sva = pdnxt) {
5238 pdnxt = (sva + NBPDR) & ~PDRMASK;
5241 pde = pmap_pde(pmap, sva);
5243 if ((oldpde & PG_V) == 0)
5245 else if ((oldpde & PG_PS) != 0) {
5246 if ((oldpde & PG_MANAGED) == 0)
5248 if (!pv_lists_locked) {
5249 pv_lists_locked = TRUE;
5250 if (!rw_try_wlock(&pvh_global_lock)) {
5252 pmap_invalidate_all(pmap);
5258 if (!pmap_demote_pde(pmap, pde, sva)) {
5260 * The large page mapping was destroyed.
5266 * Unless the page mappings are wired, remove the
5267 * mapping to a single page so that a subsequent
5268 * access may repromote. Since the underlying page
5269 * table page is fully populated, this removal never
5270 * frees a page table page.
5272 if ((oldpde & PG_W) == 0) {
5273 pte = pmap_pte_quick(pmap, sva);
5274 KASSERT((*pte & PG_V) != 0,
5275 ("pmap_advise: invalid PTE"));
5276 pmap_remove_pte(pmap, pte, sva, NULL);
5283 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
5285 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
5287 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5288 if (advice == MADV_DONTNEED) {
5290 * Future calls to pmap_is_modified()
5291 * can be avoided by making the page
5294 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
5297 atomic_clear_int((u_int *)pte, PG_M | PG_A);
5298 } else if ((*pte & PG_A) != 0)
5299 atomic_clear_int((u_int *)pte, PG_A);
5302 if ((*pte & PG_G) != 0) {
5310 pmap_invalidate_range(pmap, va, sva);
5315 pmap_invalidate_range(pmap, va, sva);
5318 pmap_invalidate_all(pmap);
5319 if (pv_lists_locked) {
5321 rw_wunlock(&pvh_global_lock);
5327 * Clear the modify bits on the specified physical page.
5330 pmap_clear_modify(vm_page_t m)
5332 struct md_page *pvh;
5333 pv_entry_t next_pv, pv;
5335 pd_entry_t oldpde, *pde;
5336 pt_entry_t oldpte, *pte;
5339 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5340 ("pmap_clear_modify: page %p is not managed", m));
5341 VM_OBJECT_ASSERT_WLOCKED(m->object);
5342 KASSERT(!vm_page_xbusied(m),
5343 ("pmap_clear_modify: page %p is exclusive busied", m));
5346 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5347 * If the object containing the page is locked and the page is not
5348 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5350 if ((m->aflags & PGA_WRITEABLE) == 0)
5352 rw_wlock(&pvh_global_lock);
5354 if ((m->flags & PG_FICTITIOUS) != 0)
5355 goto small_mappings;
5356 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5357 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5361 pde = pmap_pde(pmap, va);
5363 if ((oldpde & PG_RW) != 0) {
5364 if (pmap_demote_pde(pmap, pde, va)) {
5365 if ((oldpde & PG_W) == 0) {
5367 * Write protect the mapping to a
5368 * single page so that a subsequent
5369 * write access may repromote.
5371 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5373 pte = pmap_pte_quick(pmap, va);
5375 if ((oldpte & PG_V) != 0) {
5377 * Regardless of whether a pte is 32 or 64 bits
5378 * in size, PG_RW and PG_M are among the least
5379 * significant 32 bits.
5381 while (!atomic_cmpset_int((u_int *)pte,
5383 oldpte & ~(PG_M | PG_RW)))
5386 pmap_invalidate_page(pmap, va);
5394 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5397 pde = pmap_pde(pmap, pv->pv_va);
5398 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5399 " a 4mpage in page %p's pv list", m));
5400 pte = pmap_pte_quick(pmap, pv->pv_va);
5401 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5403 * Regardless of whether a pte is 32 or 64 bits
5404 * in size, PG_M is among the least significant
5407 atomic_clear_int((u_int *)pte, PG_M);
5408 pmap_invalidate_page(pmap, pv->pv_va);
5413 rw_wunlock(&pvh_global_lock);
5417 * Miscellaneous support routines follow
5420 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5421 static __inline void
5422 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5427 * The cache mode bits are all in the low 32-bits of the
5428 * PTE, so we can just spin on updating the low 32-bits.
5431 opte = *(u_int *)pte;
5432 npte = opte & ~PG_PTE_CACHE;
5434 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5437 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5438 static __inline void
5439 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5444 * The cache mode bits are all in the low 32-bits of the
5445 * PDE, so we can just spin on updating the low 32-bits.
5448 opde = *(u_int *)pde;
5449 npde = opde & ~PG_PDE_CACHE;
5451 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5455 * Map a set of physical memory pages into the kernel virtual
5456 * address space. Return a pointer to where it is mapped. This
5457 * routine is intended to be used for mapping device memory,
5461 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5463 struct pmap_preinit_mapping *ppim;
5464 vm_offset_t va, offset;
5468 offset = pa & PAGE_MASK;
5469 size = round_page(offset + size);
5472 if (pa < PMAP_MAP_LOW && pa + size <= PMAP_MAP_LOW)
5473 va = pa + PMAP_MAP_LOW;
5474 else if (!pmap_initialized) {
5476 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5477 ppim = pmap_preinit_mapping + i;
5478 if (ppim->va == 0) {
5482 ppim->va = virtual_avail;
5483 virtual_avail += size;
5489 panic("%s: too many preinit mappings", __func__);
5492 * If we have a preinit mapping, re-use it.
5494 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5495 ppim = pmap_preinit_mapping + i;
5496 if (ppim->pa == pa && ppim->sz == size &&
5498 return ((void *)(ppim->va + offset));
5500 va = kva_alloc(size);
5502 panic("%s: Couldn't allocate KVA", __func__);
5504 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5505 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5506 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5507 pmap_invalidate_cache_range(va, va + size);
5508 return ((void *)(va + offset));
5512 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5515 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5519 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5522 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5526 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5528 struct pmap_preinit_mapping *ppim;
5532 if (va >= PMAP_MAP_LOW && va <= KERNBASE && va + size <= KERNBASE)
5534 offset = va & PAGE_MASK;
5535 size = round_page(offset + size);
5536 va = trunc_page(va);
5537 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5538 ppim = pmap_preinit_mapping + i;
5539 if (ppim->va == va && ppim->sz == size) {
5540 if (pmap_initialized)
5546 if (va + size == virtual_avail)
5551 if (pmap_initialized)
5556 * Sets the memory attribute for the specified page.
5559 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5562 m->md.pat_mode = ma;
5563 if ((m->flags & PG_FICTITIOUS) != 0)
5567 * If "m" is a normal page, flush it from the cache.
5568 * See pmap_invalidate_cache_range().
5570 * First, try to find an existing mapping of the page by sf
5571 * buffer. sf_buf_invalidate_cache() modifies mapping and
5572 * flushes the cache.
5574 if (sf_buf_invalidate_cache(m))
5578 * If page is not mapped by sf buffer, but CPU does not
5579 * support self snoop, map the page transient and do
5580 * invalidation. In the worst case, whole cache is flushed by
5581 * pmap_invalidate_cache_range().
5583 if ((cpu_feature & CPUID_SS) == 0)
5588 pmap_flush_page(vm_page_t m)
5590 pt_entry_t *cmap_pte2;
5592 vm_offset_t sva, eva;
5595 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5596 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5599 cmap_pte2 = pc->pc_cmap_pte2;
5600 mtx_lock(&pc->pc_cmap_lock);
5602 panic("pmap_flush_page: CMAP2 busy");
5603 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5604 PG_A | PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode,
5606 invlcaddr(pc->pc_cmap_addr2);
5607 sva = (vm_offset_t)pc->pc_cmap_addr2;
5608 eva = sva + PAGE_SIZE;
5611 * Use mfence or sfence despite the ordering implied by
5612 * mtx_{un,}lock() because clflush on non-Intel CPUs
5613 * and clflushopt are not guaranteed to be ordered by
5614 * any other instruction.
5618 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5620 for (; sva < eva; sva += cpu_clflush_line_size) {
5628 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5632 mtx_unlock(&pc->pc_cmap_lock);
5634 pmap_invalidate_cache();
5638 * Changes the specified virtual address range's memory type to that given by
5639 * the parameter "mode". The specified virtual address range must be
5640 * completely contained within either the kernel map.
5642 * Returns zero if the change completed successfully, and either EINVAL or
5643 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5644 * of the virtual address range was not mapped, and ENOMEM is returned if
5645 * there was insufficient memory available to complete the change.
5648 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5650 vm_offset_t base, offset, tmpva;
5653 int cache_bits_pte, cache_bits_pde;
5656 base = trunc_page(va);
5657 offset = va & PAGE_MASK;
5658 size = round_page(offset + size);
5661 * Only supported on kernel virtual addresses above the recursive map.
5663 if (base < VM_MIN_KERNEL_ADDRESS)
5666 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
5667 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
5671 * Pages that aren't mapped aren't supported. Also break down
5672 * 2/4MB pages into 4KB pages if required.
5674 PMAP_LOCK(kernel_pmap);
5675 for (tmpva = base; tmpva < base + size; ) {
5676 pde = pmap_pde(kernel_pmap, tmpva);
5678 PMAP_UNLOCK(kernel_pmap);
5683 * If the current 2/4MB page already has
5684 * the required memory type, then we need not
5685 * demote this page. Just increment tmpva to
5686 * the next 2/4MB page frame.
5688 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5689 tmpva = trunc_4mpage(tmpva) + NBPDR;
5694 * If the current offset aligns with a 2/4MB
5695 * page frame and there is at least 2/4MB left
5696 * within the range, then we need not break
5697 * down this page into 4KB pages.
5699 if ((tmpva & PDRMASK) == 0 &&
5700 tmpva + PDRMASK < base + size) {
5704 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5705 PMAP_UNLOCK(kernel_pmap);
5709 pte = vtopte(tmpva);
5711 PMAP_UNLOCK(kernel_pmap);
5716 PMAP_UNLOCK(kernel_pmap);
5719 * Ok, all the pages exist, so run through them updating their
5720 * cache mode if required.
5722 for (tmpva = base; tmpva < base + size; ) {
5723 pde = pmap_pde(kernel_pmap, tmpva);
5725 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5726 pmap_pde_attr(pde, cache_bits_pde);
5729 tmpva = trunc_4mpage(tmpva) + NBPDR;
5731 pte = vtopte(tmpva);
5732 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5733 pmap_pte_attr(pte, cache_bits_pte);
5741 * Flush CPU caches to make sure any data isn't cached that
5742 * shouldn't be, etc.
5745 pmap_invalidate_range(kernel_pmap, base, tmpva);
5746 pmap_invalidate_cache_range(base, tmpva);
5752 * perform the pmap work for mincore
5755 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5764 pde = *pmap_pde(pmap, addr);
5766 if ((pde & PG_PS) != 0) {
5768 /* Compute the physical address of the 4KB page. */
5769 pa = ((pde & PG_PS_FRAME) | (addr & PDRMASK)) &
5771 val = MINCORE_SUPER;
5773 pte = pmap_pte_ufast(pmap, addr, pde);
5774 pa = pte & PG_FRAME;
5782 if ((pte & PG_V) != 0) {
5783 val |= MINCORE_INCORE;
5784 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5785 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5786 if ((pte & PG_A) != 0)
5787 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5789 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5790 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5791 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5792 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5793 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5796 PA_UNLOCK_COND(*locked_pa);
5802 pmap_activate(struct thread *td)
5804 pmap_t pmap, oldpmap;
5809 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5810 oldpmap = PCPU_GET(curpmap);
5811 cpuid = PCPU_GET(cpuid);
5813 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5814 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5816 CPU_CLR(cpuid, &oldpmap->pm_active);
5817 CPU_SET(cpuid, &pmap->pm_active);
5819 #if defined(PAE) || defined(PAE_TABLES)
5820 cr3 = vtophys(pmap->pm_pdpt);
5822 cr3 = vtophys(pmap->pm_pdir);
5825 * pmap_activate is for the current thread on the current cpu
5827 td->td_pcb->pcb_cr3 = cr3;
5828 PCPU_SET(curpmap, pmap);
5833 pmap_activate_boot(pmap_t pmap)
5837 cpuid = PCPU_GET(cpuid);
5839 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5841 CPU_SET(cpuid, &pmap->pm_active);
5843 PCPU_SET(curpmap, pmap);
5847 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5852 * Increase the starting virtual address of the given mapping if a
5853 * different alignment might result in more superpage mappings.
5856 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5857 vm_offset_t *addr, vm_size_t size)
5859 vm_offset_t superpage_offset;
5863 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5864 offset += ptoa(object->pg_color);
5865 superpage_offset = offset & PDRMASK;
5866 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5867 (*addr & PDRMASK) == superpage_offset)
5869 if ((*addr & PDRMASK) < superpage_offset)
5870 *addr = (*addr & ~PDRMASK) + superpage_offset;
5872 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5876 pmap_quick_enter_page(vm_page_t m)
5882 qaddr = PCPU_GET(qmap_addr);
5883 pte = vtopte(qaddr);
5885 KASSERT(*pte == 0, ("pmap_quick_enter_page: PTE busy"));
5886 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5887 pmap_cache_bits(kernel_pmap, pmap_page_get_memattr(m), 0);
5894 pmap_quick_remove_page(vm_offset_t addr)
5899 qaddr = PCPU_GET(qmap_addr);
5900 pte = vtopte(qaddr);
5902 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5903 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5909 static vmem_t *pmap_trm_arena;
5910 static vmem_addr_t pmap_trm_arena_last = PMAP_TRM_MIN_ADDRESS;
5911 static int trm_guard = PAGE_SIZE;
5914 pmap_trm_import(void *unused __unused, vmem_size_t size, int flags,
5918 vmem_addr_t af, addr, prev_addr;
5919 pt_entry_t *trm_pte;
5921 prev_addr = atomic_load_long(&pmap_trm_arena_last);
5922 size = round_page(size) + trm_guard;
5924 if (prev_addr + size < prev_addr || prev_addr + size < size ||
5925 prev_addr + size > PMAP_TRM_MAX_ADDRESS)
5927 addr = prev_addr + size;
5928 if (atomic_fcmpset_int(&pmap_trm_arena_last, &prev_addr, addr))
5931 prev_addr += trm_guard;
5932 trm_pte = PTmap + atop(prev_addr);
5933 for (af = prev_addr; af < addr; af += PAGE_SIZE) {
5934 m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5935 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
5936 pte_store(&trm_pte[atop(af - prev_addr)], VM_PAGE_TO_PHYS(m) |
5937 PG_M | PG_A | PG_RW | PG_V | pgeflag |
5938 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE));
5945 void pmap_init_trm(void)
5949 TUNABLE_INT_FETCH("machdep.trm_guard", &trm_guard);
5950 if ((trm_guard & PAGE_MASK) != 0)
5952 pmap_trm_arena = vmem_create("i386trampoline", 0, 0, 1, 0, M_WAITOK);
5953 vmem_set_import(pmap_trm_arena, pmap_trm_import, NULL, NULL, PAGE_SIZE);
5954 pd_m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5955 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK | VM_ALLOC_ZERO);
5956 if ((pd_m->flags & PG_ZERO) == 0)
5957 pmap_zero_page(pd_m);
5958 PTD[TRPTDI] = VM_PAGE_TO_PHYS(pd_m) | PG_M | PG_A | PG_RW | PG_V |
5959 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, TRUE);
5963 pmap_trm_alloc(size_t size, int flags)
5968 MPASS((flags & ~(M_WAITOK | M_NOWAIT | M_ZERO)) == 0);
5969 error = vmem_xalloc(pmap_trm_arena, roundup2(size, 4), sizeof(int),
5970 0, 0, VMEM_ADDR_MIN, VMEM_ADDR_MAX, flags | M_FIRSTFIT, &res);
5973 if ((flags & M_ZERO) != 0)
5974 bzero((void *)res, size);
5975 return ((void *)res);
5979 pmap_trm_free(void *addr, size_t size)
5982 vmem_free(pmap_trm_arena, (uintptr_t)addr, roundup2(size, 4));
5985 #if defined(PMAP_DEBUG)
5986 pmap_pid_dump(int pid)
5993 sx_slock(&allproc_lock);
5994 FOREACH_PROC_IN_SYSTEM(p) {
5995 if (p->p_pid != pid)
6001 pmap = vmspace_pmap(p->p_vmspace);
6002 for (i = 0; i < NPDEPTD; i++) {
6005 vm_offset_t base = i << PDRSHIFT;
6007 pde = &pmap->pm_pdir[i];
6008 if (pde && pmap_pde_v(pde)) {
6009 for (j = 0; j < NPTEPG; j++) {
6010 vm_offset_t va = base + (j << PAGE_SHIFT);
6011 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
6016 sx_sunlock(&allproc_lock);
6019 pte = pmap_pte(pmap, va);
6020 if (pte && pmap_pte_v(pte)) {
6024 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
6025 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
6026 va, pa, m->hold_count, m->wire_count, m->flags);
6041 sx_sunlock(&allproc_lock);