2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
50 * Copyright (c) 2018 The FreeBSD Foundation
51 * All rights reserved.
53 * This software was developed for the FreeBSD Project by Jake Burkholder,
54 * Safeport Network Services, and Network Associates Laboratories, the
55 * Security Research Division of Network Associates, Inc. under
56 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
57 * CHATS research program.
59 * Portions of this software were developed by
60 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
61 * the FreeBSD Foundation.
63 * Redistribution and use in source and binary forms, with or without
64 * modification, are permitted provided that the following conditions
66 * 1. Redistributions of source code must retain the above copyright
67 * notice, this list of conditions and the following disclaimer.
68 * 2. Redistributions in binary form must reproduce the above copyright
69 * notice, this list of conditions and the following disclaimer in the
70 * documentation and/or other materials provided with the distribution.
72 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
73 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
75 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
78 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
79 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
80 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
81 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
85 #include <sys/cdefs.h>
86 __FBSDID("$FreeBSD$");
89 * Manages physical address maps.
91 * Since the information managed by this module is
92 * also stored by the logical address mapping module,
93 * this module may throw away valid virtual-to-physical
94 * mappings at almost any time. However, invalidations
95 * of virtual-to-physical mappings must be done as
98 * In order to cope with hardware architectures which
99 * make virtual-to-physical map invalidates expensive,
100 * this module may delay invalidate or reduced protection
101 * operations until such time as they are actually
102 * necessary. This module is given full information as
103 * to which processors are currently using which maps,
104 * and to when physical maps must be made correct.
107 #include "opt_apic.h"
109 #include "opt_pmap.h"
113 #include <sys/param.h>
114 #include <sys/systm.h>
115 #include <sys/kernel.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/proc.h>
123 #include <sys/rwlock.h>
124 #include <sys/sf_buf.h>
126 #include <sys/vmmeter.h>
127 #include <sys/sched.h>
128 #include <sys/sysctl.h>
130 #include <sys/vmem.h>
133 #include <vm/vm_param.h>
134 #include <vm/vm_kern.h>
135 #include <vm/vm_page.h>
136 #include <vm/vm_map.h>
137 #include <vm/vm_object.h>
138 #include <vm/vm_extern.h>
139 #include <vm/vm_pageout.h>
140 #include <vm/vm_pager.h>
141 #include <vm/vm_phys.h>
142 #include <vm/vm_radix.h>
143 #include <vm/vm_reserv.h>
148 #include <machine/intr_machdep.h>
149 #include <x86/apicvar.h>
151 #include <x86/ifunc.h>
152 #include <machine/bootinfo.h>
153 #include <machine/cpu.h>
154 #include <machine/cputypes.h>
155 #include <machine/md_var.h>
156 #include <machine/pcb.h>
157 #include <machine/specialreg.h>
159 #include <machine/smp.h>
161 #include <machine/pmap_base.h>
163 #if !defined(DIAGNOSTIC)
164 #ifdef __GNUC_GNU_INLINE__
165 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
167 #define PMAP_INLINE extern inline
174 #define PV_STAT(x) do { x ; } while (0)
176 #define PV_STAT(x) do { } while (0)
179 #define pa_index(pa) ((pa) >> PDRSHIFT)
180 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
183 * PTmap is recursive pagemap at top of virtual address space.
184 * Within PTmap, the page directory can be found (third indirection).
186 #define PTmap ((pt_entry_t *)(PTDPTDI << PDRSHIFT))
187 #define PTD ((pd_entry_t *)((PTDPTDI << PDRSHIFT) + (PTDPTDI * PAGE_SIZE)))
188 #define PTDpde ((pd_entry_t *)((PTDPTDI << PDRSHIFT) + (PTDPTDI * PAGE_SIZE) + \
189 (PTDPTDI * PDESIZE)))
192 * Translate a virtual address to the kernel virtual address of its page table
193 * entry (PTE). This can be used recursively. If the address of a PTE as
194 * previously returned by this macro is itself given as the argument, then the
195 * address of the page directory entry (PDE) that maps the PTE will be
198 * This macro may be used before pmap_bootstrap() is called.
200 #define vtopte(va) (PTmap + i386_btop(va))
203 * Get PDEs and PTEs for user/kernel address space
205 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
206 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
208 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
209 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
210 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
211 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
212 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
214 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
215 atomic_clear_int((u_int *)(pte), PG_W))
216 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
218 _Static_assert(sizeof(struct pmap) <= sizeof(struct pmap_KBI),
221 static int pgeflag = 0; /* PG_G or-in */
222 static int pseflag = 0; /* PG_PS or-in */
224 static int nkpt = NKPT;
228 static uma_zone_t pdptzone;
231 _Static_assert(VM_MAXUSER_ADDRESS == VADDR(TRPTDI, 0), "VM_MAXUSER_ADDRESS");
232 _Static_assert(VM_MAX_KERNEL_ADDRESS <= VADDR(PTDPTDI, 0),
233 "VM_MAX_KERNEL_ADDRESS");
234 _Static_assert(PMAP_MAP_LOW == VADDR(LOWPTDI, 0), "PMAP_MAP_LOW");
235 _Static_assert(KERNLOAD == (KERNPTDI << PDRSHIFT), "KERNLOAD");
237 extern int pat_works;
238 extern int pg_ps_enabled;
240 extern int elf32_nxstack;
242 #define PAT_INDEX_SIZE 8
243 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
246 * pmap_mapdev support pre initialization (i.e. console)
248 #define PMAP_PREINIT_MAPPING_COUNT 8
249 static struct pmap_preinit_mapping {
254 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
255 static int pmap_initialized;
257 static struct rwlock_padalign pvh_global_lock;
260 * Data for the pv entry allocation mechanism
262 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
263 extern int pv_entry_max, pv_entry_count;
264 static int pv_entry_high_water = 0;
265 static struct md_page *pv_table;
266 extern int shpgperproc;
268 static struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
269 static int pv_maxchunks; /* How many chunks we have KVA for */
270 static vm_offset_t pv_vafree; /* freelist stored in the PTE */
273 * All those kernel PT submaps that BSD is so fond of
275 static pt_entry_t *CMAP3;
276 static pd_entry_t *KPTD;
277 static caddr_t CADDR3;
282 static caddr_t crashdumpmap;
284 static pt_entry_t *PMAP1 = NULL, *PMAP2, *PMAP3;
285 static pt_entry_t *PADDR1 = NULL, *PADDR2, *PADDR3;
287 static int PMAP1cpu, PMAP3cpu;
288 extern int PMAP1changedcpu;
290 extern int PMAP1changed;
291 extern int PMAP1unchanged;
292 static struct mtx PMAP2mutex;
295 * Internal flags for pmap_enter()'s helper functions.
297 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
298 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
300 static void free_pv_chunk(struct pv_chunk *pc);
301 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
302 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
303 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
304 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
306 #if VM_NRESERVLEVEL > 0
307 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
309 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
310 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
312 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
314 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
315 static bool pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
317 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
318 u_int flags, vm_page_t m);
319 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
320 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
321 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
322 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
324 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
325 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
326 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
327 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
328 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
329 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
330 #if VM_NRESERVLEVEL > 0
331 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
333 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
335 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
336 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
337 struct spglist *free);
338 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
339 struct spglist *free);
340 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
341 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
342 struct spglist *free);
343 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
344 struct spglist *free);
345 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
347 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
348 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
350 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
352 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
354 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
356 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
357 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
358 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
359 static void pmap_pte_release(pt_entry_t *pte);
360 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
362 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain,
363 uint8_t *flags, int wait);
365 static void pmap_init_trm(void);
366 static void pmap_invalidate_all_int(pmap_t pmap);
368 static __inline void pagezero(void *page);
370 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
371 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
374 extern u_long physfree; /* phys addr of next free page */
375 extern u_long vm86phystk;/* PA of vm86/bios stack */
376 extern u_long vm86paddr;/* address of vm86 region */
377 extern int vm86pa; /* phys addr of vm86 region */
378 extern u_long KERNend; /* phys addr end of kernel (just after bss) */
380 pd_entry_t *IdlePTD_pae; /* phys addr of kernel PTD */
381 pdpt_entry_t *IdlePDPT; /* phys addr of kernel PDPT */
382 pt_entry_t *KPTmap_pae; /* address of kernel page tables */
383 #define IdlePTD IdlePTD_pae
384 #define KPTmap KPTmap_pae
386 pd_entry_t *IdlePTD_nopae;
387 pt_entry_t *KPTmap_nopae;
388 #define IdlePTD IdlePTD_nopae
389 #define KPTmap KPTmap_nopae
391 extern u_long KPTphys; /* phys addr of kernel page tables */
392 extern u_long tramp_idleptd;
395 allocpages(u_int cnt, u_long *physfree)
400 *physfree += PAGE_SIZE * cnt;
401 bzero((void *)res, PAGE_SIZE * cnt);
406 pmap_cold_map(u_long pa, u_long va, u_long cnt)
410 for (pt = (pt_entry_t *)KPTphys + atop(va); cnt > 0;
411 cnt--, pt++, va += PAGE_SIZE, pa += PAGE_SIZE)
412 *pt = pa | PG_V | PG_RW | PG_A | PG_M;
416 pmap_cold_mapident(u_long pa, u_long cnt)
419 pmap_cold_map(pa, pa, cnt);
422 _Static_assert(LOWPTDI * 2 * NBPDR == KERNBASE,
423 "Broken double-map of zero PTD");
426 __CONCAT(PMTYPE, remap_lower)(bool enable)
430 for (i = 0; i < LOWPTDI; i++)
431 IdlePTD[i] = enable ? IdlePTD[LOWPTDI + i] : 0;
432 load_cr3(rcr3()); /* invalidate TLB */
436 * Called from locore.s before paging is enabled. Sets up the first
437 * kernel page table. Since kernel is mapped with PA == VA, this code
438 * does not require relocations.
441 __CONCAT(PMTYPE, cold)(void)
447 physfree = (u_long)&_end;
448 if (bootinfo.bi_esymtab != 0)
449 physfree = bootinfo.bi_esymtab;
450 if (bootinfo.bi_kernend != 0)
451 physfree = bootinfo.bi_kernend;
452 physfree = roundup2(physfree, NBPDR);
455 /* Allocate Kernel Page Tables */
456 KPTphys = allocpages(NKPT, &physfree);
457 KPTmap = (pt_entry_t *)KPTphys;
459 /* Allocate Page Table Directory */
461 /* XXX only need 32 bytes (easier for now) */
462 IdlePDPT = (pdpt_entry_t *)allocpages(1, &physfree);
464 IdlePTD = (pd_entry_t *)allocpages(NPGPTD, &physfree);
467 * Allocate KSTACK. Leave a guard page between IdlePTD and
468 * proc0kstack, to control stack overflow for thread0 and
469 * prevent corruption of the page table. We leak the guard
470 * physical memory due to 1:1 mappings.
472 allocpages(1, &physfree);
473 proc0kstack = allocpages(TD0_KSTACK_PAGES, &physfree);
475 /* vm86/bios stack */
476 vm86phystk = allocpages(1, &physfree);
478 /* pgtable + ext + IOPAGES */
479 vm86paddr = vm86pa = allocpages(3, &physfree);
481 /* Install page tables into PTD. Page table page 1 is wasted. */
482 for (a = 0; a < NKPT; a++)
483 IdlePTD[a] = (KPTphys + ptoa(a)) | PG_V | PG_RW | PG_A | PG_M;
486 /* PAE install PTD pointers into PDPT */
487 for (a = 0; a < NPGPTD; a++)
488 IdlePDPT[a] = ((u_int)IdlePTD + ptoa(a)) | PG_V;
492 * Install recursive mapping for kernel page tables into
495 for (a = 0; a < NPGPTD; a++)
496 IdlePTD[PTDPTDI + a] = ((u_int)IdlePTD + ptoa(a)) | PG_V |
500 * Initialize page table pages mapping physical address zero
501 * through the (physical) end of the kernel. Many of these
502 * pages must be reserved, and we reserve them all and map
503 * them linearly for convenience. We do this even if we've
504 * enabled PSE above; we'll just switch the corresponding
505 * kernel PDEs before we turn on paging.
507 * This and all other page table entries allow read and write
508 * access for various reasons. Kernel mappings never have any
509 * access restrictions.
511 pmap_cold_mapident(0, atop(NBPDR) * LOWPTDI);
512 pmap_cold_map(0, NBPDR * LOWPTDI, atop(NBPDR) * LOWPTDI);
513 pmap_cold_mapident(KERNBASE, atop(KERNend - KERNBASE));
515 /* Map page table directory */
517 pmap_cold_mapident((u_long)IdlePDPT, 1);
519 pmap_cold_mapident((u_long)IdlePTD, NPGPTD);
521 /* Map early KPTmap. It is really pmap_cold_mapident. */
522 pmap_cold_map(KPTphys, (u_long)KPTmap, NKPT);
524 /* Map proc0kstack */
525 pmap_cold_mapident(proc0kstack, TD0_KSTACK_PAGES);
526 /* ISA hole already mapped */
528 pmap_cold_mapident(vm86phystk, 1);
529 pmap_cold_mapident(vm86pa, 3);
531 /* Map page 0 into the vm86 page table */
532 *(pt_entry_t *)vm86pa = 0 | PG_RW | PG_U | PG_A | PG_M | PG_V;
534 /* ...likewise for the ISA hole for vm86 */
535 for (pt = (pt_entry_t *)vm86pa + atop(ISA_HOLE_START), a = 0;
536 a < atop(ISA_HOLE_LENGTH); a++, pt++)
537 *pt = (ISA_HOLE_START + ptoa(a)) | PG_RW | PG_U | PG_A |
540 /* Enable PSE, PGE, VME, and PAE if configured. */
542 if ((cpu_feature & CPUID_PSE) != 0) {
546 * Superpage mapping of the kernel text. Existing 4k
547 * page table pages are wasted.
549 for (a = KERNBASE; a < KERNend; a += NBPDR)
550 IdlePTD[a >> PDRSHIFT] = a | PG_PS | PG_A | PG_M |
553 if ((cpu_feature & CPUID_PGE) != 0) {
557 ncr4 |= (cpu_feature & CPUID_VME) != 0 ? CR4_VME : 0;
562 load_cr4(rcr4() | ncr4);
564 /* Now enable paging */
566 cr3 = (u_int)IdlePDPT;
568 cr3 = (u_int)IdlePTD;
572 load_cr0(rcr0() | CR0_PG);
575 * Now running relocated at KERNBASE where the system is
580 * Remove the lowest part of the double mapping of low memory
581 * to get some null pointer checks.
583 __CONCAT(PMTYPE, remap_lower)(false);
585 kernel_vm_end = /* 0 + */ NKPT * NBPDR;
587 i386_pmap_VM_NFREEORDER = VM_NFREEORDER_PAE;
588 i386_pmap_VM_LEVEL_0_ORDER = VM_LEVEL_0_ORDER_PAE;
589 i386_pmap_PDRSHIFT = PDRSHIFT_PAE;
591 i386_pmap_VM_NFREEORDER = VM_NFREEORDER_NOPAE;
592 i386_pmap_VM_LEVEL_0_ORDER = VM_LEVEL_0_ORDER_NOPAE;
593 i386_pmap_PDRSHIFT = PDRSHIFT_NOPAE;
598 __CONCAT(PMTYPE, set_nx)(void)
602 if ((amd_feature & AMDID_NX) == 0)
606 /* EFER.EFER_NXE is set in initializecpu(). */
611 * Bootstrap the system enough to run with virtual memory.
613 * On the i386 this is called after pmap_cold() created initial
614 * kernel page table and enabled paging, and just syncs the pmap
615 * module with what has already been done.
618 __CONCAT(PMTYPE, bootstrap)(vm_paddr_t firstaddr)
621 pt_entry_t *pte, *unused;
626 res = atop(firstaddr - (vm_paddr_t)KERNLOAD);
629 * Add a physical memory segment (vm_phys_seg) corresponding to the
630 * preallocated kernel page table pages so that vm_page structures
631 * representing these pages will be created. The vm_page structures
632 * are required for promotion of the corresponding kernel virtual
633 * addresses to superpage mappings.
635 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
638 * Initialize the first available kernel virtual address.
639 * However, using "firstaddr" may waste a few pages of the
640 * kernel virtual address space, because pmap_cold() may not
641 * have mapped every physical page that it allocated.
642 * Preferably, pmap_cold() would provide a first unused
643 * virtual address in addition to "firstaddr".
645 virtual_avail = (vm_offset_t)firstaddr;
646 virtual_end = VM_MAX_KERNEL_ADDRESS;
649 * Initialize the kernel pmap (which is statically allocated).
650 * Count bootstrap data as being resident in case any of this data is
651 * later unmapped (using pmap_remove()) and freed.
653 PMAP_LOCK_INIT(kernel_pmap);
654 kernel_pmap->pm_pdir = IdlePTD;
656 kernel_pmap->pm_pdpt = IdlePDPT;
658 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
659 kernel_pmap->pm_stats.resident_count = res;
660 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
663 * Initialize the global pv list lock.
665 rw_init(&pvh_global_lock, "pmap pv global");
668 * Reserve some special page table entries/VA space for temporary
671 #define SYSMAP(c, p, v, n) \
672 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
679 * Initialize temporary map objects on the current CPU for use
681 * CMAP1/CMAP2 are used for zeroing and copying pages.
682 * CMAP3 is used for the boot-time memory test.
685 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
686 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1)
687 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1)
688 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1)
690 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
695 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
698 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
700 SYSMAP(caddr_t, unused, ptvmmap, 1)
703 * msgbufp is used to map the system message buffer.
705 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
708 * KPTmap is used by pmap_kextract().
710 * KPTmap is first initialized by pmap_cold(). However, that initial
711 * KPTmap can only support NKPT page table pages. Here, a larger
712 * KPTmap is created that can support KVA_PAGES page table pages.
714 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
716 for (i = 0; i < NKPT; i++)
717 KPTD[i] = (KPTphys + ptoa(i)) | PG_RW | PG_V;
720 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
723 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
724 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
725 SYSMAP(pt_entry_t *, PMAP3, PADDR3, 1)
727 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
732 * Initialize the PAT MSR if present.
733 * pmap_init_pat() clears and sets CR4_PGE, which, as a
734 * side-effect, invalidates stale PG_G TLB entries that might
735 * have been created in our pre-boot environment. We assume
736 * that PAT support implies PGE and in reverse, PGE presence
737 * comes with PAT. Both features were added for Pentium Pro.
743 pmap_init_reserved_pages(void)
758 mtx_init(&pc->pc_copyout_mlock, "cpmlk", NULL, MTX_DEF |
760 pc->pc_copyout_maddr = kva_alloc(ptoa(2));
761 if (pc->pc_copyout_maddr == 0)
762 panic("unable to allocate non-sleepable copyout KVA");
763 sx_init(&pc->pc_copyout_slock, "cpslk");
764 pc->pc_copyout_saddr = kva_alloc(ptoa(2));
765 if (pc->pc_copyout_saddr == 0)
766 panic("unable to allocate sleepable copyout KVA");
767 pc->pc_pmap_eh_va = kva_alloc(ptoa(1));
768 if (pc->pc_pmap_eh_va == 0)
769 panic("unable to allocate pmap_extract_and_hold KVA");
770 pc->pc_pmap_eh_ptep = (char *)vtopte(pc->pc_pmap_eh_va);
773 * Skip if the mappings have already been initialized,
774 * i.e. this is the BSP.
776 if (pc->pc_cmap_addr1 != 0)
779 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
780 pages = kva_alloc(PAGE_SIZE * 3);
782 panic("unable to allocate CMAP KVA");
783 pc->pc_cmap_pte1 = vtopte(pages);
784 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE);
785 pc->pc_cmap_addr1 = (caddr_t)pages;
786 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE);
787 pc->pc_qmap_addr = pages + ptoa(2);
791 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
797 __CONCAT(PMTYPE, init_pat)(void)
799 int pat_table[PAT_INDEX_SIZE];
804 /* Set default PAT index table. */
805 for (i = 0; i < PAT_INDEX_SIZE; i++)
807 pat_table[PAT_WRITE_BACK] = 0;
808 pat_table[PAT_WRITE_THROUGH] = 1;
809 pat_table[PAT_UNCACHEABLE] = 3;
810 pat_table[PAT_WRITE_COMBINING] = 3;
811 pat_table[PAT_WRITE_PROTECTED] = 3;
812 pat_table[PAT_UNCACHED] = 3;
815 * Bail if this CPU doesn't implement PAT.
816 * We assume that PAT support implies PGE.
818 if ((cpu_feature & CPUID_PAT) == 0) {
819 for (i = 0; i < PAT_INDEX_SIZE; i++)
820 pat_index[i] = pat_table[i];
826 * Due to some Intel errata, we can only safely use the lower 4
829 * Intel Pentium III Processor Specification Update
830 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
833 * Intel Pentium IV Processor Specification Update
834 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
836 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
837 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
840 /* Initialize default PAT entries. */
841 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
842 PAT_VALUE(1, PAT_WRITE_THROUGH) |
843 PAT_VALUE(2, PAT_UNCACHED) |
844 PAT_VALUE(3, PAT_UNCACHEABLE) |
845 PAT_VALUE(4, PAT_WRITE_BACK) |
846 PAT_VALUE(5, PAT_WRITE_THROUGH) |
847 PAT_VALUE(6, PAT_UNCACHED) |
848 PAT_VALUE(7, PAT_UNCACHEABLE);
852 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
853 * Program 5 and 6 as WP and WC.
854 * Leave 4 and 7 as WB and UC.
856 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
857 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
858 PAT_VALUE(6, PAT_WRITE_COMBINING);
859 pat_table[PAT_UNCACHED] = 2;
860 pat_table[PAT_WRITE_PROTECTED] = 5;
861 pat_table[PAT_WRITE_COMBINING] = 6;
864 * Just replace PAT Index 2 with WC instead of UC-.
866 pat_msr &= ~PAT_MASK(2);
867 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
868 pat_table[PAT_WRITE_COMBINING] = 2;
873 load_cr4(cr4 & ~CR4_PGE);
875 /* Disable caches (CD = 1, NW = 0). */
877 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
879 /* Flushes caches and TLBs. */
883 /* Update PAT and index table. */
884 wrmsr(MSR_PAT, pat_msr);
885 for (i = 0; i < PAT_INDEX_SIZE; i++)
886 pat_index[i] = pat_table[i];
888 /* Flush caches and TLBs again. */
892 /* Restore caches and PGE. */
899 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain, uint8_t *flags,
903 /* Inform UMA that this allocator uses kernel_map/object. */
904 *flags = UMA_SLAB_KERNEL;
905 return ((void *)kmem_alloc_contig_domainset(DOMAINSET_FIXED(domain),
906 bytes, wait, 0x0ULL, 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
911 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
913 * - Must deal with pages in order to ensure that none of the PG_* bits
914 * are ever set, PG_V in particular.
915 * - Assumes we can write to ptes without pte_store() atomic ops, even
916 * on PAE systems. This should be ok.
917 * - Assumes nothing will ever test these addresses for 0 to indicate
918 * no mapping instead of correctly checking PG_V.
919 * - Assumes a vm_offset_t will fit in a pte (true for i386).
920 * Because PG_V is never set, there can be no mappings to invalidate.
923 pmap_ptelist_alloc(vm_offset_t *head)
930 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
934 panic("pmap_ptelist_alloc: va with PG_V set!");
940 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
945 panic("pmap_ptelist_free: freeing va with PG_V set!");
947 *pte = *head; /* virtual! PG_V is 0 though */
952 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
958 for (i = npages - 1; i >= 0; i--) {
959 va = (vm_offset_t)base + i * PAGE_SIZE;
960 pmap_ptelist_free(head, va);
966 * Initialize the pmap module.
967 * Called by vm_init, to initialize any structures that the pmap
968 * system needs to map virtual memory.
971 __CONCAT(PMTYPE, init)(void)
973 struct pmap_preinit_mapping *ppim;
979 * Initialize the vm page array entries for the kernel pmap's
982 PMAP_LOCK(kernel_pmap);
983 for (i = 0; i < NKPT; i++) {
984 mpte = PHYS_TO_VM_PAGE(KPTphys + ptoa(i));
985 KASSERT(mpte >= vm_page_array &&
986 mpte < &vm_page_array[vm_page_array_size],
987 ("pmap_init: page table page is out of range"));
988 mpte->pindex = i + KPTDI;
989 mpte->phys_addr = KPTphys + ptoa(i);
990 mpte->wire_count = 1;
992 KERNBASE <= i << PDRSHIFT && i << PDRSHIFT < KERNend &&
993 pmap_insert_pt_page(kernel_pmap, mpte))
994 panic("pmap_init: pmap_insert_pt_page failed");
996 PMAP_UNLOCK(kernel_pmap);
1000 * Initialize the address space (zone) for the pv entries. Set a
1001 * high water mark so that the system can recover from excessive
1002 * numbers of pv entries.
1004 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1005 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1006 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1007 pv_entry_max = roundup(pv_entry_max, _NPCPV);
1008 pv_entry_high_water = 9 * (pv_entry_max / 10);
1011 * If the kernel is running on a virtual machine, then it must assume
1012 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1013 * be prepared for the hypervisor changing the vendor and family that
1014 * are reported by CPUID. Consequently, the workaround for AMD Family
1015 * 10h Erratum 383 is enabled if the processor's feature set does not
1016 * include at least one feature that is only supported by older Intel
1017 * or newer AMD processors.
1019 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
1020 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1021 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1023 workaround_erratum383 = 1;
1026 * Are large page mappings supported and enabled?
1028 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1031 else if (pg_ps_enabled) {
1032 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1033 ("pmap_init: can't assign to pagesizes[1]"));
1034 pagesizes[1] = NBPDR;
1038 * Calculate the size of the pv head table for superpages.
1039 * Handle the possibility that "vm_phys_segs[...].end" is zero.
1041 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
1042 PAGE_SIZE) / NBPDR + 1;
1045 * Allocate memory for the pv head table for superpages.
1047 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1049 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1050 for (i = 0; i < pv_npg; i++)
1051 TAILQ_INIT(&pv_table[i].pv_list);
1053 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
1054 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
1055 if (pv_chunkbase == NULL)
1056 panic("pmap_init: not enough kvm for pv chunks");
1057 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
1058 #ifdef PMAP_PAE_COMP
1059 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
1060 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
1061 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1062 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
1065 pmap_initialized = 1;
1070 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1071 ppim = pmap_preinit_mapping + i;
1074 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
1075 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
1080 extern u_long pmap_pde_demotions;
1081 extern u_long pmap_pde_mappings;
1082 extern u_long pmap_pde_p_failures;
1083 extern u_long pmap_pde_promotions;
1085 /***************************************************
1086 * Low level helper routines.....
1087 ***************************************************/
1090 __CONCAT(PMTYPE, is_valid_memattr)(pmap_t pmap __unused, vm_memattr_t mode)
1093 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
1094 pat_index[(int)mode] >= 0);
1098 * Determine the appropriate bits to set in a PTE or PDE for a specified
1102 __CONCAT(PMTYPE, cache_bits)(pmap_t pmap, int mode, boolean_t is_pde)
1104 int cache_bits, pat_flag, pat_idx;
1106 if (!pmap_is_valid_memattr(pmap, mode))
1107 panic("Unknown caching mode %d\n", mode);
1109 /* The PAT bit is different for PTE's and PDE's. */
1110 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
1112 /* Map the caching mode to a PAT index. */
1113 pat_idx = pat_index[mode];
1115 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1118 cache_bits |= pat_flag;
1120 cache_bits |= PG_NC_PCD;
1122 cache_bits |= PG_NC_PWT;
1123 return (cache_bits);
1127 __CONCAT(PMTYPE, ps_enabled)(pmap_t pmap __unused)
1130 return (pg_ps_enabled);
1134 * The caller is responsible for maintaining TLB consistency.
1137 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
1141 pde = pmap_pde(kernel_pmap, va);
1142 pde_store(pde, newpde);
1146 * After changing the page size for the specified virtual address in the page
1147 * table, flush the corresponding entries from the processor's TLB. Only the
1148 * calling processor's TLB is affected.
1150 * The calling thread must be pinned to a processor.
1153 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
1156 if ((newpde & PG_PS) == 0)
1157 /* Demotion: flush a specific 2MB page mapping. */
1159 else /* if ((newpde & PG_G) == 0) */
1161 * Promotion: flush every 4KB page mapping from the TLB
1162 * because there are too many to flush individually.
1169 * For SMP, these functions have to use the IPI mechanism for coherence.
1171 * N.B.: Before calling any of the following TLB invalidation functions,
1172 * the calling processor must ensure that all stores updating a non-
1173 * kernel page table are globally performed. Otherwise, another
1174 * processor could cache an old, pre-update entry without being
1175 * invalidated. This can happen one of two ways: (1) The pmap becomes
1176 * active on another processor after its pm_active field is checked by
1177 * one of the following functions but before a store updating the page
1178 * table is globally performed. (2) The pmap becomes active on another
1179 * processor before its pm_active field is checked but due to
1180 * speculative loads one of the following functions stills reads the
1181 * pmap as inactive on the other processor.
1183 * The kernel page table is exempt because its pm_active field is
1184 * immutable. The kernel page table is always active on every
1188 pmap_invalidate_page_int(pmap_t pmap, vm_offset_t va)
1190 cpuset_t *mask, other_cpus;
1194 if (pmap == kernel_pmap) {
1197 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1200 cpuid = PCPU_GET(cpuid);
1201 other_cpus = all_cpus;
1202 CPU_CLR(cpuid, &other_cpus);
1203 CPU_AND(&other_cpus, &pmap->pm_active);
1206 smp_masked_invlpg(*mask, va, pmap);
1210 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1211 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1214 pmap_invalidate_range_int(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1216 cpuset_t *mask, other_cpus;
1220 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1221 pmap_invalidate_all_int(pmap);
1226 if (pmap == kernel_pmap) {
1227 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1230 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1233 cpuid = PCPU_GET(cpuid);
1234 other_cpus = all_cpus;
1235 CPU_CLR(cpuid, &other_cpus);
1236 CPU_AND(&other_cpus, &pmap->pm_active);
1239 smp_masked_invlpg_range(*mask, sva, eva, pmap);
1244 pmap_invalidate_all_int(pmap_t pmap)
1246 cpuset_t *mask, other_cpus;
1250 if (pmap == kernel_pmap) {
1253 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1256 cpuid = PCPU_GET(cpuid);
1257 other_cpus = all_cpus;
1258 CPU_CLR(cpuid, &other_cpus);
1259 CPU_AND(&other_cpus, &pmap->pm_active);
1262 smp_masked_invltlb(*mask, pmap);
1267 __CONCAT(PMTYPE, invalidate_cache)(void)
1277 cpuset_t invalidate; /* processors that invalidate their TLB */
1281 u_int store; /* processor that updates the PDE */
1285 pmap_update_pde_kernel(void *arg)
1287 struct pde_action *act = arg;
1290 if (act->store == PCPU_GET(cpuid)) {
1291 pde = pmap_pde(kernel_pmap, act->va);
1292 pde_store(pde, act->newpde);
1297 pmap_update_pde_user(void *arg)
1299 struct pde_action *act = arg;
1301 if (act->store == PCPU_GET(cpuid))
1302 pde_store(act->pde, act->newpde);
1306 pmap_update_pde_teardown(void *arg)
1308 struct pde_action *act = arg;
1310 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1311 pmap_update_pde_invalidate(act->va, act->newpde);
1315 * Change the page size for the specified virtual address in a way that
1316 * prevents any possibility of the TLB ever having two entries that map the
1317 * same virtual address using different page sizes. This is the recommended
1318 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1319 * machine check exception for a TLB state that is improperly diagnosed as a
1323 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1325 struct pde_action act;
1326 cpuset_t active, other_cpus;
1330 cpuid = PCPU_GET(cpuid);
1331 other_cpus = all_cpus;
1332 CPU_CLR(cpuid, &other_cpus);
1333 if (pmap == kernel_pmap)
1336 active = pmap->pm_active;
1337 if (CPU_OVERLAP(&active, &other_cpus)) {
1339 act.invalidate = active;
1342 act.newpde = newpde;
1343 CPU_SET(cpuid, &active);
1344 smp_rendezvous_cpus(active,
1345 smp_no_rendezvous_barrier, pmap == kernel_pmap ?
1346 pmap_update_pde_kernel : pmap_update_pde_user,
1347 pmap_update_pde_teardown, &act);
1349 if (pmap == kernel_pmap)
1350 pmap_kenter_pde(va, newpde);
1352 pde_store(pde, newpde);
1353 if (CPU_ISSET(cpuid, &active))
1354 pmap_update_pde_invalidate(va, newpde);
1360 * Normal, non-SMP, 486+ invalidation functions.
1361 * We inline these within pmap.c for speed.
1364 pmap_invalidate_page_int(pmap_t pmap, vm_offset_t va)
1367 if (pmap == kernel_pmap)
1372 pmap_invalidate_range_int(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1376 if (pmap == kernel_pmap)
1377 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1382 pmap_invalidate_all_int(pmap_t pmap)
1385 if (pmap == kernel_pmap)
1390 __CONCAT(PMTYPE, invalidate_cache)(void)
1397 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1400 if (pmap == kernel_pmap)
1401 pmap_kenter_pde(va, newpde);
1403 pde_store(pde, newpde);
1404 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1405 pmap_update_pde_invalidate(va, newpde);
1410 __CONCAT(PMTYPE, invalidate_page)(pmap_t pmap, vm_offset_t va)
1413 pmap_invalidate_page_int(pmap, va);
1417 __CONCAT(PMTYPE, invalidate_range)(pmap_t pmap, vm_offset_t sva,
1421 pmap_invalidate_range_int(pmap, sva, eva);
1425 __CONCAT(PMTYPE, invalidate_all)(pmap_t pmap)
1428 pmap_invalidate_all_int(pmap);
1432 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1436 * When the PDE has PG_PROMOTED set, the 2- or 4MB page mapping was
1437 * created by a promotion that did not invalidate the 512 or 1024 4KB
1438 * page mappings that might exist in the TLB. Consequently, at this
1439 * point, the TLB may hold both 4KB and 2- or 4MB page mappings for
1440 * the address range [va, va + NBPDR). Therefore, the entire range
1441 * must be invalidated here. In contrast, when PG_PROMOTED is clear,
1442 * the TLB will not hold any 4KB page mappings for the address range
1443 * [va, va + NBPDR), and so a single INVLPG suffices to invalidate the
1444 * 2- or 4MB page mapping from the TLB.
1446 if ((pde & PG_PROMOTED) != 0)
1447 pmap_invalidate_range_int(pmap, va, va + NBPDR - 1);
1449 pmap_invalidate_page_int(pmap, va);
1453 * Are we current address space or kernel?
1456 pmap_is_current(pmap_t pmap)
1459 return (pmap == kernel_pmap);
1463 * If the given pmap is not the current or kernel pmap, the returned pte must
1464 * be released by passing it to pmap_pte_release().
1467 __CONCAT(PMTYPE, pte)(pmap_t pmap, vm_offset_t va)
1472 pde = pmap_pde(pmap, va);
1476 /* are we current address space or kernel? */
1477 if (pmap_is_current(pmap))
1478 return (vtopte(va));
1479 mtx_lock(&PMAP2mutex);
1480 newpf = *pde & PG_FRAME;
1481 if ((*PMAP2 & PG_FRAME) != newpf) {
1482 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1483 pmap_invalidate_page_int(kernel_pmap,
1484 (vm_offset_t)PADDR2);
1486 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1492 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1495 static __inline void
1496 pmap_pte_release(pt_entry_t *pte)
1499 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1500 mtx_unlock(&PMAP2mutex);
1504 * NB: The sequence of updating a page table followed by accesses to the
1505 * corresponding pages is subject to the situation described in the "AMD64
1506 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1507 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1508 * right after modifying the PTE bits is crucial.
1510 static __inline void
1511 invlcaddr(void *caddr)
1514 invlpg((u_int)caddr);
1518 * Super fast pmap_pte routine best used when scanning
1519 * the pv lists. This eliminates many coarse-grained
1520 * invltlb calls. Note that many of the pv list
1521 * scans are across different pmaps. It is very wasteful
1522 * to do an entire invltlb for checking a single mapping.
1524 * If the given pmap is not the current pmap, pvh_global_lock
1525 * must be held and curthread pinned to a CPU.
1528 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1533 pde = pmap_pde(pmap, va);
1537 /* are we current address space or kernel? */
1538 if (pmap_is_current(pmap))
1539 return (vtopte(va));
1540 rw_assert(&pvh_global_lock, RA_WLOCKED);
1541 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1542 newpf = *pde & PG_FRAME;
1543 if ((*PMAP1 & PG_FRAME) != newpf) {
1544 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1546 PMAP1cpu = PCPU_GET(cpuid);
1552 if (PMAP1cpu != PCPU_GET(cpuid)) {
1553 PMAP1cpu = PCPU_GET(cpuid);
1559 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1565 pmap_pte_quick3(pmap_t pmap, vm_offset_t va)
1570 pde = pmap_pde(pmap, va);
1574 rw_assert(&pvh_global_lock, RA_WLOCKED);
1575 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1576 newpf = *pde & PG_FRAME;
1577 if ((*PMAP3 & PG_FRAME) != newpf) {
1578 *PMAP3 = newpf | PG_RW | PG_V | PG_A | PG_M;
1580 PMAP3cpu = PCPU_GET(cpuid);
1586 if (PMAP3cpu != PCPU_GET(cpuid)) {
1587 PMAP3cpu = PCPU_GET(cpuid);
1593 return (PADDR3 + (i386_btop(va) & (NPTEPG - 1)));
1599 pmap_pte_ufast(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1601 pt_entry_t *eh_ptep, pte, *ptep;
1603 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1606 eh_ptep = (pt_entry_t *)PCPU_GET(pmap_eh_ptep);
1607 if ((*eh_ptep & PG_FRAME) != pde) {
1608 *eh_ptep = pde | PG_RW | PG_V | PG_A | PG_M;
1609 invlcaddr((void *)PCPU_GET(pmap_eh_va));
1611 ptep = (pt_entry_t *)PCPU_GET(pmap_eh_va) + (i386_btop(va) &
1619 * Extract from the kernel page table the physical address that is mapped by
1620 * the given virtual address "va".
1622 * This function may be used before pmap_bootstrap() is called.
1625 __CONCAT(PMTYPE, kextract)(vm_offset_t va)
1629 if ((pa = pte_load(&PTD[va >> PDRSHIFT])) & PG_PS) {
1630 pa = (pa & PG_PS_FRAME) | (va & PDRMASK);
1633 * Beware of a concurrent promotion that changes the PDE at
1634 * this point! For example, vtopte() must not be used to
1635 * access the PTE because it would use the new PDE. It is,
1636 * however, safe to use the old PDE because the page table
1637 * page is preserved by the promotion.
1639 pa = KPTmap[i386_btop(va)];
1640 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
1646 * Routine: pmap_extract
1648 * Extract the physical page address associated
1649 * with the given map/virtual_address pair.
1652 __CONCAT(PMTYPE, extract)(pmap_t pmap, vm_offset_t va)
1660 pde = pmap->pm_pdir[va >> PDRSHIFT];
1662 if ((pde & PG_PS) != 0)
1663 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1665 pte = pmap_pte_ufast(pmap, va, pde);
1666 rtval = (pte & PG_FRAME) | (va & PAGE_MASK);
1674 * Routine: pmap_extract_and_hold
1676 * Atomically extract and hold the physical page
1677 * with the given pmap and virtual address pair
1678 * if that mapping permits the given protection.
1681 __CONCAT(PMTYPE, extract_and_hold)(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1692 pde = *pmap_pde(pmap, va);
1695 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1696 if (vm_page_pa_tryrelock(pmap, (pde &
1697 PG_PS_FRAME) | (va & PDRMASK), &pa))
1699 m = PHYS_TO_VM_PAGE(pa);
1702 pte = pmap_pte_ufast(pmap, va, pde);
1704 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1705 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1708 m = PHYS_TO_VM_PAGE(pa);
1719 /***************************************************
1720 * Low level mapping routines.....
1721 ***************************************************/
1724 * Add a wired page to the kva.
1725 * Note: not SMP coherent.
1727 * This function may be used before pmap_bootstrap() is called.
1730 __CONCAT(PMTYPE, kenter)(vm_offset_t va, vm_paddr_t pa)
1735 pte_store(pte, pa | PG_RW | PG_V);
1738 static __inline void
1739 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1744 pte_store(pte, pa | PG_RW | PG_V | pmap_cache_bits(kernel_pmap,
1749 * Remove a page from the kernel pagetables.
1750 * Note: not SMP coherent.
1752 * This function may be used before pmap_bootstrap() is called.
1755 __CONCAT(PMTYPE, kremove)(vm_offset_t va)
1764 * Used to map a range of physical addresses into kernel
1765 * virtual address space.
1767 * The value passed in '*virt' is a suggested virtual address for
1768 * the mapping. Architectures which can support a direct-mapped
1769 * physical to virtual region can return the appropriate address
1770 * within that region, leaving '*virt' unchanged. Other
1771 * architectures should map the pages starting at '*virt' and
1772 * update '*virt' with the first usable address after the mapped
1776 __CONCAT(PMTYPE, map)(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end,
1779 vm_offset_t va, sva;
1780 vm_paddr_t superpage_offset;
1785 * Does the physical address range's size and alignment permit at
1786 * least one superpage mapping to be created?
1788 superpage_offset = start & PDRMASK;
1789 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1791 * Increase the starting virtual address so that its alignment
1792 * does not preclude the use of superpage mappings.
1794 if ((va & PDRMASK) < superpage_offset)
1795 va = (va & ~PDRMASK) + superpage_offset;
1796 else if ((va & PDRMASK) > superpage_offset)
1797 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1800 while (start < end) {
1801 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1803 KASSERT((va & PDRMASK) == 0,
1804 ("pmap_map: misaligned va %#x", va));
1805 newpde = start | PG_PS | PG_RW | PG_V;
1806 pmap_kenter_pde(va, newpde);
1810 pmap_kenter(va, start);
1815 pmap_invalidate_range_int(kernel_pmap, sva, va);
1822 * Add a list of wired pages to the kva
1823 * this routine is only used for temporary
1824 * kernel mappings that do not need to have
1825 * page modification or references recorded.
1826 * Note that old mappings are simply written
1827 * over. The page *must* be wired.
1828 * Note: SMP coherent. Uses a ranged shootdown IPI.
1831 __CONCAT(PMTYPE, qenter)(vm_offset_t sva, vm_page_t *ma, int count)
1833 pt_entry_t *endpte, oldpte, pa, *pte;
1838 endpte = pte + count;
1839 while (pte < endpte) {
1841 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(kernel_pmap,
1843 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1845 #ifdef PMAP_PAE_COMP
1846 pte_store(pte, pa | pg_nx | PG_RW | PG_V);
1848 pte_store(pte, pa | PG_RW | PG_V);
1853 if (__predict_false((oldpte & PG_V) != 0))
1854 pmap_invalidate_range_int(kernel_pmap, sva, sva + count *
1859 * This routine tears out page mappings from the
1860 * kernel -- it is meant only for temporary mappings.
1861 * Note: SMP coherent. Uses a ranged shootdown IPI.
1864 __CONCAT(PMTYPE, qremove)(vm_offset_t sva, int count)
1869 while (count-- > 0) {
1873 pmap_invalidate_range_int(kernel_pmap, sva, va);
1876 /***************************************************
1877 * Page table page management routines.....
1878 ***************************************************/
1880 * Schedule the specified unused page table page to be freed. Specifically,
1881 * add the page to the specified list of pages that will be released to the
1882 * physical memory manager after the TLB has been updated.
1884 static __inline void
1885 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1886 boolean_t set_PG_ZERO)
1890 m->flags |= PG_ZERO;
1892 m->flags &= ~PG_ZERO;
1893 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1897 * Inserts the specified page table page into the specified pmap's collection
1898 * of idle page table pages. Each of a pmap's page table pages is responsible
1899 * for mapping a distinct range of virtual addresses. The pmap's collection is
1900 * ordered by this virtual address range.
1903 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1906 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1907 return (vm_radix_insert(&pmap->pm_root, mpte));
1911 * Removes the page table page mapping the specified virtual address from the
1912 * specified pmap's collection of idle page table pages, and returns it.
1913 * Otherwise, returns NULL if there is no page table page corresponding to the
1914 * specified virtual address.
1916 static __inline vm_page_t
1917 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
1920 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1921 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT));
1925 * Decrements a page table page's wire count, which is used to record the
1926 * number of valid page table entries within the page. If the wire count
1927 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1928 * page table page was unmapped and FALSE otherwise.
1930 static inline boolean_t
1931 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1935 if (m->wire_count == 0) {
1936 _pmap_unwire_ptp(pmap, m, free);
1943 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1947 * unmap the page table page
1949 pmap->pm_pdir[m->pindex] = 0;
1950 --pmap->pm_stats.resident_count;
1953 * There is not need to invalidate the recursive mapping since
1954 * we never instantiate such mapping for the usermode pmaps,
1955 * and never remove page table pages from the kernel pmap.
1956 * Put page on a list so that it is released since all TLB
1957 * shootdown is done.
1959 MPASS(pmap != kernel_pmap);
1960 pmap_add_delayed_free_list(m, free, TRUE);
1964 * After removing a page table entry, this routine is used to
1965 * conditionally free the page, and manage the hold/wire counts.
1968 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1973 if (pmap == kernel_pmap)
1975 ptepde = *pmap_pde(pmap, va);
1976 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1977 return (pmap_unwire_ptp(pmap, mpte, free));
1981 * Initialize the pmap for the swapper process.
1984 __CONCAT(PMTYPE, pinit0)(pmap_t pmap)
1987 PMAP_LOCK_INIT(pmap);
1988 pmap->pm_pdir = IdlePTD;
1989 #ifdef PMAP_PAE_COMP
1990 pmap->pm_pdpt = IdlePDPT;
1992 pmap->pm_root.rt_root = 0;
1993 CPU_ZERO(&pmap->pm_active);
1994 TAILQ_INIT(&pmap->pm_pvchunk);
1995 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1996 pmap_activate_boot(pmap);
2000 * Initialize a preallocated and zeroed pmap structure,
2001 * such as one in a vmspace structure.
2004 __CONCAT(PMTYPE, pinit)(pmap_t pmap)
2010 * No need to allocate page table space yet but we do need a valid
2011 * page directory table.
2013 if (pmap->pm_pdir == NULL) {
2014 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
2015 if (pmap->pm_pdir == NULL)
2017 #ifdef PMAP_PAE_COMP
2018 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
2019 KASSERT(((vm_offset_t)pmap->pm_pdpt &
2020 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
2021 ("pmap_pinit: pdpt misaligned"));
2022 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
2023 ("pmap_pinit: pdpt above 4g"));
2025 pmap->pm_root.rt_root = 0;
2027 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2028 ("pmap_pinit: pmap has reserved page table page(s)"));
2031 * allocate the page directory page(s)
2033 for (i = 0; i < NPGPTD; i++) {
2034 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2035 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
2036 pmap->pm_ptdpg[i] = m;
2037 #ifdef PMAP_PAE_COMP
2038 pmap->pm_pdpt[i] = VM_PAGE_TO_PHYS(m) | PG_V;
2042 pmap_qenter((vm_offset_t)pmap->pm_pdir, pmap->pm_ptdpg, NPGPTD);
2044 for (i = 0; i < NPGPTD; i++)
2045 if ((pmap->pm_ptdpg[i]->flags & PG_ZERO) == 0)
2046 pagezero(pmap->pm_pdir + (i * NPDEPG));
2048 /* Install the trampoline mapping. */
2049 pmap->pm_pdir[TRPTDI] = PTD[TRPTDI];
2051 CPU_ZERO(&pmap->pm_active);
2052 TAILQ_INIT(&pmap->pm_pvchunk);
2053 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2059 * this routine is called if the page table page is not
2063 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
2069 * Allocate a page table page.
2071 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2072 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2073 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2075 rw_wunlock(&pvh_global_lock);
2077 rw_wlock(&pvh_global_lock);
2082 * Indicate the need to retry. While waiting, the page table
2083 * page may have been allocated.
2087 if ((m->flags & PG_ZERO) == 0)
2091 * Map the pagetable page into the process address space, if
2092 * it isn't already there.
2095 pmap->pm_stats.resident_count++;
2097 ptepa = VM_PAGE_TO_PHYS(m);
2098 pmap->pm_pdir[ptepindex] =
2099 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
2105 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
2112 * Calculate pagetable page index
2114 ptepindex = va >> PDRSHIFT;
2117 * Get the page directory entry
2119 ptepa = pmap->pm_pdir[ptepindex];
2122 * This supports switching from a 4MB page to a
2125 if (ptepa & PG_PS) {
2126 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
2127 ptepa = pmap->pm_pdir[ptepindex];
2131 * If the page table page is mapped, we just increment the
2132 * hold count, and activate it.
2135 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
2139 * Here if the pte page isn't mapped, or if it has
2142 m = _pmap_allocpte(pmap, ptepindex, flags);
2143 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2150 /***************************************************
2151 * Pmap allocation/deallocation routines.
2152 ***************************************************/
2155 * Release any resources held by the given physical map.
2156 * Called when a pmap initialized by pmap_pinit is being released.
2157 * Should only be called if the map contains no valid mappings.
2160 __CONCAT(PMTYPE, release)(pmap_t pmap)
2165 KASSERT(pmap->pm_stats.resident_count == 0,
2166 ("pmap_release: pmap resident count %ld != 0",
2167 pmap->pm_stats.resident_count));
2168 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2169 ("pmap_release: pmap has reserved page table page(s)"));
2170 KASSERT(CPU_EMPTY(&pmap->pm_active),
2171 ("releasing active pmap %p", pmap));
2173 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2175 for (i = 0; i < NPGPTD; i++) {
2176 m = pmap->pm_ptdpg[i];
2177 #ifdef PMAP_PAE_COMP
2178 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2179 ("pmap_release: got wrong ptd page"));
2181 vm_page_unwire_noq(m);
2187 * grow the number of kernel page table entries, if needed
2190 __CONCAT(PMTYPE, growkernel)(vm_offset_t addr)
2192 vm_paddr_t ptppaddr;
2196 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2197 addr = roundup2(addr, NBPDR);
2198 if (addr - 1 >= vm_map_max(kernel_map))
2199 addr = vm_map_max(kernel_map);
2200 while (kernel_vm_end < addr) {
2201 if (pdir_pde(PTD, kernel_vm_end)) {
2202 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2203 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2204 kernel_vm_end = vm_map_max(kernel_map);
2210 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2211 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2214 panic("pmap_growkernel: no memory to grow kernel");
2218 if ((nkpg->flags & PG_ZERO) == 0)
2219 pmap_zero_page(nkpg);
2220 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2221 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2222 pdir_pde(KPTD, kernel_vm_end) = newpdir;
2224 pmap_kenter_pde(kernel_vm_end, newpdir);
2225 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2226 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2227 kernel_vm_end = vm_map_max(kernel_map);
2234 /***************************************************
2235 * page management routines.
2236 ***************************************************/
2238 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2239 CTASSERT(_NPCM == 11);
2240 CTASSERT(_NPCPV == 336);
2242 static __inline struct pv_chunk *
2243 pv_to_chunk(pv_entry_t pv)
2246 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2249 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2251 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2252 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2254 static const uint32_t pc_freemask[_NPCM] = {
2255 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2256 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2257 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2258 PC_FREE0_9, PC_FREE10
2262 extern int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2263 extern long pv_entry_frees, pv_entry_allocs;
2264 extern int pv_entry_spare;
2268 * We are in a serious low memory condition. Resort to
2269 * drastic measures to free some pages so we can allocate
2270 * another pv entry chunk.
2273 pmap_pv_reclaim(pmap_t locked_pmap)
2276 struct pv_chunk *pc;
2277 struct md_page *pvh;
2280 pt_entry_t *pte, tpte;
2284 struct spglist free;
2286 int bit, field, freed;
2288 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2292 TAILQ_INIT(&newtail);
2293 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2294 SLIST_EMPTY(&free))) {
2295 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2296 if (pmap != pc->pc_pmap) {
2298 pmap_invalidate_all_int(pmap);
2299 if (pmap != locked_pmap)
2303 /* Avoid deadlock and lock recursion. */
2304 if (pmap > locked_pmap)
2306 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2308 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2314 * Destroy every non-wired, 4 KB page mapping in the chunk.
2317 for (field = 0; field < _NPCM; field++) {
2318 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2319 inuse != 0; inuse &= ~(1UL << bit)) {
2321 pv = &pc->pc_pventry[field * 32 + bit];
2323 pde = pmap_pde(pmap, va);
2324 if ((*pde & PG_PS) != 0)
2326 pte = __CONCAT(PMTYPE, pte)(pmap, va);
2328 if ((tpte & PG_W) == 0)
2329 tpte = pte_load_clear(pte);
2330 pmap_pte_release(pte);
2331 if ((tpte & PG_W) != 0)
2334 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2336 if ((tpte & PG_G) != 0)
2337 pmap_invalidate_page_int(pmap, va);
2338 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2339 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2341 if ((tpte & PG_A) != 0)
2342 vm_page_aflag_set(m, PGA_REFERENCED);
2343 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2344 if (TAILQ_EMPTY(&m->md.pv_list) &&
2345 (m->flags & PG_FICTITIOUS) == 0) {
2346 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2347 if (TAILQ_EMPTY(&pvh->pv_list)) {
2348 vm_page_aflag_clear(m,
2352 pc->pc_map[field] |= 1UL << bit;
2353 pmap_unuse_pt(pmap, va, &free);
2358 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2361 /* Every freed mapping is for a 4 KB page. */
2362 pmap->pm_stats.resident_count -= freed;
2363 PV_STAT(pv_entry_frees += freed);
2364 PV_STAT(pv_entry_spare += freed);
2365 pv_entry_count -= freed;
2366 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2367 for (field = 0; field < _NPCM; field++)
2368 if (pc->pc_map[field] != pc_freemask[field]) {
2369 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2371 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2374 * One freed pv entry in locked_pmap is
2377 if (pmap == locked_pmap)
2381 if (field == _NPCM) {
2382 PV_STAT(pv_entry_spare -= _NPCPV);
2383 PV_STAT(pc_chunk_count--);
2384 PV_STAT(pc_chunk_frees++);
2385 /* Entire chunk is free; return it. */
2386 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2387 pmap_qremove((vm_offset_t)pc, 1);
2388 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2393 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2395 pmap_invalidate_all_int(pmap);
2396 if (pmap != locked_pmap)
2399 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2400 m_pc = SLIST_FIRST(&free);
2401 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2402 /* Recycle a freed page table page. */
2403 m_pc->wire_count = 1;
2405 vm_page_free_pages_toq(&free, true);
2410 * free the pv_entry back to the free list
2413 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2415 struct pv_chunk *pc;
2416 int idx, field, bit;
2418 rw_assert(&pvh_global_lock, RA_WLOCKED);
2419 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2420 PV_STAT(pv_entry_frees++);
2421 PV_STAT(pv_entry_spare++);
2423 pc = pv_to_chunk(pv);
2424 idx = pv - &pc->pc_pventry[0];
2427 pc->pc_map[field] |= 1ul << bit;
2428 for (idx = 0; idx < _NPCM; idx++)
2429 if (pc->pc_map[idx] != pc_freemask[idx]) {
2431 * 98% of the time, pc is already at the head of the
2432 * list. If it isn't already, move it to the head.
2434 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2436 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2437 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2442 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2447 free_pv_chunk(struct pv_chunk *pc)
2451 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2452 PV_STAT(pv_entry_spare -= _NPCPV);
2453 PV_STAT(pc_chunk_count--);
2454 PV_STAT(pc_chunk_frees++);
2455 /* entire chunk is free, return it */
2456 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2457 pmap_qremove((vm_offset_t)pc, 1);
2458 vm_page_unwire(m, PQ_NONE);
2460 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2464 * get a new pv_entry, allocating a block from the system
2468 get_pv_entry(pmap_t pmap, boolean_t try)
2470 static const struct timeval printinterval = { 60, 0 };
2471 static struct timeval lastprint;
2474 struct pv_chunk *pc;
2477 rw_assert(&pvh_global_lock, RA_WLOCKED);
2478 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2479 PV_STAT(pv_entry_allocs++);
2481 if (pv_entry_count > pv_entry_high_water)
2482 if (ratecheck(&lastprint, &printinterval))
2483 printf("Approaching the limit on PV entries, consider "
2484 "increasing either the vm.pmap.shpgperproc or the "
2485 "vm.pmap.pv_entries tunable.\n");
2487 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2489 for (field = 0; field < _NPCM; field++) {
2490 if (pc->pc_map[field]) {
2491 bit = bsfl(pc->pc_map[field]);
2495 if (field < _NPCM) {
2496 pv = &pc->pc_pventry[field * 32 + bit];
2497 pc->pc_map[field] &= ~(1ul << bit);
2498 /* If this was the last item, move it to tail */
2499 for (field = 0; field < _NPCM; field++)
2500 if (pc->pc_map[field] != 0) {
2501 PV_STAT(pv_entry_spare--);
2502 return (pv); /* not full, return */
2504 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2505 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2506 PV_STAT(pv_entry_spare--);
2511 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2512 * global lock. If "pv_vafree" is currently non-empty, it will
2513 * remain non-empty until pmap_ptelist_alloc() completes.
2515 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2516 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2519 PV_STAT(pc_chunk_tryfail++);
2522 m = pmap_pv_reclaim(pmap);
2526 PV_STAT(pc_chunk_count++);
2527 PV_STAT(pc_chunk_allocs++);
2528 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2529 pmap_qenter((vm_offset_t)pc, &m, 1);
2531 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2532 for (field = 1; field < _NPCM; field++)
2533 pc->pc_map[field] = pc_freemask[field];
2534 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2535 pv = &pc->pc_pventry[0];
2536 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2537 PV_STAT(pv_entry_spare += _NPCPV - 1);
2541 static __inline pv_entry_t
2542 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2546 rw_assert(&pvh_global_lock, RA_WLOCKED);
2547 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2548 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2549 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2557 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2559 struct md_page *pvh;
2561 vm_offset_t va_last;
2564 rw_assert(&pvh_global_lock, RA_WLOCKED);
2565 KASSERT((pa & PDRMASK) == 0,
2566 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2569 * Transfer the 4mpage's pv entry for this mapping to the first
2572 pvh = pa_to_pvh(pa);
2573 va = trunc_4mpage(va);
2574 pv = pmap_pvh_remove(pvh, pmap, va);
2575 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2576 m = PHYS_TO_VM_PAGE(pa);
2577 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2578 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2579 va_last = va + NBPDR - PAGE_SIZE;
2582 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2583 ("pmap_pv_demote_pde: page %p is not managed", m));
2585 pmap_insert_entry(pmap, va, m);
2586 } while (va < va_last);
2589 #if VM_NRESERVLEVEL > 0
2591 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2593 struct md_page *pvh;
2595 vm_offset_t va_last;
2598 rw_assert(&pvh_global_lock, RA_WLOCKED);
2599 KASSERT((pa & PDRMASK) == 0,
2600 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2603 * Transfer the first page's pv entry for this mapping to the
2604 * 4mpage's pv list. Aside from avoiding the cost of a call
2605 * to get_pv_entry(), a transfer avoids the possibility that
2606 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2607 * removes one of the mappings that is being promoted.
2609 m = PHYS_TO_VM_PAGE(pa);
2610 va = trunc_4mpage(va);
2611 pv = pmap_pvh_remove(&m->md, pmap, va);
2612 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2613 pvh = pa_to_pvh(pa);
2614 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2615 /* Free the remaining NPTEPG - 1 pv entries. */
2616 va_last = va + NBPDR - PAGE_SIZE;
2620 pmap_pvh_free(&m->md, pmap, va);
2621 } while (va < va_last);
2623 #endif /* VM_NRESERVLEVEL > 0 */
2626 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2630 pv = pmap_pvh_remove(pvh, pmap, va);
2631 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2632 free_pv_entry(pmap, pv);
2636 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2638 struct md_page *pvh;
2640 rw_assert(&pvh_global_lock, RA_WLOCKED);
2641 pmap_pvh_free(&m->md, pmap, va);
2642 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2643 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2644 if (TAILQ_EMPTY(&pvh->pv_list))
2645 vm_page_aflag_clear(m, PGA_WRITEABLE);
2650 * Create a pv entry for page at pa for
2654 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2658 rw_assert(&pvh_global_lock, RA_WLOCKED);
2659 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2660 pv = get_pv_entry(pmap, FALSE);
2662 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2666 * Conditionally create a pv entry.
2669 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2673 rw_assert(&pvh_global_lock, RA_WLOCKED);
2674 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2675 if (pv_entry_count < pv_entry_high_water &&
2676 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2678 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2685 * Create the pv entries for each of the pages within a superpage.
2688 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags)
2690 struct md_page *pvh;
2694 rw_assert(&pvh_global_lock, RA_WLOCKED);
2695 noreclaim = (flags & PMAP_ENTER_NORECLAIM) != 0;
2696 if ((noreclaim && pv_entry_count >= pv_entry_high_water) ||
2697 (pv = get_pv_entry(pmap, noreclaim)) == NULL)
2700 pvh = pa_to_pvh(pde & PG_PS_FRAME);
2701 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2706 * Fills a page table page with mappings to consecutive physical pages.
2709 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2713 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2715 newpte += PAGE_SIZE;
2720 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2721 * 2- or 4MB page mapping is invalidated.
2724 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2726 pd_entry_t newpde, oldpde;
2727 pt_entry_t *firstpte, newpte;
2730 struct spglist free;
2733 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2735 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2736 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2737 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
2739 KASSERT((oldpde & PG_W) == 0,
2740 ("pmap_demote_pde: page table page for a wired mapping"
2744 * Invalidate the 2- or 4MB page mapping and return
2745 * "failure" if the mapping was never accessed or the
2746 * allocation of the new page table page fails.
2748 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2749 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2750 VM_ALLOC_WIRED)) == NULL) {
2752 sva = trunc_4mpage(va);
2753 pmap_remove_pde(pmap, pde, sva, &free);
2754 if ((oldpde & PG_G) == 0)
2755 pmap_invalidate_pde_page(pmap, sva, oldpde);
2756 vm_page_free_pages_toq(&free, true);
2757 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2758 " in pmap %p", va, pmap);
2761 if (pmap != kernel_pmap)
2762 pmap->pm_stats.resident_count++;
2764 mptepa = VM_PAGE_TO_PHYS(mpte);
2767 * If the page mapping is in the kernel's address space, then the
2768 * KPTmap can provide access to the page table page. Otherwise,
2769 * temporarily map the page table page (mpte) into the kernel's
2770 * address space at either PADDR1 or PADDR2.
2772 if (pmap == kernel_pmap)
2773 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2774 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2775 if ((*PMAP1 & PG_FRAME) != mptepa) {
2776 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2778 PMAP1cpu = PCPU_GET(cpuid);
2784 if (PMAP1cpu != PCPU_GET(cpuid)) {
2785 PMAP1cpu = PCPU_GET(cpuid);
2793 mtx_lock(&PMAP2mutex);
2794 if ((*PMAP2 & PG_FRAME) != mptepa) {
2795 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2796 pmap_invalidate_page_int(kernel_pmap,
2797 (vm_offset_t)PADDR2);
2801 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2802 KASSERT((oldpde & PG_A) != 0,
2803 ("pmap_demote_pde: oldpde is missing PG_A"));
2804 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2805 ("pmap_demote_pde: oldpde is missing PG_M"));
2806 newpte = oldpde & ~PG_PS;
2807 if ((newpte & PG_PDE_PAT) != 0)
2808 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2811 * If the page table page is new, initialize it.
2813 if (mpte->wire_count == 1) {
2814 mpte->wire_count = NPTEPG;
2815 pmap_fill_ptp(firstpte, newpte);
2817 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2818 ("pmap_demote_pde: firstpte and newpte map different physical"
2822 * If the mapping has changed attributes, update the page table
2825 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2826 pmap_fill_ptp(firstpte, newpte);
2829 * Demote the mapping. This pmap is locked. The old PDE has
2830 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2831 * set. Thus, there is no danger of a race with another
2832 * processor changing the setting of PG_A and/or PG_M between
2833 * the read above and the store below.
2835 if (workaround_erratum383)
2836 pmap_update_pde(pmap, va, pde, newpde);
2837 else if (pmap == kernel_pmap)
2838 pmap_kenter_pde(va, newpde);
2840 pde_store(pde, newpde);
2841 if (firstpte == PADDR2)
2842 mtx_unlock(&PMAP2mutex);
2845 * Invalidate the recursive mapping of the page table page.
2847 pmap_invalidate_page_int(pmap, (vm_offset_t)vtopte(va));
2850 * Demote the pv entry. This depends on the earlier demotion
2851 * of the mapping. Specifically, the (re)creation of a per-
2852 * page pv entry might trigger the execution of pmap_collect(),
2853 * which might reclaim a newly (re)created per-page pv entry
2854 * and destroy the associated mapping. In order to destroy
2855 * the mapping, the PDE must have already changed from mapping
2856 * the 2mpage to referencing the page table page.
2858 if ((oldpde & PG_MANAGED) != 0)
2859 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2861 pmap_pde_demotions++;
2862 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2863 " in pmap %p", va, pmap);
2868 * Removes a 2- or 4MB page mapping from the kernel pmap.
2871 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2877 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2878 mpte = pmap_remove_pt_page(pmap, va);
2880 panic("pmap_remove_kernel_pde: Missing pt page.");
2882 mptepa = VM_PAGE_TO_PHYS(mpte);
2883 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2886 * Initialize the page table page.
2888 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2891 * Remove the mapping.
2893 if (workaround_erratum383)
2894 pmap_update_pde(pmap, va, pde, newpde);
2896 pmap_kenter_pde(va, newpde);
2899 * Invalidate the recursive mapping of the page table page.
2901 pmap_invalidate_page_int(pmap, (vm_offset_t)vtopte(va));
2905 * pmap_remove_pde: do the things to unmap a superpage in a process
2908 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2909 struct spglist *free)
2911 struct md_page *pvh;
2913 vm_offset_t eva, va;
2916 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2917 KASSERT((sva & PDRMASK) == 0,
2918 ("pmap_remove_pde: sva is not 4mpage aligned"));
2919 oldpde = pte_load_clear(pdq);
2921 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2924 * Machines that don't support invlpg, also don't support
2927 if ((oldpde & PG_G) != 0)
2928 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
2930 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2931 if (oldpde & PG_MANAGED) {
2932 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2933 pmap_pvh_free(pvh, pmap, sva);
2935 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2936 va < eva; va += PAGE_SIZE, m++) {
2937 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2940 vm_page_aflag_set(m, PGA_REFERENCED);
2941 if (TAILQ_EMPTY(&m->md.pv_list) &&
2942 TAILQ_EMPTY(&pvh->pv_list))
2943 vm_page_aflag_clear(m, PGA_WRITEABLE);
2946 if (pmap == kernel_pmap) {
2947 pmap_remove_kernel_pde(pmap, pdq, sva);
2949 mpte = pmap_remove_pt_page(pmap, sva);
2951 pmap->pm_stats.resident_count--;
2952 KASSERT(mpte->wire_count == NPTEPG,
2953 ("pmap_remove_pde: pte page wire count error"));
2954 mpte->wire_count = 0;
2955 pmap_add_delayed_free_list(mpte, free, FALSE);
2961 * pmap_remove_pte: do the things to unmap a page in a process
2964 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
2965 struct spglist *free)
2970 rw_assert(&pvh_global_lock, RA_WLOCKED);
2971 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2972 oldpte = pte_load_clear(ptq);
2973 KASSERT(oldpte != 0,
2974 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
2976 pmap->pm_stats.wired_count -= 1;
2978 * Machines that don't support invlpg, also don't support
2982 pmap_invalidate_page_int(kernel_pmap, va);
2983 pmap->pm_stats.resident_count -= 1;
2984 if (oldpte & PG_MANAGED) {
2985 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2986 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2989 vm_page_aflag_set(m, PGA_REFERENCED);
2990 pmap_remove_entry(pmap, m, va);
2992 return (pmap_unuse_pt(pmap, va, free));
2996 * Remove a single page from a process address space
2999 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
3003 rw_assert(&pvh_global_lock, RA_WLOCKED);
3004 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3005 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3006 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
3008 pmap_remove_pte(pmap, pte, va, free);
3009 pmap_invalidate_page_int(pmap, va);
3013 * Removes the specified range of addresses from the page table page.
3016 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
3017 struct spglist *free)
3022 rw_assert(&pvh_global_lock, RA_WLOCKED);
3023 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3024 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3026 for (pte = pmap_pte_quick(pmap, sva); sva != eva; pte++,
3032 * The TLB entry for a PG_G mapping is invalidated by
3033 * pmap_remove_pte().
3035 if ((*pte & PG_G) == 0)
3038 if (pmap_remove_pte(pmap, pte, sva, free))
3045 * Remove the given range of addresses from the specified map.
3047 * It is assumed that the start and end are properly
3048 * rounded to the page size.
3051 __CONCAT(PMTYPE, remove)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3055 struct spglist free;
3059 * Perform an unsynchronized read. This is, however, safe.
3061 if (pmap->pm_stats.resident_count == 0)
3067 rw_wlock(&pvh_global_lock);
3072 * special handling of removing one page. a very
3073 * common operation and easy to short circuit some
3076 if ((sva + PAGE_SIZE == eva) &&
3077 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
3078 pmap_remove_page(pmap, sva, &free);
3082 for (; sva < eva; sva = pdnxt) {
3086 * Calculate index for next page table.
3088 pdnxt = (sva + NBPDR) & ~PDRMASK;
3091 if (pmap->pm_stats.resident_count == 0)
3094 pdirindex = sva >> PDRSHIFT;
3095 ptpaddr = pmap->pm_pdir[pdirindex];
3098 * Weed out invalid mappings. Note: we assume that the page
3099 * directory table is always allocated, and in kernel virtual.
3105 * Check for large page.
3107 if ((ptpaddr & PG_PS) != 0) {
3109 * Are we removing the entire large page? If not,
3110 * demote the mapping and fall through.
3112 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3114 * The TLB entry for a PG_G mapping is
3115 * invalidated by pmap_remove_pde().
3117 if ((ptpaddr & PG_G) == 0)
3119 pmap_remove_pde(pmap,
3120 &pmap->pm_pdir[pdirindex], sva, &free);
3122 } else if (!pmap_demote_pde(pmap,
3123 &pmap->pm_pdir[pdirindex], sva)) {
3124 /* The large page mapping was destroyed. */
3130 * Limit our scan to either the end of the va represented
3131 * by the current page table page, or to the end of the
3132 * range being removed.
3137 if (pmap_remove_ptes(pmap, sva, pdnxt, &free))
3143 pmap_invalidate_all_int(pmap);
3144 rw_wunlock(&pvh_global_lock);
3146 vm_page_free_pages_toq(&free, true);
3150 * Routine: pmap_remove_all
3152 * Removes this physical page from
3153 * all physical maps in which it resides.
3154 * Reflects back modify bits to the pager.
3157 * Original versions of this routine were very
3158 * inefficient because they iteratively called
3159 * pmap_remove (slow...)
3163 __CONCAT(PMTYPE, remove_all)(vm_page_t m)
3165 struct md_page *pvh;
3168 pt_entry_t *pte, tpte;
3171 struct spglist free;
3173 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3174 ("pmap_remove_all: page %p is not managed", m));
3176 rw_wlock(&pvh_global_lock);
3178 if ((m->flags & PG_FICTITIOUS) != 0)
3179 goto small_mappings;
3180 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3181 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3185 pde = pmap_pde(pmap, va);
3186 (void)pmap_demote_pde(pmap, pde, va);
3190 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3193 pmap->pm_stats.resident_count--;
3194 pde = pmap_pde(pmap, pv->pv_va);
3195 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3196 " a 4mpage in page %p's pv list", m));
3197 pte = pmap_pte_quick(pmap, pv->pv_va);
3198 tpte = pte_load_clear(pte);
3199 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3202 pmap->pm_stats.wired_count--;
3204 vm_page_aflag_set(m, PGA_REFERENCED);
3207 * Update the vm_page_t clean and reference bits.
3209 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3211 pmap_unuse_pt(pmap, pv->pv_va, &free);
3212 pmap_invalidate_page_int(pmap, pv->pv_va);
3213 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3214 free_pv_entry(pmap, pv);
3217 vm_page_aflag_clear(m, PGA_WRITEABLE);
3219 rw_wunlock(&pvh_global_lock);
3220 vm_page_free_pages_toq(&free, true);
3224 * pmap_protect_pde: do the things to protect a 4mpage in a process
3227 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3229 pd_entry_t newpde, oldpde;
3230 vm_offset_t eva, va;
3232 boolean_t anychanged;
3234 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3235 KASSERT((sva & PDRMASK) == 0,
3236 ("pmap_protect_pde: sva is not 4mpage aligned"));
3239 oldpde = newpde = *pde;
3240 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
3241 (PG_MANAGED | PG_M | PG_RW)) {
3243 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3244 va < eva; va += PAGE_SIZE, m++)
3247 if ((prot & VM_PROT_WRITE) == 0)
3248 newpde &= ~(PG_RW | PG_M);
3249 #ifdef PMAP_PAE_COMP
3250 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
3253 if (newpde != oldpde) {
3255 * As an optimization to future operations on this PDE, clear
3256 * PG_PROMOTED. The impending invalidation will remove any
3257 * lingering 4KB page mappings from the TLB.
3259 if (!pde_cmpset(pde, oldpde, newpde & ~PG_PROMOTED))
3261 if ((oldpde & PG_G) != 0)
3262 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
3266 return (anychanged);
3270 * Set the physical protection on the
3271 * specified range of this map as requested.
3274 __CONCAT(PMTYPE, protect)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
3280 boolean_t anychanged, pv_lists_locked;
3282 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3283 if (prot == VM_PROT_NONE) {
3284 pmap_remove(pmap, sva, eva);
3288 #ifdef PMAP_PAE_COMP
3289 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
3290 (VM_PROT_WRITE | VM_PROT_EXECUTE))
3293 if (prot & VM_PROT_WRITE)
3297 if (pmap_is_current(pmap))
3298 pv_lists_locked = FALSE;
3300 pv_lists_locked = TRUE;
3302 rw_wlock(&pvh_global_lock);
3308 for (; sva < eva; sva = pdnxt) {
3309 pt_entry_t obits, pbits;
3312 pdnxt = (sva + NBPDR) & ~PDRMASK;
3316 pdirindex = sva >> PDRSHIFT;
3317 ptpaddr = pmap->pm_pdir[pdirindex];
3320 * Weed out invalid mappings. Note: we assume that the page
3321 * directory table is always allocated, and in kernel virtual.
3327 * Check for large page.
3329 if ((ptpaddr & PG_PS) != 0) {
3331 * Are we protecting the entire large page? If not,
3332 * demote the mapping and fall through.
3334 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3336 * The TLB entry for a PG_G mapping is
3337 * invalidated by pmap_protect_pde().
3339 if (pmap_protect_pde(pmap,
3340 &pmap->pm_pdir[pdirindex], sva, prot))
3344 if (!pv_lists_locked) {
3345 pv_lists_locked = TRUE;
3346 if (!rw_try_wlock(&pvh_global_lock)) {
3348 pmap_invalidate_all_int(
3355 if (!pmap_demote_pde(pmap,
3356 &pmap->pm_pdir[pdirindex], sva)) {
3358 * The large page mapping was
3369 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3375 * Regardless of whether a pte is 32 or 64 bits in
3376 * size, PG_RW, PG_A, and PG_M are among the least
3377 * significant 32 bits.
3379 obits = pbits = *pte;
3380 if ((pbits & PG_V) == 0)
3383 if ((prot & VM_PROT_WRITE) == 0) {
3384 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3385 (PG_MANAGED | PG_M | PG_RW)) {
3386 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3389 pbits &= ~(PG_RW | PG_M);
3391 #ifdef PMAP_PAE_COMP
3392 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
3396 if (pbits != obits) {
3397 #ifdef PMAP_PAE_COMP
3398 if (!atomic_cmpset_64(pte, obits, pbits))
3401 if (!atomic_cmpset_int((u_int *)pte, obits,
3406 pmap_invalidate_page_int(pmap, sva);
3413 pmap_invalidate_all_int(pmap);
3414 if (pv_lists_locked) {
3416 rw_wunlock(&pvh_global_lock);
3421 #if VM_NRESERVLEVEL > 0
3423 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3424 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3425 * For promotion to occur, two conditions must be met: (1) the 4KB page
3426 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3427 * mappings must have identical characteristics.
3429 * Managed (PG_MANAGED) mappings within the kernel address space are not
3430 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3431 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3435 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3438 pt_entry_t *firstpte, oldpte, pa, *pte;
3439 vm_offset_t oldpteva;
3442 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3445 * Examine the first PTE in the specified PTP. Abort if this PTE is
3446 * either invalid, unused, or does not map the first 4KB physical page
3447 * within a 2- or 4MB page.
3449 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3452 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3453 pmap_pde_p_failures++;
3454 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3455 " in pmap %p", va, pmap);
3458 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3459 pmap_pde_p_failures++;
3460 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3461 " in pmap %p", va, pmap);
3464 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3466 * When PG_M is already clear, PG_RW can be cleared without
3467 * a TLB invalidation.
3469 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3476 * Examine each of the other PTEs in the specified PTP. Abort if this
3477 * PTE maps an unexpected 4KB physical page or does not have identical
3478 * characteristics to the first PTE.
3480 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3481 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3484 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3485 pmap_pde_p_failures++;
3486 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3487 " in pmap %p", va, pmap);
3490 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3492 * When PG_M is already clear, PG_RW can be cleared
3493 * without a TLB invalidation.
3495 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3499 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3501 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3502 " in pmap %p", oldpteva, pmap);
3504 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3505 pmap_pde_p_failures++;
3506 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3507 " in pmap %p", va, pmap);
3514 * Save the page table page in its current state until the PDE
3515 * mapping the superpage is demoted by pmap_demote_pde() or
3516 * destroyed by pmap_remove_pde().
3518 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3519 KASSERT(mpte >= vm_page_array &&
3520 mpte < &vm_page_array[vm_page_array_size],
3521 ("pmap_promote_pde: page table page is out of range"));
3522 KASSERT(mpte->pindex == va >> PDRSHIFT,
3523 ("pmap_promote_pde: page table page's pindex is wrong"));
3524 if (pmap_insert_pt_page(pmap, mpte)) {
3525 pmap_pde_p_failures++;
3527 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3533 * Promote the pv entries.
3535 if ((newpde & PG_MANAGED) != 0)
3536 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3539 * Propagate the PAT index to its proper position.
3541 if ((newpde & PG_PTE_PAT) != 0)
3542 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3545 * Map the superpage.
3547 if (workaround_erratum383)
3548 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3549 else if (pmap == kernel_pmap)
3550 pmap_kenter_pde(va, PG_PROMOTED | PG_PS | newpde);
3552 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
3554 pmap_pde_promotions++;
3555 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3556 " in pmap %p", va, pmap);
3558 #endif /* VM_NRESERVLEVEL > 0 */
3561 * Insert the given physical page (p) at
3562 * the specified virtual address (v) in the
3563 * target physical map with the protection requested.
3565 * If specified, the page will be wired down, meaning
3566 * that the related pte can not be reclaimed.
3568 * NB: This is the only routine which MAY NOT lazy-evaluate
3569 * or lose information. That is, this routine must actually
3570 * insert this page into the given map NOW.
3573 __CONCAT(PMTYPE, enter)(pmap_t pmap, vm_offset_t va, vm_page_t m,
3574 vm_prot_t prot, u_int flags, int8_t psind)
3578 pt_entry_t newpte, origpte;
3584 va = trunc_page(va);
3585 KASSERT((pmap == kernel_pmap && va < VM_MAX_KERNEL_ADDRESS) ||
3586 (pmap != kernel_pmap && va < VM_MAXUSER_ADDRESS),
3587 ("pmap_enter: toobig k%d %#x", pmap == kernel_pmap, va));
3588 KASSERT(va < PMAP_TRM_MIN_ADDRESS,
3589 ("pmap_enter: invalid to pmap_enter into trampoline (va: 0x%x)",
3591 KASSERT(pmap != kernel_pmap || (m->oflags & VPO_UNMANAGED) != 0 ||
3592 va < kmi.clean_sva || va >= kmi.clean_eva,
3593 ("pmap_enter: managed mapping within the clean submap"));
3594 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3595 VM_OBJECT_ASSERT_LOCKED(m->object);
3596 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
3597 ("pmap_enter: flags %u has reserved bits set", flags));
3598 pa = VM_PAGE_TO_PHYS(m);
3599 newpte = (pt_entry_t)(pa | PG_A | PG_V);
3600 if ((flags & VM_PROT_WRITE) != 0)
3602 if ((prot & VM_PROT_WRITE) != 0)
3604 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
3605 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
3606 #ifdef PMAP_PAE_COMP
3607 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
3610 if ((flags & PMAP_ENTER_WIRED) != 0)
3612 if (pmap != kernel_pmap)
3614 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
3615 if ((m->oflags & VPO_UNMANAGED) == 0)
3616 newpte |= PG_MANAGED;
3618 rw_wlock(&pvh_global_lock);
3622 /* Assert the required virtual and physical alignment. */
3623 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
3624 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3625 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m);
3629 pde = pmap_pde(pmap, va);
3630 if (pmap != kernel_pmap) {
3633 * In the case that a page table page is not resident,
3634 * we are creating it here. pmap_allocpte() handles
3637 mpte = pmap_allocpte(pmap, va, flags);
3639 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3640 ("pmap_allocpte failed with sleep allowed"));
3641 rv = KERN_RESOURCE_SHORTAGE;
3646 * va is for KVA, so pmap_demote_pde() will never fail
3647 * to install a page table page. PG_V is also
3648 * asserted by pmap_demote_pde().
3651 KASSERT(pde != NULL && (*pde & PG_V) != 0,
3652 ("KVA %#x invalid pde pdir %#jx", va,
3653 (uintmax_t)pmap->pm_pdir[PTDPTDI]));
3654 if ((*pde & PG_PS) != 0)
3655 pmap_demote_pde(pmap, pde, va);
3657 pte = pmap_pte_quick(pmap, va);
3660 * Page Directory table entry is not valid, which should not
3661 * happen. We should have either allocated the page table
3662 * page or demoted the existing mapping above.
3665 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3666 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3673 * Is the specified virtual address already mapped?
3675 if ((origpte & PG_V) != 0) {
3677 * Wiring change, just update stats. We don't worry about
3678 * wiring PT pages as they remain resident as long as there
3679 * are valid mappings in them. Hence, if a user page is wired,
3680 * the PT page will be also.
3682 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
3683 pmap->pm_stats.wired_count++;
3684 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
3685 pmap->pm_stats.wired_count--;
3688 * Remove the extra PT page reference.
3692 KASSERT(mpte->wire_count > 0,
3693 ("pmap_enter: missing reference to page table page,"
3698 * Has the physical page changed?
3700 opa = origpte & PG_FRAME;
3703 * No, might be a protection or wiring change.
3705 if ((origpte & PG_MANAGED) != 0 &&
3706 (newpte & PG_RW) != 0)
3707 vm_page_aflag_set(m, PGA_WRITEABLE);
3708 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
3714 * The physical page has changed. Temporarily invalidate
3715 * the mapping. This ensures that all threads sharing the
3716 * pmap keep a consistent view of the mapping, which is
3717 * necessary for the correct handling of COW faults. It
3718 * also permits reuse of the old mapping's PV entry,
3719 * avoiding an allocation.
3721 * For consistency, handle unmanaged mappings the same way.
3723 origpte = pte_load_clear(pte);
3724 KASSERT((origpte & PG_FRAME) == opa,
3725 ("pmap_enter: unexpected pa update for %#x", va));
3726 if ((origpte & PG_MANAGED) != 0) {
3727 om = PHYS_TO_VM_PAGE(opa);
3730 * The pmap lock is sufficient to synchronize with
3731 * concurrent calls to pmap_page_test_mappings() and
3732 * pmap_ts_referenced().
3734 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3736 if ((origpte & PG_A) != 0)
3737 vm_page_aflag_set(om, PGA_REFERENCED);
3738 pv = pmap_pvh_remove(&om->md, pmap, va);
3740 ("pmap_enter: no PV entry for %#x", va));
3741 if ((newpte & PG_MANAGED) == 0)
3742 free_pv_entry(pmap, pv);
3743 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3744 TAILQ_EMPTY(&om->md.pv_list) &&
3745 ((om->flags & PG_FICTITIOUS) != 0 ||
3746 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3747 vm_page_aflag_clear(om, PGA_WRITEABLE);
3749 if ((origpte & PG_A) != 0)
3750 pmap_invalidate_page_int(pmap, va);
3754 * Increment the counters.
3756 if ((newpte & PG_W) != 0)
3757 pmap->pm_stats.wired_count++;
3758 pmap->pm_stats.resident_count++;
3762 * Enter on the PV list if part of our managed memory.
3764 if ((newpte & PG_MANAGED) != 0) {
3766 pv = get_pv_entry(pmap, FALSE);
3769 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3770 if ((newpte & PG_RW) != 0)
3771 vm_page_aflag_set(m, PGA_WRITEABLE);
3777 if ((origpte & PG_V) != 0) {
3779 origpte = pte_load_store(pte, newpte);
3780 KASSERT((origpte & PG_FRAME) == pa,
3781 ("pmap_enter: unexpected pa update for %#x", va));
3782 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
3784 if ((origpte & PG_MANAGED) != 0)
3788 * Although the PTE may still have PG_RW set, TLB
3789 * invalidation may nonetheless be required because
3790 * the PTE no longer has PG_M set.
3793 #ifdef PMAP_PAE_COMP
3794 else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
3796 * This PTE change does not require TLB invalidation.
3801 if ((origpte & PG_A) != 0)
3802 pmap_invalidate_page_int(pmap, va);
3804 pte_store(pte, newpte);
3808 #if VM_NRESERVLEVEL > 0
3810 * If both the page table page and the reservation are fully
3811 * populated, then attempt promotion.
3813 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3814 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3815 vm_reserv_level_iffullpop(m) == 0)
3816 pmap_promote_pde(pmap, pde, va);
3822 rw_wunlock(&pvh_global_lock);
3828 * Tries to create a read- and/or execute-only 2 or 4 MB page mapping. Returns
3829 * true if successful. Returns false if (1) a mapping already exists at the
3830 * specified virtual address or (2) a PV entry cannot be allocated without
3831 * reclaiming another PV entry.
3834 pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3838 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3839 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
3841 if ((m->oflags & VPO_UNMANAGED) == 0)
3842 newpde |= PG_MANAGED;
3843 #ifdef PMAP_PAE_COMP
3844 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
3847 if (pmap != kernel_pmap)
3849 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
3850 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL) ==
3855 * Tries to create the specified 2 or 4 MB page mapping. Returns KERN_SUCCESS
3856 * if the mapping was created, and either KERN_FAILURE or
3857 * KERN_RESOURCE_SHORTAGE otherwise. Returns KERN_FAILURE if
3858 * PMAP_ENTER_NOREPLACE was specified and a mapping already exists at the
3859 * specified virtual address. Returns KERN_RESOURCE_SHORTAGE if
3860 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3862 * The parameter "m" is only used when creating a managed, writeable mapping.
3865 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
3868 struct spglist free;
3869 pd_entry_t oldpde, *pde;
3872 rw_assert(&pvh_global_lock, RA_WLOCKED);
3873 KASSERT((newpde & (PG_M | PG_RW)) != PG_RW,
3874 ("pmap_enter_pde: newpde is missing PG_M"));
3875 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3876 pde = pmap_pde(pmap, va);
3878 if ((oldpde & PG_V) != 0) {
3879 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
3880 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3881 " in pmap %p", va, pmap);
3882 return (KERN_FAILURE);
3884 /* Break the existing mapping(s). */
3886 if ((oldpde & PG_PS) != 0) {
3888 * If the PDE resulted from a promotion, then a
3889 * reserved PT page could be freed.
3891 (void)pmap_remove_pde(pmap, pde, va, &free);
3892 if ((oldpde & PG_G) == 0)
3893 pmap_invalidate_pde_page(pmap, va, oldpde);
3895 if (pmap_remove_ptes(pmap, va, va + NBPDR, &free))
3896 pmap_invalidate_all_int(pmap);
3898 vm_page_free_pages_toq(&free, true);
3899 if (pmap == kernel_pmap) {
3900 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3901 if (pmap_insert_pt_page(pmap, mt)) {
3903 * XXX Currently, this can't happen because
3904 * we do not perform pmap_enter(psind == 1)
3905 * on the kernel pmap.
3907 panic("pmap_enter_pde: trie insert failed");
3910 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
3913 if ((newpde & PG_MANAGED) != 0) {
3915 * Abort this mapping if its PV entry could not be created.
3917 if (!pmap_pv_insert_pde(pmap, va, newpde, flags)) {
3918 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3919 " in pmap %p", va, pmap);
3920 return (KERN_RESOURCE_SHORTAGE);
3922 if ((newpde & PG_RW) != 0) {
3923 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
3924 vm_page_aflag_set(mt, PGA_WRITEABLE);
3929 * Increment counters.
3931 if ((newpde & PG_W) != 0)
3932 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
3933 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3936 * Map the superpage. (This is not a promoted mapping; there will not
3937 * be any lingering 4KB page mappings in the TLB.)
3939 pde_store(pde, newpde);
3941 pmap_pde_mappings++;
3942 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3943 " in pmap %p", va, pmap);
3944 return (KERN_SUCCESS);
3948 * Maps a sequence of resident pages belonging to the same object.
3949 * The sequence begins with the given page m_start. This page is
3950 * mapped at the given virtual address start. Each subsequent page is
3951 * mapped at a virtual address that is offset from start by the same
3952 * amount as the page is offset from m_start within the object. The
3953 * last page in the sequence is the page with the largest offset from
3954 * m_start that can be mapped at a virtual address less than the given
3955 * virtual address end. Not every virtual page between start and end
3956 * is mapped; only those for which a resident page exists with the
3957 * corresponding offset from m_start are mapped.
3960 __CONCAT(PMTYPE, enter_object)(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3961 vm_page_t m_start, vm_prot_t prot)
3965 vm_pindex_t diff, psize;
3967 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3969 psize = atop(end - start);
3972 rw_wlock(&pvh_global_lock);
3974 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3975 va = start + ptoa(diff);
3976 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3977 m->psind == 1 && pg_ps_enabled &&
3978 pmap_enter_4mpage(pmap, va, m, prot))
3979 m = &m[NBPDR / PAGE_SIZE - 1];
3981 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3983 m = TAILQ_NEXT(m, listq);
3985 rw_wunlock(&pvh_global_lock);
3990 * this code makes some *MAJOR* assumptions:
3991 * 1. Current pmap & pmap exists.
3994 * 4. No page table pages.
3995 * but is *MUCH* faster than pmap_enter...
3999 __CONCAT(PMTYPE, enter_quick)(pmap_t pmap, vm_offset_t va, vm_page_t m,
4003 rw_wlock(&pvh_global_lock);
4005 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
4006 rw_wunlock(&pvh_global_lock);
4011 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4012 vm_prot_t prot, vm_page_t mpte)
4014 pt_entry_t newpte, *pte;
4015 struct spglist free;
4017 KASSERT(pmap != kernel_pmap || va < kmi.clean_sva ||
4018 va >= kmi.clean_eva || (m->oflags & VPO_UNMANAGED) != 0,
4019 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4020 rw_assert(&pvh_global_lock, RA_WLOCKED);
4021 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4024 * In the case that a page table page is not
4025 * resident, we are creating it here.
4027 if (pmap != kernel_pmap) {
4032 * Calculate pagetable page index
4034 ptepindex = va >> PDRSHIFT;
4035 if (mpte && (mpte->pindex == ptepindex)) {
4039 * Get the page directory entry
4041 ptepa = pmap->pm_pdir[ptepindex];
4044 * If the page table page is mapped, we just increment
4045 * the hold count, and activate it.
4050 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
4053 mpte = _pmap_allocpte(pmap, ptepindex,
4054 PMAP_ENTER_NOSLEEP);
4064 pte = pmap_pte_quick(pmap, va);
4075 * Enter on the PV list if part of our managed memory.
4077 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4078 !pmap_try_insert_pv_entry(pmap, va, m)) {
4081 if (pmap_unwire_ptp(pmap, mpte, &free)) {
4082 pmap_invalidate_page_int(pmap, va);
4083 vm_page_free_pages_toq(&free, true);
4093 * Increment counters
4095 pmap->pm_stats.resident_count++;
4097 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
4098 pmap_cache_bits(pmap, m->md.pat_mode, 0);
4099 if ((m->oflags & VPO_UNMANAGED) == 0)
4100 newpte |= PG_MANAGED;
4101 #ifdef PMAP_PAE_COMP
4102 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
4105 if (pmap != kernel_pmap)
4107 pte_store(pte, newpte);
4113 * Make a temporary mapping for a physical address. This is only intended
4114 * to be used for panic dumps.
4117 __CONCAT(PMTYPE, kenter_temporary)(vm_paddr_t pa, int i)
4121 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
4122 pmap_kenter(va, pa);
4124 return ((void *)crashdumpmap);
4128 * This code maps large physical mmap regions into the
4129 * processor address space. Note that some shortcuts
4130 * are taken, but the code works.
4133 __CONCAT(PMTYPE, object_init_pt)(pmap_t pmap, vm_offset_t addr,
4134 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
4137 vm_paddr_t pa, ptepa;
4141 VM_OBJECT_ASSERT_WLOCKED(object);
4142 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4143 ("pmap_object_init_pt: non-device object"));
4144 if (pg_ps_enabled &&
4145 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
4146 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4148 p = vm_page_lookup(object, pindex);
4149 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4150 ("pmap_object_init_pt: invalid page %p", p));
4151 pat_mode = p->md.pat_mode;
4154 * Abort the mapping if the first page is not physically
4155 * aligned to a 2/4MB page boundary.
4157 ptepa = VM_PAGE_TO_PHYS(p);
4158 if (ptepa & (NBPDR - 1))
4162 * Skip the first page. Abort the mapping if the rest of
4163 * the pages are not physically contiguous or have differing
4164 * memory attributes.
4166 p = TAILQ_NEXT(p, listq);
4167 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4169 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4170 ("pmap_object_init_pt: invalid page %p", p));
4171 if (pa != VM_PAGE_TO_PHYS(p) ||
4172 pat_mode != p->md.pat_mode)
4174 p = TAILQ_NEXT(p, listq);
4178 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
4179 * "size" is a multiple of 2/4M, adding the PAT setting to
4180 * "pa" will not affect the termination of this loop.
4183 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
4184 pa < ptepa + size; pa += NBPDR) {
4185 pde = pmap_pde(pmap, addr);
4187 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4188 PG_U | PG_RW | PG_V);
4189 pmap->pm_stats.resident_count += NBPDR /
4191 pmap_pde_mappings++;
4193 /* Else continue on if the PDE is already valid. */
4201 * Clear the wired attribute from the mappings for the specified range of
4202 * addresses in the given pmap. Every valid mapping within that range
4203 * must have the wired attribute set. In contrast, invalid mappings
4204 * cannot have the wired attribute set, so they are ignored.
4206 * The wired attribute of the page table entry is not a hardware feature,
4207 * so there is no need to invalidate any TLB entries.
4210 __CONCAT(PMTYPE, unwire)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4215 boolean_t pv_lists_locked;
4217 if (pmap_is_current(pmap))
4218 pv_lists_locked = FALSE;
4220 pv_lists_locked = TRUE;
4222 rw_wlock(&pvh_global_lock);
4226 for (; sva < eva; sva = pdnxt) {
4227 pdnxt = (sva + NBPDR) & ~PDRMASK;
4230 pde = pmap_pde(pmap, sva);
4231 if ((*pde & PG_V) == 0)
4233 if ((*pde & PG_PS) != 0) {
4234 if ((*pde & PG_W) == 0)
4235 panic("pmap_unwire: pde %#jx is missing PG_W",
4239 * Are we unwiring the entire large page? If not,
4240 * demote the mapping and fall through.
4242 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4244 * Regardless of whether a pde (or pte) is 32
4245 * or 64 bits in size, PG_W is among the least
4246 * significant 32 bits.
4248 atomic_clear_int((u_int *)pde, PG_W);
4249 pmap->pm_stats.wired_count -= NBPDR /
4253 if (!pv_lists_locked) {
4254 pv_lists_locked = TRUE;
4255 if (!rw_try_wlock(&pvh_global_lock)) {
4262 if (!pmap_demote_pde(pmap, pde, sva))
4263 panic("pmap_unwire: demotion failed");
4268 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4270 if ((*pte & PG_V) == 0)
4272 if ((*pte & PG_W) == 0)
4273 panic("pmap_unwire: pte %#jx is missing PG_W",
4277 * PG_W must be cleared atomically. Although the pmap
4278 * lock synchronizes access to PG_W, another processor
4279 * could be setting PG_M and/or PG_A concurrently.
4281 * PG_W is among the least significant 32 bits.
4283 atomic_clear_int((u_int *)pte, PG_W);
4284 pmap->pm_stats.wired_count--;
4287 if (pv_lists_locked) {
4289 rw_wunlock(&pvh_global_lock);
4296 * Copy the range specified by src_addr/len
4297 * from the source map to the range dst_addr/len
4298 * in the destination map.
4300 * This routine is only advisory and need not do anything. Since
4301 * current pmap is always the kernel pmap when executing in
4302 * kernel, and we do not copy from the kernel pmap to a user
4303 * pmap, this optimization is not usable in 4/4G full split i386
4308 __CONCAT(PMTYPE, copy)(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
4309 vm_size_t len, vm_offset_t src_addr)
4311 struct spglist free;
4312 pt_entry_t *src_pte, *dst_pte, ptetemp;
4313 pd_entry_t srcptepaddr;
4314 vm_page_t dstmpte, srcmpte;
4315 vm_offset_t addr, end_addr, pdnxt;
4318 if (dst_addr != src_addr)
4321 end_addr = src_addr + len;
4323 rw_wlock(&pvh_global_lock);
4324 if (dst_pmap < src_pmap) {
4325 PMAP_LOCK(dst_pmap);
4326 PMAP_LOCK(src_pmap);
4328 PMAP_LOCK(src_pmap);
4329 PMAP_LOCK(dst_pmap);
4332 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4333 KASSERT(addr < PMAP_TRM_MIN_ADDRESS,
4334 ("pmap_copy: invalid to pmap_copy the trampoline"));
4336 pdnxt = (addr + NBPDR) & ~PDRMASK;
4339 ptepindex = addr >> PDRSHIFT;
4341 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4342 if (srcptepaddr == 0)
4345 if (srcptepaddr & PG_PS) {
4346 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4348 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4349 ((srcptepaddr & PG_MANAGED) == 0 ||
4350 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
4351 PMAP_ENTER_NORECLAIM))) {
4352 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4354 dst_pmap->pm_stats.resident_count +=
4356 pmap_pde_mappings++;
4361 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4362 KASSERT(srcmpte->wire_count > 0,
4363 ("pmap_copy: source page table page is unused"));
4365 if (pdnxt > end_addr)
4368 src_pte = pmap_pte_quick3(src_pmap, addr);
4369 while (addr < pdnxt) {
4372 * we only virtual copy managed pages
4374 if ((ptetemp & PG_MANAGED) != 0) {
4375 dstmpte = pmap_allocpte(dst_pmap, addr,
4376 PMAP_ENTER_NOSLEEP);
4377 if (dstmpte == NULL)
4379 dst_pte = pmap_pte_quick(dst_pmap, addr);
4380 if (*dst_pte == 0 &&
4381 pmap_try_insert_pv_entry(dst_pmap, addr,
4382 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4384 * Clear the wired, modified, and
4385 * accessed (referenced) bits
4388 *dst_pte = ptetemp & ~(PG_W | PG_M |
4390 dst_pmap->pm_stats.resident_count++;
4393 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4395 pmap_invalidate_page_int(
4397 vm_page_free_pages_toq(&free,
4402 if (dstmpte->wire_count >= srcmpte->wire_count)
4411 rw_wunlock(&pvh_global_lock);
4412 PMAP_UNLOCK(src_pmap);
4413 PMAP_UNLOCK(dst_pmap);
4417 * Zero 1 page of virtual memory mapped from a hardware page by the caller.
4419 static __inline void
4420 pagezero(void *page)
4422 #if defined(I686_CPU)
4423 if (cpu_class == CPUCLASS_686) {
4424 if (cpu_feature & CPUID_SSE2)
4425 sse2_pagezero(page);
4427 i686_pagezero(page);
4430 bzero(page, PAGE_SIZE);
4434 * Zero the specified hardware page.
4437 __CONCAT(PMTYPE, zero_page)(vm_page_t m)
4439 pt_entry_t *cmap_pte2;
4444 cmap_pte2 = pc->pc_cmap_pte2;
4445 mtx_lock(&pc->pc_cmap_lock);
4447 panic("pmap_zero_page: CMAP2 busy");
4448 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4449 pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
4450 invlcaddr(pc->pc_cmap_addr2);
4451 pagezero(pc->pc_cmap_addr2);
4455 * Unpin the thread before releasing the lock. Otherwise the thread
4456 * could be rescheduled while still bound to the current CPU, only
4457 * to unpin itself immediately upon resuming execution.
4460 mtx_unlock(&pc->pc_cmap_lock);
4464 * Zero an an area within a single hardware page. off and size must not
4465 * cover an area beyond a single hardware page.
4468 __CONCAT(PMTYPE, zero_page_area)(vm_page_t m, int off, int size)
4470 pt_entry_t *cmap_pte2;
4475 cmap_pte2 = pc->pc_cmap_pte2;
4476 mtx_lock(&pc->pc_cmap_lock);
4478 panic("pmap_zero_page_area: CMAP2 busy");
4479 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4480 pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
4481 invlcaddr(pc->pc_cmap_addr2);
4482 if (off == 0 && size == PAGE_SIZE)
4483 pagezero(pc->pc_cmap_addr2);
4485 bzero(pc->pc_cmap_addr2 + off, size);
4488 mtx_unlock(&pc->pc_cmap_lock);
4492 * Copy 1 specified hardware page to another.
4495 __CONCAT(PMTYPE, copy_page)(vm_page_t src, vm_page_t dst)
4497 pt_entry_t *cmap_pte1, *cmap_pte2;
4502 cmap_pte1 = pc->pc_cmap_pte1;
4503 cmap_pte2 = pc->pc_cmap_pte2;
4504 mtx_lock(&pc->pc_cmap_lock);
4506 panic("pmap_copy_page: CMAP1 busy");
4508 panic("pmap_copy_page: CMAP2 busy");
4509 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4510 pmap_cache_bits(kernel_pmap, src->md.pat_mode, 0);
4511 invlcaddr(pc->pc_cmap_addr1);
4512 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4513 pmap_cache_bits(kernel_pmap, dst->md.pat_mode, 0);
4514 invlcaddr(pc->pc_cmap_addr2);
4515 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE);
4519 mtx_unlock(&pc->pc_cmap_lock);
4523 __CONCAT(PMTYPE, copy_pages)(vm_page_t ma[], vm_offset_t a_offset,
4524 vm_page_t mb[], vm_offset_t b_offset, int xfersize)
4526 vm_page_t a_pg, b_pg;
4528 vm_offset_t a_pg_offset, b_pg_offset;
4529 pt_entry_t *cmap_pte1, *cmap_pte2;
4535 cmap_pte1 = pc->pc_cmap_pte1;
4536 cmap_pte2 = pc->pc_cmap_pte2;
4537 mtx_lock(&pc->pc_cmap_lock);
4538 if (*cmap_pte1 != 0)
4539 panic("pmap_copy_pages: CMAP1 busy");
4540 if (*cmap_pte2 != 0)
4541 panic("pmap_copy_pages: CMAP2 busy");
4542 while (xfersize > 0) {
4543 a_pg = ma[a_offset >> PAGE_SHIFT];
4544 a_pg_offset = a_offset & PAGE_MASK;
4545 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4546 b_pg = mb[b_offset >> PAGE_SHIFT];
4547 b_pg_offset = b_offset & PAGE_MASK;
4548 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4549 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4550 pmap_cache_bits(kernel_pmap, a_pg->md.pat_mode, 0);
4551 invlcaddr(pc->pc_cmap_addr1);
4552 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4553 PG_M | pmap_cache_bits(kernel_pmap, b_pg->md.pat_mode, 0);
4554 invlcaddr(pc->pc_cmap_addr2);
4555 a_cp = pc->pc_cmap_addr1 + a_pg_offset;
4556 b_cp = pc->pc_cmap_addr2 + b_pg_offset;
4557 bcopy(a_cp, b_cp, cnt);
4565 mtx_unlock(&pc->pc_cmap_lock);
4569 * Returns true if the pmap's pv is one of the first
4570 * 16 pvs linked to from this page. This count may
4571 * be changed upwards or downwards in the future; it
4572 * is only necessary that true be returned for a small
4573 * subset of pmaps for proper page aging.
4576 __CONCAT(PMTYPE, page_exists_quick)(pmap_t pmap, vm_page_t m)
4578 struct md_page *pvh;
4583 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4584 ("pmap_page_exists_quick: page %p is not managed", m));
4586 rw_wlock(&pvh_global_lock);
4587 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4588 if (PV_PMAP(pv) == pmap) {
4596 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4597 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4598 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4599 if (PV_PMAP(pv) == pmap) {
4608 rw_wunlock(&pvh_global_lock);
4613 * pmap_page_wired_mappings:
4615 * Return the number of managed mappings to the given physical page
4619 __CONCAT(PMTYPE, page_wired_mappings)(vm_page_t m)
4624 if ((m->oflags & VPO_UNMANAGED) != 0)
4626 rw_wlock(&pvh_global_lock);
4627 count = pmap_pvh_wired_mappings(&m->md, count);
4628 if ((m->flags & PG_FICTITIOUS) == 0) {
4629 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4632 rw_wunlock(&pvh_global_lock);
4637 * pmap_pvh_wired_mappings:
4639 * Return the updated number "count" of managed mappings that are wired.
4642 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4648 rw_assert(&pvh_global_lock, RA_WLOCKED);
4650 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4653 pte = pmap_pte_quick(pmap, pv->pv_va);
4654 if ((*pte & PG_W) != 0)
4663 * Returns TRUE if the given page is mapped individually or as part of
4664 * a 4mpage. Otherwise, returns FALSE.
4667 __CONCAT(PMTYPE, page_is_mapped)(vm_page_t m)
4671 if ((m->oflags & VPO_UNMANAGED) != 0)
4673 rw_wlock(&pvh_global_lock);
4674 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4675 ((m->flags & PG_FICTITIOUS) == 0 &&
4676 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4677 rw_wunlock(&pvh_global_lock);
4682 * Remove all pages from specified address space
4683 * this aids process exit speeds. Also, this code
4684 * is special cased for current process only, but
4685 * can have the more generic (and slightly slower)
4686 * mode enabled. This is much faster than pmap_remove
4687 * in the case of running down an entire address space.
4690 __CONCAT(PMTYPE, remove_pages)(pmap_t pmap)
4692 pt_entry_t *pte, tpte;
4693 vm_page_t m, mpte, mt;
4695 struct md_page *pvh;
4696 struct pv_chunk *pc, *npc;
4697 struct spglist free;
4700 uint32_t inuse, bitmask;
4703 if (pmap != PCPU_GET(curpmap)) {
4704 printf("warning: pmap_remove_pages called with non-current pmap\n");
4708 rw_wlock(&pvh_global_lock);
4711 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4712 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4715 for (field = 0; field < _NPCM; field++) {
4716 inuse = ~pc->pc_map[field] & pc_freemask[field];
4717 while (inuse != 0) {
4719 bitmask = 1UL << bit;
4720 idx = field * 32 + bit;
4721 pv = &pc->pc_pventry[idx];
4724 pte = pmap_pde(pmap, pv->pv_va);
4726 if ((tpte & PG_PS) == 0) {
4727 pte = pmap_pte_quick(pmap, pv->pv_va);
4728 tpte = *pte & ~PG_PTE_PAT;
4733 "TPTE at %p IS ZERO @ VA %08x\n",
4739 * We cannot remove wired pages from a process' mapping at this time
4746 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4747 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4748 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4749 m, (uintmax_t)m->phys_addr,
4752 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4753 m < &vm_page_array[vm_page_array_size],
4754 ("pmap_remove_pages: bad tpte %#jx",
4760 * Update the vm_page_t clean/reference bits.
4762 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4763 if ((tpte & PG_PS) != 0) {
4764 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4771 PV_STAT(pv_entry_frees++);
4772 PV_STAT(pv_entry_spare++);
4774 pc->pc_map[field] |= bitmask;
4775 if ((tpte & PG_PS) != 0) {
4776 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4777 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4778 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4779 if (TAILQ_EMPTY(&pvh->pv_list)) {
4780 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4781 if (TAILQ_EMPTY(&mt->md.pv_list))
4782 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4784 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
4786 pmap->pm_stats.resident_count--;
4787 KASSERT(mpte->wire_count == NPTEPG,
4788 ("pmap_remove_pages: pte page wire count error"));
4789 mpte->wire_count = 0;
4790 pmap_add_delayed_free_list(mpte, &free, FALSE);
4793 pmap->pm_stats.resident_count--;
4794 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4795 if (TAILQ_EMPTY(&m->md.pv_list) &&
4796 (m->flags & PG_FICTITIOUS) == 0) {
4797 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4798 if (TAILQ_EMPTY(&pvh->pv_list))
4799 vm_page_aflag_clear(m, PGA_WRITEABLE);
4801 pmap_unuse_pt(pmap, pv->pv_va, &free);
4806 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4811 pmap_invalidate_all_int(pmap);
4812 rw_wunlock(&pvh_global_lock);
4814 vm_page_free_pages_toq(&free, true);
4820 * Return whether or not the specified physical page was modified
4821 * in any physical maps.
4824 __CONCAT(PMTYPE, is_modified)(vm_page_t m)
4828 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4829 ("pmap_is_modified: page %p is not managed", m));
4832 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4833 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4834 * is clear, no PTEs can have PG_M set.
4836 VM_OBJECT_ASSERT_WLOCKED(m->object);
4837 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4839 rw_wlock(&pvh_global_lock);
4840 rv = pmap_is_modified_pvh(&m->md) ||
4841 ((m->flags & PG_FICTITIOUS) == 0 &&
4842 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4843 rw_wunlock(&pvh_global_lock);
4848 * Returns TRUE if any of the given mappings were used to modify
4849 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4850 * mappings are supported.
4853 pmap_is_modified_pvh(struct md_page *pvh)
4860 rw_assert(&pvh_global_lock, RA_WLOCKED);
4863 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4866 pte = pmap_pte_quick(pmap, pv->pv_va);
4867 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4877 * pmap_is_prefaultable:
4879 * Return whether or not the specified virtual address is elgible
4883 __CONCAT(PMTYPE, is_prefaultable)(pmap_t pmap, vm_offset_t addr)
4890 pde = *pmap_pde(pmap, addr);
4891 if (pde != 0 && (pde & PG_PS) == 0)
4892 rv = pmap_pte_ufast(pmap, addr, pde) == 0;
4898 * pmap_is_referenced:
4900 * Return whether or not the specified physical page was referenced
4901 * in any physical maps.
4904 __CONCAT(PMTYPE, is_referenced)(vm_page_t m)
4908 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4909 ("pmap_is_referenced: page %p is not managed", m));
4910 rw_wlock(&pvh_global_lock);
4911 rv = pmap_is_referenced_pvh(&m->md) ||
4912 ((m->flags & PG_FICTITIOUS) == 0 &&
4913 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4914 rw_wunlock(&pvh_global_lock);
4919 * Returns TRUE if any of the given mappings were referenced and FALSE
4920 * otherwise. Both page and 4mpage mappings are supported.
4923 pmap_is_referenced_pvh(struct md_page *pvh)
4930 rw_assert(&pvh_global_lock, RA_WLOCKED);
4933 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4936 pte = pmap_pte_quick(pmap, pv->pv_va);
4937 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4947 * Clear the write and modified bits in each of the given page's mappings.
4950 __CONCAT(PMTYPE, remove_write)(vm_page_t m)
4952 struct md_page *pvh;
4953 pv_entry_t next_pv, pv;
4956 pt_entry_t oldpte, *pte;
4959 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4960 ("pmap_remove_write: page %p is not managed", m));
4963 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4964 * set by another thread while the object is locked. Thus,
4965 * if PGA_WRITEABLE is clear, no page table entries need updating.
4967 VM_OBJECT_ASSERT_WLOCKED(m->object);
4968 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4970 rw_wlock(&pvh_global_lock);
4972 if ((m->flags & PG_FICTITIOUS) != 0)
4973 goto small_mappings;
4974 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4975 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4979 pde = pmap_pde(pmap, va);
4980 if ((*pde & PG_RW) != 0)
4981 (void)pmap_demote_pde(pmap, pde, va);
4985 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4988 pde = pmap_pde(pmap, pv->pv_va);
4989 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
4990 " a 4mpage in page %p's pv list", m));
4991 pte = pmap_pte_quick(pmap, pv->pv_va);
4994 if ((oldpte & PG_RW) != 0) {
4996 * Regardless of whether a pte is 32 or 64 bits
4997 * in size, PG_RW and PG_M are among the least
4998 * significant 32 bits.
5000 if (!atomic_cmpset_int((u_int *)pte, oldpte,
5001 oldpte & ~(PG_RW | PG_M)))
5003 if ((oldpte & PG_M) != 0)
5005 pmap_invalidate_page_int(pmap, pv->pv_va);
5009 vm_page_aflag_clear(m, PGA_WRITEABLE);
5011 rw_wunlock(&pvh_global_lock);
5015 * pmap_ts_referenced:
5017 * Return a count of reference bits for a page, clearing those bits.
5018 * It is not necessary for every reference bit to be cleared, but it
5019 * is necessary that 0 only be returned when there are truly no
5020 * reference bits set.
5022 * As an optimization, update the page's dirty field if a modified bit is
5023 * found while counting reference bits. This opportunistic update can be
5024 * performed at low cost and can eliminate the need for some future calls
5025 * to pmap_is_modified(). However, since this function stops after
5026 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5027 * dirty pages. Those dirty pages will only be detected by a future call
5028 * to pmap_is_modified().
5031 __CONCAT(PMTYPE, ts_referenced)(vm_page_t m)
5033 struct md_page *pvh;
5041 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5042 ("pmap_ts_referenced: page %p is not managed", m));
5043 pa = VM_PAGE_TO_PHYS(m);
5044 pvh = pa_to_pvh(pa);
5045 rw_wlock(&pvh_global_lock);
5047 if ((m->flags & PG_FICTITIOUS) != 0 ||
5048 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5049 goto small_mappings;
5054 pde = pmap_pde(pmap, pv->pv_va);
5055 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5057 * Although "*pde" is mapping a 2/4MB page, because
5058 * this function is called at a 4KB page granularity,
5059 * we only update the 4KB page under test.
5063 if ((*pde & PG_A) != 0) {
5065 * Since this reference bit is shared by either 1024
5066 * or 512 4KB pages, it should not be cleared every
5067 * time it is tested. Apply a simple "hash" function
5068 * on the physical page number, the virtual superpage
5069 * number, and the pmap address to select one 4KB page
5070 * out of the 1024 or 512 on which testing the
5071 * reference bit will result in clearing that bit.
5072 * This function is designed to avoid the selection of
5073 * the same 4KB page for every 2- or 4MB page mapping.
5075 * On demotion, a mapping that hasn't been referenced
5076 * is simply destroyed. To avoid the possibility of a
5077 * subsequent page fault on a demoted wired mapping,
5078 * always leave its reference bit set. Moreover,
5079 * since the superpage is wired, the current state of
5080 * its reference bit won't affect page replacement.
5082 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
5083 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
5084 (*pde & PG_W) == 0) {
5085 atomic_clear_int((u_int *)pde, PG_A);
5086 pmap_invalidate_page_int(pmap, pv->pv_va);
5091 /* Rotate the PV list if it has more than one entry. */
5092 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5093 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5094 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5096 if (rtval >= PMAP_TS_REFERENCED_MAX)
5098 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5100 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5106 pde = pmap_pde(pmap, pv->pv_va);
5107 KASSERT((*pde & PG_PS) == 0,
5108 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
5110 pte = pmap_pte_quick(pmap, pv->pv_va);
5111 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5113 if ((*pte & PG_A) != 0) {
5114 atomic_clear_int((u_int *)pte, PG_A);
5115 pmap_invalidate_page_int(pmap, pv->pv_va);
5119 /* Rotate the PV list if it has more than one entry. */
5120 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5121 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5122 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5124 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
5125 PMAP_TS_REFERENCED_MAX);
5128 rw_wunlock(&pvh_global_lock);
5133 * Apply the given advice to the specified range of addresses within the
5134 * given pmap. Depending on the advice, clear the referenced and/or
5135 * modified flags in each mapping and set the mapped page's dirty field.
5138 __CONCAT(PMTYPE, advise)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
5141 pd_entry_t oldpde, *pde;
5143 vm_offset_t va, pdnxt;
5145 boolean_t anychanged, pv_lists_locked;
5147 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5149 if (pmap_is_current(pmap))
5150 pv_lists_locked = FALSE;
5152 pv_lists_locked = TRUE;
5154 rw_wlock(&pvh_global_lock);
5159 for (; sva < eva; sva = pdnxt) {
5160 pdnxt = (sva + NBPDR) & ~PDRMASK;
5163 pde = pmap_pde(pmap, sva);
5165 if ((oldpde & PG_V) == 0)
5167 else if ((oldpde & PG_PS) != 0) {
5168 if ((oldpde & PG_MANAGED) == 0)
5170 if (!pv_lists_locked) {
5171 pv_lists_locked = TRUE;
5172 if (!rw_try_wlock(&pvh_global_lock)) {
5174 pmap_invalidate_all_int(pmap);
5180 if (!pmap_demote_pde(pmap, pde, sva)) {
5182 * The large page mapping was destroyed.
5188 * Unless the page mappings are wired, remove the
5189 * mapping to a single page so that a subsequent
5190 * access may repromote. Since the underlying page
5191 * table page is fully populated, this removal never
5192 * frees a page table page.
5194 if ((oldpde & PG_W) == 0) {
5195 pte = pmap_pte_quick(pmap, sva);
5196 KASSERT((*pte & PG_V) != 0,
5197 ("pmap_advise: invalid PTE"));
5198 pmap_remove_pte(pmap, pte, sva, NULL);
5205 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
5207 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
5209 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5210 if (advice == MADV_DONTNEED) {
5212 * Future calls to pmap_is_modified()
5213 * can be avoided by making the page
5216 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
5219 atomic_clear_int((u_int *)pte, PG_M | PG_A);
5220 } else if ((*pte & PG_A) != 0)
5221 atomic_clear_int((u_int *)pte, PG_A);
5224 if ((*pte & PG_G) != 0) {
5232 pmap_invalidate_range_int(pmap, va, sva);
5237 pmap_invalidate_range_int(pmap, va, sva);
5240 pmap_invalidate_all_int(pmap);
5241 if (pv_lists_locked) {
5243 rw_wunlock(&pvh_global_lock);
5249 * Clear the modify bits on the specified physical page.
5252 __CONCAT(PMTYPE, clear_modify)(vm_page_t m)
5254 struct md_page *pvh;
5255 pv_entry_t next_pv, pv;
5257 pd_entry_t oldpde, *pde;
5258 pt_entry_t oldpte, *pte;
5261 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5262 ("pmap_clear_modify: page %p is not managed", m));
5263 VM_OBJECT_ASSERT_WLOCKED(m->object);
5264 KASSERT(!vm_page_xbusied(m),
5265 ("pmap_clear_modify: page %p is exclusive busied", m));
5268 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5269 * If the object containing the page is locked and the page is not
5270 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5272 if ((m->aflags & PGA_WRITEABLE) == 0)
5274 rw_wlock(&pvh_global_lock);
5276 if ((m->flags & PG_FICTITIOUS) != 0)
5277 goto small_mappings;
5278 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5279 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5283 pde = pmap_pde(pmap, va);
5285 if ((oldpde & PG_RW) != 0) {
5286 if (pmap_demote_pde(pmap, pde, va)) {
5287 if ((oldpde & PG_W) == 0) {
5289 * Write protect the mapping to a
5290 * single page so that a subsequent
5291 * write access may repromote.
5293 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5295 pte = pmap_pte_quick(pmap, va);
5297 if ((oldpte & PG_V) != 0) {
5299 * Regardless of whether a pte is 32 or 64 bits
5300 * in size, PG_RW and PG_M are among the least
5301 * significant 32 bits.
5303 while (!atomic_cmpset_int((u_int *)pte,
5305 oldpte & ~(PG_M | PG_RW)))
5308 pmap_invalidate_page_int(pmap,
5317 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5320 pde = pmap_pde(pmap, pv->pv_va);
5321 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5322 " a 4mpage in page %p's pv list", m));
5323 pte = pmap_pte_quick(pmap, pv->pv_va);
5324 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5326 * Regardless of whether a pte is 32 or 64 bits
5327 * in size, PG_M is among the least significant
5330 atomic_clear_int((u_int *)pte, PG_M);
5331 pmap_invalidate_page_int(pmap, pv->pv_va);
5336 rw_wunlock(&pvh_global_lock);
5340 * Miscellaneous support routines follow
5343 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5344 static __inline void
5345 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5350 * The cache mode bits are all in the low 32-bits of the
5351 * PTE, so we can just spin on updating the low 32-bits.
5354 opte = *(u_int *)pte;
5355 npte = opte & ~PG_PTE_CACHE;
5357 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5360 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5361 static __inline void
5362 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5367 * The cache mode bits are all in the low 32-bits of the
5368 * PDE, so we can just spin on updating the low 32-bits.
5371 opde = *(u_int *)pde;
5372 npde = opde & ~PG_PDE_CACHE;
5374 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5378 * Map a set of physical memory pages into the kernel virtual
5379 * address space. Return a pointer to where it is mapped. This
5380 * routine is intended to be used for mapping device memory,
5384 __CONCAT(PMTYPE, mapdev_attr)(vm_paddr_t pa, vm_size_t size, int mode)
5386 struct pmap_preinit_mapping *ppim;
5387 vm_offset_t va, offset;
5391 offset = pa & PAGE_MASK;
5392 size = round_page(offset + size);
5395 if (pa < PMAP_MAP_LOW && pa + size <= PMAP_MAP_LOW)
5396 va = pa + PMAP_MAP_LOW;
5397 else if (!pmap_initialized) {
5399 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5400 ppim = pmap_preinit_mapping + i;
5401 if (ppim->va == 0) {
5405 ppim->va = virtual_avail;
5406 virtual_avail += size;
5412 panic("%s: too many preinit mappings", __func__);
5415 * If we have a preinit mapping, re-use it.
5417 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5418 ppim = pmap_preinit_mapping + i;
5419 if (ppim->pa == pa && ppim->sz == size &&
5421 return ((void *)(ppim->va + offset));
5423 va = kva_alloc(size);
5425 panic("%s: Couldn't allocate KVA", __func__);
5427 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5428 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5429 pmap_invalidate_range_int(kernel_pmap, va, va + tmpsize);
5430 pmap_invalidate_cache_range(va, va + size);
5431 return ((void *)(va + offset));
5435 __CONCAT(PMTYPE, unmapdev)(vm_offset_t va, vm_size_t size)
5437 struct pmap_preinit_mapping *ppim;
5441 if (va >= PMAP_MAP_LOW && va <= KERNBASE && va + size <= KERNBASE)
5443 offset = va & PAGE_MASK;
5444 size = round_page(offset + size);
5445 va = trunc_page(va);
5446 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5447 ppim = pmap_preinit_mapping + i;
5448 if (ppim->va == va && ppim->sz == size) {
5449 if (pmap_initialized)
5455 if (va + size == virtual_avail)
5460 if (pmap_initialized)
5465 * Sets the memory attribute for the specified page.
5468 __CONCAT(PMTYPE, page_set_memattr)(vm_page_t m, vm_memattr_t ma)
5471 m->md.pat_mode = ma;
5472 if ((m->flags & PG_FICTITIOUS) != 0)
5476 * If "m" is a normal page, flush it from the cache.
5477 * See pmap_invalidate_cache_range().
5479 * First, try to find an existing mapping of the page by sf
5480 * buffer. sf_buf_invalidate_cache() modifies mapping and
5481 * flushes the cache.
5483 if (sf_buf_invalidate_cache(m))
5487 * If page is not mapped by sf buffer, but CPU does not
5488 * support self snoop, map the page transient and do
5489 * invalidation. In the worst case, whole cache is flushed by
5490 * pmap_invalidate_cache_range().
5492 if ((cpu_feature & CPUID_SS) == 0)
5497 __CONCAT(PMTYPE, flush_page)(vm_page_t m)
5499 pt_entry_t *cmap_pte2;
5501 vm_offset_t sva, eva;
5504 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5505 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5508 cmap_pte2 = pc->pc_cmap_pte2;
5509 mtx_lock(&pc->pc_cmap_lock);
5511 panic("pmap_flush_page: CMAP2 busy");
5512 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5513 PG_A | PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode,
5515 invlcaddr(pc->pc_cmap_addr2);
5516 sva = (vm_offset_t)pc->pc_cmap_addr2;
5517 eva = sva + PAGE_SIZE;
5520 * Use mfence or sfence despite the ordering implied by
5521 * mtx_{un,}lock() because clflush on non-Intel CPUs
5522 * and clflushopt are not guaranteed to be ordered by
5523 * any other instruction.
5527 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5529 for (; sva < eva; sva += cpu_clflush_line_size) {
5537 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5541 mtx_unlock(&pc->pc_cmap_lock);
5543 pmap_invalidate_cache();
5547 * Changes the specified virtual address range's memory type to that given by
5548 * the parameter "mode". The specified virtual address range must be
5549 * completely contained within either the kernel map.
5551 * Returns zero if the change completed successfully, and either EINVAL or
5552 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5553 * of the virtual address range was not mapped, and ENOMEM is returned if
5554 * there was insufficient memory available to complete the change.
5557 __CONCAT(PMTYPE, change_attr)(vm_offset_t va, vm_size_t size, int mode)
5559 vm_offset_t base, offset, tmpva;
5562 int cache_bits_pte, cache_bits_pde;
5565 base = trunc_page(va);
5566 offset = va & PAGE_MASK;
5567 size = round_page(offset + size);
5570 * Only supported on kernel virtual addresses above the recursive map.
5572 if (base < VM_MIN_KERNEL_ADDRESS)
5575 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
5576 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
5580 * Pages that aren't mapped aren't supported. Also break down
5581 * 2/4MB pages into 4KB pages if required.
5583 PMAP_LOCK(kernel_pmap);
5584 for (tmpva = base; tmpva < base + size; ) {
5585 pde = pmap_pde(kernel_pmap, tmpva);
5587 PMAP_UNLOCK(kernel_pmap);
5592 * If the current 2/4MB page already has
5593 * the required memory type, then we need not
5594 * demote this page. Just increment tmpva to
5595 * the next 2/4MB page frame.
5597 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5598 tmpva = trunc_4mpage(tmpva) + NBPDR;
5603 * If the current offset aligns with a 2/4MB
5604 * page frame and there is at least 2/4MB left
5605 * within the range, then we need not break
5606 * down this page into 4KB pages.
5608 if ((tmpva & PDRMASK) == 0 &&
5609 tmpva + PDRMASK < base + size) {
5613 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5614 PMAP_UNLOCK(kernel_pmap);
5618 pte = vtopte(tmpva);
5620 PMAP_UNLOCK(kernel_pmap);
5625 PMAP_UNLOCK(kernel_pmap);
5628 * Ok, all the pages exist, so run through them updating their
5629 * cache mode if required.
5631 for (tmpva = base; tmpva < base + size; ) {
5632 pde = pmap_pde(kernel_pmap, tmpva);
5634 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5635 pmap_pde_attr(pde, cache_bits_pde);
5638 tmpva = trunc_4mpage(tmpva) + NBPDR;
5640 pte = vtopte(tmpva);
5641 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5642 pmap_pte_attr(pte, cache_bits_pte);
5650 * Flush CPU caches to make sure any data isn't cached that
5651 * shouldn't be, etc.
5654 pmap_invalidate_range_int(kernel_pmap, base, tmpva);
5655 pmap_invalidate_cache_range(base, tmpva);
5661 * perform the pmap work for mincore
5664 __CONCAT(PMTYPE, mincore)(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5673 pde = *pmap_pde(pmap, addr);
5675 if ((pde & PG_PS) != 0) {
5677 /* Compute the physical address of the 4KB page. */
5678 pa = ((pde & PG_PS_FRAME) | (addr & PDRMASK)) &
5680 val = MINCORE_SUPER;
5682 pte = pmap_pte_ufast(pmap, addr, pde);
5683 pa = pte & PG_FRAME;
5691 if ((pte & PG_V) != 0) {
5692 val |= MINCORE_INCORE;
5693 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5694 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5695 if ((pte & PG_A) != 0)
5696 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5698 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5699 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5700 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5701 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5702 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5705 PA_UNLOCK_COND(*locked_pa);
5711 __CONCAT(PMTYPE, activate)(struct thread *td)
5713 pmap_t pmap, oldpmap;
5718 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5719 oldpmap = PCPU_GET(curpmap);
5720 cpuid = PCPU_GET(cpuid);
5722 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5723 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5725 CPU_CLR(cpuid, &oldpmap->pm_active);
5726 CPU_SET(cpuid, &pmap->pm_active);
5728 #ifdef PMAP_PAE_COMP
5729 cr3 = vtophys(pmap->pm_pdpt);
5731 cr3 = vtophys(pmap->pm_pdir);
5734 * pmap_activate is for the current thread on the current cpu
5736 td->td_pcb->pcb_cr3 = cr3;
5737 PCPU_SET(curpmap, pmap);
5742 __CONCAT(PMTYPE, activate_boot)(pmap_t pmap)
5746 cpuid = PCPU_GET(cpuid);
5748 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5750 CPU_SET(cpuid, &pmap->pm_active);
5752 PCPU_SET(curpmap, pmap);
5756 * Increase the starting virtual address of the given mapping if a
5757 * different alignment might result in more superpage mappings.
5760 __CONCAT(PMTYPE, align_superpage)(vm_object_t object, vm_ooffset_t offset,
5761 vm_offset_t *addr, vm_size_t size)
5763 vm_offset_t superpage_offset;
5767 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5768 offset += ptoa(object->pg_color);
5769 superpage_offset = offset & PDRMASK;
5770 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5771 (*addr & PDRMASK) == superpage_offset)
5773 if ((*addr & PDRMASK) < superpage_offset)
5774 *addr = (*addr & ~PDRMASK) + superpage_offset;
5776 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5780 __CONCAT(PMTYPE, quick_enter_page)(vm_page_t m)
5786 qaddr = PCPU_GET(qmap_addr);
5787 pte = vtopte(qaddr);
5790 ("pmap_quick_enter_page: PTE busy %#jx", (uintmax_t)*pte));
5791 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5792 pmap_cache_bits(kernel_pmap, pmap_page_get_memattr(m), 0);
5799 __CONCAT(PMTYPE, quick_remove_page)(vm_offset_t addr)
5804 qaddr = PCPU_GET(qmap_addr);
5805 pte = vtopte(qaddr);
5807 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5808 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5814 static vmem_t *pmap_trm_arena;
5815 static vmem_addr_t pmap_trm_arena_last = PMAP_TRM_MIN_ADDRESS;
5816 static int trm_guard = PAGE_SIZE;
5819 pmap_trm_import(void *unused __unused, vmem_size_t size, int flags,
5823 vmem_addr_t af, addr, prev_addr;
5824 pt_entry_t *trm_pte;
5826 prev_addr = atomic_load_long(&pmap_trm_arena_last);
5827 size = round_page(size) + trm_guard;
5829 if (prev_addr + size < prev_addr || prev_addr + size < size ||
5830 prev_addr + size > PMAP_TRM_MAX_ADDRESS)
5832 addr = prev_addr + size;
5833 if (atomic_fcmpset_int(&pmap_trm_arena_last, &prev_addr, addr))
5836 prev_addr += trm_guard;
5837 trm_pte = PTmap + atop(prev_addr);
5838 for (af = prev_addr; af < addr; af += PAGE_SIZE) {
5839 m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5840 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
5841 pte_store(&trm_pte[atop(af - prev_addr)], VM_PAGE_TO_PHYS(m) |
5842 PG_M | PG_A | PG_RW | PG_V | pgeflag |
5843 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE));
5854 TUNABLE_INT_FETCH("machdep.trm_guard", &trm_guard);
5855 if ((trm_guard & PAGE_MASK) != 0)
5857 pmap_trm_arena = vmem_create("i386trampoline", 0, 0, 1, 0, M_WAITOK);
5858 vmem_set_import(pmap_trm_arena, pmap_trm_import, NULL, NULL, PAGE_SIZE);
5859 pd_m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5860 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK | VM_ALLOC_ZERO);
5861 if ((pd_m->flags & PG_ZERO) == 0)
5862 pmap_zero_page(pd_m);
5863 PTD[TRPTDI] = VM_PAGE_TO_PHYS(pd_m) | PG_M | PG_A | PG_RW | PG_V |
5864 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, TRUE);
5868 __CONCAT(PMTYPE, trm_alloc)(size_t size, int flags)
5873 MPASS((flags & ~(M_WAITOK | M_NOWAIT | M_ZERO)) == 0);
5874 error = vmem_xalloc(pmap_trm_arena, roundup2(size, 4), sizeof(int),
5875 0, 0, VMEM_ADDR_MIN, VMEM_ADDR_MAX, flags | M_FIRSTFIT, &res);
5878 if ((flags & M_ZERO) != 0)
5879 bzero((void *)res, size);
5880 return ((void *)res);
5884 __CONCAT(PMTYPE, trm_free)(void *addr, size_t size)
5887 vmem_free(pmap_trm_arena, (uintptr_t)addr, roundup2(size, 4));
5890 #if defined(PMAP_DEBUG)
5891 pmap_pid_dump(int pid)
5898 sx_slock(&allproc_lock);
5899 FOREACH_PROC_IN_SYSTEM(p) {
5900 if (p->p_pid != pid)
5906 pmap = vmspace_pmap(p->p_vmspace);
5907 for (i = 0; i < NPDEPTD; i++) {
5910 vm_offset_t base = i << PDRSHIFT;
5912 pde = &pmap->pm_pdir[i];
5913 if (pde && pmap_pde_v(pde)) {
5914 for (j = 0; j < NPTEPG; j++) {
5915 vm_offset_t va = base + (j << PAGE_SHIFT);
5916 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5921 sx_sunlock(&allproc_lock);
5924 pte = pmap_pte(pmap, va);
5925 if (pte && pmap_pte_v(pte)) {
5929 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5930 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5931 va, pa, m->hold_count, m->wire_count, m->flags);
5946 sx_sunlock(&allproc_lock);
5952 __CONCAT(PMTYPE, ksetrw)(vm_offset_t va)
5955 *vtopte(va) |= PG_RW;
5959 __CONCAT(PMTYPE, remap_lowptdi)(bool enable)
5962 PTD[KPTDI] = enable ? PTD[LOWPTDI] : 0;
5967 __CONCAT(PMTYPE, get_map_low)(void)
5970 return (PMAP_MAP_LOW);
5974 __CONCAT(PMTYPE, get_vm_maxuser_address)(void)
5977 return (VM_MAXUSER_ADDRESS);
5981 __CONCAT(PMTYPE, pg_frame)(vm_paddr_t pa)
5984 return (pa & PG_FRAME);
5988 __CONCAT(PMTYPE, sf_buf_map)(struct sf_buf *sf)
5990 pt_entry_t opte, *ptep;
5993 * Update the sf_buf's virtual-to-physical mapping, flushing the
5994 * virtual address from the TLB. Since the reference count for
5995 * the sf_buf's old mapping was zero, that mapping is not
5996 * currently in use. Consequently, there is no need to exchange
5997 * the old and new PTEs atomically, even under PAE.
5999 ptep = vtopte(sf->kva);
6001 *ptep = VM_PAGE_TO_PHYS(sf->m) | PG_RW | PG_V |
6002 pmap_cache_bits(kernel_pmap, sf->m->md.pat_mode, 0);
6005 * Avoid unnecessary TLB invalidations: If the sf_buf's old
6006 * virtual-to-physical mapping was not used, then any processor
6007 * that has invalidated the sf_buf's virtual address from its TLB
6008 * since the last used mapping need not invalidate again.
6011 if ((opte & (PG_V | PG_A)) == (PG_V | PG_A))
6012 CPU_ZERO(&sf->cpumask);
6014 if ((opte & (PG_V | PG_A)) == (PG_V | PG_A))
6015 pmap_invalidate_page_int(kernel_pmap, sf->kva);
6020 __CONCAT(PMTYPE, cp_slow0_map)(vm_offset_t kaddr, int plen, vm_page_t *ma)
6025 for (i = 0, pte = vtopte(kaddr); i < plen; i++, pte++) {
6026 *pte = PG_V | PG_RW | PG_A | PG_M | VM_PAGE_TO_PHYS(ma[i]) |
6027 pmap_cache_bits(kernel_pmap, pmap_page_get_memattr(ma[i]),
6029 invlpg(kaddr + ptoa(i));
6034 __CONCAT(PMTYPE, get_kcr3)(void)
6037 #ifdef PMAP_PAE_COMP
6038 return ((u_int)IdlePDPT);
6040 return ((u_int)IdlePTD);
6045 __CONCAT(PMTYPE, get_cr3)(pmap_t pmap)
6048 #ifdef PMAP_PAE_COMP
6049 return ((u_int)vtophys(pmap->pm_pdpt));
6051 return ((u_int)vtophys(pmap->pm_pdir));
6056 __CONCAT(PMTYPE, cmap3)(vm_paddr_t pa, u_int pte_bits)
6061 *pte = pa | pte_bits;
6067 __CONCAT(PMTYPE, basemem_setup)(u_int basemem)
6073 * Map pages between basemem and ISA_HOLE_START, if any, r/w into
6074 * the vm86 page table so that vm86 can scribble on them using
6075 * the vm86 map too. XXX: why 2 ways for this and only 1 way for
6076 * page 0, at least as initialized here?
6078 pte = (pt_entry_t *)vm86paddr;
6079 for (i = basemem / 4; i < 160; i++)
6080 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
6083 struct bios16_pmap_handle {
6086 pt_entry_t orig_ptd;
6090 __CONCAT(PMTYPE, bios16_enter)(void)
6092 struct bios16_pmap_handle *h;
6095 * no page table, so create one and install it.
6097 h = malloc(sizeof(struct bios16_pmap_handle), M_TEMP, M_WAITOK);
6098 h->pte = (pt_entry_t *)malloc(PAGE_SIZE, M_TEMP, M_WAITOK);
6100 *h->pte = vm86phystk | PG_RW | PG_V;
6101 h->orig_ptd = *h->ptd;
6102 *h->ptd = vtophys(h->pte) | PG_RW | PG_V;
6103 pmap_invalidate_all_int(kernel_pmap); /* XXX insurance for now */
6108 __CONCAT(PMTYPE, bios16_leave)(void *arg)
6110 struct bios16_pmap_handle *h;
6113 *h->ptd = h->orig_ptd; /* remove page table */
6115 * XXX only needs to be invlpg(0) but that doesn't work on the 386
6117 pmap_invalidate_all_int(kernel_pmap);
6118 free(h->pte, M_TEMP); /* ... and free it */
6122 .pm_##a = __CONCAT(PMTYPE, a),
6124 struct pmap_methods __CONCAT(PMTYPE, methods) = {
6128 PMM(align_superpage)
6129 PMM(quick_enter_page)
6130 PMM(quick_remove_page)
6134 PMM(get_vm_maxuser_address)
6147 PMM(is_valid_memattr)
6166 PMM(kenter_temporary)
6169 PMM(page_exists_quick)
6170 PMM(page_wired_mappings)
6174 PMM(is_prefaultable)
6180 PMM(page_set_memattr)
6182 PMM(extract_and_hold)
6193 PMM(invalidate_page)
6194 PMM(invalidate_range)
6196 PMM(invalidate_cache)