2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
50 * Copyright (c) 2018 The FreeBSD Foundation
51 * All rights reserved.
53 * This software was developed for the FreeBSD Project by Jake Burkholder,
54 * Safeport Network Services, and Network Associates Laboratories, the
55 * Security Research Division of Network Associates, Inc. under
56 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
57 * CHATS research program.
59 * Portions of this software were developed by
60 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
61 * the FreeBSD Foundation.
63 * Redistribution and use in source and binary forms, with or without
64 * modification, are permitted provided that the following conditions
66 * 1. Redistributions of source code must retain the above copyright
67 * notice, this list of conditions and the following disclaimer.
68 * 2. Redistributions in binary form must reproduce the above copyright
69 * notice, this list of conditions and the following disclaimer in the
70 * documentation and/or other materials provided with the distribution.
72 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
73 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
75 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
78 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
79 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
80 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
81 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
85 #include <sys/cdefs.h>
86 __FBSDID("$FreeBSD$");
89 * Manages physical address maps.
91 * Since the information managed by this module is
92 * also stored by the logical address mapping module,
93 * this module may throw away valid virtual-to-physical
94 * mappings at almost any time. However, invalidations
95 * of virtual-to-physical mappings must be done as
98 * In order to cope with hardware architectures which
99 * make virtual-to-physical map invalidates expensive,
100 * this module may delay invalidate or reduced protection
101 * operations until such time as they are actually
102 * necessary. This module is given full information as
103 * to which processors are currently using which maps,
104 * and to when physical maps must be made correct.
107 #include "opt_apic.h"
109 #include "opt_pmap.h"
113 #include <sys/param.h>
114 #include <sys/systm.h>
115 #include <sys/kernel.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/proc.h>
123 #include <sys/rwlock.h>
124 #include <sys/sf_buf.h>
126 #include <sys/vmmeter.h>
127 #include <sys/sched.h>
128 #include <sys/sysctl.h>
130 #include <sys/vmem.h>
133 #include <vm/vm_param.h>
134 #include <vm/vm_kern.h>
135 #include <vm/vm_page.h>
136 #include <vm/vm_map.h>
137 #include <vm/vm_object.h>
138 #include <vm/vm_extern.h>
139 #include <vm/vm_pageout.h>
140 #include <vm/vm_pager.h>
141 #include <vm/vm_phys.h>
142 #include <vm/vm_radix.h>
143 #include <vm/vm_reserv.h>
148 #include <machine/intr_machdep.h>
149 #include <x86/apicvar.h>
151 #include <machine/bootinfo.h>
152 #include <machine/cpu.h>
153 #include <machine/cputypes.h>
154 #include <machine/md_var.h>
155 #include <machine/pcb.h>
156 #include <machine/specialreg.h>
158 #include <machine/smp.h>
161 #ifndef PMAP_SHPGPERPROC
162 #define PMAP_SHPGPERPROC 200
165 #if !defined(DIAGNOSTIC)
166 #ifdef __GNUC_GNU_INLINE__
167 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
169 #define PMAP_INLINE extern inline
176 #define PV_STAT(x) do { x ; } while (0)
178 #define PV_STAT(x) do { } while (0)
181 #define pa_index(pa) ((pa) >> PDRSHIFT)
182 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
185 * Get PDEs and PTEs for user/kernel address space
187 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
188 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
190 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
191 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
192 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
193 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
194 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
196 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
197 atomic_clear_int((u_int *)(pte), PG_W))
198 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
200 struct pmap kernel_pmap_store;
202 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
203 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
204 int pgeflag = 0; /* PG_G or-in */
205 int pseflag = 0; /* PG_PS or-in */
207 static int nkpt = NKPT;
208 vm_offset_t kernel_vm_end = /* 0 + */ NKPT * NBPDR;
210 #if defined(PAE) || defined(PAE_TABLES)
212 static uma_zone_t pdptzone;
215 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
217 static int pat_works = 1;
218 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
219 "Is page attribute table fully functional?");
221 static int pg_ps_enabled = 1;
222 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
223 &pg_ps_enabled, 0, "Are large page mappings enabled?");
225 #define PAT_INDEX_SIZE 8
226 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
229 * pmap_mapdev support pre initialization (i.e. console)
231 #define PMAP_PREINIT_MAPPING_COUNT 8
232 static struct pmap_preinit_mapping {
237 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
238 static int pmap_initialized;
240 static struct rwlock_padalign pvh_global_lock;
243 * Data for the pv entry allocation mechanism
245 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
246 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
247 static struct md_page *pv_table;
248 static int shpgperproc = PMAP_SHPGPERPROC;
250 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
251 int pv_maxchunks; /* How many chunks we have KVA for */
252 vm_offset_t pv_vafree; /* freelist stored in the PTE */
255 * All those kernel PT submaps that BSD is so fond of
258 static pd_entry_t *KPTD;
265 static caddr_t crashdumpmap;
267 static pt_entry_t *PMAP1 = NULL, *PMAP2;
268 static pt_entry_t *PADDR1 = NULL, *PADDR2;
271 static int PMAP1changedcpu;
272 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
274 "Number of times pmap_pte_quick changed CPU with same PMAP1");
276 static int PMAP1changed;
277 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
279 "Number of times pmap_pte_quick changed PMAP1");
280 static int PMAP1unchanged;
281 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
283 "Number of times pmap_pte_quick didn't change PMAP1");
284 static struct mtx PMAP2mutex;
288 static void free_pv_chunk(struct pv_chunk *pc);
289 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
290 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
291 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
292 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
293 #if VM_NRESERVLEVEL > 0
294 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
296 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
297 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
299 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
301 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
302 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
304 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
305 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
306 static void pmap_flush_page(vm_page_t m);
307 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
308 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
310 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
311 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
312 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
313 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
314 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
315 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
316 #if VM_NRESERVLEVEL > 0
317 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
319 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
321 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
322 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
323 struct spglist *free);
324 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
325 struct spglist *free);
326 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
327 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
328 struct spglist *free);
329 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
331 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
332 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
334 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
336 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
338 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
340 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
341 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
342 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
343 static void pmap_pte_release(pt_entry_t *pte);
344 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
345 #if defined(PAE) || defined(PAE_TABLES)
346 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain,
347 uint8_t *flags, int wait);
349 static void pmap_init_trm(void);
351 static __inline void pagezero(void *page);
353 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
354 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
356 void pmap_cold(void);
358 u_long physfree; /* phys addr of next free page */
359 u_long vm86phystk; /* PA of vm86/bios stack */
360 u_long vm86paddr; /* address of vm86 region */
361 int vm86pa; /* phys addr of vm86 region */
362 u_long KERNend; /* phys addr end of kernel (just after bss) */
363 pd_entry_t *IdlePTD; /* phys addr of kernel PTD */
364 #if defined(PAE) || defined(PAE_TABLES)
365 pdpt_entry_t *IdlePDPT; /* phys addr of kernel PDPT */
367 pt_entry_t *KPTmap; /* address of kernel page tables */
368 u_long KPTphys; /* phys addr of kernel page tables */
369 extern u_long tramp_idleptd;
372 allocpages(u_int cnt, u_long *physfree)
377 *physfree += PAGE_SIZE * cnt;
378 bzero((void *)res, PAGE_SIZE * cnt);
383 pmap_cold_map(u_long pa, u_long va, u_long cnt)
387 for (pt = (pt_entry_t *)KPTphys + atop(va); cnt > 0;
388 cnt--, pt++, va += PAGE_SIZE, pa += PAGE_SIZE)
389 *pt = pa | PG_V | PG_RW | PG_A | PG_M;
393 pmap_cold_mapident(u_long pa, u_long cnt)
396 pmap_cold_map(pa, pa, cnt);
399 _Static_assert(2 * NBPDR == KERNBASE, "Broken double-map of zero PTD");
402 * Called from locore.s before paging is enabled. Sets up the first
403 * kernel page table. Since kernel is mapped with PA == VA, this code
404 * does not require relocations.
413 physfree = (u_long)&_end;
414 if (bootinfo.bi_esymtab != 0)
415 physfree = bootinfo.bi_esymtab;
416 if (bootinfo.bi_kernend != 0)
417 physfree = bootinfo.bi_kernend;
418 physfree = roundup2(physfree, NBPDR);
421 /* Allocate Kernel Page Tables */
422 KPTphys = allocpages(NKPT, &physfree);
423 KPTmap = (pt_entry_t *)KPTphys;
425 /* Allocate Page Table Directory */
426 #if defined(PAE) || defined(PAE_TABLES)
427 /* XXX only need 32 bytes (easier for now) */
428 IdlePDPT = (pdpt_entry_t *)allocpages(1, &physfree);
430 IdlePTD = (pd_entry_t *)allocpages(NPGPTD, &physfree);
433 * Allocate KSTACK. Leave a guard page between IdlePTD and
434 * proc0kstack, to control stack overflow for thread0 and
435 * prevent corruption of the page table. We leak the guard
436 * physical memory due to 1:1 mappings.
438 allocpages(1, &physfree);
439 proc0kstack = allocpages(TD0_KSTACK_PAGES, &physfree);
441 /* vm86/bios stack */
442 vm86phystk = allocpages(1, &physfree);
444 /* pgtable + ext + IOPAGES */
445 vm86paddr = vm86pa = allocpages(3, &physfree);
447 /* Install page tables into PTD. Page table page 1 is wasted. */
448 for (a = 0; a < NKPT; a++)
449 IdlePTD[a] = (KPTphys + ptoa(a)) | PG_V | PG_RW | PG_A | PG_M;
451 #if defined(PAE) || defined(PAE_TABLES)
452 /* PAE install PTD pointers into PDPT */
453 for (a = 0; a < NPGPTD; a++)
454 IdlePDPT[a] = ((u_int)IdlePTD + ptoa(a)) | PG_V;
458 * Install recursive mapping for kernel page tables into
461 for (a = 0; a < NPGPTD; a++)
462 IdlePTD[PTDPTDI + a] = ((u_int)IdlePTD + ptoa(a)) | PG_V |
466 * Initialize page table pages mapping physical address zero
467 * through the (physical) end of the kernel. Many of these
468 * pages must be reserved, and we reserve them all and map
469 * them linearly for convenience. We do this even if we've
470 * enabled PSE above; we'll just switch the corresponding
471 * kernel PDEs before we turn on paging.
473 * This and all other page table entries allow read and write
474 * access for various reasons. Kernel mappings never have any
475 * access restrictions.
477 pmap_cold_mapident(0, atop(NBPDR));
478 pmap_cold_map(0, NBPDR, atop(NBPDR));
479 pmap_cold_mapident(KERNBASE, atop(KERNend - KERNBASE));
481 /* Map page table directory */
482 #if defined(PAE) || defined(PAE_TABLES)
483 pmap_cold_mapident((u_long)IdlePDPT, 1);
485 pmap_cold_mapident((u_long)IdlePTD, NPGPTD);
487 /* Map early KPTmap. It is really pmap_cold_mapident. */
488 pmap_cold_map(KPTphys, (u_long)KPTmap, NKPT);
490 /* Map proc0kstack */
491 pmap_cold_mapident(proc0kstack, TD0_KSTACK_PAGES);
492 /* ISA hole already mapped */
494 pmap_cold_mapident(vm86phystk, 1);
495 pmap_cold_mapident(vm86pa, 3);
497 /* Map page 0 into the vm86 page table */
498 *(pt_entry_t *)vm86pa = 0 | PG_RW | PG_U | PG_A | PG_M | PG_V;
500 /* ...likewise for the ISA hole for vm86 */
501 for (pt = (pt_entry_t *)vm86pa + atop(ISA_HOLE_START), a = 0;
502 a < atop(ISA_HOLE_LENGTH); a++, pt++)
503 *pt = (ISA_HOLE_START + ptoa(a)) | PG_RW | PG_U | PG_A |
506 /* Enable PSE, PGE, VME, and PAE if configured. */
508 if ((cpu_feature & CPUID_PSE) != 0) {
511 * Superpage mapping of the kernel text. Existing 4k
512 * page table pages are wasted.
514 for (a = KERNBASE; a < KERNend; a += NBPDR)
515 IdlePTD[a >> PDRSHIFT] = a | PG_PS | PG_A | PG_M |
518 if ((cpu_feature & CPUID_PGE) != 0) {
522 ncr4 |= (cpu_feature & CPUID_VME) != 0 ? CR4_VME : 0;
523 #if defined(PAE) || defined(PAE_TABLES)
527 load_cr4(rcr4() | ncr4);
529 /* Now enable paging */
530 #if defined(PAE) || defined(PAE_TABLES)
531 cr3 = (u_int)IdlePDPT;
533 cr3 = (u_int)IdlePTD;
537 load_cr0(rcr0() | CR0_PG);
540 * Now running relocated at KERNBASE where the system is
545 * Remove the lowest part of the double mapping of low memory
546 * to get some null pointer checks.
549 load_cr3(cr3); /* invalidate TLB */
553 * Bootstrap the system enough to run with virtual memory.
555 * On the i386 this is called after mapping has already been enabled
556 * in locore.s with the page table created in pmap_cold(),
557 * and just syncs the pmap module with what has already been done.
560 pmap_bootstrap(vm_paddr_t firstaddr)
563 pt_entry_t *pte, *unused;
568 * Add a physical memory segment (vm_phys_seg) corresponding to the
569 * preallocated kernel page table pages so that vm_page structures
570 * representing these pages will be created. The vm_page structures
571 * are required for promotion of the corresponding kernel virtual
572 * addresses to superpage mappings.
574 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
577 * Initialize the first available kernel virtual address. However,
578 * using "firstaddr" may waste a few pages of the kernel virtual
579 * address space, because locore may not have mapped every physical
580 * page that it allocated. Preferably, locore would provide a first
581 * unused virtual address in addition to "firstaddr".
583 virtual_avail = (vm_offset_t)firstaddr;
585 virtual_end = VM_MAX_KERNEL_ADDRESS;
588 * Initialize the kernel pmap (which is statically allocated).
590 PMAP_LOCK_INIT(kernel_pmap);
591 kernel_pmap->pm_pdir = IdlePTD;
592 #if defined(PAE) || defined(PAE_TABLES)
593 kernel_pmap->pm_pdpt = IdlePDPT;
595 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
596 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
599 * Initialize the global pv list lock.
601 rw_init(&pvh_global_lock, "pmap pv global");
604 * Reserve some special page table entries/VA space for temporary
607 #define SYSMAP(c, p, v, n) \
608 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
615 * Initialize temporary map objects on the current CPU for use
617 * CMAP1/CMAP2 are used for zeroing and copying pages.
618 * CMAP3 is used for the boot-time memory test.
621 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
622 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1)
623 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1)
624 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1)
626 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
631 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
634 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
636 SYSMAP(caddr_t, unused, ptvmmap, 1)
639 * msgbufp is used to map the system message buffer.
641 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
644 * KPTmap is used by pmap_kextract().
646 * KPTmap is first initialized by locore. However, that initial
647 * KPTmap can only support NKPT page table pages. Here, a larger
648 * KPTmap is created that can support KVA_PAGES page table pages.
650 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
652 for (i = 0; i < NKPT; i++)
653 KPTD[i] = (KPTphys + ptoa(i)) | PG_RW | PG_V;
656 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
659 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
660 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
662 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
667 * Initialize the PAT MSR if present.
668 * pmap_init_pat() clears and sets CR4_PGE, which, as a
669 * side-effect, invalidates stale PG_G TLB entries that might
670 * have been created in our pre-boot environment. We assume
671 * that PAT support implies PGE and in reverse, PGE presence
672 * comes with PAT. Both features were added for Pentium Pro.
678 pmap_init_reserved_pages(void)
686 mtx_init(&pc->pc_copyout_mlock, "cpmlk", NULL, MTX_DEF |
688 pc->pc_copyout_maddr = kva_alloc(ptoa(2));
689 if (pc->pc_copyout_maddr == 0)
690 panic("unable to allocate non-sleepable copyout KVA");
691 sx_init(&pc->pc_copyout_slock, "cpslk");
692 pc->pc_copyout_saddr = kva_alloc(ptoa(2));
693 if (pc->pc_copyout_saddr == 0)
694 panic("unable to allocate sleepable copyout KVA");
697 * Skip if the mappings have already been initialized,
698 * i.e. this is the BSP.
700 if (pc->pc_cmap_addr1 != 0)
703 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
704 pages = kva_alloc(PAGE_SIZE * 3);
706 panic("unable to allocate CMAP KVA");
707 pc->pc_cmap_pte1 = vtopte(pages);
708 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE);
709 pc->pc_cmap_addr1 = (caddr_t)pages;
710 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE);
711 pc->pc_qmap_addr = pages + atop(2);
715 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
723 int pat_table[PAT_INDEX_SIZE];
728 /* Set default PAT index table. */
729 for (i = 0; i < PAT_INDEX_SIZE; i++)
731 pat_table[PAT_WRITE_BACK] = 0;
732 pat_table[PAT_WRITE_THROUGH] = 1;
733 pat_table[PAT_UNCACHEABLE] = 3;
734 pat_table[PAT_WRITE_COMBINING] = 3;
735 pat_table[PAT_WRITE_PROTECTED] = 3;
736 pat_table[PAT_UNCACHED] = 3;
739 * Bail if this CPU doesn't implement PAT.
740 * We assume that PAT support implies PGE.
742 if ((cpu_feature & CPUID_PAT) == 0) {
743 for (i = 0; i < PAT_INDEX_SIZE; i++)
744 pat_index[i] = pat_table[i];
750 * Due to some Intel errata, we can only safely use the lower 4
753 * Intel Pentium III Processor Specification Update
754 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
757 * Intel Pentium IV Processor Specification Update
758 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
760 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
761 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
764 /* Initialize default PAT entries. */
765 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
766 PAT_VALUE(1, PAT_WRITE_THROUGH) |
767 PAT_VALUE(2, PAT_UNCACHED) |
768 PAT_VALUE(3, PAT_UNCACHEABLE) |
769 PAT_VALUE(4, PAT_WRITE_BACK) |
770 PAT_VALUE(5, PAT_WRITE_THROUGH) |
771 PAT_VALUE(6, PAT_UNCACHED) |
772 PAT_VALUE(7, PAT_UNCACHEABLE);
776 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
777 * Program 5 and 6 as WP and WC.
778 * Leave 4 and 7 as WB and UC.
780 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
781 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
782 PAT_VALUE(6, PAT_WRITE_COMBINING);
783 pat_table[PAT_UNCACHED] = 2;
784 pat_table[PAT_WRITE_PROTECTED] = 5;
785 pat_table[PAT_WRITE_COMBINING] = 6;
788 * Just replace PAT Index 2 with WC instead of UC-.
790 pat_msr &= ~PAT_MASK(2);
791 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
792 pat_table[PAT_WRITE_COMBINING] = 2;
797 load_cr4(cr4 & ~CR4_PGE);
799 /* Disable caches (CD = 1, NW = 0). */
801 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
803 /* Flushes caches and TLBs. */
807 /* Update PAT and index table. */
808 wrmsr(MSR_PAT, pat_msr);
809 for (i = 0; i < PAT_INDEX_SIZE; i++)
810 pat_index[i] = pat_table[i];
812 /* Flush caches and TLBs again. */
816 /* Restore caches and PGE. */
822 * Initialize a vm_page's machine-dependent fields.
825 pmap_page_init(vm_page_t m)
828 TAILQ_INIT(&m->md.pv_list);
829 m->md.pat_mode = PAT_WRITE_BACK;
832 #if defined(PAE) || defined(PAE_TABLES)
834 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain, uint8_t *flags,
838 /* Inform UMA that this allocator uses kernel_map/object. */
839 *flags = UMA_SLAB_KERNEL;
840 return ((void *)kmem_alloc_contig_domain(domain, bytes, wait, 0x0ULL,
841 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
846 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
848 * - Must deal with pages in order to ensure that none of the PG_* bits
849 * are ever set, PG_V in particular.
850 * - Assumes we can write to ptes without pte_store() atomic ops, even
851 * on PAE systems. This should be ok.
852 * - Assumes nothing will ever test these addresses for 0 to indicate
853 * no mapping instead of correctly checking PG_V.
854 * - Assumes a vm_offset_t will fit in a pte (true for i386).
855 * Because PG_V is never set, there can be no mappings to invalidate.
858 pmap_ptelist_alloc(vm_offset_t *head)
865 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
869 panic("pmap_ptelist_alloc: va with PG_V set!");
875 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
880 panic("pmap_ptelist_free: freeing va with PG_V set!");
882 *pte = *head; /* virtual! PG_V is 0 though */
887 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
893 for (i = npages - 1; i >= 0; i--) {
894 va = (vm_offset_t)base + i * PAGE_SIZE;
895 pmap_ptelist_free(head, va);
901 * Initialize the pmap module.
902 * Called by vm_init, to initialize any structures that the pmap
903 * system needs to map virtual memory.
908 struct pmap_preinit_mapping *ppim;
914 * Initialize the vm page array entries for the kernel pmap's
917 for (i = 0; i < NKPT; i++) {
918 mpte = PHYS_TO_VM_PAGE(KPTphys + ptoa(i));
919 KASSERT(mpte >= vm_page_array &&
920 mpte < &vm_page_array[vm_page_array_size],
921 ("pmap_init: page table page is out of range"));
922 mpte->pindex = i + KPTDI;
923 mpte->phys_addr = KPTphys + ptoa(i);
927 * Initialize the address space (zone) for the pv entries. Set a
928 * high water mark so that the system can recover from excessive
929 * numbers of pv entries.
931 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
932 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
933 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
934 pv_entry_max = roundup(pv_entry_max, _NPCPV);
935 pv_entry_high_water = 9 * (pv_entry_max / 10);
938 * If the kernel is running on a virtual machine, then it must assume
939 * that MCA is enabled by the hypervisor. Moreover, the kernel must
940 * be prepared for the hypervisor changing the vendor and family that
941 * are reported by CPUID. Consequently, the workaround for AMD Family
942 * 10h Erratum 383 is enabled if the processor's feature set does not
943 * include at least one feature that is only supported by older Intel
944 * or newer AMD processors.
946 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
947 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
948 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
950 workaround_erratum383 = 1;
953 * Are large page mappings supported and enabled?
955 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
958 else if (pg_ps_enabled) {
959 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
960 ("pmap_init: can't assign to pagesizes[1]"));
961 pagesizes[1] = NBPDR;
965 * Calculate the size of the pv head table for superpages.
966 * Handle the possibility that "vm_phys_segs[...].end" is zero.
968 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
969 PAGE_SIZE) / NBPDR + 1;
972 * Allocate memory for the pv head table for superpages.
974 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
976 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
978 for (i = 0; i < pv_npg; i++)
979 TAILQ_INIT(&pv_table[i].pv_list);
981 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
982 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
983 if (pv_chunkbase == NULL)
984 panic("pmap_init: not enough kvm for pv chunks");
985 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
986 #if defined(PAE) || defined(PAE_TABLES)
987 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
988 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
989 UMA_ZONE_VM | UMA_ZONE_NOFREE);
990 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
993 pmap_initialized = 1;
998 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
999 ppim = pmap_preinit_mapping + i;
1002 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
1003 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
1009 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
1010 "Max number of PV entries");
1011 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
1012 "Page share factor per proc");
1014 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1015 "2/4MB page mapping counters");
1017 static u_long pmap_pde_demotions;
1018 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1019 &pmap_pde_demotions, 0, "2/4MB page demotions");
1021 static u_long pmap_pde_mappings;
1022 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1023 &pmap_pde_mappings, 0, "2/4MB page mappings");
1025 static u_long pmap_pde_p_failures;
1026 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1027 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
1029 static u_long pmap_pde_promotions;
1030 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1031 &pmap_pde_promotions, 0, "2/4MB page promotions");
1033 /***************************************************
1034 * Low level helper routines.....
1035 ***************************************************/
1038 * Determine the appropriate bits to set in a PTE or PDE for a specified
1042 pmap_cache_bits(int mode, boolean_t is_pde)
1044 int cache_bits, pat_flag, pat_idx;
1046 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
1047 panic("Unknown caching mode %d\n", mode);
1049 /* The PAT bit is different for PTE's and PDE's. */
1050 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
1052 /* Map the caching mode to a PAT index. */
1053 pat_idx = pat_index[mode];
1055 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1058 cache_bits |= pat_flag;
1060 cache_bits |= PG_NC_PCD;
1062 cache_bits |= PG_NC_PWT;
1063 return (cache_bits);
1067 * The caller is responsible for maintaining TLB consistency.
1070 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
1074 pde = pmap_pde(kernel_pmap, va);
1075 pde_store(pde, newpde);
1079 * After changing the page size for the specified virtual address in the page
1080 * table, flush the corresponding entries from the processor's TLB. Only the
1081 * calling processor's TLB is affected.
1083 * The calling thread must be pinned to a processor.
1086 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
1089 if ((newpde & PG_PS) == 0)
1090 /* Demotion: flush a specific 2MB page mapping. */
1092 else /* if ((newpde & PG_G) == 0) */
1094 * Promotion: flush every 4KB page mapping from the TLB
1095 * because there are too many to flush individually.
1110 * For SMP, these functions have to use the IPI mechanism for coherence.
1112 * N.B.: Before calling any of the following TLB invalidation functions,
1113 * the calling processor must ensure that all stores updating a non-
1114 * kernel page table are globally performed. Otherwise, another
1115 * processor could cache an old, pre-update entry without being
1116 * invalidated. This can happen one of two ways: (1) The pmap becomes
1117 * active on another processor after its pm_active field is checked by
1118 * one of the following functions but before a store updating the page
1119 * table is globally performed. (2) The pmap becomes active on another
1120 * processor before its pm_active field is checked but due to
1121 * speculative loads one of the following functions stills reads the
1122 * pmap as inactive on the other processor.
1124 * The kernel page table is exempt because its pm_active field is
1125 * immutable. The kernel page table is always active on every
1129 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1131 cpuset_t *mask, other_cpus;
1135 if (pmap == kernel_pmap) {
1138 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1141 cpuid = PCPU_GET(cpuid);
1142 other_cpus = all_cpus;
1143 CPU_CLR(cpuid, &other_cpus);
1144 CPU_AND(&other_cpus, &pmap->pm_active);
1147 smp_masked_invlpg(*mask, va, pmap);
1151 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1152 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1155 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1157 cpuset_t *mask, other_cpus;
1161 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1162 pmap_invalidate_all(pmap);
1167 if (pmap == kernel_pmap) {
1168 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1171 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1174 cpuid = PCPU_GET(cpuid);
1175 other_cpus = all_cpus;
1176 CPU_CLR(cpuid, &other_cpus);
1177 CPU_AND(&other_cpus, &pmap->pm_active);
1180 smp_masked_invlpg_range(*mask, sva, eva, pmap);
1185 pmap_invalidate_all(pmap_t pmap)
1187 cpuset_t *mask, other_cpus;
1191 if (pmap == kernel_pmap) {
1194 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1197 cpuid = PCPU_GET(cpuid);
1198 other_cpus = all_cpus;
1199 CPU_CLR(cpuid, &other_cpus);
1200 CPU_AND(&other_cpus, &pmap->pm_active);
1203 smp_masked_invltlb(*mask, pmap);
1208 pmap_invalidate_cache(void)
1218 cpuset_t invalidate; /* processors that invalidate their TLB */
1222 u_int store; /* processor that updates the PDE */
1226 pmap_update_pde_kernel(void *arg)
1228 struct pde_action *act = arg;
1231 if (act->store == PCPU_GET(cpuid)) {
1232 pde = pmap_pde(kernel_pmap, act->va);
1233 pde_store(pde, act->newpde);
1238 pmap_update_pde_user(void *arg)
1240 struct pde_action *act = arg;
1242 if (act->store == PCPU_GET(cpuid))
1243 pde_store(act->pde, act->newpde);
1247 pmap_update_pde_teardown(void *arg)
1249 struct pde_action *act = arg;
1251 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1252 pmap_update_pde_invalidate(act->va, act->newpde);
1256 * Change the page size for the specified virtual address in a way that
1257 * prevents any possibility of the TLB ever having two entries that map the
1258 * same virtual address using different page sizes. This is the recommended
1259 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1260 * machine check exception for a TLB state that is improperly diagnosed as a
1264 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1266 struct pde_action act;
1267 cpuset_t active, other_cpus;
1271 cpuid = PCPU_GET(cpuid);
1272 other_cpus = all_cpus;
1273 CPU_CLR(cpuid, &other_cpus);
1274 if (pmap == kernel_pmap)
1277 active = pmap->pm_active;
1278 if (CPU_OVERLAP(&active, &other_cpus)) {
1280 act.invalidate = active;
1283 act.newpde = newpde;
1284 CPU_SET(cpuid, &active);
1285 smp_rendezvous_cpus(active,
1286 smp_no_rendezvous_barrier, pmap == kernel_pmap ?
1287 pmap_update_pde_kernel : pmap_update_pde_user,
1288 pmap_update_pde_teardown, &act);
1290 if (pmap == kernel_pmap)
1291 pmap_kenter_pde(va, newpde);
1293 pde_store(pde, newpde);
1294 if (CPU_ISSET(cpuid, &active))
1295 pmap_update_pde_invalidate(va, newpde);
1301 * Normal, non-SMP, 486+ invalidation functions.
1302 * We inline these within pmap.c for speed.
1305 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1308 if (pmap == kernel_pmap)
1313 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1317 if (pmap == kernel_pmap)
1318 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1323 pmap_invalidate_all(pmap_t pmap)
1326 if (pmap == kernel_pmap)
1331 pmap_invalidate_cache(void)
1338 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1341 if (pmap == kernel_pmap)
1342 pmap_kenter_pde(va, newpde);
1344 pde_store(pde, newpde);
1345 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1346 pmap_update_pde_invalidate(va, newpde);
1351 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1355 * When the PDE has PG_PROMOTED set, the 2- or 4MB page mapping was
1356 * created by a promotion that did not invalidate the 512 or 1024 4KB
1357 * page mappings that might exist in the TLB. Consequently, at this
1358 * point, the TLB may hold both 4KB and 2- or 4MB page mappings for
1359 * the address range [va, va + NBPDR). Therefore, the entire range
1360 * must be invalidated here. In contrast, when PG_PROMOTED is clear,
1361 * the TLB will not hold any 4KB page mappings for the address range
1362 * [va, va + NBPDR), and so a single INVLPG suffices to invalidate the
1363 * 2- or 4MB page mapping from the TLB.
1365 if ((pde & PG_PROMOTED) != 0)
1366 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
1368 pmap_invalidate_page(pmap, va);
1371 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1374 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1378 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
1380 KASSERT((sva & PAGE_MASK) == 0,
1381 ("pmap_invalidate_cache_range: sva not page-aligned"));
1382 KASSERT((eva & PAGE_MASK) == 0,
1383 ("pmap_invalidate_cache_range: eva not page-aligned"));
1386 if ((cpu_feature & CPUID_SS) != 0 && !force)
1387 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1388 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
1389 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1392 * XXX: Some CPUs fault, hang, or trash the local APIC
1393 * registers if we use CLFLUSH on the local APIC
1394 * range. The local APIC is always uncached, so we
1395 * don't need to flush for that range anyway.
1397 if (pmap_kextract(sva) == lapic_paddr)
1401 * Otherwise, do per-cache line flush. Use the sfence
1402 * instruction to insure that previous stores are
1403 * included in the write-back. The processor
1404 * propagates flush to other processors in the cache
1408 for (; sva < eva; sva += cpu_clflush_line_size)
1411 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1412 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1414 if (pmap_kextract(sva) == lapic_paddr)
1418 * Writes are ordered by CLFLUSH on Intel CPUs.
1420 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1422 for (; sva < eva; sva += cpu_clflush_line_size)
1424 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1429 * No targeted cache flush methods are supported by CPU,
1430 * or the supplied range is bigger than 2MB.
1431 * Globally invalidate cache.
1433 pmap_invalidate_cache();
1438 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1442 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1443 (cpu_feature & CPUID_CLFSH) == 0) {
1444 pmap_invalidate_cache();
1446 for (i = 0; i < count; i++)
1447 pmap_flush_page(pages[i]);
1452 * Are we current address space or kernel?
1455 pmap_is_current(pmap_t pmap)
1458 return (pmap == kernel_pmap);
1462 * If the given pmap is not the current or kernel pmap, the returned pte must
1463 * be released by passing it to pmap_pte_release().
1466 pmap_pte(pmap_t pmap, vm_offset_t va)
1471 pde = pmap_pde(pmap, va);
1475 /* are we current address space or kernel? */
1476 if (pmap_is_current(pmap))
1477 return (vtopte(va));
1478 mtx_lock(&PMAP2mutex);
1479 newpf = *pde & PG_FRAME;
1480 if ((*PMAP2 & PG_FRAME) != newpf) {
1481 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1482 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1484 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1490 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1493 static __inline void
1494 pmap_pte_release(pt_entry_t *pte)
1497 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1498 mtx_unlock(&PMAP2mutex);
1502 * NB: The sequence of updating a page table followed by accesses to the
1503 * corresponding pages is subject to the situation described in the "AMD64
1504 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1505 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1506 * right after modifying the PTE bits is crucial.
1508 static __inline void
1509 invlcaddr(void *caddr)
1512 invlpg((u_int)caddr);
1516 * Super fast pmap_pte routine best used when scanning
1517 * the pv lists. This eliminates many coarse-grained
1518 * invltlb calls. Note that many of the pv list
1519 * scans are across different pmaps. It is very wasteful
1520 * to do an entire invltlb for checking a single mapping.
1522 * If the given pmap is not the current pmap, pvh_global_lock
1523 * must be held and curthread pinned to a CPU.
1526 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1531 pde = pmap_pde(pmap, va);
1535 /* are we current address space or kernel? */
1536 if (pmap_is_current(pmap))
1537 return (vtopte(va));
1538 rw_assert(&pvh_global_lock, RA_WLOCKED);
1539 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1540 newpf = *pde & PG_FRAME;
1541 if ((*PMAP1 & PG_FRAME) != newpf) {
1542 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1544 PMAP1cpu = PCPU_GET(cpuid);
1550 if (PMAP1cpu != PCPU_GET(cpuid)) {
1551 PMAP1cpu = PCPU_GET(cpuid);
1557 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1563 * Routine: pmap_extract
1565 * Extract the physical page address associated
1566 * with the given map/virtual_address pair.
1569 pmap_extract(pmap_t pmap, vm_offset_t va)
1577 pde = pmap->pm_pdir[va >> PDRSHIFT];
1579 if ((pde & PG_PS) != 0)
1580 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1582 pte = pmap_pte(pmap, va);
1583 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK);
1584 pmap_pte_release(pte);
1592 * Routine: pmap_extract_and_hold
1594 * Atomically extract and hold the physical page
1595 * with the given pmap and virtual address pair
1596 * if that mapping permits the given protection.
1599 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1602 pt_entry_t pte, *ptep;
1610 pde = *pmap_pde(pmap, va);
1613 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1614 if (vm_page_pa_tryrelock(pmap, (pde &
1615 PG_PS_FRAME) | (va & PDRMASK), &pa))
1617 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1622 ptep = pmap_pte(pmap, va);
1624 pmap_pte_release(ptep);
1626 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1627 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1630 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1640 /***************************************************
1641 * Low level mapping routines.....
1642 ***************************************************/
1645 * Add a wired page to the kva.
1646 * Note: not SMP coherent.
1648 * This function may be used before pmap_bootstrap() is called.
1651 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1656 pte_store(pte, pa | PG_RW | PG_V);
1659 static __inline void
1660 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1665 pte_store(pte, pa | PG_RW | PG_V | pmap_cache_bits(mode, 0));
1669 * Remove a page from the kernel pagetables.
1670 * Note: not SMP coherent.
1672 * This function may be used before pmap_bootstrap() is called.
1675 pmap_kremove(vm_offset_t va)
1684 * Used to map a range of physical addresses into kernel
1685 * virtual address space.
1687 * The value passed in '*virt' is a suggested virtual address for
1688 * the mapping. Architectures which can support a direct-mapped
1689 * physical to virtual region can return the appropriate address
1690 * within that region, leaving '*virt' unchanged. Other
1691 * architectures should map the pages starting at '*virt' and
1692 * update '*virt' with the first usable address after the mapped
1696 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1698 vm_offset_t va, sva;
1699 vm_paddr_t superpage_offset;
1704 * Does the physical address range's size and alignment permit at
1705 * least one superpage mapping to be created?
1707 superpage_offset = start & PDRMASK;
1708 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1710 * Increase the starting virtual address so that its alignment
1711 * does not preclude the use of superpage mappings.
1713 if ((va & PDRMASK) < superpage_offset)
1714 va = (va & ~PDRMASK) + superpage_offset;
1715 else if ((va & PDRMASK) > superpage_offset)
1716 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1719 while (start < end) {
1720 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1722 KASSERT((va & PDRMASK) == 0,
1723 ("pmap_map: misaligned va %#x", va));
1724 newpde = start | PG_PS | PG_RW | PG_V;
1725 pmap_kenter_pde(va, newpde);
1729 pmap_kenter(va, start);
1734 pmap_invalidate_range(kernel_pmap, sva, va);
1741 * Add a list of wired pages to the kva
1742 * this routine is only used for temporary
1743 * kernel mappings that do not need to have
1744 * page modification or references recorded.
1745 * Note that old mappings are simply written
1746 * over. The page *must* be wired.
1747 * Note: SMP coherent. Uses a ranged shootdown IPI.
1750 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1752 pt_entry_t *endpte, oldpte, pa, *pte;
1757 endpte = pte + count;
1758 while (pte < endpte) {
1760 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1761 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1763 #if defined(PAE) || defined(PAE_TABLES)
1764 pte_store(pte, pa | pg_nx | PG_RW | PG_V);
1766 pte_store(pte, pa | PG_RW | PG_V);
1771 if (__predict_false((oldpte & PG_V) != 0))
1772 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1777 * This routine tears out page mappings from the
1778 * kernel -- it is meant only for temporary mappings.
1779 * Note: SMP coherent. Uses a ranged shootdown IPI.
1782 pmap_qremove(vm_offset_t sva, int count)
1787 while (count-- > 0) {
1791 pmap_invalidate_range(kernel_pmap, sva, va);
1794 /***************************************************
1795 * Page table page management routines.....
1796 ***************************************************/
1798 * Schedule the specified unused page table page to be freed. Specifically,
1799 * add the page to the specified list of pages that will be released to the
1800 * physical memory manager after the TLB has been updated.
1802 static __inline void
1803 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1804 boolean_t set_PG_ZERO)
1808 m->flags |= PG_ZERO;
1810 m->flags &= ~PG_ZERO;
1811 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1815 * Inserts the specified page table page into the specified pmap's collection
1816 * of idle page table pages. Each of a pmap's page table pages is responsible
1817 * for mapping a distinct range of virtual addresses. The pmap's collection is
1818 * ordered by this virtual address range.
1821 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1824 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1825 return (vm_radix_insert(&pmap->pm_root, mpte));
1829 * Removes the page table page mapping the specified virtual address from the
1830 * specified pmap's collection of idle page table pages, and returns it.
1831 * Otherwise, returns NULL if there is no page table page corresponding to the
1832 * specified virtual address.
1834 static __inline vm_page_t
1835 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
1838 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1839 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT));
1843 * Decrements a page table page's wire count, which is used to record the
1844 * number of valid page table entries within the page. If the wire count
1845 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1846 * page table page was unmapped and FALSE otherwise.
1848 static inline boolean_t
1849 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1853 if (m->wire_count == 0) {
1854 _pmap_unwire_ptp(pmap, m, free);
1861 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1866 * unmap the page table page
1868 pmap->pm_pdir[m->pindex] = 0;
1869 --pmap->pm_stats.resident_count;
1872 * Do an invltlb to make the invalidated mapping
1873 * take effect immediately.
1875 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex);
1876 pmap_invalidate_page(pmap, pteva);
1879 * Put page on a list so that it is released after
1880 * *ALL* TLB shootdown is done
1882 pmap_add_delayed_free_list(m, free, TRUE);
1886 * After removing a page table entry, this routine is used to
1887 * conditionally free the page, and manage the hold/wire counts.
1890 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1895 if (pmap == kernel_pmap)
1897 ptepde = *pmap_pde(pmap, va);
1898 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1899 return (pmap_unwire_ptp(pmap, mpte, free));
1903 * Initialize the pmap for the swapper process.
1906 pmap_pinit0(pmap_t pmap)
1909 PMAP_LOCK_INIT(pmap);
1910 pmap->pm_pdir = IdlePTD;
1911 #if defined(PAE) || defined(PAE_TABLES)
1912 pmap->pm_pdpt = IdlePDPT;
1914 pmap->pm_root.rt_root = 0;
1915 CPU_ZERO(&pmap->pm_active);
1916 PCPU_SET(curpmap, pmap);
1917 TAILQ_INIT(&pmap->pm_pvchunk);
1918 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1922 * Initialize a preallocated and zeroed pmap structure,
1923 * such as one in a vmspace structure.
1926 pmap_pinit(pmap_t pmap)
1932 * No need to allocate page table space yet but we do need a valid
1933 * page directory table.
1935 if (pmap->pm_pdir == NULL) {
1936 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
1937 if (pmap->pm_pdir == NULL)
1939 #if defined(PAE) || defined(PAE_TABLES)
1940 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
1941 KASSERT(((vm_offset_t)pmap->pm_pdpt &
1942 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
1943 ("pmap_pinit: pdpt misaligned"));
1944 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
1945 ("pmap_pinit: pdpt above 4g"));
1947 pmap->pm_root.rt_root = 0;
1949 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1950 ("pmap_pinit: pmap has reserved page table page(s)"));
1953 * allocate the page directory page(s)
1955 for (i = 0; i < NPGPTD;) {
1956 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1957 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1961 pmap->pm_ptdpg[i] = m;
1962 #if defined(PAE) || defined(PAE_TABLES)
1963 pmap->pm_pdpt[i] = VM_PAGE_TO_PHYS(m) | PG_V;
1969 pmap_qenter((vm_offset_t)pmap->pm_pdir, pmap->pm_ptdpg, NPGPTD);
1971 for (i = 0; i < NPGPTD; i++)
1972 if ((pmap->pm_ptdpg[i]->flags & PG_ZERO) == 0)
1973 pagezero(pmap->pm_pdir + (i * NPDEPG));
1975 /* Install the trampoline mapping. */
1976 pmap->pm_pdir[TRPTDI] = PTD[TRPTDI];
1978 CPU_ZERO(&pmap->pm_active);
1979 TAILQ_INIT(&pmap->pm_pvchunk);
1980 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1986 * this routine is called if the page table page is not
1990 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
1996 * Allocate a page table page.
1998 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1999 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2000 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2002 rw_wunlock(&pvh_global_lock);
2004 rw_wlock(&pvh_global_lock);
2009 * Indicate the need to retry. While waiting, the page table
2010 * page may have been allocated.
2014 if ((m->flags & PG_ZERO) == 0)
2018 * Map the pagetable page into the process address space, if
2019 * it isn't already there.
2022 pmap->pm_stats.resident_count++;
2024 ptepa = VM_PAGE_TO_PHYS(m);
2025 pmap->pm_pdir[ptepindex] =
2026 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
2032 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
2039 * Calculate pagetable page index
2041 ptepindex = va >> PDRSHIFT;
2044 * Get the page directory entry
2046 ptepa = pmap->pm_pdir[ptepindex];
2049 * This supports switching from a 4MB page to a
2052 if (ptepa & PG_PS) {
2053 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
2054 ptepa = pmap->pm_pdir[ptepindex];
2058 * If the page table page is mapped, we just increment the
2059 * hold count, and activate it.
2062 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
2066 * Here if the pte page isn't mapped, or if it has
2069 m = _pmap_allocpte(pmap, ptepindex, flags);
2070 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2077 /***************************************************
2078 * Pmap allocation/deallocation routines.
2079 ***************************************************/
2082 * Release any resources held by the given physical map.
2083 * Called when a pmap initialized by pmap_pinit is being released.
2084 * Should only be called if the map contains no valid mappings.
2087 pmap_release(pmap_t pmap)
2092 KASSERT(pmap->pm_stats.resident_count == 0,
2093 ("pmap_release: pmap resident count %ld != 0",
2094 pmap->pm_stats.resident_count));
2095 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2096 ("pmap_release: pmap has reserved page table page(s)"));
2097 KASSERT(CPU_EMPTY(&pmap->pm_active),
2098 ("releasing active pmap %p", pmap));
2100 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2102 for (i = 0; i < NPGPTD; i++) {
2103 m = pmap->pm_ptdpg[i];
2104 #if defined(PAE) || defined(PAE_TABLES)
2105 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2106 ("pmap_release: got wrong ptd page"));
2108 vm_page_unwire_noq(m);
2114 kvm_size(SYSCTL_HANDLER_ARGS)
2116 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2118 return (sysctl_handle_long(oidp, &ksize, 0, req));
2120 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2121 0, 0, kvm_size, "IU", "Size of KVM");
2124 kvm_free(SYSCTL_HANDLER_ARGS)
2126 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2128 return (sysctl_handle_long(oidp, &kfree, 0, req));
2130 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2131 0, 0, kvm_free, "IU", "Amount of KVM free");
2134 * grow the number of kernel page table entries, if needed
2137 pmap_growkernel(vm_offset_t addr)
2139 vm_paddr_t ptppaddr;
2143 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2144 addr = roundup2(addr, NBPDR);
2145 if (addr - 1 >= kernel_map->max_offset)
2146 addr = kernel_map->max_offset;
2147 while (kernel_vm_end < addr) {
2148 if (pdir_pde(PTD, kernel_vm_end)) {
2149 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2150 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2151 kernel_vm_end = kernel_map->max_offset;
2157 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2158 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2161 panic("pmap_growkernel: no memory to grow kernel");
2165 if ((nkpg->flags & PG_ZERO) == 0)
2166 pmap_zero_page(nkpg);
2167 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2168 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2169 pdir_pde(KPTD, kernel_vm_end) = newpdir;
2171 pmap_kenter_pde(kernel_vm_end, newpdir);
2172 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2173 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2174 kernel_vm_end = kernel_map->max_offset;
2181 /***************************************************
2182 * page management routines.
2183 ***************************************************/
2185 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2186 CTASSERT(_NPCM == 11);
2187 CTASSERT(_NPCPV == 336);
2189 static __inline struct pv_chunk *
2190 pv_to_chunk(pv_entry_t pv)
2193 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2196 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2198 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2199 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2201 static const uint32_t pc_freemask[_NPCM] = {
2202 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2203 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2204 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2205 PC_FREE0_9, PC_FREE10
2208 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2209 "Current number of pv entries");
2212 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2214 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2215 "Current number of pv entry chunks");
2216 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2217 "Current number of pv entry chunks allocated");
2218 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2219 "Current number of pv entry chunks frees");
2220 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2221 "Number of times tried to get a chunk page but failed.");
2223 static long pv_entry_frees, pv_entry_allocs;
2224 static int pv_entry_spare;
2226 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2227 "Current number of pv entry frees");
2228 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2229 "Current number of pv entry allocs");
2230 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2231 "Current number of spare pv entries");
2235 * We are in a serious low memory condition. Resort to
2236 * drastic measures to free some pages so we can allocate
2237 * another pv entry chunk.
2240 pmap_pv_reclaim(pmap_t locked_pmap)
2243 struct pv_chunk *pc;
2244 struct md_page *pvh;
2247 pt_entry_t *pte, tpte;
2251 struct spglist free;
2253 int bit, field, freed;
2255 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2259 TAILQ_INIT(&newtail);
2260 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2261 SLIST_EMPTY(&free))) {
2262 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2263 if (pmap != pc->pc_pmap) {
2265 pmap_invalidate_all(pmap);
2266 if (pmap != locked_pmap)
2270 /* Avoid deadlock and lock recursion. */
2271 if (pmap > locked_pmap)
2273 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2275 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2281 * Destroy every non-wired, 4 KB page mapping in the chunk.
2284 for (field = 0; field < _NPCM; field++) {
2285 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2286 inuse != 0; inuse &= ~(1UL << bit)) {
2288 pv = &pc->pc_pventry[field * 32 + bit];
2290 pde = pmap_pde(pmap, va);
2291 if ((*pde & PG_PS) != 0)
2293 pte = pmap_pte(pmap, va);
2295 if ((tpte & PG_W) == 0)
2296 tpte = pte_load_clear(pte);
2297 pmap_pte_release(pte);
2298 if ((tpte & PG_W) != 0)
2301 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2303 if ((tpte & PG_G) != 0)
2304 pmap_invalidate_page(pmap, va);
2305 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2306 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2308 if ((tpte & PG_A) != 0)
2309 vm_page_aflag_set(m, PGA_REFERENCED);
2310 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2311 if (TAILQ_EMPTY(&m->md.pv_list) &&
2312 (m->flags & PG_FICTITIOUS) == 0) {
2313 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2314 if (TAILQ_EMPTY(&pvh->pv_list)) {
2315 vm_page_aflag_clear(m,
2319 pc->pc_map[field] |= 1UL << bit;
2320 pmap_unuse_pt(pmap, va, &free);
2325 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2328 /* Every freed mapping is for a 4 KB page. */
2329 pmap->pm_stats.resident_count -= freed;
2330 PV_STAT(pv_entry_frees += freed);
2331 PV_STAT(pv_entry_spare += freed);
2332 pv_entry_count -= freed;
2333 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2334 for (field = 0; field < _NPCM; field++)
2335 if (pc->pc_map[field] != pc_freemask[field]) {
2336 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2338 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2341 * One freed pv entry in locked_pmap is
2344 if (pmap == locked_pmap)
2348 if (field == _NPCM) {
2349 PV_STAT(pv_entry_spare -= _NPCPV);
2350 PV_STAT(pc_chunk_count--);
2351 PV_STAT(pc_chunk_frees++);
2352 /* Entire chunk is free; return it. */
2353 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2354 pmap_qremove((vm_offset_t)pc, 1);
2355 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2360 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2362 pmap_invalidate_all(pmap);
2363 if (pmap != locked_pmap)
2366 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2367 m_pc = SLIST_FIRST(&free);
2368 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2369 /* Recycle a freed page table page. */
2370 m_pc->wire_count = 1;
2372 vm_page_free_pages_toq(&free, true);
2377 * free the pv_entry back to the free list
2380 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2382 struct pv_chunk *pc;
2383 int idx, field, bit;
2385 rw_assert(&pvh_global_lock, RA_WLOCKED);
2386 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2387 PV_STAT(pv_entry_frees++);
2388 PV_STAT(pv_entry_spare++);
2390 pc = pv_to_chunk(pv);
2391 idx = pv - &pc->pc_pventry[0];
2394 pc->pc_map[field] |= 1ul << bit;
2395 for (idx = 0; idx < _NPCM; idx++)
2396 if (pc->pc_map[idx] != pc_freemask[idx]) {
2398 * 98% of the time, pc is already at the head of the
2399 * list. If it isn't already, move it to the head.
2401 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2403 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2404 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2409 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2414 free_pv_chunk(struct pv_chunk *pc)
2418 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2419 PV_STAT(pv_entry_spare -= _NPCPV);
2420 PV_STAT(pc_chunk_count--);
2421 PV_STAT(pc_chunk_frees++);
2422 /* entire chunk is free, return it */
2423 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2424 pmap_qremove((vm_offset_t)pc, 1);
2425 vm_page_unwire(m, PQ_NONE);
2427 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2431 * get a new pv_entry, allocating a block from the system
2435 get_pv_entry(pmap_t pmap, boolean_t try)
2437 static const struct timeval printinterval = { 60, 0 };
2438 static struct timeval lastprint;
2441 struct pv_chunk *pc;
2444 rw_assert(&pvh_global_lock, RA_WLOCKED);
2445 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2446 PV_STAT(pv_entry_allocs++);
2448 if (pv_entry_count > pv_entry_high_water)
2449 if (ratecheck(&lastprint, &printinterval))
2450 printf("Approaching the limit on PV entries, consider "
2451 "increasing either the vm.pmap.shpgperproc or the "
2452 "vm.pmap.pv_entry_max tunable.\n");
2454 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2456 for (field = 0; field < _NPCM; field++) {
2457 if (pc->pc_map[field]) {
2458 bit = bsfl(pc->pc_map[field]);
2462 if (field < _NPCM) {
2463 pv = &pc->pc_pventry[field * 32 + bit];
2464 pc->pc_map[field] &= ~(1ul << bit);
2465 /* If this was the last item, move it to tail */
2466 for (field = 0; field < _NPCM; field++)
2467 if (pc->pc_map[field] != 0) {
2468 PV_STAT(pv_entry_spare--);
2469 return (pv); /* not full, return */
2471 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2472 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2473 PV_STAT(pv_entry_spare--);
2478 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2479 * global lock. If "pv_vafree" is currently non-empty, it will
2480 * remain non-empty until pmap_ptelist_alloc() completes.
2482 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2483 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2486 PV_STAT(pc_chunk_tryfail++);
2489 m = pmap_pv_reclaim(pmap);
2493 PV_STAT(pc_chunk_count++);
2494 PV_STAT(pc_chunk_allocs++);
2495 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2496 pmap_qenter((vm_offset_t)pc, &m, 1);
2498 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2499 for (field = 1; field < _NPCM; field++)
2500 pc->pc_map[field] = pc_freemask[field];
2501 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2502 pv = &pc->pc_pventry[0];
2503 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2504 PV_STAT(pv_entry_spare += _NPCPV - 1);
2508 static __inline pv_entry_t
2509 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2513 rw_assert(&pvh_global_lock, RA_WLOCKED);
2514 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2515 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2516 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2524 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2526 struct md_page *pvh;
2528 vm_offset_t va_last;
2531 rw_assert(&pvh_global_lock, RA_WLOCKED);
2532 KASSERT((pa & PDRMASK) == 0,
2533 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2536 * Transfer the 4mpage's pv entry for this mapping to the first
2539 pvh = pa_to_pvh(pa);
2540 va = trunc_4mpage(va);
2541 pv = pmap_pvh_remove(pvh, pmap, va);
2542 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2543 m = PHYS_TO_VM_PAGE(pa);
2544 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2545 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2546 va_last = va + NBPDR - PAGE_SIZE;
2549 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2550 ("pmap_pv_demote_pde: page %p is not managed", m));
2552 pmap_insert_entry(pmap, va, m);
2553 } while (va < va_last);
2556 #if VM_NRESERVLEVEL > 0
2558 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2560 struct md_page *pvh;
2562 vm_offset_t va_last;
2565 rw_assert(&pvh_global_lock, RA_WLOCKED);
2566 KASSERT((pa & PDRMASK) == 0,
2567 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2570 * Transfer the first page's pv entry for this mapping to the
2571 * 4mpage's pv list. Aside from avoiding the cost of a call
2572 * to get_pv_entry(), a transfer avoids the possibility that
2573 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2574 * removes one of the mappings that is being promoted.
2576 m = PHYS_TO_VM_PAGE(pa);
2577 va = trunc_4mpage(va);
2578 pv = pmap_pvh_remove(&m->md, pmap, va);
2579 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2580 pvh = pa_to_pvh(pa);
2581 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2582 /* Free the remaining NPTEPG - 1 pv entries. */
2583 va_last = va + NBPDR - PAGE_SIZE;
2587 pmap_pvh_free(&m->md, pmap, va);
2588 } while (va < va_last);
2590 #endif /* VM_NRESERVLEVEL > 0 */
2593 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2597 pv = pmap_pvh_remove(pvh, pmap, va);
2598 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2599 free_pv_entry(pmap, pv);
2603 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2605 struct md_page *pvh;
2607 rw_assert(&pvh_global_lock, RA_WLOCKED);
2608 pmap_pvh_free(&m->md, pmap, va);
2609 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2610 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2611 if (TAILQ_EMPTY(&pvh->pv_list))
2612 vm_page_aflag_clear(m, PGA_WRITEABLE);
2617 * Create a pv entry for page at pa for
2621 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2625 rw_assert(&pvh_global_lock, RA_WLOCKED);
2626 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2627 pv = get_pv_entry(pmap, FALSE);
2629 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2633 * Conditionally create a pv entry.
2636 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2640 rw_assert(&pvh_global_lock, RA_WLOCKED);
2641 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2642 if (pv_entry_count < pv_entry_high_water &&
2643 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2645 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2652 * Create the pv entries for each of the pages within a superpage.
2655 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2657 struct md_page *pvh;
2660 rw_assert(&pvh_global_lock, RA_WLOCKED);
2661 if (pv_entry_count < pv_entry_high_water &&
2662 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2664 pvh = pa_to_pvh(pa);
2665 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2672 * Fills a page table page with mappings to consecutive physical pages.
2675 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2679 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2681 newpte += PAGE_SIZE;
2686 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2687 * 2- or 4MB page mapping is invalidated.
2690 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2692 pd_entry_t newpde, oldpde;
2693 pt_entry_t *firstpte, newpte;
2696 struct spglist free;
2699 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2701 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2702 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2703 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
2705 KASSERT((oldpde & PG_W) == 0,
2706 ("pmap_demote_pde: page table page for a wired mapping"
2710 * Invalidate the 2- or 4MB page mapping and return
2711 * "failure" if the mapping was never accessed or the
2712 * allocation of the new page table page fails.
2714 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2715 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2716 VM_ALLOC_WIRED)) == NULL) {
2718 sva = trunc_4mpage(va);
2719 pmap_remove_pde(pmap, pde, sva, &free);
2720 if ((oldpde & PG_G) == 0)
2721 pmap_invalidate_pde_page(pmap, sva, oldpde);
2722 vm_page_free_pages_toq(&free, true);
2723 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2724 " in pmap %p", va, pmap);
2727 if (pmap != kernel_pmap)
2728 pmap->pm_stats.resident_count++;
2730 mptepa = VM_PAGE_TO_PHYS(mpte);
2733 * If the page mapping is in the kernel's address space, then the
2734 * KPTmap can provide access to the page table page. Otherwise,
2735 * temporarily map the page table page (mpte) into the kernel's
2736 * address space at either PADDR1 or PADDR2.
2738 if (pmap == kernel_pmap)
2739 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2740 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2741 if ((*PMAP1 & PG_FRAME) != mptepa) {
2742 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2744 PMAP1cpu = PCPU_GET(cpuid);
2750 if (PMAP1cpu != PCPU_GET(cpuid)) {
2751 PMAP1cpu = PCPU_GET(cpuid);
2759 mtx_lock(&PMAP2mutex);
2760 if ((*PMAP2 & PG_FRAME) != mptepa) {
2761 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2762 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2766 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2767 KASSERT((oldpde & PG_A) != 0,
2768 ("pmap_demote_pde: oldpde is missing PG_A"));
2769 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2770 ("pmap_demote_pde: oldpde is missing PG_M"));
2771 newpte = oldpde & ~PG_PS;
2772 if ((newpte & PG_PDE_PAT) != 0)
2773 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2776 * If the page table page is new, initialize it.
2778 if (mpte->wire_count == 1) {
2779 mpte->wire_count = NPTEPG;
2780 pmap_fill_ptp(firstpte, newpte);
2782 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2783 ("pmap_demote_pde: firstpte and newpte map different physical"
2787 * If the mapping has changed attributes, update the page table
2790 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2791 pmap_fill_ptp(firstpte, newpte);
2794 * Demote the mapping. This pmap is locked. The old PDE has
2795 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2796 * set. Thus, there is no danger of a race with another
2797 * processor changing the setting of PG_A and/or PG_M between
2798 * the read above and the store below.
2800 if (workaround_erratum383)
2801 pmap_update_pde(pmap, va, pde, newpde);
2802 else if (pmap == kernel_pmap)
2803 pmap_kenter_pde(va, newpde);
2805 pde_store(pde, newpde);
2806 if (firstpte == PADDR2)
2807 mtx_unlock(&PMAP2mutex);
2810 * Invalidate the recursive mapping of the page table page.
2812 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2815 * Demote the pv entry. This depends on the earlier demotion
2816 * of the mapping. Specifically, the (re)creation of a per-
2817 * page pv entry might trigger the execution of pmap_collect(),
2818 * which might reclaim a newly (re)created per-page pv entry
2819 * and destroy the associated mapping. In order to destroy
2820 * the mapping, the PDE must have already changed from mapping
2821 * the 2mpage to referencing the page table page.
2823 if ((oldpde & PG_MANAGED) != 0)
2824 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2826 pmap_pde_demotions++;
2827 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2828 " in pmap %p", va, pmap);
2833 * Removes a 2- or 4MB page mapping from the kernel pmap.
2836 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2842 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2843 mpte = pmap_remove_pt_page(pmap, va);
2845 panic("pmap_remove_kernel_pde: Missing pt page.");
2847 mptepa = VM_PAGE_TO_PHYS(mpte);
2848 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2851 * Initialize the page table page.
2853 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2856 * Remove the mapping.
2858 if (workaround_erratum383)
2859 pmap_update_pde(pmap, va, pde, newpde);
2861 pmap_kenter_pde(va, newpde);
2864 * Invalidate the recursive mapping of the page table page.
2866 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2870 * pmap_remove_pde: do the things to unmap a superpage in a process
2873 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2874 struct spglist *free)
2876 struct md_page *pvh;
2878 vm_offset_t eva, va;
2881 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2882 KASSERT((sva & PDRMASK) == 0,
2883 ("pmap_remove_pde: sva is not 4mpage aligned"));
2884 oldpde = pte_load_clear(pdq);
2886 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2889 * Machines that don't support invlpg, also don't support
2892 if ((oldpde & PG_G) != 0)
2893 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
2895 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2896 if (oldpde & PG_MANAGED) {
2897 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2898 pmap_pvh_free(pvh, pmap, sva);
2900 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2901 va < eva; va += PAGE_SIZE, m++) {
2902 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2905 vm_page_aflag_set(m, PGA_REFERENCED);
2906 if (TAILQ_EMPTY(&m->md.pv_list) &&
2907 TAILQ_EMPTY(&pvh->pv_list))
2908 vm_page_aflag_clear(m, PGA_WRITEABLE);
2911 if (pmap == kernel_pmap) {
2912 pmap_remove_kernel_pde(pmap, pdq, sva);
2914 mpte = pmap_remove_pt_page(pmap, sva);
2916 pmap->pm_stats.resident_count--;
2917 KASSERT(mpte->wire_count == NPTEPG,
2918 ("pmap_remove_pde: pte page wire count error"));
2919 mpte->wire_count = 0;
2920 pmap_add_delayed_free_list(mpte, free, FALSE);
2926 * pmap_remove_pte: do the things to unmap a page in a process
2929 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
2930 struct spglist *free)
2935 rw_assert(&pvh_global_lock, RA_WLOCKED);
2936 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2937 oldpte = pte_load_clear(ptq);
2938 KASSERT(oldpte != 0,
2939 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
2941 pmap->pm_stats.wired_count -= 1;
2943 * Machines that don't support invlpg, also don't support
2947 pmap_invalidate_page(kernel_pmap, va);
2948 pmap->pm_stats.resident_count -= 1;
2949 if (oldpte & PG_MANAGED) {
2950 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2951 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2954 vm_page_aflag_set(m, PGA_REFERENCED);
2955 pmap_remove_entry(pmap, m, va);
2957 return (pmap_unuse_pt(pmap, va, free));
2961 * Remove a single page from a process address space
2964 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
2968 rw_assert(&pvh_global_lock, RA_WLOCKED);
2969 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
2970 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2971 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
2973 pmap_remove_pte(pmap, pte, va, free);
2974 pmap_invalidate_page(pmap, va);
2978 * Remove the given range of addresses from the specified map.
2980 * It is assumed that the start and end are properly
2981 * rounded to the page size.
2984 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2989 struct spglist free;
2993 * Perform an unsynchronized read. This is, however, safe.
2995 if (pmap->pm_stats.resident_count == 0)
3001 rw_wlock(&pvh_global_lock);
3006 * special handling of removing one page. a very
3007 * common operation and easy to short circuit some
3010 if ((sva + PAGE_SIZE == eva) &&
3011 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
3012 pmap_remove_page(pmap, sva, &free);
3016 for (; sva < eva; sva = pdnxt) {
3020 * Calculate index for next page table.
3022 pdnxt = (sva + NBPDR) & ~PDRMASK;
3025 if (pmap->pm_stats.resident_count == 0)
3028 pdirindex = sva >> PDRSHIFT;
3029 ptpaddr = pmap->pm_pdir[pdirindex];
3032 * Weed out invalid mappings. Note: we assume that the page
3033 * directory table is always allocated, and in kernel virtual.
3039 * Check for large page.
3041 if ((ptpaddr & PG_PS) != 0) {
3043 * Are we removing the entire large page? If not,
3044 * demote the mapping and fall through.
3046 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3048 * The TLB entry for a PG_G mapping is
3049 * invalidated by pmap_remove_pde().
3051 if ((ptpaddr & PG_G) == 0)
3053 pmap_remove_pde(pmap,
3054 &pmap->pm_pdir[pdirindex], sva, &free);
3056 } else if (!pmap_demote_pde(pmap,
3057 &pmap->pm_pdir[pdirindex], sva)) {
3058 /* The large page mapping was destroyed. */
3064 * Limit our scan to either the end of the va represented
3065 * by the current page table page, or to the end of the
3066 * range being removed.
3071 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3077 * The TLB entry for a PG_G mapping is invalidated
3078 * by pmap_remove_pte().
3080 if ((*pte & PG_G) == 0)
3082 if (pmap_remove_pte(pmap, pte, sva, &free))
3089 pmap_invalidate_all(pmap);
3090 rw_wunlock(&pvh_global_lock);
3092 vm_page_free_pages_toq(&free, true);
3096 * Routine: pmap_remove_all
3098 * Removes this physical page from
3099 * all physical maps in which it resides.
3100 * Reflects back modify bits to the pager.
3103 * Original versions of this routine were very
3104 * inefficient because they iteratively called
3105 * pmap_remove (slow...)
3109 pmap_remove_all(vm_page_t m)
3111 struct md_page *pvh;
3114 pt_entry_t *pte, tpte;
3117 struct spglist free;
3119 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3120 ("pmap_remove_all: page %p is not managed", m));
3122 rw_wlock(&pvh_global_lock);
3124 if ((m->flags & PG_FICTITIOUS) != 0)
3125 goto small_mappings;
3126 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3127 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3131 pde = pmap_pde(pmap, va);
3132 (void)pmap_demote_pde(pmap, pde, va);
3136 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3139 pmap->pm_stats.resident_count--;
3140 pde = pmap_pde(pmap, pv->pv_va);
3141 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3142 " a 4mpage in page %p's pv list", m));
3143 pte = pmap_pte_quick(pmap, pv->pv_va);
3144 tpte = pte_load_clear(pte);
3145 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3148 pmap->pm_stats.wired_count--;
3150 vm_page_aflag_set(m, PGA_REFERENCED);
3153 * Update the vm_page_t clean and reference bits.
3155 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3157 pmap_unuse_pt(pmap, pv->pv_va, &free);
3158 pmap_invalidate_page(pmap, pv->pv_va);
3159 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3160 free_pv_entry(pmap, pv);
3163 vm_page_aflag_clear(m, PGA_WRITEABLE);
3165 rw_wunlock(&pvh_global_lock);
3166 vm_page_free_pages_toq(&free, true);
3170 * pmap_protect_pde: do the things to protect a 4mpage in a process
3173 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3175 pd_entry_t newpde, oldpde;
3176 vm_offset_t eva, va;
3178 boolean_t anychanged;
3180 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3181 KASSERT((sva & PDRMASK) == 0,
3182 ("pmap_protect_pde: sva is not 4mpage aligned"));
3185 oldpde = newpde = *pde;
3186 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
3187 (PG_MANAGED | PG_M | PG_RW)) {
3189 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3190 va < eva; va += PAGE_SIZE, m++)
3193 if ((prot & VM_PROT_WRITE) == 0)
3194 newpde &= ~(PG_RW | PG_M);
3195 #if defined(PAE) || defined(PAE_TABLES)
3196 if ((prot & VM_PROT_EXECUTE) == 0)
3199 if (newpde != oldpde) {
3201 * As an optimization to future operations on this PDE, clear
3202 * PG_PROMOTED. The impending invalidation will remove any
3203 * lingering 4KB page mappings from the TLB.
3205 if (!pde_cmpset(pde, oldpde, newpde & ~PG_PROMOTED))
3207 if ((oldpde & PG_G) != 0)
3208 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
3212 return (anychanged);
3216 * Set the physical protection on the
3217 * specified range of this map as requested.
3220 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3225 boolean_t anychanged, pv_lists_locked;
3227 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3228 if (prot == VM_PROT_NONE) {
3229 pmap_remove(pmap, sva, eva);
3233 #if defined(PAE) || defined(PAE_TABLES)
3234 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3235 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3238 if (prot & VM_PROT_WRITE)
3242 if (pmap_is_current(pmap))
3243 pv_lists_locked = FALSE;
3245 pv_lists_locked = TRUE;
3247 rw_wlock(&pvh_global_lock);
3253 for (; sva < eva; sva = pdnxt) {
3254 pt_entry_t obits, pbits;
3257 pdnxt = (sva + NBPDR) & ~PDRMASK;
3261 pdirindex = sva >> PDRSHIFT;
3262 ptpaddr = pmap->pm_pdir[pdirindex];
3265 * Weed out invalid mappings. Note: we assume that the page
3266 * directory table is always allocated, and in kernel virtual.
3272 * Check for large page.
3274 if ((ptpaddr & PG_PS) != 0) {
3276 * Are we protecting the entire large page? If not,
3277 * demote the mapping and fall through.
3279 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3281 * The TLB entry for a PG_G mapping is
3282 * invalidated by pmap_protect_pde().
3284 if (pmap_protect_pde(pmap,
3285 &pmap->pm_pdir[pdirindex], sva, prot))
3289 if (!pv_lists_locked) {
3290 pv_lists_locked = TRUE;
3291 if (!rw_try_wlock(&pvh_global_lock)) {
3293 pmap_invalidate_all(
3300 if (!pmap_demote_pde(pmap,
3301 &pmap->pm_pdir[pdirindex], sva)) {
3303 * The large page mapping was
3314 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3320 * Regardless of whether a pte is 32 or 64 bits in
3321 * size, PG_RW, PG_A, and PG_M are among the least
3322 * significant 32 bits.
3324 obits = pbits = *pte;
3325 if ((pbits & PG_V) == 0)
3328 if ((prot & VM_PROT_WRITE) == 0) {
3329 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3330 (PG_MANAGED | PG_M | PG_RW)) {
3331 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3334 pbits &= ~(PG_RW | PG_M);
3336 #if defined(PAE) || defined(PAE_TABLES)
3337 if ((prot & VM_PROT_EXECUTE) == 0)
3341 if (pbits != obits) {
3342 #if defined(PAE) || defined(PAE_TABLES)
3343 if (!atomic_cmpset_64(pte, obits, pbits))
3346 if (!atomic_cmpset_int((u_int *)pte, obits,
3351 pmap_invalidate_page(pmap, sva);
3358 pmap_invalidate_all(pmap);
3359 if (pv_lists_locked) {
3361 rw_wunlock(&pvh_global_lock);
3366 #if VM_NRESERVLEVEL > 0
3368 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3369 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3370 * For promotion to occur, two conditions must be met: (1) the 4KB page
3371 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3372 * mappings must have identical characteristics.
3374 * Managed (PG_MANAGED) mappings within the kernel address space are not
3375 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3376 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3380 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3383 pt_entry_t *firstpte, oldpte, pa, *pte;
3384 vm_offset_t oldpteva;
3387 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3390 * Examine the first PTE in the specified PTP. Abort if this PTE is
3391 * either invalid, unused, or does not map the first 4KB physical page
3392 * within a 2- or 4MB page.
3394 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3397 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3398 pmap_pde_p_failures++;
3399 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3400 " in pmap %p", va, pmap);
3403 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3404 pmap_pde_p_failures++;
3405 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3406 " in pmap %p", va, pmap);
3409 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3411 * When PG_M is already clear, PG_RW can be cleared without
3412 * a TLB invalidation.
3414 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3421 * Examine each of the other PTEs in the specified PTP. Abort if this
3422 * PTE maps an unexpected 4KB physical page or does not have identical
3423 * characteristics to the first PTE.
3425 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3426 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3429 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3430 pmap_pde_p_failures++;
3431 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3432 " in pmap %p", va, pmap);
3435 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3437 * When PG_M is already clear, PG_RW can be cleared
3438 * without a TLB invalidation.
3440 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3444 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3446 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3447 " in pmap %p", oldpteva, pmap);
3449 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3450 pmap_pde_p_failures++;
3451 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3452 " in pmap %p", va, pmap);
3459 * Save the page table page in its current state until the PDE
3460 * mapping the superpage is demoted by pmap_demote_pde() or
3461 * destroyed by pmap_remove_pde().
3463 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3464 KASSERT(mpte >= vm_page_array &&
3465 mpte < &vm_page_array[vm_page_array_size],
3466 ("pmap_promote_pde: page table page is out of range"));
3467 KASSERT(mpte->pindex == va >> PDRSHIFT,
3468 ("pmap_promote_pde: page table page's pindex is wrong"));
3469 if (pmap_insert_pt_page(pmap, mpte)) {
3470 pmap_pde_p_failures++;
3472 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3478 * Promote the pv entries.
3480 if ((newpde & PG_MANAGED) != 0)
3481 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3484 * Propagate the PAT index to its proper position.
3486 if ((newpde & PG_PTE_PAT) != 0)
3487 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3490 * Map the superpage.
3492 if (workaround_erratum383)
3493 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3494 else if (pmap == kernel_pmap)
3495 pmap_kenter_pde(va, PG_PROMOTED | PG_PS | newpde);
3497 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
3499 pmap_pde_promotions++;
3500 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3501 " in pmap %p", va, pmap);
3503 #endif /* VM_NRESERVLEVEL > 0 */
3506 * Insert the given physical page (p) at
3507 * the specified virtual address (v) in the
3508 * target physical map with the protection requested.
3510 * If specified, the page will be wired down, meaning
3511 * that the related pte can not be reclaimed.
3513 * NB: This is the only routine which MAY NOT lazy-evaluate
3514 * or lose information. That is, this routine must actually
3515 * insert this page into the given map NOW.
3518 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3519 u_int flags, int8_t psind)
3523 pt_entry_t newpte, origpte;
3527 boolean_t invlva, wired;
3529 va = trunc_page(va);
3531 wired = (flags & PMAP_ENTER_WIRED) != 0;
3533 KASSERT((pmap == kernel_pmap && va < VM_MAX_KERNEL_ADDRESS) ||
3534 (pmap != kernel_pmap && va < VM_MAXUSER_ADDRESS),
3535 ("pmap_enter: toobig k%d %#x", pmap == kernel_pmap, va));
3536 KASSERT(va < PMAP_TRM_MIN_ADDRESS,
3537 ("pmap_enter: invalid to pmap_enter into trampoline (va: 0x%x)",
3539 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3540 VM_OBJECT_ASSERT_LOCKED(m->object);
3542 rw_wlock(&pvh_global_lock);
3546 pde = pmap_pde(pmap, va);
3547 if (pmap != kernel_pmap) {
3550 * In the case that a page table page is not resident,
3551 * we are creating it here. pmap_allocpte() handles
3554 mpte = pmap_allocpte(pmap, va, flags);
3556 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3557 ("pmap_allocpte failed with sleep allowed"));
3559 rw_wunlock(&pvh_global_lock);
3561 return (KERN_RESOURCE_SHORTAGE);
3565 * va is for KVA, so pmap_demote_pde() will never fail
3566 * to install a page table page. PG_V is also
3567 * asserted by pmap_demote_pde().
3569 KASSERT(pde != NULL && (*pde & PG_V) != 0,
3570 ("KVA %#x invalid pde pdir %#jx", va,
3571 (uintmax_t)pmap->pm_pdir[PTDPTDI]));
3572 if ((*pde & PG_PS) != 0)
3573 pmap_demote_pde(pmap, pde, va);
3575 pte = pmap_pte_quick(pmap, va);
3578 * Page Directory table entry is not valid, which should not
3579 * happen. We should have either allocated the page table
3580 * page or demoted the existing mapping above.
3583 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3584 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3587 pa = VM_PAGE_TO_PHYS(m);
3590 opa = origpte & PG_FRAME;
3593 * Mapping has not changed, must be protection or wiring change.
3595 if (origpte && (opa == pa)) {
3597 * Wiring change, just update stats. We don't worry about
3598 * wiring PT pages as they remain resident as long as there
3599 * are valid mappings in them. Hence, if a user page is wired,
3600 * the PT page will be also.
3602 if (wired && ((origpte & PG_W) == 0))
3603 pmap->pm_stats.wired_count++;
3604 else if (!wired && (origpte & PG_W))
3605 pmap->pm_stats.wired_count--;
3608 * Remove extra pte reference
3613 if (origpte & PG_MANAGED) {
3623 * Mapping has changed, invalidate old range and fall through to
3624 * handle validating new mapping.
3628 pmap->pm_stats.wired_count--;
3629 if (origpte & PG_MANAGED) {
3630 om = PHYS_TO_VM_PAGE(opa);
3631 pv = pmap_pvh_remove(&om->md, pmap, va);
3635 KASSERT(mpte->wire_count > 0,
3636 ("pmap_enter: missing reference to page table page,"
3640 pmap->pm_stats.resident_count++;
3643 * Enter on the PV list if part of our managed memory.
3645 if ((m->oflags & VPO_UNMANAGED) == 0) {
3646 KASSERT(pmap != kernel_pmap || va < kmi.clean_sva ||
3647 va >= kmi.clean_eva,
3648 ("pmap_enter: managed mapping within the clean submap"));
3650 pv = get_pv_entry(pmap, FALSE);
3652 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3654 } else if (pv != NULL)
3655 free_pv_entry(pmap, pv);
3658 * Increment counters
3661 pmap->pm_stats.wired_count++;
3665 * Now validate mapping with desired protection/wiring.
3667 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V);
3668 if ((prot & VM_PROT_WRITE) != 0) {
3670 if ((newpte & PG_MANAGED) != 0)
3671 vm_page_aflag_set(m, PGA_WRITEABLE);
3673 #if defined(PAE) || defined(PAE_TABLES)
3674 if ((prot & VM_PROT_EXECUTE) == 0)
3679 if (pmap != kernel_pmap)
3683 * if the mapping or permission bits are different, we need
3684 * to update the pte.
3686 if ((origpte & ~(PG_M|PG_A)) != newpte) {
3688 if ((flags & VM_PROT_WRITE) != 0)
3690 if (origpte & PG_V) {
3692 origpte = pte_load_store(pte, newpte);
3693 if (origpte & PG_A) {
3694 if (origpte & PG_MANAGED)
3695 vm_page_aflag_set(om, PGA_REFERENCED);
3696 if (opa != VM_PAGE_TO_PHYS(m))
3698 #if defined(PAE) || defined(PAE_TABLES)
3699 if ((origpte & PG_NX) == 0 &&
3700 (newpte & PG_NX) != 0)
3704 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
3705 if ((origpte & PG_MANAGED) != 0)
3707 if ((prot & VM_PROT_WRITE) == 0)
3710 if ((origpte & PG_MANAGED) != 0 &&
3711 TAILQ_EMPTY(&om->md.pv_list) &&
3712 ((om->flags & PG_FICTITIOUS) != 0 ||
3713 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3714 vm_page_aflag_clear(om, PGA_WRITEABLE);
3716 pmap_invalidate_page(pmap, va);
3718 pte_store(pte, newpte);
3721 #if VM_NRESERVLEVEL > 0
3723 * If both the page table page and the reservation are fully
3724 * populated, then attempt promotion.
3726 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3727 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3728 vm_reserv_level_iffullpop(m) == 0)
3729 pmap_promote_pde(pmap, pde, va);
3733 rw_wunlock(&pvh_global_lock);
3735 return (KERN_SUCCESS);
3739 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and
3740 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
3741 * blocking, (2) a mapping already exists at the specified virtual address, or
3742 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3745 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3747 pd_entry_t *pde, newpde;
3749 rw_assert(&pvh_global_lock, RA_WLOCKED);
3750 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3751 pde = pmap_pde(pmap, va);
3753 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3754 " in pmap %p", va, pmap);
3757 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3759 if ((m->oflags & VPO_UNMANAGED) == 0) {
3760 newpde |= PG_MANAGED;
3763 * Abort this mapping if its PV entry could not be created.
3765 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) {
3766 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3767 " in pmap %p", va, pmap);
3771 #if defined(PAE) || defined(PAE_TABLES)
3772 if ((prot & VM_PROT_EXECUTE) == 0)
3775 if (va < VM_MAXUSER_ADDRESS)
3779 * Increment counters.
3781 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3784 * Map the superpage. (This is not a promoted mapping; there will not
3785 * be any lingering 4KB page mappings in the TLB.)
3787 pde_store(pde, newpde);
3789 pmap_pde_mappings++;
3790 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3791 " in pmap %p", va, pmap);
3796 * Maps a sequence of resident pages belonging to the same object.
3797 * The sequence begins with the given page m_start. This page is
3798 * mapped at the given virtual address start. Each subsequent page is
3799 * mapped at a virtual address that is offset from start by the same
3800 * amount as the page is offset from m_start within the object. The
3801 * last page in the sequence is the page with the largest offset from
3802 * m_start that can be mapped at a virtual address less than the given
3803 * virtual address end. Not every virtual page between start and end
3804 * is mapped; only those for which a resident page exists with the
3805 * corresponding offset from m_start are mapped.
3808 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3809 vm_page_t m_start, vm_prot_t prot)
3813 vm_pindex_t diff, psize;
3815 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3817 psize = atop(end - start);
3820 rw_wlock(&pvh_global_lock);
3822 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3823 va = start + ptoa(diff);
3824 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3825 m->psind == 1 && pg_ps_enabled &&
3826 pmap_enter_pde(pmap, va, m, prot))
3827 m = &m[NBPDR / PAGE_SIZE - 1];
3829 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3831 m = TAILQ_NEXT(m, listq);
3833 rw_wunlock(&pvh_global_lock);
3838 * this code makes some *MAJOR* assumptions:
3839 * 1. Current pmap & pmap exists.
3842 * 4. No page table pages.
3843 * but is *MUCH* faster than pmap_enter...
3847 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3850 rw_wlock(&pvh_global_lock);
3852 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
3853 rw_wunlock(&pvh_global_lock);
3858 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3859 vm_prot_t prot, vm_page_t mpte)
3863 struct spglist free;
3865 KASSERT(pmap != kernel_pmap || va < kmi.clean_sva ||
3866 va >= kmi.clean_eva || (m->oflags & VPO_UNMANAGED) != 0,
3867 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3868 rw_assert(&pvh_global_lock, RA_WLOCKED);
3869 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3872 * In the case that a page table page is not
3873 * resident, we are creating it here.
3875 if (pmap != kernel_pmap) {
3880 * Calculate pagetable page index
3882 ptepindex = va >> PDRSHIFT;
3883 if (mpte && (mpte->pindex == ptepindex)) {
3887 * Get the page directory entry
3889 ptepa = pmap->pm_pdir[ptepindex];
3892 * If the page table page is mapped, we just increment
3893 * the hold count, and activate it.
3898 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
3901 mpte = _pmap_allocpte(pmap, ptepindex,
3902 PMAP_ENTER_NOSLEEP);
3911 /* XXXKIB: pmap_pte_quick() instead ? */
3912 pte = pmap_pte(pmap, va);
3918 pmap_pte_release(pte);
3923 * Enter on the PV list if part of our managed memory.
3925 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3926 !pmap_try_insert_pv_entry(pmap, va, m)) {
3929 if (pmap_unwire_ptp(pmap, mpte, &free)) {
3930 pmap_invalidate_page(pmap, va);
3931 vm_page_free_pages_toq(&free, true);
3936 pmap_pte_release(pte);
3941 * Increment counters
3943 pmap->pm_stats.resident_count++;
3945 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3946 #if defined(PAE) || defined(PAE_TABLES)
3947 if ((prot & VM_PROT_EXECUTE) == 0)
3952 * Now validate mapping with RO protection
3954 if ((m->oflags & VPO_UNMANAGED) != 0)
3955 pte_store(pte, pa | PG_V | PG_U);
3957 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3958 pmap_pte_release(pte);
3963 * Make a temporary mapping for a physical address. This is only intended
3964 * to be used for panic dumps.
3967 pmap_kenter_temporary(vm_paddr_t pa, int i)
3971 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3972 pmap_kenter(va, pa);
3974 return ((void *)crashdumpmap);
3978 * This code maps large physical mmap regions into the
3979 * processor address space. Note that some shortcuts
3980 * are taken, but the code works.
3983 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3984 vm_pindex_t pindex, vm_size_t size)
3987 vm_paddr_t pa, ptepa;
3991 VM_OBJECT_ASSERT_WLOCKED(object);
3992 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3993 ("pmap_object_init_pt: non-device object"));
3995 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3996 if (!vm_object_populate(object, pindex, pindex + atop(size)))
3998 p = vm_page_lookup(object, pindex);
3999 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4000 ("pmap_object_init_pt: invalid page %p", p));
4001 pat_mode = p->md.pat_mode;
4004 * Abort the mapping if the first page is not physically
4005 * aligned to a 2/4MB page boundary.
4007 ptepa = VM_PAGE_TO_PHYS(p);
4008 if (ptepa & (NBPDR - 1))
4012 * Skip the first page. Abort the mapping if the rest of
4013 * the pages are not physically contiguous or have differing
4014 * memory attributes.
4016 p = TAILQ_NEXT(p, listq);
4017 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4019 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4020 ("pmap_object_init_pt: invalid page %p", p));
4021 if (pa != VM_PAGE_TO_PHYS(p) ||
4022 pat_mode != p->md.pat_mode)
4024 p = TAILQ_NEXT(p, listq);
4028 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
4029 * "size" is a multiple of 2/4M, adding the PAT setting to
4030 * "pa" will not affect the termination of this loop.
4033 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
4034 size; pa += NBPDR) {
4035 pde = pmap_pde(pmap, addr);
4037 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4038 PG_U | PG_RW | PG_V);
4039 pmap->pm_stats.resident_count += NBPDR /
4041 pmap_pde_mappings++;
4043 /* Else continue on if the PDE is already valid. */
4051 * Clear the wired attribute from the mappings for the specified range of
4052 * addresses in the given pmap. Every valid mapping within that range
4053 * must have the wired attribute set. In contrast, invalid mappings
4054 * cannot have the wired attribute set, so they are ignored.
4056 * The wired attribute of the page table entry is not a hardware feature,
4057 * so there is no need to invalidate any TLB entries.
4060 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4065 boolean_t pv_lists_locked;
4067 if (pmap_is_current(pmap))
4068 pv_lists_locked = FALSE;
4070 pv_lists_locked = TRUE;
4072 rw_wlock(&pvh_global_lock);
4076 for (; sva < eva; sva = pdnxt) {
4077 pdnxt = (sva + NBPDR) & ~PDRMASK;
4080 pde = pmap_pde(pmap, sva);
4081 if ((*pde & PG_V) == 0)
4083 if ((*pde & PG_PS) != 0) {
4084 if ((*pde & PG_W) == 0)
4085 panic("pmap_unwire: pde %#jx is missing PG_W",
4089 * Are we unwiring the entire large page? If not,
4090 * demote the mapping and fall through.
4092 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4094 * Regardless of whether a pde (or pte) is 32
4095 * or 64 bits in size, PG_W is among the least
4096 * significant 32 bits.
4098 atomic_clear_int((u_int *)pde, PG_W);
4099 pmap->pm_stats.wired_count -= NBPDR /
4103 if (!pv_lists_locked) {
4104 pv_lists_locked = TRUE;
4105 if (!rw_try_wlock(&pvh_global_lock)) {
4112 if (!pmap_demote_pde(pmap, pde, sva))
4113 panic("pmap_unwire: demotion failed");
4118 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4120 if ((*pte & PG_V) == 0)
4122 if ((*pte & PG_W) == 0)
4123 panic("pmap_unwire: pte %#jx is missing PG_W",
4127 * PG_W must be cleared atomically. Although the pmap
4128 * lock synchronizes access to PG_W, another processor
4129 * could be setting PG_M and/or PG_A concurrently.
4131 * PG_W is among the least significant 32 bits.
4133 atomic_clear_int((u_int *)pte, PG_W);
4134 pmap->pm_stats.wired_count--;
4137 if (pv_lists_locked) {
4139 rw_wunlock(&pvh_global_lock);
4146 * Copy the range specified by src_addr/len
4147 * from the source map to the range dst_addr/len
4148 * in the destination map.
4150 * This routine is only advisory and need not do anything. Since
4151 * current pmap is always the kernel pmap when executing in
4152 * kernel, and we do not copy from the kernel pmap to a user
4153 * pmap, this optimization is not usable in 4/4G full split i386
4158 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4159 vm_offset_t src_addr)
4164 * Zero 1 page of virtual memory mapped from a hardware page by the caller.
4166 static __inline void
4167 pagezero(void *page)
4169 #if defined(I686_CPU)
4170 if (cpu_class == CPUCLASS_686) {
4171 if (cpu_feature & CPUID_SSE2)
4172 sse2_pagezero(page);
4174 i686_pagezero(page);
4177 bzero(page, PAGE_SIZE);
4181 * Zero the specified hardware page.
4184 pmap_zero_page(vm_page_t m)
4186 pt_entry_t *cmap_pte2;
4191 cmap_pte2 = pc->pc_cmap_pte2;
4192 mtx_lock(&pc->pc_cmap_lock);
4194 panic("pmap_zero_page: CMAP2 busy");
4195 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4196 pmap_cache_bits(m->md.pat_mode, 0);
4197 invlcaddr(pc->pc_cmap_addr2);
4198 pagezero(pc->pc_cmap_addr2);
4202 * Unpin the thread before releasing the lock. Otherwise the thread
4203 * could be rescheduled while still bound to the current CPU, only
4204 * to unpin itself immediately upon resuming execution.
4207 mtx_unlock(&pc->pc_cmap_lock);
4211 * Zero an an area within a single hardware page. off and size must not
4212 * cover an area beyond a single hardware page.
4215 pmap_zero_page_area(vm_page_t m, int off, int size)
4217 pt_entry_t *cmap_pte2;
4222 cmap_pte2 = pc->pc_cmap_pte2;
4223 mtx_lock(&pc->pc_cmap_lock);
4225 panic("pmap_zero_page_area: CMAP2 busy");
4226 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4227 pmap_cache_bits(m->md.pat_mode, 0);
4228 invlcaddr(pc->pc_cmap_addr2);
4229 if (off == 0 && size == PAGE_SIZE)
4230 pagezero(pc->pc_cmap_addr2);
4232 bzero(pc->pc_cmap_addr2 + off, size);
4235 mtx_unlock(&pc->pc_cmap_lock);
4239 * Copy 1 specified hardware page to another.
4242 pmap_copy_page(vm_page_t src, vm_page_t dst)
4244 pt_entry_t *cmap_pte1, *cmap_pte2;
4249 cmap_pte1 = pc->pc_cmap_pte1;
4250 cmap_pte2 = pc->pc_cmap_pte2;
4251 mtx_lock(&pc->pc_cmap_lock);
4253 panic("pmap_copy_page: CMAP1 busy");
4255 panic("pmap_copy_page: CMAP2 busy");
4256 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4257 pmap_cache_bits(src->md.pat_mode, 0);
4258 invlcaddr(pc->pc_cmap_addr1);
4259 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4260 pmap_cache_bits(dst->md.pat_mode, 0);
4261 invlcaddr(pc->pc_cmap_addr2);
4262 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE);
4266 mtx_unlock(&pc->pc_cmap_lock);
4269 int unmapped_buf_allowed = 1;
4272 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4273 vm_offset_t b_offset, int xfersize)
4275 vm_page_t a_pg, b_pg;
4277 vm_offset_t a_pg_offset, b_pg_offset;
4278 pt_entry_t *cmap_pte1, *cmap_pte2;
4284 cmap_pte1 = pc->pc_cmap_pte1;
4285 cmap_pte2 = pc->pc_cmap_pte2;
4286 mtx_lock(&pc->pc_cmap_lock);
4287 if (*cmap_pte1 != 0)
4288 panic("pmap_copy_pages: CMAP1 busy");
4289 if (*cmap_pte2 != 0)
4290 panic("pmap_copy_pages: CMAP2 busy");
4291 while (xfersize > 0) {
4292 a_pg = ma[a_offset >> PAGE_SHIFT];
4293 a_pg_offset = a_offset & PAGE_MASK;
4294 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4295 b_pg = mb[b_offset >> PAGE_SHIFT];
4296 b_pg_offset = b_offset & PAGE_MASK;
4297 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4298 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4299 pmap_cache_bits(a_pg->md.pat_mode, 0);
4300 invlcaddr(pc->pc_cmap_addr1);
4301 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4302 PG_M | pmap_cache_bits(b_pg->md.pat_mode, 0);
4303 invlcaddr(pc->pc_cmap_addr2);
4304 a_cp = pc->pc_cmap_addr1 + a_pg_offset;
4305 b_cp = pc->pc_cmap_addr2 + b_pg_offset;
4306 bcopy(a_cp, b_cp, cnt);
4314 mtx_unlock(&pc->pc_cmap_lock);
4318 * Returns true if the pmap's pv is one of the first
4319 * 16 pvs linked to from this page. This count may
4320 * be changed upwards or downwards in the future; it
4321 * is only necessary that true be returned for a small
4322 * subset of pmaps for proper page aging.
4325 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4327 struct md_page *pvh;
4332 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4333 ("pmap_page_exists_quick: page %p is not managed", m));
4335 rw_wlock(&pvh_global_lock);
4336 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4337 if (PV_PMAP(pv) == pmap) {
4345 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4346 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4347 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4348 if (PV_PMAP(pv) == pmap) {
4357 rw_wunlock(&pvh_global_lock);
4362 * pmap_page_wired_mappings:
4364 * Return the number of managed mappings to the given physical page
4368 pmap_page_wired_mappings(vm_page_t m)
4373 if ((m->oflags & VPO_UNMANAGED) != 0)
4375 rw_wlock(&pvh_global_lock);
4376 count = pmap_pvh_wired_mappings(&m->md, count);
4377 if ((m->flags & PG_FICTITIOUS) == 0) {
4378 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4381 rw_wunlock(&pvh_global_lock);
4386 * pmap_pvh_wired_mappings:
4388 * Return the updated number "count" of managed mappings that are wired.
4391 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4397 rw_assert(&pvh_global_lock, RA_WLOCKED);
4399 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4402 pte = pmap_pte_quick(pmap, pv->pv_va);
4403 if ((*pte & PG_W) != 0)
4412 * Returns TRUE if the given page is mapped individually or as part of
4413 * a 4mpage. Otherwise, returns FALSE.
4416 pmap_page_is_mapped(vm_page_t m)
4420 if ((m->oflags & VPO_UNMANAGED) != 0)
4422 rw_wlock(&pvh_global_lock);
4423 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4424 ((m->flags & PG_FICTITIOUS) == 0 &&
4425 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4426 rw_wunlock(&pvh_global_lock);
4431 * Remove all pages from specified address space
4432 * this aids process exit speeds. Also, this code
4433 * is special cased for current process only, but
4434 * can have the more generic (and slightly slower)
4435 * mode enabled. This is much faster than pmap_remove
4436 * in the case of running down an entire address space.
4439 pmap_remove_pages(pmap_t pmap)
4441 pt_entry_t *pte, tpte;
4442 vm_page_t m, mpte, mt;
4444 struct md_page *pvh;
4445 struct pv_chunk *pc, *npc;
4446 struct spglist free;
4449 uint32_t inuse, bitmask;
4452 if (pmap != PCPU_GET(curpmap)) {
4453 printf("warning: pmap_remove_pages called with non-current pmap\n");
4457 rw_wlock(&pvh_global_lock);
4460 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4461 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4464 for (field = 0; field < _NPCM; field++) {
4465 inuse = ~pc->pc_map[field] & pc_freemask[field];
4466 while (inuse != 0) {
4468 bitmask = 1UL << bit;
4469 idx = field * 32 + bit;
4470 pv = &pc->pc_pventry[idx];
4473 pte = pmap_pde(pmap, pv->pv_va);
4475 if ((tpte & PG_PS) == 0) {
4476 pte = pmap_pte_quick(pmap, pv->pv_va);
4477 tpte = *pte & ~PG_PTE_PAT;
4482 "TPTE at %p IS ZERO @ VA %08x\n",
4488 * We cannot remove wired pages from a process' mapping at this time
4495 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4496 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4497 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4498 m, (uintmax_t)m->phys_addr,
4501 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4502 m < &vm_page_array[vm_page_array_size],
4503 ("pmap_remove_pages: bad tpte %#jx",
4509 * Update the vm_page_t clean/reference bits.
4511 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4512 if ((tpte & PG_PS) != 0) {
4513 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4520 PV_STAT(pv_entry_frees++);
4521 PV_STAT(pv_entry_spare++);
4523 pc->pc_map[field] |= bitmask;
4524 if ((tpte & PG_PS) != 0) {
4525 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4526 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4527 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4528 if (TAILQ_EMPTY(&pvh->pv_list)) {
4529 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4530 if (TAILQ_EMPTY(&mt->md.pv_list))
4531 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4533 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
4535 pmap->pm_stats.resident_count--;
4536 KASSERT(mpte->wire_count == NPTEPG,
4537 ("pmap_remove_pages: pte page wire count error"));
4538 mpte->wire_count = 0;
4539 pmap_add_delayed_free_list(mpte, &free, FALSE);
4542 pmap->pm_stats.resident_count--;
4543 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4544 if (TAILQ_EMPTY(&m->md.pv_list) &&
4545 (m->flags & PG_FICTITIOUS) == 0) {
4546 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4547 if (TAILQ_EMPTY(&pvh->pv_list))
4548 vm_page_aflag_clear(m, PGA_WRITEABLE);
4550 pmap_unuse_pt(pmap, pv->pv_va, &free);
4555 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4560 pmap_invalidate_all(pmap);
4561 rw_wunlock(&pvh_global_lock);
4563 vm_page_free_pages_toq(&free, true);
4569 * Return whether or not the specified physical page was modified
4570 * in any physical maps.
4573 pmap_is_modified(vm_page_t m)
4577 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4578 ("pmap_is_modified: page %p is not managed", m));
4581 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4582 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4583 * is clear, no PTEs can have PG_M set.
4585 VM_OBJECT_ASSERT_WLOCKED(m->object);
4586 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4588 rw_wlock(&pvh_global_lock);
4589 rv = pmap_is_modified_pvh(&m->md) ||
4590 ((m->flags & PG_FICTITIOUS) == 0 &&
4591 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4592 rw_wunlock(&pvh_global_lock);
4597 * Returns TRUE if any of the given mappings were used to modify
4598 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4599 * mappings are supported.
4602 pmap_is_modified_pvh(struct md_page *pvh)
4609 rw_assert(&pvh_global_lock, RA_WLOCKED);
4612 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4615 pte = pmap_pte_quick(pmap, pv->pv_va);
4616 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4626 * pmap_is_prefaultable:
4628 * Return whether or not the specified virtual address is elgible
4632 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4640 pde = pmap_pde(pmap, addr);
4641 if (*pde != 0 && (*pde & PG_PS) == 0) {
4642 pte = pmap_pte(pmap, addr);
4645 pmap_pte_release(pte);
4652 * pmap_is_referenced:
4654 * Return whether or not the specified physical page was referenced
4655 * in any physical maps.
4658 pmap_is_referenced(vm_page_t m)
4662 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4663 ("pmap_is_referenced: page %p is not managed", m));
4664 rw_wlock(&pvh_global_lock);
4665 rv = pmap_is_referenced_pvh(&m->md) ||
4666 ((m->flags & PG_FICTITIOUS) == 0 &&
4667 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4668 rw_wunlock(&pvh_global_lock);
4673 * Returns TRUE if any of the given mappings were referenced and FALSE
4674 * otherwise. Both page and 4mpage mappings are supported.
4677 pmap_is_referenced_pvh(struct md_page *pvh)
4684 rw_assert(&pvh_global_lock, RA_WLOCKED);
4687 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4690 pte = pmap_pte_quick(pmap, pv->pv_va);
4691 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4701 * Clear the write and modified bits in each of the given page's mappings.
4704 pmap_remove_write(vm_page_t m)
4706 struct md_page *pvh;
4707 pv_entry_t next_pv, pv;
4710 pt_entry_t oldpte, *pte;
4713 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4714 ("pmap_remove_write: page %p is not managed", m));
4717 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4718 * set by another thread while the object is locked. Thus,
4719 * if PGA_WRITEABLE is clear, no page table entries need updating.
4721 VM_OBJECT_ASSERT_WLOCKED(m->object);
4722 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4724 rw_wlock(&pvh_global_lock);
4726 if ((m->flags & PG_FICTITIOUS) != 0)
4727 goto small_mappings;
4728 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4729 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4733 pde = pmap_pde(pmap, va);
4734 if ((*pde & PG_RW) != 0)
4735 (void)pmap_demote_pde(pmap, pde, va);
4739 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4742 pde = pmap_pde(pmap, pv->pv_va);
4743 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
4744 " a 4mpage in page %p's pv list", m));
4745 pte = pmap_pte_quick(pmap, pv->pv_va);
4748 if ((oldpte & PG_RW) != 0) {
4750 * Regardless of whether a pte is 32 or 64 bits
4751 * in size, PG_RW and PG_M are among the least
4752 * significant 32 bits.
4754 if (!atomic_cmpset_int((u_int *)pte, oldpte,
4755 oldpte & ~(PG_RW | PG_M)))
4757 if ((oldpte & PG_M) != 0)
4759 pmap_invalidate_page(pmap, pv->pv_va);
4763 vm_page_aflag_clear(m, PGA_WRITEABLE);
4765 rw_wunlock(&pvh_global_lock);
4769 * pmap_ts_referenced:
4771 * Return a count of reference bits for a page, clearing those bits.
4772 * It is not necessary for every reference bit to be cleared, but it
4773 * is necessary that 0 only be returned when there are truly no
4774 * reference bits set.
4776 * As an optimization, update the page's dirty field if a modified bit is
4777 * found while counting reference bits. This opportunistic update can be
4778 * performed at low cost and can eliminate the need for some future calls
4779 * to pmap_is_modified(). However, since this function stops after
4780 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4781 * dirty pages. Those dirty pages will only be detected by a future call
4782 * to pmap_is_modified().
4785 pmap_ts_referenced(vm_page_t m)
4787 struct md_page *pvh;
4795 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4796 ("pmap_ts_referenced: page %p is not managed", m));
4797 pa = VM_PAGE_TO_PHYS(m);
4798 pvh = pa_to_pvh(pa);
4799 rw_wlock(&pvh_global_lock);
4801 if ((m->flags & PG_FICTITIOUS) != 0 ||
4802 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4803 goto small_mappings;
4808 pde = pmap_pde(pmap, pv->pv_va);
4809 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4811 * Although "*pde" is mapping a 2/4MB page, because
4812 * this function is called at a 4KB page granularity,
4813 * we only update the 4KB page under test.
4817 if ((*pde & PG_A) != 0) {
4819 * Since this reference bit is shared by either 1024
4820 * or 512 4KB pages, it should not be cleared every
4821 * time it is tested. Apply a simple "hash" function
4822 * on the physical page number, the virtual superpage
4823 * number, and the pmap address to select one 4KB page
4824 * out of the 1024 or 512 on which testing the
4825 * reference bit will result in clearing that bit.
4826 * This function is designed to avoid the selection of
4827 * the same 4KB page for every 2- or 4MB page mapping.
4829 * On demotion, a mapping that hasn't been referenced
4830 * is simply destroyed. To avoid the possibility of a
4831 * subsequent page fault on a demoted wired mapping,
4832 * always leave its reference bit set. Moreover,
4833 * since the superpage is wired, the current state of
4834 * its reference bit won't affect page replacement.
4836 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
4837 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
4838 (*pde & PG_W) == 0) {
4839 atomic_clear_int((u_int *)pde, PG_A);
4840 pmap_invalidate_page(pmap, pv->pv_va);
4845 /* Rotate the PV list if it has more than one entry. */
4846 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4847 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4848 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4850 if (rtval >= PMAP_TS_REFERENCED_MAX)
4852 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4854 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4860 pde = pmap_pde(pmap, pv->pv_va);
4861 KASSERT((*pde & PG_PS) == 0,
4862 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
4864 pte = pmap_pte_quick(pmap, pv->pv_va);
4865 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4867 if ((*pte & PG_A) != 0) {
4868 atomic_clear_int((u_int *)pte, PG_A);
4869 pmap_invalidate_page(pmap, pv->pv_va);
4873 /* Rotate the PV list if it has more than one entry. */
4874 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4875 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4876 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4878 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
4879 PMAP_TS_REFERENCED_MAX);
4882 rw_wunlock(&pvh_global_lock);
4887 * Apply the given advice to the specified range of addresses within the
4888 * given pmap. Depending on the advice, clear the referenced and/or
4889 * modified flags in each mapping and set the mapped page's dirty field.
4892 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4894 pd_entry_t oldpde, *pde;
4896 vm_offset_t va, pdnxt;
4898 boolean_t anychanged, pv_lists_locked;
4900 if (advice != MADV_DONTNEED && advice != MADV_FREE)
4902 if (pmap_is_current(pmap))
4903 pv_lists_locked = FALSE;
4905 pv_lists_locked = TRUE;
4907 rw_wlock(&pvh_global_lock);
4912 for (; sva < eva; sva = pdnxt) {
4913 pdnxt = (sva + NBPDR) & ~PDRMASK;
4916 pde = pmap_pde(pmap, sva);
4918 if ((oldpde & PG_V) == 0)
4920 else if ((oldpde & PG_PS) != 0) {
4921 if ((oldpde & PG_MANAGED) == 0)
4923 if (!pv_lists_locked) {
4924 pv_lists_locked = TRUE;
4925 if (!rw_try_wlock(&pvh_global_lock)) {
4927 pmap_invalidate_all(pmap);
4933 if (!pmap_demote_pde(pmap, pde, sva)) {
4935 * The large page mapping was destroyed.
4941 * Unless the page mappings are wired, remove the
4942 * mapping to a single page so that a subsequent
4943 * access may repromote. Since the underlying page
4944 * table page is fully populated, this removal never
4945 * frees a page table page.
4947 if ((oldpde & PG_W) == 0) {
4948 pte = pmap_pte_quick(pmap, sva);
4949 KASSERT((*pte & PG_V) != 0,
4950 ("pmap_advise: invalid PTE"));
4951 pmap_remove_pte(pmap, pte, sva, NULL);
4958 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4960 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
4962 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4963 if (advice == MADV_DONTNEED) {
4965 * Future calls to pmap_is_modified()
4966 * can be avoided by making the page
4969 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
4972 atomic_clear_int((u_int *)pte, PG_M | PG_A);
4973 } else if ((*pte & PG_A) != 0)
4974 atomic_clear_int((u_int *)pte, PG_A);
4977 if ((*pte & PG_G) != 0) {
4985 pmap_invalidate_range(pmap, va, sva);
4990 pmap_invalidate_range(pmap, va, sva);
4993 pmap_invalidate_all(pmap);
4994 if (pv_lists_locked) {
4996 rw_wunlock(&pvh_global_lock);
5002 * Clear the modify bits on the specified physical page.
5005 pmap_clear_modify(vm_page_t m)
5007 struct md_page *pvh;
5008 pv_entry_t next_pv, pv;
5010 pd_entry_t oldpde, *pde;
5011 pt_entry_t oldpte, *pte;
5014 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5015 ("pmap_clear_modify: page %p is not managed", m));
5016 VM_OBJECT_ASSERT_WLOCKED(m->object);
5017 KASSERT(!vm_page_xbusied(m),
5018 ("pmap_clear_modify: page %p is exclusive busied", m));
5021 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5022 * If the object containing the page is locked and the page is not
5023 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5025 if ((m->aflags & PGA_WRITEABLE) == 0)
5027 rw_wlock(&pvh_global_lock);
5029 if ((m->flags & PG_FICTITIOUS) != 0)
5030 goto small_mappings;
5031 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5032 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5036 pde = pmap_pde(pmap, va);
5038 if ((oldpde & PG_RW) != 0) {
5039 if (pmap_demote_pde(pmap, pde, va)) {
5040 if ((oldpde & PG_W) == 0) {
5042 * Write protect the mapping to a
5043 * single page so that a subsequent
5044 * write access may repromote.
5046 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5048 pte = pmap_pte_quick(pmap, va);
5050 if ((oldpte & PG_V) != 0) {
5052 * Regardless of whether a pte is 32 or 64 bits
5053 * in size, PG_RW and PG_M are among the least
5054 * significant 32 bits.
5056 while (!atomic_cmpset_int((u_int *)pte,
5058 oldpte & ~(PG_M | PG_RW)))
5061 pmap_invalidate_page(pmap, va);
5069 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5072 pde = pmap_pde(pmap, pv->pv_va);
5073 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5074 " a 4mpage in page %p's pv list", m));
5075 pte = pmap_pte_quick(pmap, pv->pv_va);
5076 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5078 * Regardless of whether a pte is 32 or 64 bits
5079 * in size, PG_M is among the least significant
5082 atomic_clear_int((u_int *)pte, PG_M);
5083 pmap_invalidate_page(pmap, pv->pv_va);
5088 rw_wunlock(&pvh_global_lock);
5092 * Miscellaneous support routines follow
5095 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5096 static __inline void
5097 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5102 * The cache mode bits are all in the low 32-bits of the
5103 * PTE, so we can just spin on updating the low 32-bits.
5106 opte = *(u_int *)pte;
5107 npte = opte & ~PG_PTE_CACHE;
5109 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5112 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5113 static __inline void
5114 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5119 * The cache mode bits are all in the low 32-bits of the
5120 * PDE, so we can just spin on updating the low 32-bits.
5123 opde = *(u_int *)pde;
5124 npde = opde & ~PG_PDE_CACHE;
5126 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5130 * Map a set of physical memory pages into the kernel virtual
5131 * address space. Return a pointer to where it is mapped. This
5132 * routine is intended to be used for mapping device memory,
5136 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5138 struct pmap_preinit_mapping *ppim;
5139 vm_offset_t va, offset;
5143 offset = pa & PAGE_MASK;
5144 size = round_page(offset + size);
5147 if (pa < PMAP_MAP_LOW && pa + size <= PMAP_MAP_LOW)
5148 va = pa + PMAP_MAP_LOW;
5149 else if (!pmap_initialized) {
5151 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5152 ppim = pmap_preinit_mapping + i;
5153 if (ppim->va == 0) {
5157 ppim->va = virtual_avail;
5158 virtual_avail += size;
5164 panic("%s: too many preinit mappings", __func__);
5167 * If we have a preinit mapping, re-use it.
5169 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5170 ppim = pmap_preinit_mapping + i;
5171 if (ppim->pa == pa && ppim->sz == size &&
5173 return ((void *)(ppim->va + offset));
5175 va = kva_alloc(size);
5177 panic("%s: Couldn't allocate KVA", __func__);
5179 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5180 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5181 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5182 pmap_invalidate_cache_range(va, va + size, FALSE);
5183 return ((void *)(va + offset));
5187 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5190 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5194 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5197 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5201 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5203 struct pmap_preinit_mapping *ppim;
5207 if (va >= PMAP_MAP_LOW && va <= KERNBASE && va + size <= KERNBASE)
5209 offset = va & PAGE_MASK;
5210 size = round_page(offset + size);
5211 va = trunc_page(va);
5212 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5213 ppim = pmap_preinit_mapping + i;
5214 if (ppim->va == va && ppim->sz == size) {
5215 if (pmap_initialized)
5221 if (va + size == virtual_avail)
5226 if (pmap_initialized)
5231 * Sets the memory attribute for the specified page.
5234 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5237 m->md.pat_mode = ma;
5238 if ((m->flags & PG_FICTITIOUS) != 0)
5242 * If "m" is a normal page, flush it from the cache.
5243 * See pmap_invalidate_cache_range().
5245 * First, try to find an existing mapping of the page by sf
5246 * buffer. sf_buf_invalidate_cache() modifies mapping and
5247 * flushes the cache.
5249 if (sf_buf_invalidate_cache(m))
5253 * If page is not mapped by sf buffer, but CPU does not
5254 * support self snoop, map the page transient and do
5255 * invalidation. In the worst case, whole cache is flushed by
5256 * pmap_invalidate_cache_range().
5258 if ((cpu_feature & CPUID_SS) == 0)
5263 pmap_flush_page(vm_page_t m)
5265 pt_entry_t *cmap_pte2;
5267 vm_offset_t sva, eva;
5270 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5271 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5274 cmap_pte2 = pc->pc_cmap_pte2;
5275 mtx_lock(&pc->pc_cmap_lock);
5277 panic("pmap_flush_page: CMAP2 busy");
5278 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5279 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0);
5280 invlcaddr(pc->pc_cmap_addr2);
5281 sva = (vm_offset_t)pc->pc_cmap_addr2;
5282 eva = sva + PAGE_SIZE;
5285 * Use mfence or sfence despite the ordering implied by
5286 * mtx_{un,}lock() because clflush on non-Intel CPUs
5287 * and clflushopt are not guaranteed to be ordered by
5288 * any other instruction.
5292 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5294 for (; sva < eva; sva += cpu_clflush_line_size) {
5302 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5306 mtx_unlock(&pc->pc_cmap_lock);
5308 pmap_invalidate_cache();
5312 * Changes the specified virtual address range's memory type to that given by
5313 * the parameter "mode". The specified virtual address range must be
5314 * completely contained within either the kernel map.
5316 * Returns zero if the change completed successfully, and either EINVAL or
5317 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5318 * of the virtual address range was not mapped, and ENOMEM is returned if
5319 * there was insufficient memory available to complete the change.
5322 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5324 vm_offset_t base, offset, tmpva;
5327 int cache_bits_pte, cache_bits_pde;
5330 base = trunc_page(va);
5331 offset = va & PAGE_MASK;
5332 size = round_page(offset + size);
5335 * Only supported on kernel virtual addresses above the recursive map.
5337 if (base < VM_MIN_KERNEL_ADDRESS)
5340 cache_bits_pde = pmap_cache_bits(mode, 1);
5341 cache_bits_pte = pmap_cache_bits(mode, 0);
5345 * Pages that aren't mapped aren't supported. Also break down
5346 * 2/4MB pages into 4KB pages if required.
5348 PMAP_LOCK(kernel_pmap);
5349 for (tmpva = base; tmpva < base + size; ) {
5350 pde = pmap_pde(kernel_pmap, tmpva);
5352 PMAP_UNLOCK(kernel_pmap);
5357 * If the current 2/4MB page already has
5358 * the required memory type, then we need not
5359 * demote this page. Just increment tmpva to
5360 * the next 2/4MB page frame.
5362 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5363 tmpva = trunc_4mpage(tmpva) + NBPDR;
5368 * If the current offset aligns with a 2/4MB
5369 * page frame and there is at least 2/4MB left
5370 * within the range, then we need not break
5371 * down this page into 4KB pages.
5373 if ((tmpva & PDRMASK) == 0 &&
5374 tmpva + PDRMASK < base + size) {
5378 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5379 PMAP_UNLOCK(kernel_pmap);
5383 pte = vtopte(tmpva);
5385 PMAP_UNLOCK(kernel_pmap);
5390 PMAP_UNLOCK(kernel_pmap);
5393 * Ok, all the pages exist, so run through them updating their
5394 * cache mode if required.
5396 for (tmpva = base; tmpva < base + size; ) {
5397 pde = pmap_pde(kernel_pmap, tmpva);
5399 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5400 pmap_pde_attr(pde, cache_bits_pde);
5403 tmpva = trunc_4mpage(tmpva) + NBPDR;
5405 pte = vtopte(tmpva);
5406 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5407 pmap_pte_attr(pte, cache_bits_pte);
5415 * Flush CPU caches to make sure any data isn't cached that
5416 * shouldn't be, etc.
5419 pmap_invalidate_range(kernel_pmap, base, tmpva);
5420 pmap_invalidate_cache_range(base, tmpva, FALSE);
5426 * perform the pmap work for mincore
5429 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5432 pt_entry_t *ptep, pte;
5438 pdep = pmap_pde(pmap, addr);
5440 if (*pdep & PG_PS) {
5442 /* Compute the physical address of the 4KB page. */
5443 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5445 val = MINCORE_SUPER;
5447 ptep = pmap_pte(pmap, addr);
5449 pmap_pte_release(ptep);
5450 pa = pte & PG_FRAME;
5458 if ((pte & PG_V) != 0) {
5459 val |= MINCORE_INCORE;
5460 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5461 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5462 if ((pte & PG_A) != 0)
5463 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5465 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5466 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5467 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5468 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5469 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5472 PA_UNLOCK_COND(*locked_pa);
5478 pmap_activate(struct thread *td)
5480 pmap_t pmap, oldpmap;
5485 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5486 oldpmap = PCPU_GET(curpmap);
5487 cpuid = PCPU_GET(cpuid);
5489 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5490 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5492 CPU_CLR(cpuid, &oldpmap->pm_active);
5493 CPU_SET(cpuid, &pmap->pm_active);
5495 #if defined(PAE) || defined(PAE_TABLES)
5496 cr3 = vtophys(pmap->pm_pdpt);
5498 cr3 = vtophys(pmap->pm_pdir);
5501 * pmap_activate is for the current thread on the current cpu
5503 td->td_pcb->pcb_cr3 = cr3;
5504 PCPU_SET(curpmap, pmap);
5509 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5514 * Increase the starting virtual address of the given mapping if a
5515 * different alignment might result in more superpage mappings.
5518 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5519 vm_offset_t *addr, vm_size_t size)
5521 vm_offset_t superpage_offset;
5525 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5526 offset += ptoa(object->pg_color);
5527 superpage_offset = offset & PDRMASK;
5528 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5529 (*addr & PDRMASK) == superpage_offset)
5531 if ((*addr & PDRMASK) < superpage_offset)
5532 *addr = (*addr & ~PDRMASK) + superpage_offset;
5534 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5538 pmap_quick_enter_page(vm_page_t m)
5544 qaddr = PCPU_GET(qmap_addr);
5545 pte = vtopte(qaddr);
5547 KASSERT(*pte == 0, ("pmap_quick_enter_page: PTE busy"));
5548 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5549 pmap_cache_bits(pmap_page_get_memattr(m), 0);
5556 pmap_quick_remove_page(vm_offset_t addr)
5561 qaddr = PCPU_GET(qmap_addr);
5562 pte = vtopte(qaddr);
5564 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5565 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5571 static vmem_t *pmap_trm_arena;
5572 static vmem_addr_t pmap_trm_arena_last = PMAP_TRM_MIN_ADDRESS;
5573 static int trm_guard = PAGE_SIZE;
5576 pmap_trm_import(void *unused __unused, vmem_size_t size, int flags,
5580 vmem_addr_t af, addr, prev_addr;
5581 pt_entry_t *trm_pte;
5583 prev_addr = atomic_load_long(&pmap_trm_arena_last);
5584 size = round_page(size) + trm_guard;
5586 if (prev_addr + size < prev_addr || prev_addr + size < size ||
5587 prev_addr + size > PMAP_TRM_MAX_ADDRESS)
5589 addr = prev_addr + size;
5590 if (atomic_fcmpset_int(&pmap_trm_arena_last, &prev_addr, addr))
5593 prev_addr += trm_guard;
5594 trm_pte = PTmap + atop(prev_addr);
5595 for (af = prev_addr; af < addr; af += PAGE_SIZE) {
5596 m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5597 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
5598 pte_store(&trm_pte[atop(af - prev_addr)], VM_PAGE_TO_PHYS(m) |
5599 PG_M | PG_A | PG_RW | PG_V | pgeflag |
5600 pmap_cache_bits(VM_MEMATTR_DEFAULT, FALSE));
5607 void pmap_init_trm(void)
5611 TUNABLE_INT_FETCH("machdep.trm_guard", &trm_guard);
5612 if ((trm_guard & PAGE_MASK) != 0)
5614 pmap_trm_arena = vmem_create("i386trampoline", 0, 0, 1, 0, M_WAITOK);
5615 vmem_set_import(pmap_trm_arena, pmap_trm_import, NULL, NULL, PAGE_SIZE);
5616 pd_m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5617 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK | VM_ALLOC_ZERO);
5618 if ((pd_m->flags & PG_ZERO) == 0)
5619 pmap_zero_page(pd_m);
5620 PTD[TRPTDI] = VM_PAGE_TO_PHYS(pd_m) | PG_M | PG_A | PG_RW | PG_V |
5621 pmap_cache_bits(VM_MEMATTR_DEFAULT, TRUE);
5625 pmap_trm_alloc(size_t size, int flags)
5630 MPASS((flags & ~(M_WAITOK | M_NOWAIT | M_ZERO)) == 0);
5631 error = vmem_xalloc(pmap_trm_arena, roundup2(size, 4), sizeof(int),
5632 0, 0, VMEM_ADDR_MIN, VMEM_ADDR_MAX, flags | M_FIRSTFIT, &res);
5635 if ((flags & M_ZERO) != 0)
5636 bzero((void *)res, size);
5637 return ((void *)res);
5641 pmap_trm_free(void *addr, size_t size)
5644 vmem_free(pmap_trm_arena, (uintptr_t)addr, roundup2(size, 4));
5647 #if defined(PMAP_DEBUG)
5648 pmap_pid_dump(int pid)
5655 sx_slock(&allproc_lock);
5656 FOREACH_PROC_IN_SYSTEM(p) {
5657 if (p->p_pid != pid)
5663 pmap = vmspace_pmap(p->p_vmspace);
5664 for (i = 0; i < NPDEPTD; i++) {
5667 vm_offset_t base = i << PDRSHIFT;
5669 pde = &pmap->pm_pdir[i];
5670 if (pde && pmap_pde_v(pde)) {
5671 for (j = 0; j < NPTEPG; j++) {
5672 vm_offset_t va = base + (j << PAGE_SHIFT);
5673 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5678 sx_sunlock(&allproc_lock);
5681 pte = pmap_pte(pmap, va);
5682 if (pte && pmap_pte_v(pte)) {
5686 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5687 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5688 va, pa, m->hold_count, m->wire_count, m->flags);
5703 sx_sunlock(&allproc_lock);