2 * Copyright (c) 1990 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
41 * Routines to handle clock hardware.
45 * inittodr, settodr and support routines written
46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
51 #include "opt_clock.h"
55 #include <sys/param.h>
56 #include <sys/systm.h>
59 #include <sys/mutex.h>
62 #include <sys/timetc.h>
63 #include <sys/kernel.h>
64 #include <sys/sysctl.h>
67 #include <machine/clock.h>
68 #ifdef CLK_CALIBRATION_LOOP
70 #include <machine/cputypes.h>
71 #include <machine/frame.h>
72 #include <machine/limits.h>
73 #include <machine/md_var.h>
74 #include <machine/psl.h>
76 #include <machine/segments.h>
78 #if defined(SMP) || defined(APIC_IO)
79 #include <machine/smp.h>
80 #endif /* SMP || APIC_IO */
81 #include <machine/specialreg.h>
83 #include <i386/isa/icu.h>
84 #include <i386/isa/isa.h>
86 #include <isa/isavar.h>
87 #include <i386/isa/timerreg.h>
89 #include <i386/isa/intr_machdep.h>
92 #include <i386/isa/mca_machdep.h>
96 #include <i386/isa/intr_machdep.h>
97 /* The interrupt triggered by the 8254 (timer) chip */
99 static u_long read_intr_count __P((int vec));
100 static void setup_8254_mixed_mode __P((void));
104 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
105 * can use a simple formula for leap years.
107 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
108 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
110 #define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x))
113 * Time in timer cycles that it takes for microtime() to disable interrupts
114 * and latch the count. microtime() currently uses "cli; outb ..." so it
115 * normally takes less than 2 timer cycles. Add a few for cache misses.
116 * Add a few more to allow for latency in bogus calls to microtime() with
117 * interrupts already disabled.
119 #define TIMER0_LATCH_COUNT 20
122 * Maximum frequency that we are willing to allow for timer0. Must be
123 * low enough to guarantee that the timer interrupt handler returns
124 * before the next timer interrupt.
126 #define TIMER0_MAX_FREQ 20000
128 int adjkerntz; /* local offset from GMT in seconds */
130 int disable_rtc_set; /* disable resettodr() if != 0 */
131 int statclock_disable;
133 #define TIMER_FREQ 1193182
135 u_int timer_freq = TIMER_FREQ;
136 int timer0_max_count;
140 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
141 struct mtx clock_lock;
143 static int beeping = 0;
144 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
145 static u_int hardclock_max_count;
146 static u_int32_t i8254_lastcount;
147 static u_int32_t i8254_offset;
148 static int i8254_ticked;
150 * XXX new_function and timer_func should not handle clockframes, but
151 * timer_func currently needs to hold hardclock to handle the
152 * timer0_state == 0 case. We should use inthand_add()/inthand_remove()
153 * to switch between clkintr() and a slightly different timerintr().
155 static void (*new_function) __P((struct clockframe *frame));
156 static u_int new_rate;
157 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
158 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
159 static u_int timer0_prescaler_count;
161 /* Values for timerX_state: */
163 #define RELEASE_PENDING 1
165 #define ACQUIRE_PENDING 3
167 static u_char timer0_state;
168 static u_char timer2_state;
169 static void (*timer_func) __P((struct clockframe *frame)) = hardclock;
171 static unsigned i8254_get_timecount __P((struct timecounter *tc));
172 static unsigned tsc_get_timecount __P((struct timecounter *tc));
173 static void set_timer_freq(u_int freq, int intr_freq);
175 static struct timecounter tsc_timecounter = {
176 tsc_get_timecount, /* get_timecount */
178 ~0u, /* counter_mask */
183 SYSCTL_OPAQUE(_debug, OID_AUTO, tsc_timecounter, CTLFLAG_RD,
184 &tsc_timecounter, sizeof(tsc_timecounter), "S,timecounter", "");
186 static struct timecounter i8254_timecounter = {
187 i8254_get_timecount, /* get_timecount */
189 ~0u, /* counter_mask */
194 SYSCTL_OPAQUE(_debug, OID_AUTO, i8254_timecounter, CTLFLAG_RD,
195 &i8254_timecounter, sizeof(i8254_timecounter), "S,timecounter", "");
198 clkintr(struct clockframe frame)
201 if (timecounter->tc_get_timecount == i8254_get_timecount) {
202 mtx_lock_spin(&clock_lock);
206 i8254_offset += timer0_max_count;
210 mtx_unlock_spin(&clock_lock);
214 if (timer_func == hardclock)
217 switch (timer0_state) {
223 if ((timer0_prescaler_count += timer0_max_count)
224 >= hardclock_max_count) {
225 timer0_prescaler_count -= hardclock_max_count;
233 case ACQUIRE_PENDING:
234 mtx_lock_spin(&clock_lock);
235 i8254_offset = i8254_get_timecount(NULL);
237 timer0_max_count = TIMER_DIV(new_rate);
238 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
239 outb(TIMER_CNTR0, timer0_max_count & 0xff);
240 outb(TIMER_CNTR0, timer0_max_count >> 8);
241 mtx_unlock_spin(&clock_lock);
242 timer_func = new_function;
243 timer0_state = ACQUIRED;
246 case RELEASE_PENDING:
247 if ((timer0_prescaler_count += timer0_max_count)
248 >= hardclock_max_count) {
249 mtx_lock_spin(&clock_lock);
250 i8254_offset = i8254_get_timecount(NULL);
252 timer0_max_count = hardclock_max_count;
254 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
255 outb(TIMER_CNTR0, timer0_max_count & 0xff);
256 outb(TIMER_CNTR0, timer0_max_count >> 8);
257 mtx_unlock_spin(&clock_lock);
258 timer0_prescaler_count = 0;
259 timer_func = hardclock;
260 timer0_state = RELEASED;
269 /* Reset clock interrupt by asserting bit 7 of port 0x61 */
271 outb(0x61, inb(0x61) | 0x80);
276 * The acquire and release functions must be called at ipl >= splclock().
279 acquire_timer0(int rate, void (*function) __P((struct clockframe *frame)))
283 if (rate <= 0 || rate > TIMER0_MAX_FREQ)
285 switch (timer0_state) {
288 timer0_state = ACQUIRE_PENDING;
291 case RELEASE_PENDING:
292 if (rate != old_rate)
295 * The timer has been released recently, but is being
296 * re-acquired before the release completed. In this
297 * case, we simply reclaim it as if it had not been
300 timer0_state = ACQUIRED;
304 return (-1); /* busy */
306 new_function = function;
307 old_rate = new_rate = rate;
312 acquire_timer2(int mode)
315 if (timer2_state != RELEASED)
317 timer2_state = ACQUIRED;
320 * This access to the timer registers is as atomic as possible
321 * because it is a single instruction. We could do better if we
322 * knew the rate. Use of splclock() limits glitches to 10-100us,
323 * and this is probably good enough for timer2, so we aren't as
324 * careful with it as with timer0.
326 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
334 switch (timer0_state) {
337 timer0_state = RELEASE_PENDING;
340 case ACQUIRE_PENDING:
341 /* Nothing happened yet, release quickly. */
342 timer0_state = RELEASED;
355 if (timer2_state != ACQUIRED)
357 timer2_state = RELEASED;
358 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
363 * This routine receives statistical clock interrupts from the RTC.
364 * As explained above, these occur at 128 interrupts per second.
365 * When profiling, we receive interrupts at a rate of 1024 Hz.
367 * This does not actually add as much overhead as it sounds, because
368 * when the statistical clock is active, the hardclock driver no longer
369 * needs to keep (inaccurate) statistics on its own. This decouples
370 * statistics gathering from scheduling interrupts.
372 * The RTC chip requires that we read status register C (RTC_INTR)
373 * to acknowledge an interrupt, before it will generate the next one.
374 * Under high interrupt load, rtcintr() can be indefinitely delayed and
375 * the clock can tick immediately after the read from RTC_INTR. In this
376 * case, the mc146818A interrupt signal will not drop for long enough
377 * to register with the 8259 PIC. If an interrupt is missed, the stat
378 * clock will halt, considerably degrading system performance. This is
379 * why we use 'while' rather than a more straightforward 'if' below.
380 * Stat clock ticks can still be lost, causing minor loss of accuracy
381 * in the statistics, but the stat clock will no longer stop.
384 rtcintr(struct clockframe frame)
386 while (rtcin(RTC_INTR) & RTCIR_PERIOD) {
398 DB_SHOW_COMMAND(rtc, rtc)
400 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
401 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
402 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
403 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
412 mtx_lock_spin(&clock_lock);
414 /* Select timer0 and latch counter value. */
415 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
417 low = inb(TIMER_CNTR0);
418 high = inb(TIMER_CNTR0);
420 mtx_unlock_spin(&clock_lock);
421 return ((high << 8) | low);
425 * Wait "n" microseconds.
426 * Relies on timer 1 counting down from (timer_freq / hz)
427 * Note: timer had better have been programmed before this is first used!
432 int delta, prev_tick, tick, ticks_left;
437 static int state = 0;
441 for (n1 = 1; n1 <= 10000000; n1 *= 10)
446 printf("DELAY(%d)...", n);
449 * Guard against the timer being uninitialized if we are called
450 * early for console i/o.
452 if (timer0_max_count == 0)
453 set_timer_freq(timer_freq, hz);
456 * Read the counter first, so that the rest of the setup overhead is
457 * counted. Guess the initial overhead is 20 usec (on most systems it
458 * takes about 1.5 usec for each of the i/o's in getit(). The loop
459 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The
460 * multiplications and divisions to scale the count take a while).
463 n -= 0; /* XXX actually guess no initial overhead */
465 * Calculate (n * (timer_freq / 1e6)) without using floating point
466 * and without any avoidable overflows.
472 * Use fixed point to avoid a slow division by 1000000.
473 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest.
474 * 2^15 is the first power of 2 that gives exact results
475 * for n between 0 and 256.
477 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15;
480 * Don't bother using fixed point, although gcc-2.7.2
481 * generates particularly poor code for the long long
482 * division, since even the slow way will complete long
483 * before the delay is up (unless we're interrupted).
485 ticks_left = ((u_int)n * (long long)timer_freq + 999999)
488 while (ticks_left > 0) {
493 delta = prev_tick - tick;
496 delta += timer0_max_count;
498 * Guard against timer0_max_count being wrong.
499 * This shouldn't happen in normal operation,
500 * but it may happen if set_timer_freq() is
510 printf(" %d calls to getit() at %d usec each\n",
511 getit_calls, (n + 5) / getit_calls);
516 sysbeepstop(void *chan)
518 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
524 sysbeep(int pitch, int period)
528 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
530 /* Something else owns it. */
532 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */
534 mtx_lock_spin(&clock_lock);
535 outb(TIMER_CNTR2, pitch);
536 outb(TIMER_CNTR2, (pitch>>8));
537 mtx_unlock_spin(&clock_lock);
539 /* enable counter2 output to speaker */
540 outb(IO_PPI, inb(IO_PPI) | 3);
542 timeout(sysbeepstop, (void *)NULL, period);
549 * RTC support routines
562 val = inb(IO_RTC + 1);
569 writertc(u_char reg, u_char val)
577 outb(IO_RTC + 1, val);
578 inb(0x84); /* XXX work around wrong order in rtcin() */
585 return(bcd2bin(rtcin(port)));
589 calibrate_clocks(void)
592 u_int count, prev_count, tot_count;
593 int sec, start_sec, timeout;
596 printf("Calibrating clock(s) ... ");
597 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
601 /* Read the mc146818A seconds counter. */
603 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
604 sec = rtcin(RTC_SEC);
611 /* Wait for the mC146818A seconds counter to change. */
614 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
615 sec = rtcin(RTC_SEC);
616 if (sec != start_sec)
623 /* Start keeping track of the i8254 counter. */
624 prev_count = getit();
625 if (prev_count == 0 || prev_count > timer0_max_count)
632 old_tsc = 0; /* shut up gcc */
635 * Wait for the mc146818A seconds counter to change. Read the i8254
636 * counter for each iteration since this is convenient and only
637 * costs a few usec of inaccuracy. The timing of the final reads
638 * of the counters almost matches the timing of the initial reads,
639 * so the main cause of inaccuracy is the varying latency from
640 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
641 * rtcin(RTC_SEC) that returns a changed seconds count. The
642 * maximum inaccuracy from this cause is < 10 usec on 486's.
646 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
647 sec = rtcin(RTC_SEC);
649 if (count == 0 || count > timer0_max_count)
651 if (count > prev_count)
652 tot_count += prev_count - (count - timer0_max_count);
654 tot_count += prev_count - count;
656 if (sec != start_sec)
663 * Read the cpu cycle counter. The timing considerations are
664 * similar to those for the i8254 clock.
667 tsc_freq = rdtsc() - old_tsc;
671 printf("TSC clock: %u Hz, ", tsc_freq);
672 printf("i8254 clock: %u Hz\n", tot_count);
678 printf("failed, using default i8254 clock of %u Hz\n",
684 set_timer_freq(u_int freq, int intr_freq)
686 int new_timer0_max_count;
688 mtx_lock_spin(&clock_lock);
690 new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq);
691 if (new_timer0_max_count != timer0_max_count) {
692 timer0_max_count = new_timer0_max_count;
693 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
694 outb(TIMER_CNTR0, timer0_max_count & 0xff);
695 outb(TIMER_CNTR0, timer0_max_count >> 8);
697 mtx_unlock_spin(&clock_lock);
701 * i8254_restore is called from apm_default_resume() to reload
702 * the countdown register.
703 * this should not be necessary but there are broken laptops that
704 * do not restore the countdown register on resume.
705 * when it happnes, it messes up the hardclock interval and system clock,
706 * which leads to the infamous "calcru: negative time" problem.
712 mtx_lock_spin(&clock_lock);
713 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
714 outb(TIMER_CNTR0, timer0_max_count & 0xff);
715 outb(TIMER_CNTR0, timer0_max_count >> 8);
716 mtx_unlock_spin(&clock_lock);
720 * Initialize 8254 timer 0 early so that it can be used in DELAY().
721 * XXX initialization of other timers is unintentionally left blank.
728 if (cpu_feature & CPUID_TSC)
733 writertc(RTC_STATUSA, rtc_statusa);
734 writertc(RTC_STATUSB, RTCSB_24HR);
736 set_timer_freq(timer_freq, hz);
737 freq = calibrate_clocks();
738 #ifdef CLK_CALIBRATION_LOOP
741 "Press a key on the console to abort clock calibration\n");
742 while (cncheckc() == -1)
748 * Use the calibrated i8254 frequency if it seems reasonable.
749 * Otherwise use the default, and don't use the calibrated i586
752 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq;
753 if (delta < timer_freq / 100) {
754 #ifndef CLK_USE_I8254_CALIBRATION
757 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
764 "%d Hz differs from default of %d Hz by more than 1%%\n",
769 set_timer_freq(timer_freq, hz);
770 i8254_timecounter.tc_frequency = timer_freq;
771 tc_init(&i8254_timecounter);
773 #ifndef CLK_USE_TSC_CALIBRATION
777 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
781 if (tsc_present && tsc_freq == 0) {
783 * Calibration of the i586 clock relative to the mc146818A
784 * clock failed. Do a less accurate calibration relative
785 * to the i8254 clock.
787 u_int64_t old_tsc = rdtsc();
790 tsc_freq = rdtsc() - old_tsc;
791 #ifdef CLK_USE_TSC_CALIBRATION
793 printf("TSC clock: %u Hz (Method B)\n", tsc_freq);
799 * We can not use the TSC in SMP mode, until we figure out a
800 * cheap (impossible), reliable and precise (yeah right!) way
801 * to synchronize the TSCs of all the CPUs.
802 * Curse Intel for leaving the counter out of the I/O APIC.
807 * We can not use the TSC if we support APM. Precise timekeeping
808 * on an APM'ed machine is at best a fools pursuit, since
809 * any and all of the time spent in various SMM code can't
810 * be reliably accounted for. Reading the RTC is your only
811 * source of reliable time info. The i8254 looses too of course
812 * but we need to have some kind of time...
813 * We don't know at this point whether APM is going to be used
814 * or not, nor when it might be activated. Play it safe.
818 resource_int_value("apm", 0, "disabled", &disabled);
824 if (tsc_present && tsc_freq != 0 && !tsc_is_broken) {
825 tsc_timecounter.tc_frequency = tsc_freq;
826 tc_init(&tsc_timecounter);
829 #endif /* !defined(SMP) */
833 * Initialize the time of day register, based on the time base which is, e.g.
837 inittodr(time_t base)
839 unsigned long sec, days;
853 /* Look if we have a RTC present and the time is valid */
854 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
857 /* wait for time update to complete */
858 /* If RTCSA_TUP is zero, we have at least 244us before next update */
860 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
866 #ifdef USE_RTC_CENTURY
867 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
869 year = readrtc(RTC_YEAR) + 1900;
877 month = readrtc(RTC_MONTH);
878 for (m = 1; m < month; m++)
879 days += daysinmonth[m-1];
880 if ((month > 2) && LEAPYEAR(year))
882 days += readrtc(RTC_DAY) - 1;
884 for (y = 1970; y < year; y++)
885 days += DAYSPERYEAR + LEAPYEAR(y);
886 sec = ((( days * 24 +
887 readrtc(RTC_HRS)) * 60 +
888 readrtc(RTC_MIN)) * 60 +
890 /* sec now contains the number of seconds, since Jan 1 1970,
891 in the local time zone */
893 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
895 y = time_second - sec;
896 if (y <= -2 || y >= 2) {
897 /* badly off, adjust it */
906 printf("Invalid time in real time clock.\n");
907 printf("Check and reset the date immediately!\n");
911 * Write system time back to RTC
926 /* Disable RTC updates and interrupts. */
927 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
929 /* Calculate local time to put in RTC */
931 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
933 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
934 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
935 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
937 /* We have now the days since 01-01-1970 in tm */
938 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
939 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
941 y++, m = DAYSPERYEAR + LEAPYEAR(y))
944 /* Now we have the years in y and the day-of-the-year in tm */
945 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
946 #ifdef USE_RTC_CENTURY
947 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
953 if (m == 1 && LEAPYEAR(y))
960 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
961 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
963 /* Reenable RTC updates and interrupts. */
964 writertc(RTC_STATUSB, rtc_statusb);
969 * Start both clocks running.
980 if (statclock_disable) {
982 * The stat interrupt mask is different without the
983 * statistics clock. Also, don't set the interrupt
984 * flag which would normally cause the RTC to generate
987 rtc_statusb = RTCSB_24HR;
989 /* Setting stathz to nonzero early helps avoid races. */
990 stathz = RTC_NOPROFRATE;
991 profhz = RTC_PROFRATE;
994 /* Finish initializing 8253 timer 0. */
997 apic_8254_intr = isa_apic_irq(0);
999 if (apic_8254_intr >= 0 ) {
1000 if (apic_int_type(0, 0) == 3)
1001 apic_8254_trial = 1;
1003 /* look for ExtInt on pin 0 */
1004 if (apic_int_type(0, 0) == 3) {
1005 apic_8254_intr = apic_irq(0, 0);
1006 setup_8254_mixed_mode();
1008 panic("APIC_IO: Cannot route 8254 interrupt to CPU");
1011 inthand_add("clk", apic_8254_intr, (driver_intr_t *)clkintr, NULL,
1012 INTR_TYPE_CLK | INTR_FAST, &clkdesc);
1013 INTREN(1 << apic_8254_intr);
1018 * XXX Check the priority of this interrupt handler. I
1019 * couldn't find anything suitable in the BSD/OS code (grog,
1022 inthand_add("clk", 0, (driver_intr_t *)clkintr, NULL,
1023 INTR_TYPE_CLK | INTR_FAST, NULL);
1026 #endif /* APIC_IO */
1028 /* Initialize RTC. */
1029 writertc(RTC_STATUSA, rtc_statusa);
1030 writertc(RTC_STATUSB, RTCSB_24HR);
1032 /* Don't bother enabling the statistics clock. */
1033 if (statclock_disable)
1035 diag = rtcin(RTC_DIAG);
1037 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
1040 if (isa_apic_irq(8) != 8)
1041 panic("APIC RTC != 8");
1042 #endif /* APIC_IO */
1044 inthand_add("rtc", 8, (driver_intr_t *)rtcintr, NULL,
1045 INTR_TYPE_CLK | INTR_FAST, NULL);
1051 #endif /* APIC_IO */
1053 writertc(RTC_STATUSB, rtc_statusb);
1056 if (apic_8254_trial) {
1058 printf("APIC_IO: Testing 8254 interrupt delivery\n");
1059 while (read_intr_count(8) < 6)
1061 if (read_intr_count(apic_8254_intr) < 3) {
1063 * The MP table is broken.
1064 * The 8254 was not connected to the specified pin
1066 * Workaround: Limited variant of mixed mode.
1068 INTRDIS(1 << apic_8254_intr);
1069 inthand_remove(clkdesc);
1070 printf("APIC_IO: Broken MP table detected: "
1071 "8254 is not connected to "
1072 "IOAPIC #%d intpin %d\n",
1073 int_to_apicintpin[apic_8254_intr].ioapic,
1074 int_to_apicintpin[apic_8254_intr].int_pin);
1076 * Revoke current ISA IRQ 0 assignment and
1077 * configure a fallback interrupt routing from
1078 * the 8254 Timer via the 8259 PIC to the
1079 * an ExtInt interrupt line on IOAPIC #0 intpin 0.
1080 * We reuse the low level interrupt handler number.
1082 if (apic_irq(0, 0) < 0) {
1083 revoke_apic_irq(apic_8254_intr);
1084 assign_apic_irq(0, 0, apic_8254_intr);
1086 apic_8254_intr = apic_irq(0, 0);
1087 setup_8254_mixed_mode();
1088 inthand_add("clk", apic_8254_intr,
1089 (driver_intr_t *)clkintr, NULL,
1090 INTR_TYPE_CLK | INTR_FAST, NULL);
1091 INTREN(1 << apic_8254_intr);
1095 if (apic_int_type(0, 0) != 3 ||
1096 int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
1097 int_to_apicintpin[apic_8254_intr].int_pin != 0)
1098 printf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
1099 int_to_apicintpin[apic_8254_intr].ioapic,
1100 int_to_apicintpin[apic_8254_intr].int_pin);
1103 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
1110 read_intr_count(int vec)
1113 up = intr_countp[vec];
1120 setup_8254_mixed_mode()
1123 * Allow 8254 timer to INTerrupt 8259:
1124 * re-initialize master 8259:
1125 * reset; prog 4 bytes, single ICU, edge triggered
1127 outb(IO_ICU1, 0x13);
1128 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */
1129 outb(IO_ICU1 + 1, 0x00); /* ignore slave */
1130 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
1131 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
1133 /* program IO APIC for type 3 INT on INT0 */
1134 if (ext_int_setup(0, 0) < 0)
1135 panic("8254 redirect via APIC pin0 impossible!");
1140 setstatclockrate(int newhz)
1142 if (newhz == RTC_PROFRATE)
1143 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1145 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1146 writertc(RTC_STATUSA, rtc_statusa);
1150 sysctl_machdep_i8254_freq(SYSCTL_HANDLER_ARGS)
1156 * Use `i8254' instead of `timer' in external names because `timer'
1157 * is is too generic. Should use it everywhere.
1160 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
1161 if (error == 0 && req->newptr != NULL) {
1162 if (timer0_state != RELEASED)
1163 return (EBUSY); /* too much trouble to handle */
1164 set_timer_freq(freq, hz);
1165 i8254_timecounter.tc_frequency = freq;
1166 tc_update(&i8254_timecounter);
1171 SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW,
1172 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", "");
1175 sysctl_machdep_tsc_freq(SYSCTL_HANDLER_ARGS)
1180 if (tsc_timecounter.tc_frequency == 0)
1181 return (EOPNOTSUPP);
1183 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
1184 if (error == 0 && req->newptr != NULL) {
1186 tsc_timecounter.tc_frequency = tsc_freq;
1187 tc_update(&tsc_timecounter);
1192 SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_INT | CTLFLAG_RW,
1193 0, sizeof(u_int), sysctl_machdep_tsc_freq, "I", "");
1196 i8254_get_timecount(struct timecounter *tc)
1202 eflags = read_eflags();
1203 mtx_lock_spin(&clock_lock);
1205 /* Select timer0 and latch counter value. */
1206 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
1208 low = inb(TIMER_CNTR0);
1209 high = inb(TIMER_CNTR0);
1210 count = timer0_max_count - ((high << 8) | low);
1211 if (count < i8254_lastcount ||
1212 (!i8254_ticked && (clkintr_pending ||
1213 ((count < 20 || (!(eflags & PSL_I) && count < timer0_max_count / 2u)) &&
1215 #define lapic_irr1 ((volatile u_int *)&lapic)[0x210 / 4] /* XXX XXX */
1216 /* XXX this assumes that apic_8254_intr is < 24. */
1217 (lapic_irr1 & (1 << apic_8254_intr))))
1219 (inb(IO_ICU1) & 1)))
1223 i8254_offset += timer0_max_count;
1225 i8254_lastcount = count;
1226 count += i8254_offset;
1227 mtx_unlock_spin(&clock_lock);
1232 tsc_get_timecount(struct timecounter *tc)
1238 * Attach to the ISA PnP descriptors for the timer and realtime clock.
1240 static struct isa_pnp_id attimer_ids[] = {
1241 { 0x0001d041 /* PNP0100 */, "AT timer" },
1242 { 0x000bd041 /* PNP0B00 */, "AT realtime clock" },
1247 attimer_probe(device_t dev)
1251 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, attimer_ids)) <= 0)
1257 attimer_attach(device_t dev)
1262 static device_method_t attimer_methods[] = {
1263 /* Device interface */
1264 DEVMETHOD(device_probe, attimer_probe),
1265 DEVMETHOD(device_attach, attimer_attach),
1266 DEVMETHOD(device_detach, bus_generic_detach),
1267 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1268 DEVMETHOD(device_suspend, bus_generic_suspend), /* XXX stop statclock? */
1269 DEVMETHOD(device_resume, bus_generic_resume), /* XXX restart statclock? */
1273 static driver_t attimer_driver = {
1279 static devclass_t attimer_devclass;
1281 DRIVER_MODULE(attimer, isa, attimer_driver, attimer_devclass, 0, 0);