2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
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14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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32 #ifndef _MACHINE_APICVAR_H_
33 #define _MACHINE_APICVAR_H_
36 * Local && I/O APIC variable definitions.
40 * Layout of local APIC interrupt vectors:
42 * 0xff (255) +-------------+
43 * | | 15 (Spurious / IPIs / Local Interrupts)
44 * 0xf0 (240) +-------------+
45 * | | 14 (I/O Interrupts / Timer)
46 * 0xe0 (224) +-------------+
47 * | | 13 (I/O Interrupts)
48 * 0xd0 (208) +-------------+
49 * | | 12 (I/O Interrupts)
50 * 0xc0 (192) +-------------+
51 * | | 11 (I/O Interrupts)
52 * 0xb0 (176) +-------------+
53 * | | 10 (I/O Interrupts)
54 * 0xa0 (160) +-------------+
55 * | | 9 (I/O Interrupts)
56 * 0x90 (144) +-------------+
57 * | | 8 (I/O Interrupts / System Calls)
58 * 0x80 (128) +-------------+
59 * | | 7 (I/O Interrupts)
60 * 0x70 (112) +-------------+
61 * | | 6 (I/O Interrupts)
62 * 0x60 (96) +-------------+
63 * | | 5 (I/O Interrupts)
64 * 0x50 (80) +-------------+
65 * | | 4 (I/O Interrupts)
66 * 0x40 (64) +-------------+
67 * | | 3 (I/O Interrupts)
68 * 0x30 (48) +-------------+
69 * | | 2 (ATPIC Interrupts)
70 * 0x20 (32) +-------------+
71 * | | 1 (Exceptions, traps, faults, etc.)
72 * 0x10 (16) +-------------+
73 * | | 0 (Exceptions, traps, faults, etc.)
74 * 0x00 (0) +-------------+
76 * Note: 0x80 needs to be handled specially and not allocated to an
80 #define APIC_ID_ALL 0xff
82 /* I/O Interrupts are used for external devices such as ISA, PCI, etc. */
83 #define APIC_IO_INTS (IDT_IO_INTS + 16)
84 #define APIC_NUM_IOINTS 191
86 /* The timer interrupt is used for clock handling and drives hardclock, etc. */
87 #define APIC_TIMER_INT (APIC_IO_INTS + APIC_NUM_IOINTS)
90 ********************* !!! WARNING !!! ******************************
91 * Each local apic has an interrupt receive fifo that is two entries deep
92 * for each interrupt priority class (higher 4 bits of interrupt vector).
93 * Once the fifo is full the APIC can no longer receive interrupts for this
94 * class and sending IPIs from other CPUs will be blocked.
95 * To avoid deadlocks there should be no more than two IPI interrupts
96 * pending at the same time.
97 * Currently this is guaranteed by dividing the IPIs in two groups that have
98 * each at most one IPI interrupt pending. The first group is protected by the
99 * smp_ipi_mtx and waits for the completion of the IPI (Only one IPI user
100 * at a time) The second group uses a single interrupt and a bitmap to avoid
101 * redundant IPI interrupts.
103 * Right now IPI_STOP used by kdb shares the interrupt priority class with
104 * the two IPI groups mentioned above. As such IPI_STOP may cause a deadlock.
105 * Eventually IPI_STOP should use NMI IPIs - this would eliminate this and
106 * other deadlocks caused by IPI_STOP.
109 /* Interrupts for local APIC LVT entries other than the timer. */
110 #define APIC_LOCAL_INTS 240
111 #define APIC_ERROR_INT APIC_LOCAL_INTS
112 #define APIC_THERMAL_INT (APIC_LOCAL_INTS + 1)
114 #define APIC_IPI_INTS (APIC_LOCAL_INTS + 2)
115 #define IPI_RENDEZVOUS (APIC_IPI_INTS) /* Inter-CPU rendezvous. */
116 #define IPI_INVLTLB (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs */
117 #define IPI_INVLPG (APIC_IPI_INTS + 2)
118 #define IPI_INVLRNG (APIC_IPI_INTS + 3)
119 #define IPI_LAZYPMAP (APIC_IPI_INTS + 4) /* Lazy pmap release. */
120 /* Vector to handle bitmap based IPIs */
121 #define IPI_BITMAP_VECTOR (APIC_IPI_INTS + 5)
123 /* IPIs handled by IPI_BITMAPED_VECTOR (XXX ups is there a better place?) */
124 #define IPI_AST 0 /* Generate software trap. */
125 #define IPI_PREEMPT 1
126 #define IPI_BITMAP_LAST IPI_PREEMPT
127 #define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST)
129 #define IPI_STOP (APIC_IPI_INTS + 6) /* Stop CPU until restarted. */
132 * The spurious interrupt can share the priority class with the IPIs since
133 * it is not a normal interrupt. (Does not use the APIC's interrupt fifo)
135 #define APIC_SPURIOUS_INT 255
142 #define LVT_THERMAL 5
143 #define LVT_MAX LVT_THERMAL
147 #define APIC_IPI_DEST_SELF -1
148 #define APIC_IPI_DEST_ALL -2
149 #define APIC_IPI_DEST_OTHERS -3
151 #define APIC_BUS_UNKNOWN -1
152 #define APIC_BUS_ISA 0
153 #define APIC_BUS_EISA 1
154 #define APIC_BUS_PCI 2
155 #define APIC_BUS_MAX APIC_BUS_PCI
158 * An APIC enumerator is a psuedo bus driver that enumerates APIC's including
159 * CPU's and I/O APIC's.
161 struct apic_enumerator {
162 const char *apic_name;
163 int (*apic_probe)(void);
164 int (*apic_probe_cpus)(void);
165 int (*apic_setup_local)(void);
166 int (*apic_setup_io)(void);
167 SLIST_ENTRY(apic_enumerator) apic_next;
171 IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3),
172 IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6),
173 IDTVEC(apic_isr7), IDTVEC(spuriousint), IDTVEC(timerint);
175 u_int apic_irq_to_idt(u_int irq);
176 u_int apic_idt_to_irq(u_int vector);
177 void apic_register_enumerator(struct apic_enumerator *enumerator);
178 void *ioapic_create(uintptr_t addr, int32_t id, int intbase);
179 int ioapic_disable_pin(void *cookie, u_int pin);
180 int ioapic_get_vector(void *cookie, u_int pin);
181 int ioapic_next_logical_cluster(void);
182 void ioapic_register(void *cookie);
183 int ioapic_remap_vector(void *cookie, u_int pin, int vector);
184 int ioapic_set_bus(void *cookie, u_int pin, int bus_type);
185 int ioapic_set_extint(void *cookie, u_int pin);
186 int ioapic_set_nmi(void *cookie, u_int pin);
187 int ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol);
188 int ioapic_set_triggermode(void *cookie, u_int pin,
189 enum intr_trigger trigger);
190 int ioapic_set_smi(void *cookie, u_int pin);
191 void lapic_create(u_int apic_id, int boot_cpu);
192 void lapic_disable(void);
193 void lapic_dump(const char *str);
194 void lapic_enable_intr(u_int vector);
195 void lapic_eoi(void);
197 void lapic_init(uintptr_t addr);
198 int lapic_intr_pending(u_int vector);
199 void lapic_ipi_raw(register_t icrlo, u_int dest);
200 void lapic_ipi_vectored(u_int vector, int dest);
201 int lapic_ipi_wait(int delay);
202 void lapic_handle_intr(struct intrframe frame);
203 void lapic_handle_timer(struct clockframe frame);
204 void lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id);
205 int lapic_set_lvt_mask(u_int apic_id, u_int lvt, u_char masked);
206 int lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode);
207 int lapic_set_lvt_polarity(u_int apic_id, u_int lvt,
208 enum intr_polarity pol);
209 int lapic_set_lvt_triggermode(u_int apic_id, u_int lvt,
210 enum intr_trigger trigger);
211 void lapic_set_tpr(u_int vector);
212 void lapic_setup(void);
213 int lapic_setup_clock(void);
216 #endif /* _MACHINE_APICVAR_H_ */