2 * Copyright (c) 2004 John Birrell
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 /* AMD Elan SC520 Memory Mapped Configuration Region (MMCR).
29 * The layout of this structure is documented by AMD in the Elan SC520
30 * Microcontroller Register Set Manual. The field names match those
31 * described in that document. The overall structure size must be 4096
32 * bytes. Ignore fields with the 'pad' prefix - they are only present for
38 #ifndef _MACHINE_ELAN_MMCR_H_
39 #define _MACHINE_ELAN_MMCR_H_ 1
45 u_int8_t pad_0x003[0xd];
47 /* SDRAM Controller */
52 u_int8_t pad_0x01a[0x6];
59 u_int8_t pad_0x02c[0x14];
63 u_int8_t pad_0x041[0xf];
65 /* ROM/Flash Controller */
67 u_int8_t pad_0x052[0x2];
70 u_int8_t pad_0x058[0x8];
72 /* PCI Bus Host Bridge */
74 u_int16_t HBTGTIRQCTL;
75 u_int16_t HBTGTIRQSTA;
76 u_int16_t HBMSTIRQCTL;
77 u_int16_t HBMSTIRQSTA;
78 u_int8_t pad_0x06a[0x2];
81 /* System Arbitration */
86 u_int8_t pad_0x078[0x8];
88 /* System Address Mapping */
107 u_int8_t pad_0x0c8[0xb38];
109 /* GP Bus Controller */
113 u_int8_t pad_0xc04[0x4];
123 u_int8_t pad_0xc11[0xf];
125 /* Programmable Input/Output */
126 u_int16_t PIOPFS15_0;
127 u_int16_t PIOPFS31_16;
133 u_int16_t PIODIR15_0;
134 u_int16_t PIODIR31_16;
135 u_int8_t pad_0xc2e[0x2];
136 u_int16_t PIODATA15_0;
137 u_int16_t PIODATA31_16;
138 u_int16_t PIOSET15_0;
139 u_int16_t PIOSET31_16;
140 u_int16_t PIOCLR15_0;
141 u_int16_t PIOCLR31_16;
142 u_int8_t pad_0xc3c[0x24];
145 u_int16_t SWTMRMILLI;
146 u_int16_t SWTMRMICRO;
148 u_int8_t pad_0xc65[0xb];
150 /* General-Purpose Timers */
155 u_int16_t GPTMR0MAXCMPA;
156 u_int16_t GPTMR0MAXCMPB;
159 u_int16_t GPTMR1MAXCMPA;
160 u_int16_t GPTMR1MAXCMPB;
163 u_int8_t pad_0xc86[0x8];
164 u_int16_t GPTMR2MAXCMPA;
165 u_int8_t pad_0xc90[0x20];
171 u_int8_t pad_0xcb6[0xa];
173 /* UART Serial Ports */
176 u_int8_t UART1FCRSHAD;
180 u_int8_t UART2FCRSHAD;
181 u_int8_t pad_0xcc7[0x9];
183 /* Synchronous Serial Interface */
189 u_int8_t pad_0xcd5[0x2b];
191 /* Programmable Interrupt Controller */
197 u_int8_t pad_0xd05[0x3];
200 u_int8_t pad_0xd0b[0x5];
202 u_int8_t pad_0xd12[0x2];
203 u_int16_t PCIHOSTMAP;
204 u_int8_t pad_0xd16[0x2];
209 u_int8_t pad_0xd1d[0x3];
213 u_int8_t pad_0xd23[0x5];
216 u_int8_t pad_0xd2a[0x6];
221 u_int8_t pad_0xd34[0xc];
222 u_int8_t DMABCINTMAP;
229 u_int8_t pad_0xd47[0x9];
241 u_int8_t pad_0xd5b[0x15];
243 /* Reset Generation */
249 u_int8_t pad_0xd75[0xb];
251 /* GP DMA Controller */
254 u_int16_t GPDMAEXTCHMAPA;
255 u_int16_t GPDMAEXTCHMAPB;
256 u_int8_t GPDMAEXTPG0;
257 u_int8_t GPDMAEXTPG1;
258 u_int8_t GPDMAEXTPG2;
259 u_int8_t GPDMAEXTPG3;
260 u_int8_t GPDMAEXTPG5;
261 u_int8_t GPDMAEXTPG6;
262 u_int8_t GPDMAEXTPG7;
263 u_int8_t pad_0xd8d[0x3];
264 u_int8_t GPDMAEXTTC3;
265 u_int8_t GPDMAEXTTC5;
266 u_int8_t GPDMAEXTTC6;
267 u_int8_t GPDMAEXTTC7;
268 u_int8_t pad_0xd94[0x4];
271 u_int8_t GPDMABSINTENB;
273 u_int8_t pad_0xd9c[0x4];
274 u_int16_t GPDMANXTADDL3;
275 u_int16_t GPDMANXTADDH3;
276 u_int16_t GPDMANXTADDL5;
277 u_int16_t GPDMANXTADDH5;
278 u_int16_t GPDMANXTADDL6;
279 u_int16_t GPDMANXTADDH6;
280 u_int16_t GPDMANXTADDL7;
281 u_int16_t GPDMANXTADDH7;
282 u_int16_t GPDMANXTTCL3;
283 u_int8_t GPDMANXTTCH3;
285 u_int16_t GPDMANXTTCL5;
286 u_int8_t GPDMANXTTCH5;
288 u_int16_t GPDMANXTTCL6;
289 u_int8_t GPDMANXTTCH6;
291 u_int16_t GPDMANXTTCL7;
292 u_int8_t GPDMANXTTCH7;
293 u_int8_t pad_0xdc0[0x240];
296 CTASSERT(sizeof(struct elan_mmcr) == 4096);
298 extern volatile struct elan_mmcr * elan_mmcr;
300 #endif /* _MACHINE_ELAN_MMCR_H_ */