sys/i386/include/elan_mmcr.h

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2004 John Birrell
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /* AMD Elan SC520 Memory Mapped Configuration Region (MMCR).
  30  *
  31  * The layout of this structure is documented by AMD in the Elan SC520
  32  * Microcontroller Register Set Manual. The field names match those
  33  * described in that document. The overall structure size must be 4096
  34  * bytes. Ignore fields with the 'pad' prefix - they are only present for
  35  * alignment purposes.
  36  *
  37  * $FreeBSD$
  38  */
  39
  40 #ifndef _MACHINE_ELAN_MMCR_H_
  41 #define _MACHINE_ELAN_MMCR_H_ 1
  42
  43 struct elan_mmcr {
  44         /* CPU */
  45         u_int16_t       REVID;
  46         u_int8_t        CPUCTL;
  47         u_int8_t        pad_0x003[0xd];
  48
  49         /* SDRAM Controller */
  50         u_int16_t       DRCCTL;
  51         u_int16_t       DRCTMCTL;
  52         u_int16_t       DRCCFG;
  53         u_int16_t       DRCBENDADR;
  54         u_int8_t        pad_0x01a[0x6];
  55         u_int8_t        ECCCTL;
  56         u_int8_t        ECCSTA;
  57         u_int8_t        ECCCKBPOS;
  58         u_int8_t        ECCCKTEST;
  59         u_int32_t       ECCSBADD;
  60         u_int32_t       ECCMBADD;
  61         u_int8_t        pad_0x02c[0x14];
  62
  63         /* SDRAM Buffer */
  64         u_int8_t        DBCTL;
  65         u_int8_t        pad_0x041[0xf];
  66
  67         /* ROM/Flash Controller */
  68         u_int16_t       BOOTCSCTL;
  69         u_int8_t        pad_0x052[0x2];
  70         u_int16_t       ROMCS1CTL;
  71         u_int16_t       ROMCS2CTL;
  72         u_int8_t        pad_0x058[0x8];
  73
  74         /* PCI Bus Host Bridge */
  75         u_int16_t       HBCTL;
  76         u_int16_t       HBTGTIRQCTL;
  77         u_int16_t       HBTGTIRQSTA;
  78         u_int16_t       HBMSTIRQCTL;
  79         u_int16_t       HBMSTIRQSTA;
  80         u_int8_t        pad_0x06a[0x2];
  81         u_int32_t       MSTINTADD;
  82
  83         /* System Arbitration */
  84         u_int8_t        SYSARBCTL;
  85         u_int8_t        PCIARBSTA;
  86         u_int16_t       SYSARBMENB;
  87         u_int32_t       ARBPRICTL;
  88         u_int8_t        pad_0x078[0x8];
  89
  90         /* System Address Mapping */
  91         u_int32_t       ADDDECCTL;
  92         u_int32_t       WPVSTA;
  93         u_int32_t       PAR0;
  94         u_int32_t       PAR1;
  95         u_int32_t       PAR2;
  96         u_int32_t       PAR3;
  97         u_int32_t       PAR4;
  98         u_int32_t       PAR5;
  99         u_int32_t       PAR6;
 100         u_int32_t       PAR7;
 101         u_int32_t       PAR8;
 102         u_int32_t       PAR9;
 103         u_int32_t       PAR10;
 104         u_int32_t       PAR11;
 105         u_int32_t       PAR12;
 106         u_int32_t       PAR13;
 107         u_int32_t       PAR14;
 108         u_int32_t       PAR15;
 109         u_int8_t        pad_0x0c8[0xb38];
 110
 111         /* GP Bus Controller */
 112         u_int8_t        GPECHO;
 113         u_int8_t        GPCSDW;
 114         u_int16_t       GPCSQUAL;
 115         u_int8_t        pad_0xc04[0x4];
 116         u_int8_t        GPCSRT;
 117         u_int8_t        GPCSPW;
 118         u_int8_t        GPCSOFF;
 119         u_int8_t        GPRDW;
 120         u_int8_t        GPRDOFF;
 121         u_int8_t        GPWRW;
 122         u_int8_t        GPWROFF;
 123         u_int8_t        GPALEW;
 124         u_int8_t        GPALEOFF;
 125         u_int8_t        pad_0xc11[0xf];
 126
 127         /* Programmable Input/Output */
 128         u_int16_t       PIOPFS15_0;
 129         u_int16_t       PIOPFS31_16;
 130         u_int8_t        CSPFS;
 131         u_int8_t        pad_0xc25;
 132         u_int8_t        CLKSEL;
 133         u_int8_t        pad_0xc27;
 134         u_int16_t       DSCTL;
 135         u_int16_t       PIODIR15_0;
 136         u_int16_t       PIODIR31_16;
 137         u_int8_t         pad_0xc2e[0x2];
 138         u_int16_t       PIODATA15_0;
 139         u_int16_t       PIODATA31_16;
 140         u_int16_t       PIOSET15_0;
 141         u_int16_t       PIOSET31_16;
 142         u_int16_t       PIOCLR15_0;
 143         u_int16_t       PIOCLR31_16;
 144         u_int8_t        pad_0xc3c[0x24];
 145
 146         /* Software Timer */
 147         u_int16_t       SWTMRMILLI;
 148         u_int16_t       SWTMRMICRO;
 149         u_int8_t        SWTMRCFG;
 150         u_int8_t        pad_0xc65[0xb];
 151
 152         /* General-Purpose Timers */
 153         u_int8_t        GPTMRSTA;
 154         u_int8_t        pad_0xc71;
 155         u_int16_t       GPTMR0CTL;
 156         u_int16_t       GPTMR0CNT;
 157         u_int16_t       GPTMR0MAXCMPA;
 158         u_int16_t       GPTMR0MAXCMPB;
 159         u_int16_t       GPTMR1CTL;
 160         u_int16_t       GPTMR1CNT;
 161         u_int16_t       GPTMR1MAXCMPA;
 162         u_int16_t       GPTMR1MAXCMPB;
 163         u_int16_t       GPTMR2CTL;
 164         u_int16_t       GPTMR2CNT;
 165         u_int8_t        pad_0xc86[0x8];
 166         u_int16_t       GPTMR2MAXCMPA;
 167         u_int8_t        pad_0xc90[0x20];
 168
 169         /* Watchdog Timer */
 170         u_int16_t       WDTMRCTL;
 171         u_int16_t       WDTMRCNTL;
 172         u_int16_t       WDTMRCNTH;
 173         u_int8_t        pad_0xcb6[0xa];
 174
 175         /* UART Serial Ports */
 176         u_int8_t        UART1CTL;
 177         u_int8_t        UART1STA;
 178         u_int8_t        UART1FCRSHAD;
 179         u_int8_t        pad_0xcc3;
 180         u_int8_t        UART2CTL;
 181         u_int8_t        UART2STA;
 182         u_int8_t        UART2FCRSHAD;
 183         u_int8_t        pad_0xcc7[0x9];
 184
 185         /* Synchronous Serial Interface */
 186         u_int8_t        SSICTL;
 187         u_int8_t        SSIXMIT;
 188         u_int8_t        SSICMD;
 189         u_int8_t        SSISTA;
 190         u_int8_t        SSIRCV;
 191         u_int8_t        pad_0xcd5[0x2b];
 192
 193         /* Programmable Interrupt Controller */
 194         u_int8_t        PICICR;
 195         u_int8_t        pad_0xd01;
 196         u_int8_t        MPICMODE;
 197         u_int8_t        SL1PICMODE;
 198         u_int8_t        SL2PICMODE;
 199         u_int8_t        pad_0xd05[0x3];
 200         u_int16_t       SWINT16_1;
 201         u_int8_t        SWINT22_17;
 202         u_int8_t        pad_0xd0b[0x5];
 203         u_int16_t       INTPINPOL;
 204         u_int8_t        pad_0xd12[0x2];
 205         u_int16_t       PCIHOSTMAP;
 206         u_int8_t        pad_0xd16[0x2];
 207         u_int16_t       ECCMAP;
 208         u_int8_t        GPTMR0MAP;
 209         u_int8_t        GPTMR1MAP;
 210         u_int8_t        GPTMR2MAP;
 211         u_int8_t        pad_0xd1d[0x3];
 212         u_int8_t        PIT0MAP;
 213         u_int8_t        PIT1MAP;
 214         u_int8_t        PIT2MAP;
 215         u_int8_t        pad_0xd23[0x5];
 216         u_int8_t        UART1MAP;
 217         u_int8_t        UART2MAP;
 218         u_int8_t        pad_0xd2a[0x6];
 219         u_int8_t        PCIINTAMAP;
 220         u_int8_t        PCIINTBMAP;
 221         u_int8_t        PCIINTCMAP;
 222         u_int8_t        PCIINTDMAP;
 223         u_int8_t        pad_0xd34[0xc];
 224         u_int8_t        DMABCINTMAP;
 225         u_int8_t        SSIMAP;
 226         u_int8_t        WDTMAP;
 227         u_int8_t        RTCMAP;
 228         u_int8_t        WPVMAP;
 229         u_int8_t        ICEMAP;
 230         u_int8_t        FERRMAP;
 231         u_int8_t        pad_0xd47[0x9];
 232         u_int8_t        GP0IMAP;
 233         u_int8_t        GP1IMAP;
 234         u_int8_t        GP2IMAP;
 235         u_int8_t        GP3IMAP;
 236         u_int8_t        GP4IMAP;
 237         u_int8_t        GP5IMAP;
 238         u_int8_t        GP6IMAP;
 239         u_int8_t        GP7IMAP;
 240         u_int8_t        GP8IMAP;
 241         u_int8_t        GP9IMAP;
 242         u_int8_t        GP10IMAP;
 243         u_int8_t        pad_0xd5b[0x15];
 244
 245         /* Reset Generation */
 246         u_int8_t        SYSINFO;
 247         u_int8_t        pad_0xd71;
 248         u_int8_t        RESCFG;
 249         u_int8_t        pad_0xd73;
 250         u_int8_t        RESSTA;
 251         u_int8_t        pad_0xd75[0xb];
 252
 253         /* GP DMA Controller */
 254         u_int8_t        GPDMACTL;
 255         u_int8_t        GPDMAMMIO;
 256         u_int16_t       GPDMAEXTCHMAPA;
 257         u_int16_t       GPDMAEXTCHMAPB;
 258         u_int8_t        GPDMAEXTPG0;
 259         u_int8_t        GPDMAEXTPG1;
 260         u_int8_t        GPDMAEXTPG2;
 261         u_int8_t        GPDMAEXTPG3;
 262         u_int8_t        GPDMAEXTPG5;
 263         u_int8_t        GPDMAEXTPG6;
 264         u_int8_t        GPDMAEXTPG7;
 265         u_int8_t        pad_0xd8d[0x3];
 266         u_int8_t        GPDMAEXTTC3;
 267         u_int8_t        GPDMAEXTTC5;
 268         u_int8_t        GPDMAEXTTC6;
 269         u_int8_t        GPDMAEXTTC7;
 270         u_int8_t        pad_0xd94[0x4];
 271         u_int8_t        GPDMABCCTL;
 272         u_int8_t        GPDMABCSTA;
 273         u_int8_t        GPDMABSINTENB;
 274         u_int8_t        GPDMABCVAL;
 275         u_int8_t        pad_0xd9c[0x4];
 276         u_int16_t       GPDMANXTADDL3;
 277         u_int16_t       GPDMANXTADDH3;
 278         u_int16_t       GPDMANXTADDL5;
 279         u_int16_t       GPDMANXTADDH5;
 280         u_int16_t       GPDMANXTADDL6;
 281         u_int16_t       GPDMANXTADDH6;
 282         u_int16_t       GPDMANXTADDL7;
 283         u_int16_t       GPDMANXTADDH7;
 284         u_int16_t       GPDMANXTTCL3;
 285         u_int8_t        GPDMANXTTCH3;
 286         u_int8_t        pad_0xdb3;
 287         u_int16_t       GPDMANXTTCL5;
 288         u_int8_t        GPDMANXTTCH5;
 289         u_int8_t        pad_0xdb7;
 290         u_int16_t       GPDMANXTTCL6;
 291         u_int8_t        GPDMANXTTCH6;
 292         u_int8_t        pad_0xdbb;
 293         u_int16_t       GPDMANXTTCL7;
 294         u_int8_t        GPDMANXTTCH7;
 295         u_int8_t        pad_0xdc0[0x240];
 296         };
 297
 298 CTASSERT(sizeof(struct elan_mmcr) == 4096);
 299
 300 extern volatile struct elan_mmcr * elan_mmcr;
 301
 302 #endif /* _MACHINE_ELAN_MMCR_H_ */