2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2004 John Birrell
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 /* AMD Elan SC520 Memory Mapped Configuration Region (MMCR).
31 * The layout of this structure is documented by AMD in the Elan SC520
32 * Microcontroller Register Set Manual. The field names match those
33 * described in that document. The overall structure size must be 4096
34 * bytes. Ignore fields with the 'pad' prefix - they are only present for
40 #ifndef _MACHINE_ELAN_MMCR_H_
41 #define _MACHINE_ELAN_MMCR_H_ 1
47 u_int8_t pad_0x003[0xd];
49 /* SDRAM Controller */
54 u_int8_t pad_0x01a[0x6];
61 u_int8_t pad_0x02c[0x14];
65 u_int8_t pad_0x041[0xf];
67 /* ROM/Flash Controller */
69 u_int8_t pad_0x052[0x2];
72 u_int8_t pad_0x058[0x8];
74 /* PCI Bus Host Bridge */
76 u_int16_t HBTGTIRQCTL;
77 u_int16_t HBTGTIRQSTA;
78 u_int16_t HBMSTIRQCTL;
79 u_int16_t HBMSTIRQSTA;
80 u_int8_t pad_0x06a[0x2];
83 /* System Arbitration */
88 u_int8_t pad_0x078[0x8];
90 /* System Address Mapping */
109 u_int8_t pad_0x0c8[0xb38];
111 /* GP Bus Controller */
115 u_int8_t pad_0xc04[0x4];
125 u_int8_t pad_0xc11[0xf];
127 /* Programmable Input/Output */
128 u_int16_t PIOPFS15_0;
129 u_int16_t PIOPFS31_16;
135 u_int16_t PIODIR15_0;
136 u_int16_t PIODIR31_16;
137 u_int8_t pad_0xc2e[0x2];
138 u_int16_t PIODATA15_0;
139 u_int16_t PIODATA31_16;
140 u_int16_t PIOSET15_0;
141 u_int16_t PIOSET31_16;
142 u_int16_t PIOCLR15_0;
143 u_int16_t PIOCLR31_16;
144 u_int8_t pad_0xc3c[0x24];
147 u_int16_t SWTMRMILLI;
148 u_int16_t SWTMRMICRO;
150 u_int8_t pad_0xc65[0xb];
152 /* General-Purpose Timers */
157 u_int16_t GPTMR0MAXCMPA;
158 u_int16_t GPTMR0MAXCMPB;
161 u_int16_t GPTMR1MAXCMPA;
162 u_int16_t GPTMR1MAXCMPB;
165 u_int8_t pad_0xc86[0x8];
166 u_int16_t GPTMR2MAXCMPA;
167 u_int8_t pad_0xc90[0x20];
173 u_int8_t pad_0xcb6[0xa];
175 /* UART Serial Ports */
178 u_int8_t UART1FCRSHAD;
182 u_int8_t UART2FCRSHAD;
183 u_int8_t pad_0xcc7[0x9];
185 /* Synchronous Serial Interface */
191 u_int8_t pad_0xcd5[0x2b];
193 /* Programmable Interrupt Controller */
199 u_int8_t pad_0xd05[0x3];
202 u_int8_t pad_0xd0b[0x5];
204 u_int8_t pad_0xd12[0x2];
205 u_int16_t PCIHOSTMAP;
206 u_int8_t pad_0xd16[0x2];
211 u_int8_t pad_0xd1d[0x3];
215 u_int8_t pad_0xd23[0x5];
218 u_int8_t pad_0xd2a[0x6];
223 u_int8_t pad_0xd34[0xc];
224 u_int8_t DMABCINTMAP;
231 u_int8_t pad_0xd47[0x9];
243 u_int8_t pad_0xd5b[0x15];
245 /* Reset Generation */
251 u_int8_t pad_0xd75[0xb];
253 /* GP DMA Controller */
256 u_int16_t GPDMAEXTCHMAPA;
257 u_int16_t GPDMAEXTCHMAPB;
258 u_int8_t GPDMAEXTPG0;
259 u_int8_t GPDMAEXTPG1;
260 u_int8_t GPDMAEXTPG2;
261 u_int8_t GPDMAEXTPG3;
262 u_int8_t GPDMAEXTPG5;
263 u_int8_t GPDMAEXTPG6;
264 u_int8_t GPDMAEXTPG7;
265 u_int8_t pad_0xd8d[0x3];
266 u_int8_t GPDMAEXTTC3;
267 u_int8_t GPDMAEXTTC5;
268 u_int8_t GPDMAEXTTC6;
269 u_int8_t GPDMAEXTTC7;
270 u_int8_t pad_0xd94[0x4];
273 u_int8_t GPDMABSINTENB;
275 u_int8_t pad_0xd9c[0x4];
276 u_int16_t GPDMANXTADDL3;
277 u_int16_t GPDMANXTADDH3;
278 u_int16_t GPDMANXTADDL5;
279 u_int16_t GPDMANXTADDH5;
280 u_int16_t GPDMANXTADDL6;
281 u_int16_t GPDMANXTADDH6;
282 u_int16_t GPDMANXTADDL7;
283 u_int16_t GPDMANXTADDH7;
284 u_int16_t GPDMANXTTCL3;
285 u_int8_t GPDMANXTTCH3;
287 u_int16_t GPDMANXTTCL5;
288 u_int8_t GPDMANXTTCH5;
290 u_int16_t GPDMANXTTCL6;
291 u_int8_t GPDMANXTTCH6;
293 u_int16_t GPDMANXTTCL7;
294 u_int8_t GPDMANXTTCH7;
295 u_int8_t pad_0xdc0[0x240];
298 CTASSERT(sizeof(struct elan_mmcr) == 4096);
300 extern volatile struct elan_mmcr * elan_mmcr;
302 #endif /* _MACHINE_ELAN_MMCR_H_ */