2 * Copyright (c) 1995 Bruce D. Evans.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #ifndef _MACHINE_MD_VAR_H_
33 #define _MACHINE_MD_VAR_H_
36 * Miscellaneous machine-dependent declarations.
40 extern u_int basemem; /* PA of original top of base memory */
41 extern int busdma_swi_pending;
42 extern u_int cpu_exthigh;
43 extern u_int cpu_feature;
44 extern u_int cpu_feature2;
45 extern u_int amd_feature;
46 extern u_int amd_feature2;
47 extern u_int amd_pminfo;
48 extern u_int via_feature_rng;
49 extern u_int via_feature_xcrypt;
50 extern u_int cpu_clflush_line_size;
51 extern u_int cpu_stdext_feature;
52 extern u_int cpu_stdext_feature2;
53 extern u_int cpu_fxsr;
54 extern u_int cpu_high;
56 extern u_int cpu_max_ext_state_size;
57 extern u_int cpu_mxcsr_mask;
58 extern u_int cpu_procinfo;
59 extern u_int cpu_procinfo2;
60 extern char cpu_vendor[];
61 extern u_int cpu_vendor_id;
62 extern u_int cpu_mon_mwait_flags;
63 extern u_int cpu_mon_min_size;
64 extern u_int cpu_mon_max_size;
65 extern u_int cpu_maxphyaddr;
66 extern u_int cyrix_did;
67 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
68 extern int has_f00f_bug;
71 extern char hv_vendor[];
73 extern char sigcode[];
75 #ifdef COMPAT_FREEBSD4
76 extern int szfreebsd4_sigcode;
79 extern int szosigcode;
81 extern uint32_t *vm_page_dump;
82 extern int vm_page_dump_size;
83 extern int workaround_erratum383;
87 extern uint64_t xsave_mask;
89 typedef void alias_for_inthand_t(u_int cs, u_int ef, u_int esp, u_int ss);
97 struct segment_descriptor;
99 void *alloc_fpusave(int flags);
100 void bcopyb(const void *from, void *to, size_t len);
101 void busdma_swi(void);
102 bool cpu_mwait_usable(void);
103 void cpu_probe_amdc1e(void);
104 void cpu_setregs(void);
105 void cpu_switch_load_gs(void) __asm(__STRING(cpu_switch_load_gs));
106 void doreti_iret(void) __asm(__STRING(doreti_iret));
107 void doreti_iret_fault(void) __asm(__STRING(doreti_iret_fault));
108 void doreti_popl_ds(void) __asm(__STRING(doreti_popl_ds));
109 void doreti_popl_ds_fault(void) __asm(__STRING(doreti_popl_ds_fault));
110 void doreti_popl_es(void) __asm(__STRING(doreti_popl_es));
111 void doreti_popl_es_fault(void) __asm(__STRING(doreti_popl_es_fault));
112 void doreti_popl_fs(void) __asm(__STRING(doreti_popl_fs));
113 void doreti_popl_fs_fault(void) __asm(__STRING(doreti_popl_fs_fault));
114 void dump_add_page(vm_paddr_t);
115 void dump_drop_page(vm_paddr_t);
116 void finishidentcpu(void);
117 void fillw(int /*u_short*/ pat, void *base, size_t cnt);
118 void fill_based_sd(struct segment_descriptor *sdp, uint32_t base);
119 void initializecpu(void);
120 void initializecpucache(void);
121 void i686_pagezero(void *addr);
122 void sse2_pagezero(void *addr);
123 void init_AMD_Elan_sc520(void);
124 int is_physical_memory(vm_paddr_t addr);
126 vm_paddr_t kvtop(void *addr);
127 void panicifcpuunsupported(void);
128 void ppro_reenable_apic(void);
129 void printcpuinfo(void);
130 void setidt(int idx, alias_for_inthand_t *func, int typ, int dpl, int selec);
131 int user_dbreg_trap(void);
132 int minidumpsys(struct dumperinfo *);
133 union savefpu *get_pcb_user_save_td(struct thread *td);
134 union savefpu *get_pcb_user_save_pcb(struct pcb *pcb);
135 struct pcb *get_pcb_td(struct thread *td);
137 #endif /* !_MACHINE_MD_VAR_H_ */