2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $Id: mp_machdep.c,v 1.79 1998/08/24 02:28:15 bde Exp $
31 #include "opt_user_ldt.h"
34 #include <machine/smptests.h>
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/kernel.h>
43 #include <sys/sysctl.h>
45 #include <sys/dkstat.h>
49 #include <vm/vm_param.h>
51 #include <vm/vm_kern.h>
52 #include <vm/vm_extern.h>
55 #include <vm/vm_map.h>
62 #include <machine/smp.h>
63 #include <machine/apic.h>
64 #include <machine/mpapic.h>
65 #include <machine/segments.h>
66 #include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */
67 #include <machine/tss.h>
68 #include <machine/specialreg.h>
69 #include <machine/cputypes.h>
70 #include <machine/globaldata.h>
72 #include <i386/i386/cons.h> /* cngetc() */
75 #include <machine/md_var.h> /* setidt() */
76 #include <i386/isa/icu.h> /* IPIs */
77 #include <i386/isa/intr_machdep.h> /* IPIs */
80 #if defined(TEST_DEFAULT_CONFIG)
81 #define MPFPS_MPFB1 TEST_DEFAULT_CONFIG
83 #define MPFPS_MPFB1 mpfps->mpfb1
84 #endif /* TEST_DEFAULT_CONFIG */
86 #define WARMBOOT_TARGET 0
87 #define WARMBOOT_OFF (KERNBASE + 0x0467)
88 #define WARMBOOT_SEG (KERNBASE + 0x0469)
90 #define BIOS_BASE (0xf0000)
91 #define BIOS_SIZE (0x10000)
92 #define BIOS_COUNT (BIOS_SIZE/4)
94 #define CMOS_REG (0x70)
95 #define CMOS_DATA (0x71)
96 #define BIOS_RESET (0x0f)
97 #define BIOS_WARM (0x0a)
99 #define PROCENTRY_FLAG_EN 0x01
100 #define PROCENTRY_FLAG_BP 0x02
101 #define IOAPICENTRY_FLAG_EN 0x01
104 /* MP Floating Pointer Structure */
105 typedef struct MPFPS {
118 /* MP Configuration Table Header */
119 typedef struct MPCTH {
121 u_short base_table_length;
125 u_char product_id[12];
126 void *oem_table_pointer;
127 u_short oem_table_size;
130 u_short extended_table_length;
131 u_char extended_table_checksum;
136 typedef struct PROCENTRY {
141 u_long cpu_signature;
142 u_long feature_flags;
147 typedef struct BUSENTRY {
153 typedef struct IOAPICENTRY {
159 } *io_apic_entry_ptr;
161 typedef struct INTENTRY {
171 /* descriptions of MP basetable entries */
172 typedef struct BASETABLE_ENTRY {
179 * this code MUST be enabled here and in mpboot.s.
180 * it follows the very early stages of AP boot by placing values in CMOS ram.
181 * it NORMALLY will never be needed and thus the primitive method for enabling.
186 #if defined(CHECK_POINTS)
187 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
188 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
190 #define CHECK_INIT(D); \
191 CHECK_WRITE(0x34, (D)); \
192 CHECK_WRITE(0x35, (D)); \
193 CHECK_WRITE(0x36, (D)); \
194 CHECK_WRITE(0x37, (D)); \
195 CHECK_WRITE(0x38, (D)); \
196 CHECK_WRITE(0x39, (D));
198 #define CHECK_PRINT(S); \
199 printf("%s: %d, %d, %d, %d, %d, %d\n", \
208 #else /* CHECK_POINTS */
210 #define CHECK_INIT(D)
211 #define CHECK_PRINT(S)
213 #endif /* CHECK_POINTS */
216 * Values to send to the POST hardware.
218 #define MP_BOOTADDRESS_POST 0x10
219 #define MP_PROBE_POST 0x11
220 #define MPTABLE_PASS1_POST 0x12
222 #define MP_START_POST 0x13
223 #define MP_ENABLE_POST 0x14
224 #define MPTABLE_PASS2_POST 0x15
226 #define START_ALL_APS_POST 0x16
227 #define INSTALL_AP_TRAMP_POST 0x17
228 #define START_AP_POST 0x18
230 #define MP_ANNOUNCE_POST 0x19
233 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
234 int current_postcode;
236 /** XXX FIXME: what system files declare these??? */
237 extern struct region_descriptor r_gdt, r_idt;
239 int bsp_apic_ready = 0; /* flags useability of BSP apic */
240 int mp_ncpus; /* # of CPUs, including BSP */
241 int mp_naps; /* # of Applications processors */
242 int mp_nbusses; /* # of busses */
243 int mp_napics; /* # of IO APICs */
244 int boot_cpu_id; /* designated BSP */
245 vm_offset_t cpu_apic_address;
246 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
249 u_int32_t cpu_apic_versions[NCPU];
250 u_int32_t io_apic_versions[NAPIC];
252 #ifdef APIC_INTR_DIAGNOSTIC
253 int apic_itrace_enter[32];
254 int apic_itrace_tryisrlock[32];
255 int apic_itrace_gotisrlock[32];
256 int apic_itrace_active[32];
257 int apic_itrace_masked[32];
258 int apic_itrace_noisrlock[32];
259 int apic_itrace_masked2[32];
260 int apic_itrace_unmask[32];
261 int apic_itrace_noforward[32];
262 int apic_itrace_leave[32];
263 int apic_itrace_enter2[32];
264 int apic_itrace_doreti[32];
265 int apic_itrace_splz[32];
266 int apic_itrace_eoi[32];
267 #ifdef APIC_INTR_DIAGNOSTIC_IRQ
268 unsigned short apic_itrace_debugbuffer[32768];
269 int apic_itrace_debugbuffer_idx;
270 struct simplelock apic_itrace_debuglock;
274 #ifdef APIC_INTR_REORDER
276 volatile int *location;
278 } apic_isrbit_location[32];
281 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
284 * APIC ID logical/physical mapping structures.
285 * We oversize these to simplify boot-time config.
287 int cpu_num_to_apic_id[NAPICID];
288 int io_num_to_apic_id[NAPICID];
289 int apic_id_to_logical[NAPICID];
292 /* Bitmap of all available CPUs */
295 /* AP uses this PTD during bootstrap. Do not staticize. */
298 /* Hotwire a 0->4MB V==P mapping */
299 extern pt_entry_t *KPTphys;
301 /* Virtual address of per-cpu common_tss */
302 extern struct i386tss common_tss;
304 extern struct segment_descriptor common_tssd;
305 extern u_int private_tss; /* flag indicating private tss */
309 /* IdlePTD per cpu */
310 pd_entry_t *IdlePTDS[NCPU];
312 /* "my" private page table page, for BSP init */
313 extern pt_entry_t SMP_prvpt[];
315 /* Private page pointer to curcpu's PTD, used during BSP init */
316 extern pd_entry_t *my_idlePTD;
318 struct pcb stoppcbs[NCPU];
320 int smp_started; /* has the system started? */
323 * Local data and functions.
326 static int mp_capable;
327 static u_int boot_address;
328 static u_int base_memory;
330 static int picmode; /* 0: virtual wire mode, 1: PIC mode */
331 static mpfps_t mpfps;
332 static int search_for_sig(u_int32_t target, int count);
333 static void mp_enable(u_int boot_addr);
335 static int mptable_pass1(void);
336 static int mptable_pass2(void);
337 static void default_mp_table(int type);
338 static void fix_mp_table(void);
339 static void setup_apic_irq_mapping(void);
340 static void init_locks(void);
341 static int start_all_aps(u_int boot_addr);
342 static void install_ap_tramp(u_int boot_addr);
343 static int start_ap(int logicalCpu, u_int boot_addr);
346 * Calculate usable address in base memory for AP trampoline code.
349 mp_bootaddress(u_int basemem)
351 POSTCODE(MP_BOOTADDRESS_POST);
353 base_memory = basemem * 1024; /* convert to bytes */
355 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
356 if ((base_memory - boot_address) < bootMP_size)
357 boot_address -= 4096; /* not enough, lower by 4k */
364 * Look for an Intel MP spec table (ie, SMP capable hardware).
373 POSTCODE(MP_PROBE_POST);
375 /* see if EBDA exists */
376 if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) {
377 /* search first 1K of EBDA */
378 target = (u_int32_t) (segment << 4);
379 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
382 /* last 1K of base memory, effective 'top of base' passed in */
383 target = (u_int32_t) (base_memory - 0x400);
384 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
388 /* search the BIOS */
389 target = (u_int32_t) BIOS_BASE;
390 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
399 /* calculate needed resources */
402 panic("you must reconfigure your kernel");
404 /* flag fact that we are running multiple processors */
411 * Startup the SMP processors.
416 POSTCODE(MP_START_POST);
418 /* look for MP capable motherboard */
420 mp_enable(boot_address);
422 panic("MP hardware not found!");
427 * Print various information about the SMP system hardware and setup.
434 POSTCODE(MP_ANNOUNCE_POST);
436 printf("FreeBSD/SMP: Multiprocessor motherboard\n");
437 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
438 printf(", version: 0x%08x", cpu_apic_versions[0]);
439 printf(", at 0x%08x\n", cpu_apic_address);
440 for (x = 1; x <= mp_naps; ++x) {
441 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
442 printf(", version: 0x%08x", cpu_apic_versions[x]);
443 printf(", at 0x%08x\n", cpu_apic_address);
447 for (x = 0; x < mp_napics; ++x) {
448 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
449 printf(", version: 0x%08x", io_apic_versions[x]);
450 printf(", at 0x%08x\n", io_apic_address[x]);
453 printf(" Warning: APIC I/O disabled\n");
458 * AP cpu's call this to sync up protected mode.
468 r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1;
469 r_gdt.rd_base = (int) gdt;
470 lgdt(&r_gdt); /* does magic intra-segment return */
474 currentldt = _default_ldt;
477 my_tr = NGDT + cpuid;
478 gsel_tss = GSEL(my_tr, SEL_KPL);
479 gdt[my_tr].sd.sd_type = SDT_SYS386TSS;
480 common_tss.tss_esp0 = 0; /* not used until after switch */
481 common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
482 common_tss.tss_ioopt = (sizeof common_tss) << 16;
484 common_tssd = gdt[my_tr].sd;
489 load_cr0(0x8005003b); /* XXX! */
492 pmap_set_opt((unsigned *)PTD);
503 * Final configuration of the BSP's local APIC:
504 * - disable 'pic mode'.
505 * - disable 'virtual wire mode'.
509 bsp_apic_configure(void)
514 /* leave 'pic mode' if necessary */
516 outb(0x22, 0x70); /* select IMCR */
517 byte = inb(0x23); /* current contents */
518 byte |= 0x01; /* mask external INTR */
519 outb(0x23, byte); /* disconnect 8259s/NMI */
522 /* mask lint0 (the 8259 'virtual wire' connection) */
523 temp = lapic.lvt_lint0;
524 temp |= APIC_LVT_M; /* set the mask */
525 lapic.lvt_lint0 = temp;
527 /* setup lint1 to handle NMI */
528 temp = lapic.lvt_lint1;
529 temp &= ~APIC_LVT_M; /* clear the mask */
530 lapic.lvt_lint1 = temp;
533 apic_dump("bsp_apic_configure()");
538 /*******************************************************************
539 * local functions and data
543 * start the SMP system
546 mp_enable(u_int boot_addr)
557 POSTCODE(MP_ENABLE_POST);
559 /* turn on 4MB of V == P addressing so we can get to MP table */
560 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
563 /* examine the MP table for needed info, uses physical addresses */
569 /* can't process default configs till the CPU APIC is pmapped */
573 /* post scan cleanup */
575 setup_apic_irq_mapping();
579 /* fill the LOGICAL io_apic_versions table */
580 for (apic = 0; apic < mp_napics; ++apic) {
581 ux = io_apic_read(apic, IOAPIC_VER);
582 io_apic_versions[apic] = ux;
585 /* program each IO APIC in the system */
586 for (apic = 0; apic < mp_napics; ++apic)
587 if (io_apic_setup(apic) < 0)
588 panic("IO APIC setup failure");
590 /* install a 'Spurious INTerrupt' vector */
591 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
592 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
594 /* install an inter-CPU IPI for TLB invalidation */
595 setidt(XINVLTLB_OFFSET, Xinvltlb,
596 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
599 /* install an inter-CPU IPI for reading processor state */
600 setidt(XCPUCHECKSTATE_OFFSET, Xcpucheckstate,
601 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
604 /* install an inter-CPU IPI for forcing an additional software trap */
605 setidt(XCPUAST_OFFSET, Xcpuast,
606 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
608 /* install an inter-CPU IPI for interrupt forwarding */
609 setidt(XFORWARD_IRQ_OFFSET, Xforward_irq,
610 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
612 /* install an inter-CPU IPI for CPU stop/restart */
613 setidt(XCPUSTOP_OFFSET, Xcpustop,
614 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
616 #if defined(TEST_TEST1)
617 /* install a "fake hardware INTerrupt" vector */
618 setidt(XTEST1_OFFSET, Xtest1,
619 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
620 #endif /** TEST_TEST1 */
624 /* initialize all SMP locks */
627 /* start each Application Processor */
628 start_all_aps(boot_addr);
631 * The init process might be started on a different CPU now,
632 * and the boot CPU might not call prepare_usermode to get
633 * cr0 correctly configured. Thus we initialize cr0 here.
635 load_cr0(rcr0() | CR0_WP | CR0_AM);
640 * look for the MP spec signature
643 /* string defined by the Intel MP Spec as identifying the MP table */
644 #define MP_SIG 0x5f504d5f /* _MP_ */
645 #define NEXT(X) ((X) += 4)
647 search_for_sig(u_int32_t target, int count)
650 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
652 for (x = 0; x < count; NEXT(x))
653 if (addr[x] == MP_SIG)
654 /* make array index a byte index */
655 return (target + (x * sizeof(u_int32_t)));
661 static basetable_entry basetable_entry_types[] =
663 {0, 20, "Processor"},
670 typedef struct BUSDATA {
672 enum busTypes bus_type;
675 typedef struct INTDATA {
685 typedef struct BUSTYPENAME {
690 static bus_type_name bus_type_table[] =
695 {UNKNOWN_BUSTYPE, "---"},
696 {UNKNOWN_BUSTYPE, "---"},
698 {UNKNOWN_BUSTYPE, "---"},
699 {UNKNOWN_BUSTYPE, "---"},
700 {UNKNOWN_BUSTYPE, "---"},
701 {UNKNOWN_BUSTYPE, "---"},
702 {UNKNOWN_BUSTYPE, "---"},
703 {UNKNOWN_BUSTYPE, "---"},
705 {UNKNOWN_BUSTYPE, "---"},
706 {UNKNOWN_BUSTYPE, "---"},
707 {UNKNOWN_BUSTYPE, "---"},
708 {UNKNOWN_BUSTYPE, "---"},
710 {UNKNOWN_BUSTYPE, "---"}
712 /* from MP spec v1.4, table 5-1 */
713 static int default_data[7][5] =
715 /* nbus, id0, type0, id1, type1 */
716 {1, 0, ISA, 255, 255},
717 {1, 0, EISA, 255, 255},
718 {1, 0, EISA, 255, 255},
719 {0, 255, 255, 255, 255},/* MCA not supported */
721 {2, 0, EISA, 1, PCI},
722 {0, 255, 255, 255, 255} /* MCA not supported */
727 static bus_datum bus_data[NBUS];
729 /* the IO INT data, one entry per possible APIC INTerrupt */
730 static io_int io_apic_ints[NINTR];
734 static int processor_entry __P((proc_entry_ptr entry, int cpu));
735 static int bus_entry __P((bus_entry_ptr entry, int bus));
736 static int io_apic_entry __P((io_apic_entry_ptr entry, int apic));
737 static int int_entry __P((int_entry_ptr entry, int intr));
738 static int lookup_bus_type __P((char *name));
742 * 1st pass on motherboard's Intel MP specification table.
748 * cpu_apic_address (common to all CPUs)
766 POSTCODE(MPTABLE_PASS1_POST);
770 /* clear various tables */
771 for (x = 0; x < NAPICID; ++x) {
772 io_apic_address[x] = ~0; /* IO APIC address table */
775 /* init everything to empty */
781 /* check for use of 'default' configuration */
782 if (MPFPS_MPFB1 != 0) {
783 /* use default addresses */
784 cpu_apic_address = DEFAULT_APIC_BASE;
785 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
787 /* fill in with defaults */
788 mp_naps = 2; /* includes BSP */
789 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0];
796 if ((cth = mpfps->pap) == 0)
797 panic("MP Configuration Table Header MISSING!");
799 cpu_apic_address = (vm_offset_t) cth->apic_address;
801 /* walk the table, recording info of interest */
802 totalSize = cth->base_table_length - sizeof(struct MPCTH);
803 position = (u_char *) cth + sizeof(struct MPCTH);
804 count = cth->entry_count;
807 switch (type = *(u_char *) position) {
808 case 0: /* processor_entry */
809 if (((proc_entry_ptr)position)->cpu_flags
813 case 1: /* bus_entry */
816 case 2: /* io_apic_entry */
817 if (((io_apic_entry_ptr)position)->apic_flags
818 & IOAPICENTRY_FLAG_EN)
819 io_apic_address[mp_napics++] =
820 (vm_offset_t)((io_apic_entry_ptr)
821 position)->apic_address;
823 case 3: /* int_entry */
826 case 4: /* int_entry */
829 panic("mpfps Base Table HOSED!");
833 totalSize -= basetable_entry_types[type].length;
834 (u_char*)position += basetable_entry_types[type].length;
838 /* qualify the numbers */
840 #if 0 /* XXX FIXME: kern/4255 */
841 printf("Warning: only using %d of %d available CPUs!\n",
845 printf("NCPU cannot be different than actual CPU count.\n");
846 printf(" add 'options NCPU=%d' to your kernel config file,\n",
848 printf(" then rerun config & rebuild your SMP kernel\n");
851 #endif /* XXX FIXME: kern/4255 */
852 if (mp_nbusses > NBUS) {
853 printf("found %d busses, increase NBUS\n", mp_nbusses);
856 if (mp_napics > NAPIC) {
857 printf("found %d apics, increase NAPIC\n", mp_napics);
860 if (nintrs > NINTR) {
861 printf("found %d intrs, increase NINTR\n", nintrs);
867 * This is also used as a counter while starting the APs.
871 --mp_naps; /* subtract the BSP */
878 * 2nd pass on motherboard's Intel MP specification table.
882 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
883 * CPU_TO_ID(N), logical CPU to APIC ID table
884 * IO_TO_ID(N), logical IO to APIC ID table
897 int apic, bus, cpu, intr;
899 POSTCODE(MPTABLE_PASS2_POST);
901 /* clear various tables */
902 for (x = 0; x < NAPICID; ++x) {
903 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
904 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
905 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
908 /* clear bus data table */
909 for (x = 0; x < NBUS; ++x)
910 bus_data[x].bus_id = 0xff;
912 /* clear IO APIC INT table */
913 for (x = 0; x < NINTR; ++x) {
914 io_apic_ints[x].int_type = 0xff;
915 io_apic_ints[x].int_vector = 0xff;
918 /* setup the cpu/apic mapping arrays */
921 /* record whether PIC or virtual-wire mode */
922 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0;
924 /* check for use of 'default' configuration */
925 if (MPFPS_MPFB1 != 0)
926 return MPFPS_MPFB1; /* return default configuration type */
928 if ((cth = mpfps->pap) == 0)
929 panic("MP Configuration Table Header MISSING!");
931 /* walk the table, recording info of interest */
932 totalSize = cth->base_table_length - sizeof(struct MPCTH);
933 position = (u_char *) cth + sizeof(struct MPCTH);
934 count = cth->entry_count;
935 apic = bus = intr = 0;
936 cpu = 1; /* pre-count the BSP */
939 switch (type = *(u_char *) position) {
941 if (processor_entry(position, cpu))
945 if (bus_entry(position, bus))
949 if (io_apic_entry(position, apic))
953 if (int_entry(position, intr))
957 /* int_entry(position); */
960 panic("mpfps Base Table HOSED!");
964 totalSize -= basetable_entry_types[type].length;
965 (u_char *) position += basetable_entry_types[type].length;
968 if (boot_cpu_id == -1)
969 panic("NO BSP found!");
971 /* report fact that its NOT a default configuration */
977 assign_apic_irq(int apic, int intpin, int irq)
981 if (int_to_apicintpin[irq].ioapic != -1)
982 panic("assign_apic_irq: inconsistent table");
984 int_to_apicintpin[irq].ioapic = apic;
985 int_to_apicintpin[irq].int_pin = intpin;
986 int_to_apicintpin[irq].apic_address = ioapic[apic];
987 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
989 for (x = 0; x < nintrs; x++) {
990 if ((io_apic_ints[x].int_type == 0 ||
991 io_apic_ints[x].int_type == 3) &&
992 io_apic_ints[x].int_vector == 0xff &&
993 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
994 io_apic_ints[x].dst_apic_int == intpin)
995 io_apic_ints[x].int_vector = irq;
1000 * parse an Intel MP specification table
1012 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1013 * did it wrong. The MP spec says that when more than 1 PCI bus
1014 * exists the BIOS must begin with bus entries for the PCI bus and use
1015 * actual PCI bus numbering. This implies that when only 1 PCI bus
1016 * exists the BIOS can choose to ignore this ordering, and indeed many
1017 * MP motherboards do ignore it. This causes a problem when the PCI
1018 * sub-system makes requests of the MP sub-system based on PCI bus
1019 * numbers. So here we look for the situation and renumber the
1020 * busses and associated INTs in an effort to "make it right".
1023 /* find bus 0, PCI bus, count the number of PCI busses */
1024 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1025 if (bus_data[x].bus_id == 0) {
1028 if (bus_data[x].bus_type == PCI) {
1034 * bus_0 == slot of bus with ID of 0
1035 * bus_pci == slot of last PCI bus encountered
1038 /* check the 1 PCI bus case for sanity */
1039 if (num_pci_bus == 1) {
1041 /* if it is number 0 all is well */
1042 if (bus_data[bus_pci].bus_id == 0)
1045 /* mis-numbered, swap with whichever bus uses slot 0 */
1047 /* swap the bus entry types */
1048 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1049 bus_data[bus_0].bus_type = PCI;
1051 /* swap each relavant INTerrupt entry */
1052 id = bus_data[bus_pci].bus_id;
1053 for (x = 0; x < nintrs; ++x) {
1054 if (io_apic_ints[x].src_bus_id == id) {
1055 io_apic_ints[x].src_bus_id = 0;
1057 else if (io_apic_ints[x].src_bus_id == 0) {
1058 io_apic_ints[x].src_bus_id = id;
1062 /* sanity check if more than 1 PCI bus */
1063 else if (num_pci_bus > 1) {
1064 for (x = 0; x < mp_nbusses; ++x) {
1065 if (bus_data[x].bus_type != PCI)
1067 if (bus_data[x].bus_id >= num_pci_bus)
1068 panic("bad PCI bus numbering");
1075 setup_apic_irq_mapping(void)
1080 /* Assign low level interrupt handlers */
1081 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1082 int_to_apicintpin[x].ioapic = -1;
1083 int_to_apicintpin[x].int_pin = 0;
1084 int_to_apicintpin[x].apic_address = NULL;
1085 int_to_apicintpin[x].redirindex = 0;
1087 for (x = 0; x < nintrs; x++) {
1088 if (io_apic_ints[x].dst_apic_int <= APIC_INTMAPSIZE &&
1089 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1090 io_apic_ints[x].int_vector == 0xff &&
1091 (io_apic_ints[x].int_type == 0 ||
1092 io_apic_ints[x].int_type == 3)) {
1094 io_apic_ints[x].dst_apic_int,
1095 io_apic_ints[x].dst_apic_int);
1099 while (int_vector < APIC_INTMAPSIZE &&
1100 int_to_apicintpin[int_vector].ioapic != -1)
1102 for (x = 0; x < nintrs && int_vector < APIC_INTMAPSIZE; x++) {
1103 if ((io_apic_ints[x].int_type == 0 ||
1104 io_apic_ints[x].int_type == 3) &&
1105 io_apic_ints[x].int_vector == 0xff) {
1106 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1107 io_apic_ints[x].dst_apic_int,
1110 while (int_vector < APIC_INTMAPSIZE &&
1111 int_to_apicintpin[int_vector].ioapic != -1)
1119 processor_entry(proc_entry_ptr entry, int cpu)
1121 /* check for usability */
1122 if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN))
1125 /* check for BSP flag */
1126 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1127 boot_cpu_id = entry->apic_id;
1128 CPU_TO_ID(0) = entry->apic_id;
1129 ID_TO_CPU(entry->apic_id) = 0;
1130 return 0; /* its already been counted */
1133 /* add another AP to list, if less than max number of CPUs */
1135 CPU_TO_ID(cpu) = entry->apic_id;
1136 ID_TO_CPU(entry->apic_id) = cpu;
1143 bus_entry(bus_entry_ptr entry, int bus)
1148 /* encode the name into an index */
1149 for (x = 0; x < 6; ++x) {
1150 if ((c = entry->bus_type[x]) == ' ')
1156 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1157 panic("unknown bus type: '%s'", name);
1159 bus_data[bus].bus_id = entry->bus_id;
1160 bus_data[bus].bus_type = x;
1167 io_apic_entry(io_apic_entry_ptr entry, int apic)
1169 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1172 IO_TO_ID(apic) = entry->apic_id;
1173 ID_TO_IO(entry->apic_id) = apic;
1180 lookup_bus_type(char *name)
1184 for (x = 0; x < MAX_BUSTYPE; ++x)
1185 if (strcmp(bus_type_table[x].name, name) == 0)
1186 return bus_type_table[x].type;
1188 return UNKNOWN_BUSTYPE;
1193 int_entry(int_entry_ptr entry, int intr)
1195 io_apic_ints[intr].int_type = entry->int_type;
1196 io_apic_ints[intr].int_flags = entry->int_flags;
1197 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1198 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1199 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1200 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1207 apic_int_is_bus_type(int intr, int bus_type)
1211 for (bus = 0; bus < mp_nbusses; ++bus)
1212 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1213 && ((int) bus_data[bus].bus_type == bus_type))
1221 * Given a traditional ISA INT mask, return an APIC mask.
1224 isa_apic_mask(u_int isa_mask)
1229 #if defined(SKIP_IRQ15_REDIRECT)
1230 if (isa_mask == (1 << 15)) {
1231 printf("skipping ISA IRQ15 redirect\n");
1234 #endif /* SKIP_IRQ15_REDIRECT */
1236 isa_irq = ffs(isa_mask); /* find its bit position */
1237 if (isa_irq == 0) /* doesn't exist */
1239 --isa_irq; /* make it zero based */
1241 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1245 return (1 << apic_pin); /* convert pin# to a mask */
1250 * Determine which APIC pin an ISA/EISA INT is attached to.
1252 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1253 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1254 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1255 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1257 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1259 isa_apic_irq(int isa_irq)
1263 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1264 if (INTTYPE(intr) == 0) { /* standard INT */
1265 if (SRCBUSIRQ(intr) == isa_irq) {
1266 if (apic_int_is_bus_type(intr, ISA) ||
1267 apic_int_is_bus_type(intr, EISA))
1268 return INTIRQ(intr); /* found */
1272 return -1; /* NOT found */
1277 * Determine which APIC pin a PCI INT is attached to.
1279 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1280 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1281 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1283 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1287 --pciInt; /* zero based */
1289 for (intr = 0; intr < nintrs; ++intr) /* check each record */
1290 if ((INTTYPE(intr) == 0) /* standard INT */
1291 && (SRCBUSID(intr) == pciBus)
1292 && (SRCBUSDEVICE(intr) == pciDevice)
1293 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */
1294 if (apic_int_is_bus_type(intr, PCI))
1295 return INTIRQ(intr); /* exact match */
1297 return -1; /* NOT found */
1301 next_apic_irq(int irq)
1308 for (intr = 0; intr < nintrs; intr++) {
1309 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1311 bus = SRCBUSID(intr);
1312 bustype = apic_bus_type(bus);
1313 if (bustype != ISA &&
1319 if (intr >= nintrs) {
1322 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1323 if (INTTYPE(ointr) != 0)
1325 if (bus != SRCBUSID(ointr))
1327 if (bustype == PCI) {
1328 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1330 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1333 if (bustype == ISA || bustype == EISA) {
1334 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1337 if (INTPIN(intr) == INTPIN(ointr))
1341 if (ointr >= nintrs) {
1344 return INTIRQ(ointr);
1358 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1361 * Exactly what this means is unclear at this point. It is a solution
1362 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1363 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1364 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1368 undirect_isa_irq(int rirq)
1371 printf("Freeing redirected ISA irq %d.\n", rirq);
1372 /** FIXME: tickle the MB redirector chip */
1375 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1382 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1385 undirect_pci_irq(int rirq)
1389 printf("Freeing redirected PCI irq %d.\n", rirq);
1391 /** FIXME: tickle the MB redirector chip */
1395 printf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1403 * given a bus ID, return:
1404 * the bus type if found
1408 apic_bus_type(int id)
1412 for (x = 0; x < mp_nbusses; ++x)
1413 if (bus_data[x].bus_id == id)
1414 return bus_data[x].bus_type;
1421 * given a LOGICAL APIC# and pin#, return:
1422 * the associated src bus ID if found
1426 apic_src_bus_id(int apic, int pin)
1430 /* search each of the possible INTerrupt sources */
1431 for (x = 0; x < nintrs; ++x)
1432 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1433 (pin == io_apic_ints[x].dst_apic_int))
1434 return (io_apic_ints[x].src_bus_id);
1436 return -1; /* NOT found */
1441 * given a LOGICAL APIC# and pin#, return:
1442 * the associated src bus IRQ if found
1446 apic_src_bus_irq(int apic, int pin)
1450 for (x = 0; x < nintrs; x++)
1451 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1452 (pin == io_apic_ints[x].dst_apic_int))
1453 return (io_apic_ints[x].src_bus_irq);
1455 return -1; /* NOT found */
1460 * given a LOGICAL APIC# and pin#, return:
1461 * the associated INTerrupt type if found
1465 apic_int_type(int apic, int pin)
1469 /* search each of the possible INTerrupt sources */
1470 for (x = 0; x < nintrs; ++x)
1471 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1472 (pin == io_apic_ints[x].dst_apic_int))
1473 return (io_apic_ints[x].int_type);
1475 return -1; /* NOT found */
1479 apic_irq(int apic, int pin)
1484 for (x = 0; x < nintrs; ++x)
1485 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1486 (pin == io_apic_ints[x].dst_apic_int)) {
1487 res = io_apic_ints[x].int_vector;
1490 if (apic != int_to_apicintpin[res].ioapic)
1491 panic("apic_irq: inconsistent table");
1492 if (pin != int_to_apicintpin[res].int_pin)
1493 panic("apic_irq inconsistent table (2)");
1501 * given a LOGICAL APIC# and pin#, return:
1502 * the associated trigger mode if found
1506 apic_trigger(int apic, int pin)
1510 /* search each of the possible INTerrupt sources */
1511 for (x = 0; x < nintrs; ++x)
1512 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1513 (pin == io_apic_ints[x].dst_apic_int))
1514 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1516 return -1; /* NOT found */
1521 * given a LOGICAL APIC# and pin#, return:
1522 * the associated 'active' level if found
1526 apic_polarity(int apic, int pin)
1530 /* search each of the possible INTerrupt sources */
1531 for (x = 0; x < nintrs; ++x)
1532 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1533 (pin == io_apic_ints[x].dst_apic_int))
1534 return (io_apic_ints[x].int_flags & 0x03);
1536 return -1; /* NOT found */
1541 * set data according to MP defaults
1542 * FIXME: probably not complete yet...
1545 default_mp_table(int type)
1548 #if defined(APIC_IO)
1552 #endif /* APIC_IO */
1555 printf(" MP default config type: %d\n", type);
1558 printf(" bus: ISA, APIC: 82489DX\n");
1561 printf(" bus: EISA, APIC: 82489DX\n");
1564 printf(" bus: EISA, APIC: 82489DX\n");
1567 printf(" bus: MCA, APIC: 82489DX\n");
1570 printf(" bus: ISA+PCI, APIC: Integrated\n");
1573 printf(" bus: EISA+PCI, APIC: Integrated\n");
1576 printf(" bus: MCA+PCI, APIC: Integrated\n");
1579 printf(" future type\n");
1585 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1586 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1589 CPU_TO_ID(0) = boot_cpu_id;
1590 ID_TO_CPU(boot_cpu_id) = 0;
1592 /* one and only AP */
1593 CPU_TO_ID(1) = ap_cpu_id;
1594 ID_TO_CPU(ap_cpu_id) = 1;
1596 #if defined(APIC_IO)
1597 /* one and only IO APIC */
1598 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1601 * sanity check, refer to MP spec section 3.6.6, last paragraph
1602 * necessary as some hardware isn't properly setting up the IO APIC
1604 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1605 if (io_apic_id != 2) {
1607 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1608 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1609 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */
1610 ux &= ~APIC_ID_MASK; /* clear the ID field */
1611 ux |= 0x02000000; /* set it to '2' */
1612 io_apic_write(0, IOAPIC_ID, ux); /* write new value */
1613 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */
1614 if ((ux & APIC_ID_MASK) != 0x02000000)
1615 panic("can't control IO APIC ID, reg: 0x%08x", ux);
1618 IO_TO_ID(0) = io_apic_id;
1619 ID_TO_IO(io_apic_id) = 0;
1620 #endif /* APIC_IO */
1622 /* fill out bus entries */
1629 bus_data[0].bus_id = default_data[type - 1][1];
1630 bus_data[0].bus_type = default_data[type - 1][2];
1631 bus_data[1].bus_id = default_data[type - 1][3];
1632 bus_data[1].bus_type = default_data[type - 1][4];
1635 /* case 4: case 7: MCA NOT supported */
1636 default: /* illegal/reserved */
1637 panic("BAD default MP config: %d", type);
1641 #if defined(APIC_IO)
1642 /* general cases from MP v1.4, table 5-2 */
1643 for (pin = 0; pin < 16; ++pin) {
1644 io_apic_ints[pin].int_type = 0;
1645 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
1646 io_apic_ints[pin].src_bus_id = 0;
1647 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
1648 io_apic_ints[pin].dst_apic_id = io_apic_id;
1649 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
1652 /* special cases from MP v1.4, table 5-2 */
1654 io_apic_ints[2].int_type = 0xff; /* N/C */
1655 io_apic_ints[13].int_type = 0xff; /* N/C */
1656 #if !defined(APIC_MIXED_MODE)
1658 panic("sorry, can't support type 2 default yet");
1659 #endif /* APIC_MIXED_MODE */
1662 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
1665 io_apic_ints[0].int_type = 0xff; /* N/C */
1667 io_apic_ints[0].int_type = 3; /* vectored 8259 */
1668 #endif /* APIC_IO */
1673 * initialize all the SMP locks
1676 /* critical region around IO APIC, apic_imen */
1677 struct simplelock imen_lock;
1679 /* critical region around splxx(), cpl, cml, cil, ipending */
1680 struct simplelock cpl_lock;
1682 /* Make FAST_INTR() routines sequential */
1683 struct simplelock fast_intr_lock;
1685 /* critical region around INTR() routines */
1686 struct simplelock intr_lock;
1688 /* lock regions protected in UP kernel via cli/sti */
1689 struct simplelock mpintr_lock;
1691 /* lock region used by kernel profiling */
1692 struct simplelock mcount_lock;
1695 /* locks com (tty) data/hardware accesses: a FASTINTR() */
1696 struct simplelock com_lock;
1697 #endif /* USE_COMLOCK */
1699 #ifdef USE_CLOCKLOCK
1700 /* lock regions around the clock hardware */
1701 struct simplelock clock_lock;
1702 #endif /* USE_CLOCKLOCK */
1708 * Get the initial mp_lock with a count of 1 for the BSP.
1709 * This uses a LOGICAL cpu ID, ie BSP == 0.
1711 mp_lock = 0x00000001;
1713 /* ISR uses its own "giant lock" */
1714 isr_lock = FREE_LOCK;
1716 #if defined(APIC_INTR_DIAGNOSTIC) && defined(APIC_INTR_DIAGNOSTIC_IRQ)
1717 s_lock_init((struct simplelock*)&apic_itrace_debuglock);
1720 s_lock_init((struct simplelock*)&mpintr_lock);
1722 s_lock_init((struct simplelock*)&mcount_lock);
1724 s_lock_init((struct simplelock*)&fast_intr_lock);
1725 s_lock_init((struct simplelock*)&intr_lock);
1726 s_lock_init((struct simplelock*)&imen_lock);
1727 s_lock_init((struct simplelock*)&cpl_lock);
1730 s_lock_init((struct simplelock*)&com_lock);
1731 #endif /* USE_COMLOCK */
1732 #ifdef USE_CLOCKLOCK
1733 s_lock_init((struct simplelock*)&clock_lock);
1734 #endif /* USE_CLOCKLOCK */
1739 * start each AP in our list
1742 start_all_aps(u_int boot_addr)
1745 u_char mpbiosreason;
1746 u_long mpbioswarmvec;
1749 struct globaldata *gd;
1753 POSTCODE(START_ALL_APS_POST);
1755 /* initialize BSP's local APIC */
1759 /* install the AP 1st level boot code */
1760 install_ap_tramp(boot_addr);
1763 /* save the current value of the warm-start vector */
1764 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
1765 outb(CMOS_REG, BIOS_RESET);
1766 mpbiosreason = inb(CMOS_DATA);
1768 /* record BSP in CPU map */
1772 for (x = 1; x <= mp_naps; ++x) {
1774 /* This is a bit verbose, it will go away soon. */
1776 /* alloc new page table directory */
1777 newptd = (pd_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE));
1779 /* Store the virtual PTD address for this CPU */
1780 IdlePTDS[x] = newptd;
1782 /* clone currently active one (ie: IdlePTD) */
1783 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */
1785 /* set up 0 -> 4MB P==V mapping for AP boot */
1786 newptd[0] = (void *)(uintptr_t)(PG_V | PG_RW |
1787 ((uintptr_t)(void *)KPTphys & PG_FRAME));
1789 /* store PTD for this AP's boot sequence */
1790 myPTD = (pd_entry_t *)vtophys(newptd);
1792 /* alloc new page table page */
1793 newpt = (pt_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE));
1795 /* set the new PTD's private page to point there */
1796 newptd[MPPTDI] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpt));
1798 /* install self referential entry */
1799 newptd[PTDPTDI] = (pd_entry_t)(PG_V | PG_RW | vtophys(newptd));
1801 /* allocate a new private data page */
1802 gd = (struct globaldata *)kmem_alloc(kernel_map, PAGE_SIZE);
1804 /* wire it into the private page table page */
1805 newpt[0] = (pt_entry_t)(PG_V | PG_RW | vtophys(gd));
1807 /* wire the ptp into itself for access */
1808 newpt[1] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpt));
1810 /* copy in the pointer to the local apic */
1811 newpt[2] = SMP_prvpt[2];
1813 /* and the IO apic mapping[s] */
1814 for (i = 16; i < 32; i++)
1815 newpt[i] = SMP_prvpt[i];
1817 /* allocate and set up an idle stack data page */
1818 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE);
1819 for (i = 0; i < UPAGES; i++)
1820 newpt[i + 3] = (pt_entry_t)(PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
1822 newpt[3 + UPAGES] = 0; /* *prv_CMAP1 */
1823 newpt[4 + UPAGES] = 0; /* *prv_CMAP2 */
1824 newpt[5 + UPAGES] = 0; /* *prv_CMAP3 */
1825 newpt[6 + UPAGES] = 0; /* *prv_PMAP1 */
1827 /* prime data page for it to use */
1829 gd->cpu_lockid = x << 24;
1830 gd->my_idlePTD = myPTD;
1831 gd->prv_CMAP1 = &newpt[3 + UPAGES];
1832 gd->prv_CMAP2 = &newpt[4 + UPAGES];
1833 gd->prv_CMAP3 = &newpt[5 + UPAGES];
1834 gd->prv_PMAP1 = &newpt[6 + UPAGES];
1836 /* setup a vector to our boot code */
1837 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
1838 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
1839 outb(CMOS_REG, BIOS_RESET);
1840 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
1843 /* attempt to start the Application Processor */
1844 CHECK_INIT(99); /* setup checkpoints */
1845 if (!start_ap(x, boot_addr)) {
1846 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
1847 CHECK_PRINT("trace"); /* show checkpoints */
1848 /* better panic as the AP may be running loose */
1849 printf("panic y/n? [y] ");
1850 if (cngetc() != 'n')
1853 CHECK_PRINT("trace"); /* show checkpoints */
1855 /* record its version info */
1856 cpu_apic_versions[x] = cpu_apic_versions[0];
1858 all_cpus |= (1 << x); /* record AP in CPU map */
1861 /* build our map of 'other' CPUs */
1862 other_cpus = all_cpus & ~(1 << cpuid);
1864 /* fill in our (BSP) APIC version */
1865 cpu_apic_versions[0] = lapic.version;
1867 /* restore the warmstart vector */
1868 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
1869 outb(CMOS_REG, BIOS_RESET);
1870 outb(CMOS_DATA, mpbiosreason);
1873 * Set up the idle context for the BSP. Similar to above except
1874 * that some was done by locore, some by pmap.c and some is implicit
1875 * because the BSP is cpu#0 and the page is initially zero, and also
1876 * because we can refer to variables by name on the BSP..
1878 newptd = (pd_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE));
1880 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */
1881 IdlePTDS[0] = newptd;
1883 /* Point PTD[] to this page instead of IdlePTD's physical page */
1884 newptd[PTDPTDI] = (pd_entry_t)(PG_V | PG_RW | vtophys(newptd));
1886 my_idlePTD = (pd_entry_t *)vtophys(newptd);
1888 /* Allocate and setup BSP idle stack */
1889 stack = (char *)kmem_alloc(kernel_map, UPAGES * PAGE_SIZE);
1890 for (i = 0; i < UPAGES; i++)
1891 SMP_prvpt[i + 3] = (pt_entry_t)(PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
1895 for (i = 0; i < mp_ncpus; i++) {
1896 bcopy( (int *) PTD + KPTDI, (int *) IdlePTDS[i] + KPTDI, NKPDE * sizeof (int));
1899 /* number of APs actually started */
1900 return mp_ncpus - 1;
1905 * load the 1st level AP boot code into base memory.
1908 /* targets for relocation */
1909 extern void bigJump(void);
1910 extern void bootCodeSeg(void);
1911 extern void bootDataSeg(void);
1912 extern void MPentry(void);
1913 extern u_int MP_GDT;
1914 extern u_int mp_gdtbase;
1917 install_ap_tramp(u_int boot_addr)
1920 int size = *(int *) ((u_long) & bootMP_size);
1921 u_char *src = (u_char *) ((u_long) bootMP);
1922 u_char *dst = (u_char *) boot_addr + KERNBASE;
1923 u_int boot_base = (u_int) bootMP;
1928 POSTCODE(INSTALL_AP_TRAMP_POST);
1930 for (x = 0; x < size; ++x)
1934 * modify addresses in code we just moved to basemem. unfortunately we
1935 * need fairly detailed info about mpboot.s for this to work. changes
1936 * to mpboot.s might require changes here.
1939 /* boot code is located in KERNEL space */
1940 dst = (u_char *) boot_addr + KERNBASE;
1942 /* modify the lgdt arg */
1943 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
1944 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
1946 /* modify the ljmp target for MPentry() */
1947 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
1948 *dst32 = ((u_int) MPentry - KERNBASE);
1950 /* modify the target for boot code segment */
1951 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
1952 dst8 = (u_int8_t *) (dst16 + 1);
1953 *dst16 = (u_int) boot_addr & 0xffff;
1954 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
1956 /* modify the target for boot data segment */
1957 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
1958 dst8 = (u_int8_t *) (dst16 + 1);
1959 *dst16 = (u_int) boot_addr & 0xffff;
1960 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
1965 * this function starts the AP (application processor) identified
1966 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
1967 * to accomplish this. This is necessary because of the nuances
1968 * of the different hardware we might encounter. It ain't pretty,
1969 * but it seems to work.
1972 start_ap(int logical_cpu, u_int boot_addr)
1977 u_long icr_lo, icr_hi;
1979 POSTCODE(START_AP_POST);
1981 /* get the PHYSICAL APIC ID# */
1982 physical_cpu = CPU_TO_ID(logical_cpu);
1984 /* calculate the vector */
1985 vector = (boot_addr >> 12) & 0xff;
1987 /* used as a watchpoint to signal AP startup */
1991 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
1992 * and running the target CPU. OR this INIT IPI might be latched (P5
1993 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
1997 /* setup the address for the target AP */
1998 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
1999 icr_hi |= (physical_cpu << 24);
2000 lapic.icr_hi = icr_hi;
2002 /* do an INIT IPI: assert RESET */
2003 icr_lo = lapic.icr_lo & 0xfff00000;
2004 lapic.icr_lo = icr_lo | 0x0000c500;
2006 /* wait for pending status end */
2007 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2010 /* do an INIT IPI: deassert RESET */
2011 lapic.icr_lo = icr_lo | 0x00008500;
2013 /* wait for pending status end */
2014 u_sleep(10000); /* wait ~10mS */
2015 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2019 * next we do a STARTUP IPI: the previous INIT IPI might still be
2020 * latched, (P5 bug) this 1st STARTUP would then terminate
2021 * immediately, and the previously started INIT IPI would continue. OR
2022 * the previous INIT IPI has already run. and this STARTUP IPI will
2023 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2027 /* do a STARTUP IPI */
2028 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2029 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2031 u_sleep(200); /* wait ~200uS */
2034 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2035 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2036 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2037 * recognized after hardware RESET or INIT IPI.
2040 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2041 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2043 u_sleep(200); /* wait ~200uS */
2045 /* wait for it to start */
2046 set_apic_timer(5000000);/* == 5 seconds */
2047 while (read_apic_timer())
2048 if (mp_ncpus > cpus)
2049 return 1; /* return SUCCESS */
2051 return 0; /* return FAILURE */
2056 * Flush the TLB on all other CPU's
2058 * XXX: Needs to handshake and wait for completion before proceding.
2063 #if defined(APIC_IO)
2064 if (smp_started && invltlb_ok)
2065 all_but_self_ipi(XINVLTLB_OFFSET);
2066 #endif /* APIC_IO */
2072 __asm __volatile("invlpg (%0)"::"r"(addr):"memory");
2074 /* send a message to the other CPUs */
2084 * This should be implemented as load_cr3(rcr3()) when load_cr3() is
2087 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory");
2089 /* send a message to the other CPUs */
2095 * When called the executing CPU will send an IPI to all other CPUs
2096 * requesting that they halt execution.
2098 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2100 * - Signals all CPUs in map to stop.
2101 * - Waits for each to stop.
2108 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2109 * from executing at same time.
2112 stop_cpus(u_int map)
2117 /* send the Xcpustop IPI to all CPUs in map */
2118 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2120 while ((stopped_cpus & map) != map)
2128 * Called by a CPU to restart stopped CPUs.
2130 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2132 * - Signals all CPUs in map to restart.
2133 * - Waits for each to restart.
2141 restart_cpus(u_int map)
2146 started_cpus = map; /* signal other cpus to restart */
2148 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2154 int smp_active = 0; /* are the APs allowed to run? */
2155 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RW, &smp_active, 0, "");
2157 /* XXX maybe should be hw.ncpu */
2158 static int smp_cpus = 1; /* how many cpu's running */
2159 SYSCTL_INT(_machdep, OID_AUTO, smp_cpus, CTLFLAG_RD, &smp_cpus, 0, "");
2161 int invltlb_ok = 0; /* throttle smp_invltlb() till safe */
2162 SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, "");
2164 /* Warning: Do not staticize. Used from swtch.s */
2165 int do_page_zero_idle = 1; /* bzero pages for fun and profit in idleloop */
2166 SYSCTL_INT(_machdep, OID_AUTO, do_page_zero_idle, CTLFLAG_RW,
2167 &do_page_zero_idle, 0, "");
2169 /* Is forwarding of a interrupt to the CPU holding the ISR lock enabled ? */
2170 int forward_irq_enabled = 1;
2171 SYSCTL_INT(_machdep, OID_AUTO, forward_irq_enabled, CTLFLAG_RW,
2172 &forward_irq_enabled, 0, "");
2174 /* Enable forwarding of a signal to a process running on a different CPU */
2175 int forward_signal_enabled = 1;
2176 SYSCTL_INT(_machdep, OID_AUTO, forward_signal_enabled, CTLFLAG_RW,
2177 &forward_signal_enabled, 0, "");
2179 /* Enable forwarding of roundrobin to all other cpus */
2180 int forward_roundrobin_enabled = 1;
2181 SYSCTL_INT(_machdep, OID_AUTO, forward_roundrobin_enabled, CTLFLAG_RW,
2182 &forward_roundrobin_enabled, 0, "");
2185 * This is called once the rest of the system is up and running and we're
2186 * ready to let the AP's out of the pen.
2198 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2202 /* Build our map of 'other' CPUs. */
2203 other_cpus = all_cpus & ~(1 << cpuid);
2205 printf("SMP: AP CPU #%d Launched!\n", cpuid);
2207 /* XXX FIXME: i386 specific, and redundant: Setup the FPU. */
2208 load_cr0((rcr0() & ~CR0_EM) | CR0_MP | CR0_NE | CR0_TS);
2210 /* A quick check from sanity claus */
2211 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2212 if (cpuid != apic_id) {
2213 printf("SMP: cpuid = %d\n", cpuid);
2214 printf("SMP: apic_id = %d\n", apic_id);
2215 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2216 panic("cpuid mismatch! boom!!");
2221 /* Init local apic for irq's */
2225 * Activate smp_invltlb, although strictly speaking, this isn't
2226 * quite correct yet. We should have a bitfield for cpus willing
2227 * to accept TLB flush IPI's or something and sync them.
2229 if (smp_cpus == mp_ncpus) {
2231 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */
2232 smp_active = 1; /* historic */
2235 curproc = NULL; /* make sure */
2240 #define CHECKSTATE_USER 0
2241 #define CHECKSTATE_SYS 1
2242 #define CHECKSTATE_INTR 2
2244 /* Do not staticize. Used from apic_vector.s */
2245 struct proc* checkstate_curproc[NCPU];
2246 int checkstate_cpustate[NCPU];
2247 u_long checkstate_pc[NCPU];
2249 extern long cp_time[CPUSTATES];
2251 #define PC_TO_INDEX(pc, prof) \
2252 ((int)(((u_quad_t)((pc) - (prof)->pr_off) * \
2253 (u_quad_t)((prof)->pr_scale)) >> 16) & ~1)
2256 addupc_intr_forwarded(struct proc *p, int id, int *astmap)
2262 pc = checkstate_pc[id];
2263 prof = &p->p_stats->p_prof;
2264 if (pc >= prof->pr_off &&
2265 (i = PC_TO_INDEX(pc, prof)) < prof->pr_size) {
2266 if ((p->p_flag & P_OWEUPC) == 0) {
2269 p->p_flag |= P_OWEUPC;
2271 *astmap |= (1 << id);
2276 forwarded_statclock(int id, int pscnt, int *astmap)
2278 struct pstats *pstats;
2285 register struct gmonparam *g;
2289 p = checkstate_curproc[id];
2290 cpustate = checkstate_cpustate[id];
2293 case CHECKSTATE_USER:
2294 if (p->p_flag & P_PROFIL)
2295 addupc_intr_forwarded(p, id, astmap);
2299 if (p->p_nice > NZERO)
2304 case CHECKSTATE_SYS:
2307 * Kernel statistics are just like addupc_intr, only easier.
2310 if (g->state == GMON_PROF_ON) {
2311 i = checkstate_pc[id] - g->lowpc;
2312 if (i < g->textsize) {
2313 i /= HISTFRACTION * sizeof(*g->kcount);
2328 case CHECKSTATE_INTR:
2332 * Kernel statistics are just like addupc_intr, only easier.
2335 if (g->state == GMON_PROF_ON) {
2336 i = checkstate_pc[id] - g->lowpc;
2337 if (i < g->textsize) {
2338 i /= HISTFRACTION * sizeof(*g->kcount);
2351 if (++p->p_estcpu == 0)
2353 if ((p->p_estcpu & 3) == 0) {
2355 if (p->p_priority >= PUSER)
2356 p->p_priority = p->p_usrpri;
2359 /* Update resource usage integrals and maximums. */
2360 if ((pstats = p->p_stats) != NULL &&
2361 (ru = &pstats->p_ru) != NULL &&
2362 (vm = p->p_vmspace) != NULL) {
2363 ru->ru_ixrss += vm->vm_tsize * PAGE_SIZE / 1024;
2364 ru->ru_idrss += vm->vm_dsize * PAGE_SIZE / 1024;
2365 ru->ru_isrss += vm->vm_ssize * PAGE_SIZE / 1024;
2366 rss = vm->vm_pmap.pm_stats.resident_count *
2368 if (ru->ru_maxrss < rss)
2369 ru->ru_maxrss = rss;
2375 forward_statclock(int pscnt)
2381 /* Kludge. We don't yet have separate locks for the interrupts
2382 * and the kernel. This means that we cannot let the other processors
2383 * handle complex interrupts while inhibiting them from entering
2384 * the kernel in a non-interrupt context.
2386 * What we can do, without changing the locking mechanisms yet,
2387 * is letting the other processors handle a very simple interrupt
2388 * (wich determines the processor states), and do the main
2392 if (!smp_started || !invltlb_ok || cold || panicstr)
2395 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle ) */
2397 map = other_cpus & ~stopped_cpus ;
2398 checkstate_probed_cpus = 0;
2400 selected_apic_ipi(map,
2401 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2404 while (checkstate_probed_cpus != map) {
2408 #ifdef BETTER_CLOCK_DIAGNOSTIC
2409 printf("forward_statclock: checkstate %x\n",
2410 checkstate_probed_cpus);
2417 * Step 2: walk through other processors processes, update ticks and
2422 for (id = 0; id < mp_ncpus; id++) {
2425 if (((1 << id) & checkstate_probed_cpus) == 0)
2427 forwarded_statclock(id, pscnt, &map);
2430 checkstate_need_ast |= map;
2431 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2433 while ((checkstate_need_ast & map) != 0) {
2437 #ifdef BETTER_CLOCK_DIAGNOSTIC
2438 printf("forward_statclock: dropped ast 0x%x\n",
2439 checkstate_need_ast & map);
2448 forward_hardclock(int pscnt)
2453 struct pstats *pstats;
2456 /* Kludge. We don't yet have separate locks for the interrupts
2457 * and the kernel. This means that we cannot let the other processors
2458 * handle complex interrupts while inhibiting them from entering
2459 * the kernel in a non-interrupt context.
2461 * What we can do, without changing the locking mechanisms yet,
2462 * is letting the other processors handle a very simple interrupt
2463 * (wich determines the processor states), and do the main
2467 if (!smp_started || !invltlb_ok || cold || panicstr)
2470 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle) */
2472 map = other_cpus & ~stopped_cpus ;
2473 checkstate_probed_cpus = 0;
2475 selected_apic_ipi(map,
2476 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2479 while (checkstate_probed_cpus != map) {
2483 #ifdef BETTER_CLOCK_DIAGNOSTIC
2484 printf("forward_hardclock: checkstate %x\n",
2485 checkstate_probed_cpus);
2492 * Step 2: walk through other processors processes, update virtual
2493 * timer and profiling timer. If stathz == 0, also update ticks and
2498 for (id = 0; id < mp_ncpus; id++) {
2501 if (((1 << id) & checkstate_probed_cpus) == 0)
2503 p = checkstate_curproc[id];
2505 pstats = p->p_stats;
2506 if (checkstate_cpustate[id] == CHECKSTATE_USER &&
2507 timevalisset(&pstats->p_timer[ITIMER_VIRTUAL].it_value) &&
2508 itimerdecr(&pstats->p_timer[ITIMER_VIRTUAL], tick) == 0) {
2509 psignal(p, SIGVTALRM);
2512 if (timevalisset(&pstats->p_timer[ITIMER_PROF].it_value) &&
2513 itimerdecr(&pstats->p_timer[ITIMER_PROF], tick) == 0) {
2514 psignal(p, SIGPROF);
2519 forwarded_statclock( id, pscnt, &map);
2523 checkstate_need_ast |= map;
2524 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2526 while ((checkstate_need_ast & map) != 0) {
2530 #ifdef BETTER_CLOCK_DIAGNOSTIC
2531 printf("forward_hardclock: dropped ast 0x%x\n",
2532 checkstate_need_ast & map);
2540 #endif /* BETTER_CLOCK */
2543 forward_signal(struct proc *p)
2549 /* Kludge. We don't yet have separate locks for the interrupts
2550 * and the kernel. This means that we cannot let the other processors
2551 * handle complex interrupts while inhibiting them from entering
2552 * the kernel in a non-interrupt context.
2554 * What we can do, without changing the locking mechanisms yet,
2555 * is letting the other processors handle a very simple interrupt
2556 * (wich determines the processor states), and do the main
2560 if (!smp_started || !invltlb_ok || cold || panicstr)
2562 if (!forward_signal_enabled)
2565 if (p->p_stat != SRUN)
2567 id = (u_char) p->p_oncpu;
2571 checkstate_need_ast |= map;
2572 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2574 while ((checkstate_need_ast & map) != 0) {
2579 printf("forward_signal: dropped ast 0x%x\n",
2580 checkstate_need_ast & map);
2585 if (id == (u_char) p->p_oncpu)
2591 forward_roundrobin(void)
2596 if (!smp_started || !invltlb_ok || cold || panicstr)
2598 if (!forward_roundrobin_enabled)
2600 resched_cpus |= other_cpus;
2601 map = other_cpus & ~stopped_cpus ;
2603 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2605 (void) all_but_self_ipi(XCPUAST_OFFSET);
2608 while ((checkstate_need_ast & map) != 0) {
2613 printf("forward_roundrobin: dropped ast 0x%x\n",
2614 checkstate_need_ast & map);
2622 #ifdef APIC_INTR_REORDER
2624 * Maintain mapping from softintr vector to isr bit in local apic.
2627 set_lapic_isrloc(int intr, int vector)
2629 if (intr < 0 || intr > 32)
2630 panic("set_apic_isrloc: bad intr argument: %d",intr);
2631 if (vector < ICU_OFFSET || vector > 255)
2632 panic("set_apic_isrloc: bad vector argument: %d",vector);
2633 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2);
2634 apic_isrbit_location[intr].bit = (1<<(vector & 31));