2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $Id: mp_machdep.c,v 1.78 1998/08/18 07:46:58 msmith Exp $
31 #include "opt_user_ldt.h"
34 #include <machine/smptests.h>
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/kernel.h>
43 #include <sys/sysctl.h>
45 #include <sys/dkstat.h>
49 #include <vm/vm_param.h>
51 #include <vm/vm_kern.h>
52 #include <vm/vm_extern.h>
55 #include <vm/vm_map.h>
62 #include <machine/smp.h>
63 #include <machine/apic.h>
64 #include <machine/mpapic.h>
65 #include <machine/segments.h>
66 #include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */
67 #include <machine/tss.h>
68 #include <machine/specialreg.h>
69 #include <machine/cputypes.h>
70 #include <machine/globaldata.h>
72 #include <i386/i386/cons.h> /* cngetc() */
75 #include <machine/md_var.h> /* setidt() */
76 #include <i386/isa/icu.h> /* IPIs */
77 #include <i386/isa/intr_machdep.h> /* IPIs */
80 #if defined(TEST_DEFAULT_CONFIG)
81 #define MPFPS_MPFB1 TEST_DEFAULT_CONFIG
83 #define MPFPS_MPFB1 mpfps->mpfb1
84 #endif /* TEST_DEFAULT_CONFIG */
86 #define WARMBOOT_TARGET 0
87 #define WARMBOOT_OFF (KERNBASE + 0x0467)
88 #define WARMBOOT_SEG (KERNBASE + 0x0469)
90 #define BIOS_BASE (0xf0000)
91 #define BIOS_SIZE (0x10000)
92 #define BIOS_COUNT (BIOS_SIZE/4)
94 #define CMOS_REG (0x70)
95 #define CMOS_DATA (0x71)
96 #define BIOS_RESET (0x0f)
97 #define BIOS_WARM (0x0a)
99 #define PROCENTRY_FLAG_EN 0x01
100 #define PROCENTRY_FLAG_BP 0x02
101 #define IOAPICENTRY_FLAG_EN 0x01
104 /* MP Floating Pointer Structure */
105 typedef struct MPFPS {
118 /* MP Configuration Table Header */
119 typedef struct MPCTH {
121 u_short base_table_length;
125 u_char product_id[12];
126 void *oem_table_pointer;
127 u_short oem_table_size;
130 u_short extended_table_length;
131 u_char extended_table_checksum;
136 typedef struct PROCENTRY {
141 u_long cpu_signature;
142 u_long feature_flags;
147 typedef struct BUSENTRY {
153 typedef struct IOAPICENTRY {
159 } *io_apic_entry_ptr;
161 typedef struct INTENTRY {
171 /* descriptions of MP basetable entries */
172 typedef struct BASETABLE_ENTRY {
179 * this code MUST be enabled here and in mpboot.s.
180 * it follows the very early stages of AP boot by placing values in CMOS ram.
181 * it NORMALLY will never be needed and thus the primitive method for enabling.
186 #if defined(CHECK_POINTS)
187 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
188 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
190 #define CHECK_INIT(D); \
191 CHECK_WRITE(0x34, (D)); \
192 CHECK_WRITE(0x35, (D)); \
193 CHECK_WRITE(0x36, (D)); \
194 CHECK_WRITE(0x37, (D)); \
195 CHECK_WRITE(0x38, (D)); \
196 CHECK_WRITE(0x39, (D));
198 #define CHECK_PRINT(S); \
199 printf("%s: %d, %d, %d, %d, %d, %d\n", \
208 #else /* CHECK_POINTS */
210 #define CHECK_INIT(D)
211 #define CHECK_PRINT(S)
213 #endif /* CHECK_POINTS */
216 * Values to send to the POST hardware.
218 #define MP_BOOTADDRESS_POST 0x10
219 #define MP_PROBE_POST 0x11
220 #define MPTABLE_PASS1_POST 0x12
222 #define MP_START_POST 0x13
223 #define MP_ENABLE_POST 0x14
224 #define MPTABLE_PASS2_POST 0x15
226 #define START_ALL_APS_POST 0x16
227 #define INSTALL_AP_TRAMP_POST 0x17
228 #define START_AP_POST 0x18
230 #define MP_ANNOUNCE_POST 0x19
233 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
234 int current_postcode;
236 /** XXX FIXME: what system files declare these??? */
237 extern struct region_descriptor r_gdt, r_idt;
239 int bsp_apic_ready = 0; /* flags useability of BSP apic */
240 int mp_ncpus; /* # of CPUs, including BSP */
241 int mp_naps; /* # of Applications processors */
242 int mp_nbusses; /* # of busses */
243 int mp_napics; /* # of IO APICs */
244 int boot_cpu_id; /* designated BSP */
245 vm_offset_t cpu_apic_address;
246 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
249 u_int32_t cpu_apic_versions[NCPU];
250 u_int32_t io_apic_versions[NAPIC];
252 #ifdef APIC_INTR_DIAGNOSTIC
253 int apic_itrace_enter[32];
254 int apic_itrace_tryisrlock[32];
255 int apic_itrace_gotisrlock[32];
256 int apic_itrace_active[32];
257 int apic_itrace_masked[32];
258 int apic_itrace_noisrlock[32];
259 int apic_itrace_masked2[32];
260 int apic_itrace_unmask[32];
261 int apic_itrace_noforward[32];
262 int apic_itrace_leave[32];
263 int apic_itrace_enter2[32];
264 int apic_itrace_doreti[32];
265 int apic_itrace_splz[32];
266 int apic_itrace_eoi[32];
267 #ifdef APIC_INTR_DIAGNOSTIC_IRQ
268 unsigned short apic_itrace_debugbuffer[32768];
269 int apic_itrace_debugbuffer_idx;
270 struct simplelock apic_itrace_debuglock;
274 #ifdef APIC_INTR_REORDER
276 volatile int *location;
278 } apic_isrbit_location[32];
282 * APIC ID logical/physical mapping structures.
283 * We oversize these to simplify boot-time config.
285 int cpu_num_to_apic_id[NAPICID];
286 int io_num_to_apic_id[NAPICID];
287 int apic_id_to_logical[NAPICID];
290 /* Bitmap of all available CPUs */
293 /* AP uses this PTD during bootstrap. Do not staticize. */
296 /* Hotwire a 0->4MB V==P mapping */
297 extern pt_entry_t *KPTphys;
299 /* Virtual address of per-cpu common_tss */
300 extern struct i386tss common_tss;
302 extern struct segment_descriptor common_tssd;
303 extern u_int private_tss; /* flag indicating private tss */
307 /* IdlePTD per cpu */
308 pd_entry_t *IdlePTDS[NCPU];
310 /* "my" private page table page, for BSP init */
311 extern pt_entry_t SMP_prvpt[];
313 /* Private page pointer to curcpu's PTD, used during BSP init */
314 extern pd_entry_t *my_idlePTD;
316 struct pcb stoppcbs[NCPU];
318 static int smp_started; /* has the system started? */
321 * Local data and functions.
324 static int mp_capable;
325 static u_int boot_address;
326 static u_int base_memory;
328 static int picmode; /* 0: virtual wire mode, 1: PIC mode */
329 static mpfps_t mpfps;
330 static int search_for_sig(u_int32_t target, int count);
331 static void mp_enable(u_int boot_addr);
333 static int mptable_pass1(void);
334 static int mptable_pass2(void);
335 static void default_mp_table(int type);
336 static void fix_mp_table(void);
337 static void init_locks(void);
338 static int start_all_aps(u_int boot_addr);
339 static void install_ap_tramp(u_int boot_addr);
340 static int start_ap(int logicalCpu, u_int boot_addr);
343 * Calculate usable address in base memory for AP trampoline code.
346 mp_bootaddress(u_int basemem)
348 POSTCODE(MP_BOOTADDRESS_POST);
350 base_memory = basemem * 1024; /* convert to bytes */
352 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
353 if ((base_memory - boot_address) < bootMP_size)
354 boot_address -= 4096; /* not enough, lower by 4k */
361 * Look for an Intel MP spec table (ie, SMP capable hardware).
370 POSTCODE(MP_PROBE_POST);
372 /* see if EBDA exists */
373 if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) {
374 /* search first 1K of EBDA */
375 target = (u_int32_t) (segment << 4);
376 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
379 /* last 1K of base memory, effective 'top of base' passed in */
380 target = (u_int32_t) (base_memory - 0x400);
381 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
385 /* search the BIOS */
386 target = (u_int32_t) BIOS_BASE;
387 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
396 /* calculate needed resources */
399 panic("you must reconfigure your kernel");
401 /* flag fact that we are running multiple processors */
408 * Startup the SMP processors.
413 POSTCODE(MP_START_POST);
415 /* look for MP capable motherboard */
417 mp_enable(boot_address);
419 panic("MP hardware not found!");
424 * Print various information about the SMP system hardware and setup.
431 POSTCODE(MP_ANNOUNCE_POST);
433 printf("FreeBSD/SMP: Multiprocessor motherboard\n");
434 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
435 printf(", version: 0x%08x", cpu_apic_versions[0]);
436 printf(", at 0x%08x\n", cpu_apic_address);
437 for (x = 1; x <= mp_naps; ++x) {
438 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
439 printf(", version: 0x%08x", cpu_apic_versions[x]);
440 printf(", at 0x%08x\n", cpu_apic_address);
444 for (x = 0; x < mp_napics; ++x) {
445 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
446 printf(", version: 0x%08x", io_apic_versions[x]);
447 printf(", at 0x%08x\n", io_apic_address[x]);
450 printf(" Warning: APIC I/O disabled\n");
455 * AP cpu's call this to sync up protected mode.
465 r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1;
466 r_gdt.rd_base = (int) gdt;
467 lgdt(&r_gdt); /* does magic intra-segment return */
471 currentldt = _default_ldt;
474 my_tr = NGDT + cpuid;
475 gsel_tss = GSEL(my_tr, SEL_KPL);
476 gdt[my_tr].sd.sd_type = SDT_SYS386TSS;
477 common_tss.tss_esp0 = 0; /* not used until after switch */
478 common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
479 common_tss.tss_ioopt = (sizeof common_tss) << 16;
481 common_tssd = gdt[my_tr].sd;
486 load_cr0(0x8005003b); /* XXX! */
489 pmap_set_opt((unsigned *)PTD);
500 * Final configuration of the BSP's local APIC:
501 * - disable 'pic mode'.
502 * - disable 'virtual wire mode'.
506 bsp_apic_configure(void)
511 /* leave 'pic mode' if necessary */
513 outb(0x22, 0x70); /* select IMCR */
514 byte = inb(0x23); /* current contents */
515 byte |= 0x01; /* mask external INTR */
516 outb(0x23, byte); /* disconnect 8259s/NMI */
519 /* mask lint0 (the 8259 'virtual wire' connection) */
520 temp = lapic.lvt_lint0;
521 temp |= APIC_LVT_M; /* set the mask */
522 lapic.lvt_lint0 = temp;
524 /* setup lint1 to handle NMI */
525 temp = lapic.lvt_lint1;
526 temp &= ~APIC_LVT_M; /* clear the mask */
527 lapic.lvt_lint1 = temp;
530 apic_dump("bsp_apic_configure()");
535 /*******************************************************************
536 * local functions and data
540 * start the SMP system
543 mp_enable(u_int boot_addr)
554 POSTCODE(MP_ENABLE_POST);
556 /* turn on 4MB of V == P addressing so we can get to MP table */
557 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
560 /* examine the MP table for needed info, uses physical addresses */
566 /* can't process default configs till the CPU APIC is pmapped */
570 /* post scan cleanup */
575 /* fill the LOGICAL io_apic_versions table */
576 for (apic = 0; apic < mp_napics; ++apic) {
577 ux = io_apic_read(apic, IOAPIC_VER);
578 io_apic_versions[apic] = ux;
581 /* program each IO APIC in the system */
582 for (apic = 0; apic < mp_napics; ++apic)
583 if (io_apic_setup(apic) < 0)
584 panic("IO APIC setup failure");
586 /* install a 'Spurious INTerrupt' vector */
587 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
588 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
590 /* install an inter-CPU IPI for TLB invalidation */
591 setidt(XINVLTLB_OFFSET, Xinvltlb,
592 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
595 /* install an inter-CPU IPI for reading processor state */
596 setidt(XCPUCHECKSTATE_OFFSET, Xcpucheckstate,
597 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
600 /* install an inter-CPU IPI for forcing an additional software trap */
601 setidt(XCPUAST_OFFSET, Xcpuast,
602 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
604 /* install an inter-CPU IPI for interrupt forwarding */
605 setidt(XFORWARD_IRQ_OFFSET, Xforward_irq,
606 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
608 /* install an inter-CPU IPI for CPU stop/restart */
609 setidt(XCPUSTOP_OFFSET, Xcpustop,
610 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
612 #if defined(TEST_TEST1)
613 /* install a "fake hardware INTerrupt" vector */
614 setidt(XTEST1_OFFSET, Xtest1,
615 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
616 #endif /** TEST_TEST1 */
620 /* initialize all SMP locks */
623 /* start each Application Processor */
624 start_all_aps(boot_addr);
627 * The init process might be started on a different CPU now,
628 * and the boot CPU might not call prepare_usermode to get
629 * cr0 correctly configured. Thus we initialize cr0 here.
631 load_cr0(rcr0() | CR0_WP | CR0_AM);
636 * look for the MP spec signature
639 /* string defined by the Intel MP Spec as identifying the MP table */
640 #define MP_SIG 0x5f504d5f /* _MP_ */
641 #define NEXT(X) ((X) += 4)
643 search_for_sig(u_int32_t target, int count)
646 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
648 for (x = 0; x < count; NEXT(x))
649 if (addr[x] == MP_SIG)
650 /* make array index a byte index */
651 return (target + (x * sizeof(u_int32_t)));
657 static basetable_entry basetable_entry_types[] =
659 {0, 20, "Processor"},
666 typedef struct BUSDATA {
668 enum busTypes bus_type;
671 typedef struct INTDATA {
680 typedef struct BUSTYPENAME {
685 static bus_type_name bus_type_table[] =
690 {UNKNOWN_BUSTYPE, "---"},
691 {UNKNOWN_BUSTYPE, "---"},
693 {UNKNOWN_BUSTYPE, "---"},
694 {UNKNOWN_BUSTYPE, "---"},
695 {UNKNOWN_BUSTYPE, "---"},
696 {UNKNOWN_BUSTYPE, "---"},
697 {UNKNOWN_BUSTYPE, "---"},
698 {UNKNOWN_BUSTYPE, "---"},
700 {UNKNOWN_BUSTYPE, "---"},
701 {UNKNOWN_BUSTYPE, "---"},
702 {UNKNOWN_BUSTYPE, "---"},
703 {UNKNOWN_BUSTYPE, "---"},
705 {UNKNOWN_BUSTYPE, "---"}
707 /* from MP spec v1.4, table 5-1 */
708 static int default_data[7][5] =
710 /* nbus, id0, type0, id1, type1 */
711 {1, 0, ISA, 255, 255},
712 {1, 0, EISA, 255, 255},
713 {1, 0, EISA, 255, 255},
714 {0, 255, 255, 255, 255},/* MCA not supported */
716 {2, 0, EISA, 1, PCI},
717 {0, 255, 255, 255, 255} /* MCA not supported */
722 static bus_datum bus_data[NBUS];
724 /* the IO INT data, one entry per possible APIC INTerrupt */
725 static io_int io_apic_ints[NINTR];
729 static int processor_entry __P((proc_entry_ptr entry, int cpu));
730 static int bus_entry __P((bus_entry_ptr entry, int bus));
731 static int io_apic_entry __P((io_apic_entry_ptr entry, int apic));
732 static int int_entry __P((int_entry_ptr entry, int intr));
733 static int lookup_bus_type __P((char *name));
737 * 1st pass on motherboard's Intel MP specification table.
743 * cpu_apic_address (common to all CPUs)
761 POSTCODE(MPTABLE_PASS1_POST);
765 /* clear various tables */
766 for (x = 0; x < NAPICID; ++x) {
767 io_apic_address[x] = ~0; /* IO APIC address table */
770 /* init everything to empty */
776 /* check for use of 'default' configuration */
777 if (MPFPS_MPFB1 != 0) {
778 /* use default addresses */
779 cpu_apic_address = DEFAULT_APIC_BASE;
780 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
782 /* fill in with defaults */
783 mp_naps = 2; /* includes BSP */
784 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0];
791 if ((cth = mpfps->pap) == 0)
792 panic("MP Configuration Table Header MISSING!");
794 cpu_apic_address = (vm_offset_t) cth->apic_address;
796 /* walk the table, recording info of interest */
797 totalSize = cth->base_table_length - sizeof(struct MPCTH);
798 position = (u_char *) cth + sizeof(struct MPCTH);
799 count = cth->entry_count;
802 switch (type = *(u_char *) position) {
803 case 0: /* processor_entry */
804 if (((proc_entry_ptr)position)->cpu_flags
808 case 1: /* bus_entry */
811 case 2: /* io_apic_entry */
812 if (((io_apic_entry_ptr)position)->apic_flags
813 & IOAPICENTRY_FLAG_EN)
814 io_apic_address[mp_napics++] =
815 (vm_offset_t)((io_apic_entry_ptr)
816 position)->apic_address;
818 case 3: /* int_entry */
821 case 4: /* int_entry */
824 panic("mpfps Base Table HOSED!");
828 totalSize -= basetable_entry_types[type].length;
829 (u_char*)position += basetable_entry_types[type].length;
833 /* qualify the numbers */
835 #if 0 /* XXX FIXME: kern/4255 */
836 printf("Warning: only using %d of %d available CPUs!\n",
840 printf("NCPU cannot be different than actual CPU count.\n");
841 printf(" add 'options NCPU=%d' to your kernel config file,\n",
843 printf(" then rerun config & rebuild your SMP kernel\n");
846 #endif /* XXX FIXME: kern/4255 */
847 if (mp_nbusses > NBUS) {
848 printf("found %d busses, increase NBUS\n", mp_nbusses);
851 if (mp_napics > NAPIC) {
852 printf("found %d apics, increase NAPIC\n", mp_napics);
855 if (nintrs > NINTR) {
856 printf("found %d intrs, increase NINTR\n", nintrs);
862 * This is also used as a counter while starting the APs.
866 --mp_naps; /* subtract the BSP */
873 * 2nd pass on motherboard's Intel MP specification table.
877 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
878 * CPU_TO_ID(N), logical CPU to APIC ID table
879 * IO_TO_ID(N), logical IO to APIC ID table
892 int apic, bus, cpu, intr;
894 POSTCODE(MPTABLE_PASS2_POST);
896 /* clear various tables */
897 for (x = 0; x < NAPICID; ++x) {
898 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
899 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
900 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
903 /* clear bus data table */
904 for (x = 0; x < NBUS; ++x)
905 bus_data[x].bus_id = 0xff;
907 /* clear IO APIC INT table */
908 for (x = 0; x < NINTR; ++x)
909 io_apic_ints[x].int_type = 0xff;
911 /* setup the cpu/apic mapping arrays */
914 /* record whether PIC or virtual-wire mode */
915 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0;
917 /* check for use of 'default' configuration */
918 if (MPFPS_MPFB1 != 0)
919 return MPFPS_MPFB1; /* return default configuration type */
921 if ((cth = mpfps->pap) == 0)
922 panic("MP Configuration Table Header MISSING!");
924 /* walk the table, recording info of interest */
925 totalSize = cth->base_table_length - sizeof(struct MPCTH);
926 position = (u_char *) cth + sizeof(struct MPCTH);
927 count = cth->entry_count;
928 apic = bus = intr = 0;
929 cpu = 1; /* pre-count the BSP */
932 switch (type = *(u_char *) position) {
934 if (processor_entry(position, cpu))
938 if (bus_entry(position, bus))
942 if (io_apic_entry(position, apic))
946 if (int_entry(position, intr))
950 /* int_entry(position); */
953 panic("mpfps Base Table HOSED!");
957 totalSize -= basetable_entry_types[type].length;
958 (u_char *) position += basetable_entry_types[type].length;
961 if (boot_cpu_id == -1)
962 panic("NO BSP found!");
964 /* report fact that its NOT a default configuration */
970 * parse an Intel MP specification table
982 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
983 * did it wrong. The MP spec says that when more than 1 PCI bus
984 * exists the BIOS must begin with bus entries for the PCI bus and use
985 * actual PCI bus numbering. This implies that when only 1 PCI bus
986 * exists the BIOS can choose to ignore this ordering, and indeed many
987 * MP motherboards do ignore it. This causes a problem when the PCI
988 * sub-system makes requests of the MP sub-system based on PCI bus
989 * numbers. So here we look for the situation and renumber the
990 * busses and associated INTs in an effort to "make it right".
993 /* find bus 0, PCI bus, count the number of PCI busses */
994 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
995 if (bus_data[x].bus_id == 0) {
998 if (bus_data[x].bus_type == PCI) {
1004 * bus_0 == slot of bus with ID of 0
1005 * bus_pci == slot of last PCI bus encountered
1008 /* check the 1 PCI bus case for sanity */
1009 if (num_pci_bus == 1) {
1011 /* if it is number 0 all is well */
1012 if (bus_data[bus_pci].bus_id == 0)
1015 /* mis-numbered, swap with whichever bus uses slot 0 */
1017 /* swap the bus entry types */
1018 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1019 bus_data[bus_0].bus_type = PCI;
1021 /* swap each relavant INTerrupt entry */
1022 id = bus_data[bus_pci].bus_id;
1023 for (x = 0; x < nintrs; ++x) {
1024 if (io_apic_ints[x].src_bus_id == id) {
1025 io_apic_ints[x].src_bus_id = 0;
1027 else if (io_apic_ints[x].src_bus_id == 0) {
1028 io_apic_ints[x].src_bus_id = id;
1032 /* sanity check if more than 1 PCI bus */
1033 else if (num_pci_bus > 1) {
1034 for (x = 0; x < mp_nbusses; ++x) {
1035 if (bus_data[x].bus_type != PCI)
1037 if (bus_data[x].bus_id >= num_pci_bus)
1038 panic("bad PCI bus numbering");
1045 processor_entry(proc_entry_ptr entry, int cpu)
1047 /* check for usability */
1048 if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN))
1051 /* check for BSP flag */
1052 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1053 boot_cpu_id = entry->apic_id;
1054 CPU_TO_ID(0) = entry->apic_id;
1055 ID_TO_CPU(entry->apic_id) = 0;
1056 return 0; /* its already been counted */
1059 /* add another AP to list, if less than max number of CPUs */
1061 CPU_TO_ID(cpu) = entry->apic_id;
1062 ID_TO_CPU(entry->apic_id) = cpu;
1069 bus_entry(bus_entry_ptr entry, int bus)
1074 /* encode the name into an index */
1075 for (x = 0; x < 6; ++x) {
1076 if ((c = entry->bus_type[x]) == ' ')
1082 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1083 panic("unknown bus type: '%s'", name);
1085 bus_data[bus].bus_id = entry->bus_id;
1086 bus_data[bus].bus_type = x;
1093 io_apic_entry(io_apic_entry_ptr entry, int apic)
1095 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1098 IO_TO_ID(apic) = entry->apic_id;
1099 ID_TO_IO(entry->apic_id) = apic;
1106 lookup_bus_type(char *name)
1110 for (x = 0; x < MAX_BUSTYPE; ++x)
1111 if (strcmp(bus_type_table[x].name, name) == 0)
1112 return bus_type_table[x].type;
1114 return UNKNOWN_BUSTYPE;
1119 int_entry(int_entry_ptr entry, int intr)
1121 io_apic_ints[intr].int_type = entry->int_type;
1122 io_apic_ints[intr].int_flags = entry->int_flags;
1123 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1124 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1125 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1126 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1133 apic_int_is_bus_type(int intr, int bus_type)
1137 for (bus = 0; bus < mp_nbusses; ++bus)
1138 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1139 && ((int) bus_data[bus].bus_type == bus_type))
1147 * Given a traditional ISA INT mask, return an APIC mask.
1150 isa_apic_mask(u_int isa_mask)
1155 #if defined(SKIP_IRQ15_REDIRECT)
1156 if (isa_mask == (1 << 15)) {
1157 printf("skipping ISA IRQ15 redirect\n");
1160 #endif /* SKIP_IRQ15_REDIRECT */
1162 isa_irq = ffs(isa_mask); /* find its bit position */
1163 if (isa_irq == 0) /* doesn't exist */
1165 --isa_irq; /* make it zero based */
1167 apic_pin = isa_apic_pin(isa_irq); /* look for APIC connection */
1171 return (1 << apic_pin); /* convert pin# to a mask */
1176 * Determine which APIC pin an ISA/EISA INT is attached to.
1178 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1179 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1181 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1183 isa_apic_pin(int isa_irq)
1187 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1188 if (INTTYPE(intr) == 0) { /* standard INT */
1189 if (SRCBUSIRQ(intr) == isa_irq) {
1190 if (apic_int_is_bus_type(intr, ISA) ||
1191 apic_int_is_bus_type(intr, EISA))
1192 return INTPIN(intr); /* found */
1196 return -1; /* NOT found */
1201 * Determine which APIC pin a PCI INT is attached to.
1203 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1204 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1205 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1207 pci_apic_pin(int pciBus, int pciDevice, int pciInt)
1211 --pciInt; /* zero based */
1213 for (intr = 0; intr < nintrs; ++intr) /* check each record */
1214 if ((INTTYPE(intr) == 0) /* standard INT */
1215 && (SRCBUSID(intr) == pciBus)
1216 && (SRCBUSDEVICE(intr) == pciDevice)
1217 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */
1218 if (apic_int_is_bus_type(intr, PCI))
1219 return INTPIN(intr); /* exact match */
1221 return -1; /* NOT found */
1225 next_apic_pin(int pin)
1232 for (intr = 0; intr < nintrs; intr++) {
1233 if (INTPIN(intr) != pin || INTTYPE(intr) != 0)
1235 bus = SRCBUSID(intr);
1236 bustype = apic_bus_type(bus);
1237 if (bustype != ISA &&
1243 if (intr >= nintrs) {
1246 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1247 if (INTTYPE(ointr) != 0)
1249 if (bus != SRCBUSID(ointr))
1251 if (bustype == PCI) {
1252 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1254 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1257 if (bustype == ISA || bustype == EISA) {
1258 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1261 if (INTPIN(intr) == INTPIN(ointr))
1265 if (ointr >= nintrs) {
1268 return INTPIN(ointr);
1280 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1283 * Exactly what this means is unclear at this point. It is a solution
1284 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1285 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1286 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1290 undirect_isa_irq(int rirq)
1293 printf("Freeing redirected ISA irq %d.\n", rirq);
1294 /** FIXME: tickle the MB redirector chip */
1297 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1304 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1307 undirect_pci_irq(int rirq)
1311 printf("Freeing redirected PCI irq %d.\n", rirq);
1313 /** FIXME: tickle the MB redirector chip */
1317 printf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1325 * given a bus ID, return:
1326 * the bus type if found
1330 apic_bus_type(int id)
1334 for (x = 0; x < mp_nbusses; ++x)
1335 if (bus_data[x].bus_id == id)
1336 return bus_data[x].bus_type;
1343 * given a LOGICAL APIC# and pin#, return:
1344 * the associated src bus ID if found
1348 apic_src_bus_id(int apic, int pin)
1352 /* search each of the possible INTerrupt sources */
1353 for (x = 0; x < nintrs; ++x)
1354 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1355 (pin == io_apic_ints[x].dst_apic_int))
1356 return (io_apic_ints[x].src_bus_id);
1358 return -1; /* NOT found */
1363 * given a LOGICAL APIC# and pin#, return:
1364 * the associated src bus IRQ if found
1368 apic_src_bus_irq(int apic, int pin)
1372 for (x = 0; x < nintrs; x++)
1373 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1374 (pin == io_apic_ints[x].dst_apic_int))
1375 return (io_apic_ints[x].src_bus_irq);
1377 return -1; /* NOT found */
1382 * given a LOGICAL APIC# and pin#, return:
1383 * the associated INTerrupt type if found
1387 apic_int_type(int apic, int pin)
1391 /* search each of the possible INTerrupt sources */
1392 for (x = 0; x < nintrs; ++x)
1393 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1394 (pin == io_apic_ints[x].dst_apic_int))
1395 return (io_apic_ints[x].int_type);
1397 return -1; /* NOT found */
1402 * given a LOGICAL APIC# and pin#, return:
1403 * the associated trigger mode if found
1407 apic_trigger(int apic, int pin)
1411 /* search each of the possible INTerrupt sources */
1412 for (x = 0; x < nintrs; ++x)
1413 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1414 (pin == io_apic_ints[x].dst_apic_int))
1415 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1417 return -1; /* NOT found */
1422 * given a LOGICAL APIC# and pin#, return:
1423 * the associated 'active' level if found
1427 apic_polarity(int apic, int pin)
1431 /* search each of the possible INTerrupt sources */
1432 for (x = 0; x < nintrs; ++x)
1433 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1434 (pin == io_apic_ints[x].dst_apic_int))
1435 return (io_apic_ints[x].int_flags & 0x03);
1437 return -1; /* NOT found */
1442 * set data according to MP defaults
1443 * FIXME: probably not complete yet...
1446 default_mp_table(int type)
1449 #if defined(APIC_IO)
1453 #endif /* APIC_IO */
1456 printf(" MP default config type: %d\n", type);
1459 printf(" bus: ISA, APIC: 82489DX\n");
1462 printf(" bus: EISA, APIC: 82489DX\n");
1465 printf(" bus: EISA, APIC: 82489DX\n");
1468 printf(" bus: MCA, APIC: 82489DX\n");
1471 printf(" bus: ISA+PCI, APIC: Integrated\n");
1474 printf(" bus: EISA+PCI, APIC: Integrated\n");
1477 printf(" bus: MCA+PCI, APIC: Integrated\n");
1480 printf(" future type\n");
1486 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1487 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1490 CPU_TO_ID(0) = boot_cpu_id;
1491 ID_TO_CPU(boot_cpu_id) = 0;
1493 /* one and only AP */
1494 CPU_TO_ID(1) = ap_cpu_id;
1495 ID_TO_CPU(ap_cpu_id) = 1;
1497 #if defined(APIC_IO)
1498 /* one and only IO APIC */
1499 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1502 * sanity check, refer to MP spec section 3.6.6, last paragraph
1503 * necessary as some hardware isn't properly setting up the IO APIC
1505 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1506 if (io_apic_id != 2) {
1508 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1509 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1510 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */
1511 ux &= ~APIC_ID_MASK; /* clear the ID field */
1512 ux |= 0x02000000; /* set it to '2' */
1513 io_apic_write(0, IOAPIC_ID, ux); /* write new value */
1514 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */
1515 if ((ux & APIC_ID_MASK) != 0x02000000)
1516 panic("can't control IO APIC ID, reg: 0x%08x", ux);
1519 IO_TO_ID(0) = io_apic_id;
1520 ID_TO_IO(io_apic_id) = 0;
1521 #endif /* APIC_IO */
1523 /* fill out bus entries */
1530 bus_data[0].bus_id = default_data[type - 1][1];
1531 bus_data[0].bus_type = default_data[type - 1][2];
1532 bus_data[1].bus_id = default_data[type - 1][3];
1533 bus_data[1].bus_type = default_data[type - 1][4];
1536 /* case 4: case 7: MCA NOT supported */
1537 default: /* illegal/reserved */
1538 panic("BAD default MP config: %d", type);
1542 #if defined(APIC_IO)
1543 /* general cases from MP v1.4, table 5-2 */
1544 for (pin = 0; pin < 16; ++pin) {
1545 io_apic_ints[pin].int_type = 0;
1546 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
1547 io_apic_ints[pin].src_bus_id = 0;
1548 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
1549 io_apic_ints[pin].dst_apic_id = io_apic_id;
1550 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
1553 /* special cases from MP v1.4, table 5-2 */
1555 io_apic_ints[2].int_type = 0xff; /* N/C */
1556 io_apic_ints[13].int_type = 0xff; /* N/C */
1557 #if !defined(APIC_MIXED_MODE)
1559 panic("sorry, can't support type 2 default yet");
1560 #endif /* APIC_MIXED_MODE */
1563 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
1566 io_apic_ints[0].int_type = 0xff; /* N/C */
1568 io_apic_ints[0].int_type = 3; /* vectored 8259 */
1569 #endif /* APIC_IO */
1574 * initialize all the SMP locks
1577 /* critical region around IO APIC, apic_imen */
1578 struct simplelock imen_lock;
1580 /* critical region around splxx(), cpl, cml, cil, ipending */
1581 struct simplelock cpl_lock;
1583 /* Make FAST_INTR() routines sequential */
1584 struct simplelock fast_intr_lock;
1586 /* critical region around INTR() routines */
1587 struct simplelock intr_lock;
1589 /* lock regions protected in UP kernel via cli/sti */
1590 struct simplelock mpintr_lock;
1592 /* lock region used by kernel profiling */
1593 struct simplelock mcount_lock;
1596 /* locks com (tty) data/hardware accesses: a FASTINTR() */
1597 struct simplelock com_lock;
1598 #endif /* USE_COMLOCK */
1600 #ifdef USE_CLOCKLOCK
1601 /* lock regions around the clock hardware */
1602 struct simplelock clock_lock;
1603 #endif /* USE_CLOCKLOCK */
1609 * Get the initial mp_lock with a count of 1 for the BSP.
1610 * This uses a LOGICAL cpu ID, ie BSP == 0.
1612 mp_lock = 0x00000001;
1614 /* ISR uses its own "giant lock" */
1615 isr_lock = FREE_LOCK;
1617 #if defined(APIC_INTR_DIAGNOSTIC) && defined(APIC_INTR_DIAGNOSTIC_IRQ)
1618 s_lock_init((struct simplelock*)&apic_itrace_debuglock);
1621 s_lock_init((struct simplelock*)&mpintr_lock);
1623 s_lock_init((struct simplelock*)&mcount_lock);
1625 s_lock_init((struct simplelock*)&fast_intr_lock);
1626 s_lock_init((struct simplelock*)&intr_lock);
1627 s_lock_init((struct simplelock*)&imen_lock);
1628 s_lock_init((struct simplelock*)&cpl_lock);
1631 s_lock_init((struct simplelock*)&com_lock);
1632 #endif /* USE_COMLOCK */
1633 #ifdef USE_CLOCKLOCK
1634 s_lock_init((struct simplelock*)&clock_lock);
1635 #endif /* USE_CLOCKLOCK */
1640 * start each AP in our list
1643 start_all_aps(u_int boot_addr)
1646 u_char mpbiosreason;
1647 u_long mpbioswarmvec;
1650 struct globaldata *gd;
1654 POSTCODE(START_ALL_APS_POST);
1656 /* initialize BSP's local APIC */
1660 /* install the AP 1st level boot code */
1661 install_ap_tramp(boot_addr);
1664 /* save the current value of the warm-start vector */
1665 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
1666 outb(CMOS_REG, BIOS_RESET);
1667 mpbiosreason = inb(CMOS_DATA);
1669 /* record BSP in CPU map */
1673 for (x = 1; x <= mp_naps; ++x) {
1675 /* This is a bit verbose, it will go away soon. */
1677 /* alloc new page table directory */
1678 newptd = (pd_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE));
1680 /* Store the virtual PTD address for this CPU */
1681 IdlePTDS[x] = newptd;
1683 /* clone currently active one (ie: IdlePTD) */
1684 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */
1686 /* set up 0 -> 4MB P==V mapping for AP boot */
1687 newptd[0] = (void *)(uintptr_t)(PG_V | PG_RW |
1688 ((uintptr_t)(void *)KPTphys & PG_FRAME));
1690 /* store PTD for this AP's boot sequence */
1691 myPTD = (pd_entry_t *)vtophys(newptd);
1693 /* alloc new page table page */
1694 newpt = (pt_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE));
1696 /* set the new PTD's private page to point there */
1697 newptd[MPPTDI] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpt));
1699 /* install self referential entry */
1700 newptd[PTDPTDI] = (pd_entry_t)(PG_V | PG_RW | vtophys(newptd));
1702 /* allocate a new private data page */
1703 gd = (struct globaldata *)kmem_alloc(kernel_map, PAGE_SIZE);
1705 /* wire it into the private page table page */
1706 newpt[0] = (pt_entry_t)(PG_V | PG_RW | vtophys(gd));
1708 /* wire the ptp into itself for access */
1709 newpt[1] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpt));
1711 /* copy in the pointer to the local apic */
1712 newpt[2] = SMP_prvpt[2];
1714 /* and the IO apic mapping[s] */
1715 for (i = 16; i < 32; i++)
1716 newpt[i] = SMP_prvpt[i];
1718 /* allocate and set up an idle stack data page */
1719 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE);
1720 for (i = 0; i < UPAGES; i++)
1721 newpt[i + 3] = (pt_entry_t)(PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
1723 newpt[3 + UPAGES] = 0; /* *prv_CMAP1 */
1724 newpt[4 + UPAGES] = 0; /* *prv_CMAP2 */
1725 newpt[5 + UPAGES] = 0; /* *prv_CMAP3 */
1726 newpt[6 + UPAGES] = 0; /* *prv_PMAP1 */
1728 /* prime data page for it to use */
1730 gd->cpu_lockid = x << 24;
1731 gd->my_idlePTD = myPTD;
1732 gd->prv_CMAP1 = &newpt[3 + UPAGES];
1733 gd->prv_CMAP2 = &newpt[4 + UPAGES];
1734 gd->prv_CMAP3 = &newpt[5 + UPAGES];
1735 gd->prv_PMAP1 = &newpt[6 + UPAGES];
1737 /* setup a vector to our boot code */
1738 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
1739 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
1740 outb(CMOS_REG, BIOS_RESET);
1741 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
1744 /* attempt to start the Application Processor */
1745 CHECK_INIT(99); /* setup checkpoints */
1746 if (!start_ap(x, boot_addr)) {
1747 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
1748 CHECK_PRINT("trace"); /* show checkpoints */
1749 /* better panic as the AP may be running loose */
1750 printf("panic y/n? [y] ");
1751 if (cngetc() != 'n')
1754 CHECK_PRINT("trace"); /* show checkpoints */
1756 /* record its version info */
1757 cpu_apic_versions[x] = cpu_apic_versions[0];
1759 all_cpus |= (1 << x); /* record AP in CPU map */
1762 /* build our map of 'other' CPUs */
1763 other_cpus = all_cpus & ~(1 << cpuid);
1765 /* fill in our (BSP) APIC version */
1766 cpu_apic_versions[0] = lapic.version;
1768 /* restore the warmstart vector */
1769 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
1770 outb(CMOS_REG, BIOS_RESET);
1771 outb(CMOS_DATA, mpbiosreason);
1774 * Set up the idle context for the BSP. Similar to above except
1775 * that some was done by locore, some by pmap.c and some is implicit
1776 * because the BSP is cpu#0 and the page is initially zero, and also
1777 * because we can refer to variables by name on the BSP..
1779 newptd = (pd_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE));
1781 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */
1782 IdlePTDS[0] = newptd;
1784 /* Point PTD[] to this page instead of IdlePTD's physical page */
1785 newptd[PTDPTDI] = (pd_entry_t)(PG_V | PG_RW | vtophys(newptd));
1787 my_idlePTD = (pd_entry_t *)vtophys(newptd);
1789 /* Allocate and setup BSP idle stack */
1790 stack = (char *)kmem_alloc(kernel_map, UPAGES * PAGE_SIZE);
1791 for (i = 0; i < UPAGES; i++)
1792 SMP_prvpt[i + 3] = (pt_entry_t)(PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
1796 for (i = 0; i < mp_ncpus; i++) {
1797 bcopy( (int *) PTD + KPTDI, (int *) IdlePTDS[i] + KPTDI, NKPDE * sizeof (int));
1800 /* number of APs actually started */
1801 return mp_ncpus - 1;
1806 * load the 1st level AP boot code into base memory.
1809 /* targets for relocation */
1810 extern void bigJump(void);
1811 extern void bootCodeSeg(void);
1812 extern void bootDataSeg(void);
1813 extern void MPentry(void);
1814 extern u_int MP_GDT;
1815 extern u_int mp_gdtbase;
1818 install_ap_tramp(u_int boot_addr)
1821 int size = *(int *) ((u_long) & bootMP_size);
1822 u_char *src = (u_char *) ((u_long) bootMP);
1823 u_char *dst = (u_char *) boot_addr + KERNBASE;
1824 u_int boot_base = (u_int) bootMP;
1829 POSTCODE(INSTALL_AP_TRAMP_POST);
1831 for (x = 0; x < size; ++x)
1835 * modify addresses in code we just moved to basemem. unfortunately we
1836 * need fairly detailed info about mpboot.s for this to work. changes
1837 * to mpboot.s might require changes here.
1840 /* boot code is located in KERNEL space */
1841 dst = (u_char *) boot_addr + KERNBASE;
1843 /* modify the lgdt arg */
1844 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
1845 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
1847 /* modify the ljmp target for MPentry() */
1848 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
1849 *dst32 = ((u_int) MPentry - KERNBASE);
1851 /* modify the target for boot code segment */
1852 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
1853 dst8 = (u_int8_t *) (dst16 + 1);
1854 *dst16 = (u_int) boot_addr & 0xffff;
1855 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
1857 /* modify the target for boot data segment */
1858 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
1859 dst8 = (u_int8_t *) (dst16 + 1);
1860 *dst16 = (u_int) boot_addr & 0xffff;
1861 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
1866 * this function starts the AP (application processor) identified
1867 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
1868 * to accomplish this. This is necessary because of the nuances
1869 * of the different hardware we might encounter. It ain't pretty,
1870 * but it seems to work.
1873 start_ap(int logical_cpu, u_int boot_addr)
1878 u_long icr_lo, icr_hi;
1880 POSTCODE(START_AP_POST);
1882 /* get the PHYSICAL APIC ID# */
1883 physical_cpu = CPU_TO_ID(logical_cpu);
1885 /* calculate the vector */
1886 vector = (boot_addr >> 12) & 0xff;
1888 /* used as a watchpoint to signal AP startup */
1892 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
1893 * and running the target CPU. OR this INIT IPI might be latched (P5
1894 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
1898 /* setup the address for the target AP */
1899 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
1900 icr_hi |= (physical_cpu << 24);
1901 lapic.icr_hi = icr_hi;
1903 /* do an INIT IPI: assert RESET */
1904 icr_lo = lapic.icr_lo & 0xfff00000;
1905 lapic.icr_lo = icr_lo | 0x0000c500;
1907 /* wait for pending status end */
1908 while (lapic.icr_lo & APIC_DELSTAT_MASK)
1911 /* do an INIT IPI: deassert RESET */
1912 lapic.icr_lo = icr_lo | 0x00008500;
1914 /* wait for pending status end */
1915 u_sleep(10000); /* wait ~10mS */
1916 while (lapic.icr_lo & APIC_DELSTAT_MASK)
1920 * next we do a STARTUP IPI: the previous INIT IPI might still be
1921 * latched, (P5 bug) this 1st STARTUP would then terminate
1922 * immediately, and the previously started INIT IPI would continue. OR
1923 * the previous INIT IPI has already run. and this STARTUP IPI will
1924 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
1928 /* do a STARTUP IPI */
1929 lapic.icr_lo = icr_lo | 0x00000600 | vector;
1930 while (lapic.icr_lo & APIC_DELSTAT_MASK)
1932 u_sleep(200); /* wait ~200uS */
1935 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
1936 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
1937 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
1938 * recognized after hardware RESET or INIT IPI.
1941 lapic.icr_lo = icr_lo | 0x00000600 | vector;
1942 while (lapic.icr_lo & APIC_DELSTAT_MASK)
1944 u_sleep(200); /* wait ~200uS */
1946 /* wait for it to start */
1947 set_apic_timer(5000000);/* == 5 seconds */
1948 while (read_apic_timer())
1949 if (mp_ncpus > cpus)
1950 return 1; /* return SUCCESS */
1952 return 0; /* return FAILURE */
1957 * Flush the TLB on all other CPU's
1959 * XXX: Needs to handshake and wait for completion before proceding.
1964 #if defined(APIC_IO)
1965 if (smp_started && invltlb_ok)
1966 all_but_self_ipi(XINVLTLB_OFFSET);
1967 #endif /* APIC_IO */
1973 __asm __volatile("invlpg (%0)"::"r"(addr):"memory");
1975 /* send a message to the other CPUs */
1985 * This should be implemented as load_cr3(rcr3()) when load_cr3() is
1988 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory");
1990 /* send a message to the other CPUs */
1996 * When called the executing CPU will send an IPI to all other CPUs
1997 * requesting that they halt execution.
1999 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2001 * - Signals all CPUs in map to stop.
2002 * - Waits for each to stop.
2009 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2010 * from executing at same time.
2013 stop_cpus(u_int map)
2018 /* send the Xcpustop IPI to all CPUs in map */
2019 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2021 while ((stopped_cpus & map) != map)
2029 * Called by a CPU to restart stopped CPUs.
2031 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2033 * - Signals all CPUs in map to restart.
2034 * - Waits for each to restart.
2042 restart_cpus(u_int map)
2047 started_cpus = map; /* signal other cpus to restart */
2049 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2055 int smp_active = 0; /* are the APs allowed to run? */
2056 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RW, &smp_active, 0, "");
2058 /* XXX maybe should be hw.ncpu */
2059 static int smp_cpus = 1; /* how many cpu's running */
2060 SYSCTL_INT(_machdep, OID_AUTO, smp_cpus, CTLFLAG_RD, &smp_cpus, 0, "");
2062 int invltlb_ok = 0; /* throttle smp_invltlb() till safe */
2063 SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, "");
2065 /* Warning: Do not staticize. Used from swtch.s */
2066 int do_page_zero_idle = 1; /* bzero pages for fun and profit in idleloop */
2067 SYSCTL_INT(_machdep, OID_AUTO, do_page_zero_idle, CTLFLAG_RW,
2068 &do_page_zero_idle, 0, "");
2070 /* Is forwarding of a interrupt to the CPU holding the ISR lock enabled ? */
2071 int forward_irq_enabled = 1;
2072 SYSCTL_INT(_machdep, OID_AUTO, forward_irq_enabled, CTLFLAG_RW,
2073 &forward_irq_enabled, 0, "");
2075 /* Enable forwarding of a signal to a process running on a different CPU */
2076 int forward_signal_enabled = 1;
2077 SYSCTL_INT(_machdep, OID_AUTO, forward_signal_enabled, CTLFLAG_RW,
2078 &forward_signal_enabled, 0, "");
2080 /* Enable forwarding of roundrobin to all other cpus */
2081 int forward_roundrobin_enabled = 1;
2082 SYSCTL_INT(_machdep, OID_AUTO, forward_roundrobin_enabled, CTLFLAG_RW,
2083 &forward_roundrobin_enabled, 0, "");
2086 * This is called once the rest of the system is up and running and we're
2087 * ready to let the AP's out of the pen.
2099 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2103 /* Build our map of 'other' CPUs. */
2104 other_cpus = all_cpus & ~(1 << cpuid);
2106 printf("SMP: AP CPU #%d Launched!\n", cpuid);
2108 /* XXX FIXME: i386 specific, and redundant: Setup the FPU. */
2109 load_cr0((rcr0() & ~CR0_EM) | CR0_MP | CR0_NE | CR0_TS);
2111 /* A quick check from sanity claus */
2112 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2113 if (cpuid != apic_id) {
2114 printf("SMP: cpuid = %d\n", cpuid);
2115 printf("SMP: apic_id = %d\n", apic_id);
2116 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2117 panic("cpuid mismatch! boom!!");
2122 /* Init local apic for irq's */
2126 * Activate smp_invltlb, although strictly speaking, this isn't
2127 * quite correct yet. We should have a bitfield for cpus willing
2128 * to accept TLB flush IPI's or something and sync them.
2131 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */
2132 smp_active = 1; /* historic */
2134 curproc = NULL; /* make sure */
2139 #define CHECKSTATE_USER 0
2140 #define CHECKSTATE_SYS 1
2141 #define CHECKSTATE_INTR 2
2143 /* Do not staticize. Used from apic_vector.s */
2144 struct proc* checkstate_curproc[NCPU];
2145 int checkstate_cpustate[NCPU];
2146 u_long checkstate_pc[NCPU];
2148 extern long cp_time[CPUSTATES];
2150 #define PC_TO_INDEX(pc, prof) \
2151 ((int)(((u_quad_t)((pc) - (prof)->pr_off) * \
2152 (u_quad_t)((prof)->pr_scale)) >> 16) & ~1)
2155 addupc_intr_forwarded(struct proc *p, int id, int *astmap)
2161 pc = checkstate_pc[id];
2162 prof = &p->p_stats->p_prof;
2163 if (pc >= prof->pr_off &&
2164 (i = PC_TO_INDEX(pc, prof)) < prof->pr_size) {
2165 if ((p->p_flag & P_OWEUPC) == 0) {
2168 p->p_flag |= P_OWEUPC;
2170 *astmap |= (1 << id);
2175 forwarded_statclock(int id, int pscnt, int *astmap)
2177 struct pstats *pstats;
2184 register struct gmonparam *g;
2188 p = checkstate_curproc[id];
2189 cpustate = checkstate_cpustate[id];
2192 case CHECKSTATE_USER:
2193 if (p->p_flag & P_PROFIL)
2194 addupc_intr_forwarded(p, id, astmap);
2198 if (p->p_nice > NZERO)
2203 case CHECKSTATE_SYS:
2206 * Kernel statistics are just like addupc_intr, only easier.
2209 if (g->state == GMON_PROF_ON) {
2210 i = checkstate_pc[id] - g->lowpc;
2211 if (i < g->textsize) {
2212 i /= HISTFRACTION * sizeof(*g->kcount);
2227 case CHECKSTATE_INTR:
2231 * Kernel statistics are just like addupc_intr, only easier.
2234 if (g->state == GMON_PROF_ON) {
2235 i = checkstate_pc[id] - g->lowpc;
2236 if (i < g->textsize) {
2237 i /= HISTFRACTION * sizeof(*g->kcount);
2250 if (++p->p_estcpu == 0)
2252 if ((p->p_estcpu & 3) == 0) {
2254 if (p->p_priority >= PUSER)
2255 p->p_priority = p->p_usrpri;
2258 /* Update resource usage integrals and maximums. */
2259 if ((pstats = p->p_stats) != NULL &&
2260 (ru = &pstats->p_ru) != NULL &&
2261 (vm = p->p_vmspace) != NULL) {
2262 ru->ru_ixrss += vm->vm_tsize * PAGE_SIZE / 1024;
2263 ru->ru_idrss += vm->vm_dsize * PAGE_SIZE / 1024;
2264 ru->ru_isrss += vm->vm_ssize * PAGE_SIZE / 1024;
2265 rss = vm->vm_pmap.pm_stats.resident_count *
2267 if (ru->ru_maxrss < rss)
2268 ru->ru_maxrss = rss;
2274 forward_statclock(int pscnt)
2280 /* Kludge. We don't yet have separate locks for the interrupts
2281 * and the kernel. This means that we cannot let the other processors
2282 * handle complex interrupts while inhibiting them from entering
2283 * the kernel in a non-interrupt context.
2285 * What we can do, without changing the locking mechanisms yet,
2286 * is letting the other processors handle a very simple interrupt
2287 * (wich determines the processor states), and do the main
2291 if (!smp_started || !invltlb_ok || cold || panicstr)
2294 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle ) */
2296 map = other_cpus & ~stopped_cpus ;
2297 checkstate_probed_cpus = 0;
2299 selected_apic_ipi(map,
2300 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2303 while (checkstate_probed_cpus != map) {
2307 #ifdef BETTER_CLOCK_DIAGNOSTIC
2308 printf("forward_statclock: checkstate %x\n",
2309 checkstate_probed_cpus);
2316 * Step 2: walk through other processors processes, update ticks and
2321 for (id = 0; id < mp_ncpus; id++) {
2324 if (((1 << id) & checkstate_probed_cpus) == 0)
2326 forwarded_statclock(id, pscnt, &map);
2329 checkstate_need_ast |= map;
2330 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2332 while ((checkstate_need_ast & map) != 0) {
2336 #ifdef BETTER_CLOCK_DIAGNOSTIC
2337 printf("forward_statclock: dropped ast 0x%x\n",
2338 checkstate_need_ast & map);
2347 forward_hardclock(int pscnt)
2352 struct pstats *pstats;
2355 /* Kludge. We don't yet have separate locks for the interrupts
2356 * and the kernel. This means that we cannot let the other processors
2357 * handle complex interrupts while inhibiting them from entering
2358 * the kernel in a non-interrupt context.
2360 * What we can do, without changing the locking mechanisms yet,
2361 * is letting the other processors handle a very simple interrupt
2362 * (wich determines the processor states), and do the main
2366 if (!smp_started || !invltlb_ok || cold || panicstr)
2369 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle) */
2371 map = other_cpus & ~stopped_cpus ;
2372 checkstate_probed_cpus = 0;
2374 selected_apic_ipi(map,
2375 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2378 while (checkstate_probed_cpus != map) {
2382 #ifdef BETTER_CLOCK_DIAGNOSTIC
2383 printf("forward_hardclock: checkstate %x\n",
2384 checkstate_probed_cpus);
2391 * Step 2: walk through other processors processes, update virtual
2392 * timer and profiling timer. If stathz == 0, also update ticks and
2397 for (id = 0; id < mp_ncpus; id++) {
2400 if (((1 << id) & checkstate_probed_cpus) == 0)
2402 p = checkstate_curproc[id];
2404 pstats = p->p_stats;
2405 if (checkstate_cpustate[id] == CHECKSTATE_USER &&
2406 timevalisset(&pstats->p_timer[ITIMER_VIRTUAL].it_value) &&
2407 itimerdecr(&pstats->p_timer[ITIMER_VIRTUAL], tick) == 0) {
2408 psignal(p, SIGVTALRM);
2411 if (timevalisset(&pstats->p_timer[ITIMER_PROF].it_value) &&
2412 itimerdecr(&pstats->p_timer[ITIMER_PROF], tick) == 0) {
2413 psignal(p, SIGPROF);
2418 forwarded_statclock( id, pscnt, &map);
2422 checkstate_need_ast |= map;
2423 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2425 while ((checkstate_need_ast & map) != 0) {
2429 #ifdef BETTER_CLOCK_DIAGNOSTIC
2430 printf("forward_hardclock: dropped ast 0x%x\n",
2431 checkstate_need_ast & map);
2439 #endif /* BETTER_CLOCK */
2442 forward_signal(struct proc *p)
2448 /* Kludge. We don't yet have separate locks for the interrupts
2449 * and the kernel. This means that we cannot let the other processors
2450 * handle complex interrupts while inhibiting them from entering
2451 * the kernel in a non-interrupt context.
2453 * What we can do, without changing the locking mechanisms yet,
2454 * is letting the other processors handle a very simple interrupt
2455 * (wich determines the processor states), and do the main
2459 if (!smp_started || !invltlb_ok || cold || panicstr)
2461 if (!forward_signal_enabled)
2464 if (p->p_stat != SRUN)
2466 id = (u_char) p->p_oncpu;
2470 checkstate_need_ast |= map;
2471 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2473 while ((checkstate_need_ast & map) != 0) {
2478 printf("forward_signal: dropped ast 0x%x\n",
2479 checkstate_need_ast & map);
2484 if (id == (u_char) p->p_oncpu)
2490 forward_roundrobin(void)
2495 if (!smp_started || !invltlb_ok || cold || panicstr)
2497 if (!forward_roundrobin_enabled)
2499 resched_cpus |= other_cpus;
2500 map = other_cpus & ~stopped_cpus ;
2502 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2504 (void) all_but_self_ipi(XCPUAST_OFFSET);
2507 while ((checkstate_need_ast & map) != 0) {
2512 printf("forward_roundrobin: dropped ast 0x%x\n",
2513 checkstate_need_ast & map);
2521 #ifdef APIC_INTR_REORDER
2523 * Maintain mapping from softintr vector to isr bit in local apic.
2526 set_lapic_isrloc(int intr, int vector)
2528 if (intr < 0 || intr > 32)
2529 panic("set_apic_isrloc: bad intr argument: %d",intr);
2530 if (vector < ICU_OFFSET || vector > 255)
2531 panic("set_apic_isrloc: bad vector argument: %d",vector);
2532 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2);
2533 apic_isrbit_location[intr].bit = (1<<(vector & 31));