2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $Id: mp_machdep.c,v 1.82 1998/10/10 09:38:02 kato Exp $
31 #include "opt_user_ldt.h"
34 #include <machine/smptests.h>
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/kernel.h>
43 #include <sys/sysctl.h>
45 #include <sys/dkstat.h>
49 #include <vm/vm_param.h>
51 #include <vm/vm_kern.h>
52 #include <vm/vm_extern.h>
55 #include <vm/vm_map.h>
62 #include <machine/smp.h>
63 #include <machine/apic.h>
64 #include <machine/mpapic.h>
65 #include <machine/segments.h>
66 #include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */
67 #include <machine/tss.h>
68 #include <machine/specialreg.h>
69 #include <machine/cputypes.h>
70 #include <machine/globaldata.h>
72 #include <i386/i386/cons.h> /* cngetc() */
75 #include <machine/md_var.h> /* setidt() */
76 #include <i386/isa/icu.h> /* IPIs */
77 #include <i386/isa/intr_machdep.h> /* IPIs */
80 #if defined(TEST_DEFAULT_CONFIG)
81 #define MPFPS_MPFB1 TEST_DEFAULT_CONFIG
83 #define MPFPS_MPFB1 mpfps->mpfb1
84 #endif /* TEST_DEFAULT_CONFIG */
86 #define WARMBOOT_TARGET 0
87 #define WARMBOOT_OFF (KERNBASE + 0x0467)
88 #define WARMBOOT_SEG (KERNBASE + 0x0469)
91 #define BIOS_BASE (0xe8000)
92 #define BIOS_SIZE (0x18000)
94 #define BIOS_BASE (0xf0000)
95 #define BIOS_SIZE (0x10000)
97 #define BIOS_COUNT (BIOS_SIZE/4)
99 #define CMOS_REG (0x70)
100 #define CMOS_DATA (0x71)
101 #define BIOS_RESET (0x0f)
102 #define BIOS_WARM (0x0a)
104 #define PROCENTRY_FLAG_EN 0x01
105 #define PROCENTRY_FLAG_BP 0x02
106 #define IOAPICENTRY_FLAG_EN 0x01
109 /* MP Floating Pointer Structure */
110 typedef struct MPFPS {
123 /* MP Configuration Table Header */
124 typedef struct MPCTH {
126 u_short base_table_length;
130 u_char product_id[12];
131 void *oem_table_pointer;
132 u_short oem_table_size;
135 u_short extended_table_length;
136 u_char extended_table_checksum;
141 typedef struct PROCENTRY {
146 u_long cpu_signature;
147 u_long feature_flags;
152 typedef struct BUSENTRY {
158 typedef struct IOAPICENTRY {
164 } *io_apic_entry_ptr;
166 typedef struct INTENTRY {
176 /* descriptions of MP basetable entries */
177 typedef struct BASETABLE_ENTRY {
184 * this code MUST be enabled here and in mpboot.s.
185 * it follows the very early stages of AP boot by placing values in CMOS ram.
186 * it NORMALLY will never be needed and thus the primitive method for enabling.
191 #if defined(CHECK_POINTS) && !defined(PC98)
192 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
193 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
195 #define CHECK_INIT(D); \
196 CHECK_WRITE(0x34, (D)); \
197 CHECK_WRITE(0x35, (D)); \
198 CHECK_WRITE(0x36, (D)); \
199 CHECK_WRITE(0x37, (D)); \
200 CHECK_WRITE(0x38, (D)); \
201 CHECK_WRITE(0x39, (D));
203 #define CHECK_PRINT(S); \
204 printf("%s: %d, %d, %d, %d, %d, %d\n", \
213 #else /* CHECK_POINTS */
215 #define CHECK_INIT(D)
216 #define CHECK_PRINT(S)
218 #endif /* CHECK_POINTS */
221 * Values to send to the POST hardware.
223 #define MP_BOOTADDRESS_POST 0x10
224 #define MP_PROBE_POST 0x11
225 #define MPTABLE_PASS1_POST 0x12
227 #define MP_START_POST 0x13
228 #define MP_ENABLE_POST 0x14
229 #define MPTABLE_PASS2_POST 0x15
231 #define START_ALL_APS_POST 0x16
232 #define INSTALL_AP_TRAMP_POST 0x17
233 #define START_AP_POST 0x18
235 #define MP_ANNOUNCE_POST 0x19
238 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
239 int current_postcode;
241 /** XXX FIXME: what system files declare these??? */
242 extern struct region_descriptor r_gdt, r_idt;
244 int bsp_apic_ready = 0; /* flags useability of BSP apic */
245 int mp_ncpus; /* # of CPUs, including BSP */
246 int mp_naps; /* # of Applications processors */
247 int mp_nbusses; /* # of busses */
248 int mp_napics; /* # of IO APICs */
249 int boot_cpu_id; /* designated BSP */
250 vm_offset_t cpu_apic_address;
251 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
254 u_int32_t cpu_apic_versions[NCPU];
255 u_int32_t io_apic_versions[NAPIC];
257 #ifdef APIC_INTR_DIAGNOSTIC
258 int apic_itrace_enter[32];
259 int apic_itrace_tryisrlock[32];
260 int apic_itrace_gotisrlock[32];
261 int apic_itrace_active[32];
262 int apic_itrace_masked[32];
263 int apic_itrace_noisrlock[32];
264 int apic_itrace_masked2[32];
265 int apic_itrace_unmask[32];
266 int apic_itrace_noforward[32];
267 int apic_itrace_leave[32];
268 int apic_itrace_enter2[32];
269 int apic_itrace_doreti[32];
270 int apic_itrace_splz[32];
271 int apic_itrace_eoi[32];
272 #ifdef APIC_INTR_DIAGNOSTIC_IRQ
273 unsigned short apic_itrace_debugbuffer[32768];
274 int apic_itrace_debugbuffer_idx;
275 struct simplelock apic_itrace_debuglock;
279 #ifdef APIC_INTR_REORDER
281 volatile int *location;
283 } apic_isrbit_location[32];
286 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
289 * APIC ID logical/physical mapping structures.
290 * We oversize these to simplify boot-time config.
292 int cpu_num_to_apic_id[NAPICID];
293 int io_num_to_apic_id[NAPICID];
294 int apic_id_to_logical[NAPICID];
297 /* Bitmap of all available CPUs */
300 /* AP uses this PTD during bootstrap. Do not staticize. */
303 /* Hotwire a 0->4MB V==P mapping */
304 extern pt_entry_t *KPTphys;
306 /* Virtual address of per-cpu common_tss */
307 extern struct i386tss common_tss;
309 extern struct segment_descriptor common_tssd;
310 extern u_int private_tss; /* flag indicating private tss */
314 /* IdlePTD per cpu */
315 pd_entry_t *IdlePTDS[NCPU];
317 /* "my" private page table page, for BSP init */
318 extern pt_entry_t SMP_prvpt[];
320 /* Private page pointer to curcpu's PTD, used during BSP init */
321 extern pd_entry_t *my_idlePTD;
323 struct pcb stoppcbs[NCPU];
325 int smp_started; /* has the system started? */
328 * Local data and functions.
331 static int mp_capable;
332 static u_int boot_address;
333 static u_int base_memory;
335 static int picmode; /* 0: virtual wire mode, 1: PIC mode */
336 static mpfps_t mpfps;
337 static int search_for_sig(u_int32_t target, int count);
338 static void mp_enable(u_int boot_addr);
340 static int mptable_pass1(void);
341 static int mptable_pass2(void);
342 static void default_mp_table(int type);
343 static void fix_mp_table(void);
344 static void setup_apic_irq_mapping(void);
345 static void init_locks(void);
346 static int start_all_aps(u_int boot_addr);
347 static void install_ap_tramp(u_int boot_addr);
348 static int start_ap(int logicalCpu, u_int boot_addr);
351 * Calculate usable address in base memory for AP trampoline code.
354 mp_bootaddress(u_int basemem)
356 POSTCODE(MP_BOOTADDRESS_POST);
358 base_memory = basemem * 1024; /* convert to bytes */
360 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
361 if ((base_memory - boot_address) < bootMP_size)
362 boot_address -= 4096; /* not enough, lower by 4k */
369 * Look for an Intel MP spec table (ie, SMP capable hardware).
378 POSTCODE(MP_PROBE_POST);
380 /* see if EBDA exists */
381 if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) {
382 /* search first 1K of EBDA */
383 target = (u_int32_t) (segment << 4);
384 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
387 /* last 1K of base memory, effective 'top of base' passed in */
388 target = (u_int32_t) (base_memory - 0x400);
389 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
393 /* search the BIOS */
394 target = (u_int32_t) BIOS_BASE;
395 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
404 /* calculate needed resources */
407 panic("you must reconfigure your kernel");
409 /* flag fact that we are running multiple processors */
416 * Startup the SMP processors.
421 POSTCODE(MP_START_POST);
423 /* look for MP capable motherboard */
425 mp_enable(boot_address);
427 panic("MP hardware not found!");
432 * Print various information about the SMP system hardware and setup.
439 POSTCODE(MP_ANNOUNCE_POST);
441 printf("FreeBSD/SMP: Multiprocessor motherboard\n");
442 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
443 printf(", version: 0x%08x", cpu_apic_versions[0]);
444 printf(", at 0x%08x\n", cpu_apic_address);
445 for (x = 1; x <= mp_naps; ++x) {
446 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
447 printf(", version: 0x%08x", cpu_apic_versions[x]);
448 printf(", at 0x%08x\n", cpu_apic_address);
452 for (x = 0; x < mp_napics; ++x) {
453 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
454 printf(", version: 0x%08x", io_apic_versions[x]);
455 printf(", at 0x%08x\n", io_apic_address[x]);
458 printf(" Warning: APIC I/O disabled\n");
463 * AP cpu's call this to sync up protected mode.
473 r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1;
474 r_gdt.rd_base = (int) gdt;
475 lgdt(&r_gdt); /* does magic intra-segment return */
479 currentldt = _default_ldt;
482 my_tr = NGDT + cpuid;
483 gsel_tss = GSEL(my_tr, SEL_KPL);
484 gdt[my_tr].sd.sd_type = SDT_SYS386TSS;
485 common_tss.tss_esp0 = 0; /* not used until after switch */
486 common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
487 common_tss.tss_ioopt = (sizeof common_tss) << 16;
489 common_tssd = gdt[my_tr].sd;
494 load_cr0(0x8005003b); /* XXX! */
497 pmap_set_opt((unsigned *)PTD);
508 * Final configuration of the BSP's local APIC:
509 * - disable 'pic mode'.
510 * - disable 'virtual wire mode'.
514 bsp_apic_configure(void)
519 /* leave 'pic mode' if necessary */
521 outb(0x22, 0x70); /* select IMCR */
522 byte = inb(0x23); /* current contents */
523 byte |= 0x01; /* mask external INTR */
524 outb(0x23, byte); /* disconnect 8259s/NMI */
527 /* mask lint0 (the 8259 'virtual wire' connection) */
528 temp = lapic.lvt_lint0;
529 temp |= APIC_LVT_M; /* set the mask */
530 lapic.lvt_lint0 = temp;
532 /* setup lint1 to handle NMI */
533 temp = lapic.lvt_lint1;
534 temp &= ~APIC_LVT_M; /* clear the mask */
535 lapic.lvt_lint1 = temp;
538 apic_dump("bsp_apic_configure()");
543 /*******************************************************************
544 * local functions and data
548 * start the SMP system
551 mp_enable(u_int boot_addr)
562 POSTCODE(MP_ENABLE_POST);
564 /* turn on 4MB of V == P addressing so we can get to MP table */
565 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
568 /* examine the MP table for needed info, uses physical addresses */
574 /* can't process default configs till the CPU APIC is pmapped */
578 /* post scan cleanup */
580 setup_apic_irq_mapping();
584 /* fill the LOGICAL io_apic_versions table */
585 for (apic = 0; apic < mp_napics; ++apic) {
586 ux = io_apic_read(apic, IOAPIC_VER);
587 io_apic_versions[apic] = ux;
590 /* program each IO APIC in the system */
591 for (apic = 0; apic < mp_napics; ++apic)
592 if (io_apic_setup(apic) < 0)
593 panic("IO APIC setup failure");
595 /* install a 'Spurious INTerrupt' vector */
596 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
597 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
599 /* install an inter-CPU IPI for TLB invalidation */
600 setidt(XINVLTLB_OFFSET, Xinvltlb,
601 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
604 /* install an inter-CPU IPI for reading processor state */
605 setidt(XCPUCHECKSTATE_OFFSET, Xcpucheckstate,
606 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
609 /* install an inter-CPU IPI for forcing an additional software trap */
610 setidt(XCPUAST_OFFSET, Xcpuast,
611 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
613 /* install an inter-CPU IPI for interrupt forwarding */
614 setidt(XFORWARD_IRQ_OFFSET, Xforward_irq,
615 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
617 /* install an inter-CPU IPI for CPU stop/restart */
618 setidt(XCPUSTOP_OFFSET, Xcpustop,
619 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
621 #if defined(TEST_TEST1)
622 /* install a "fake hardware INTerrupt" vector */
623 setidt(XTEST1_OFFSET, Xtest1,
624 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
625 #endif /** TEST_TEST1 */
629 /* initialize all SMP locks */
632 /* start each Application Processor */
633 start_all_aps(boot_addr);
636 * The init process might be started on a different CPU now,
637 * and the boot CPU might not call prepare_usermode to get
638 * cr0 correctly configured. Thus we initialize cr0 here.
640 load_cr0(rcr0() | CR0_WP | CR0_AM);
645 * look for the MP spec signature
648 /* string defined by the Intel MP Spec as identifying the MP table */
649 #define MP_SIG 0x5f504d5f /* _MP_ */
650 #define NEXT(X) ((X) += 4)
652 search_for_sig(u_int32_t target, int count)
655 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
657 for (x = 0; x < count; NEXT(x))
658 if (addr[x] == MP_SIG)
659 /* make array index a byte index */
660 return (target + (x * sizeof(u_int32_t)));
666 static basetable_entry basetable_entry_types[] =
668 {0, 20, "Processor"},
675 typedef struct BUSDATA {
677 enum busTypes bus_type;
680 typedef struct INTDATA {
690 typedef struct BUSTYPENAME {
695 static bus_type_name bus_type_table[] =
700 {UNKNOWN_BUSTYPE, "---"},
701 {UNKNOWN_BUSTYPE, "---"},
703 {UNKNOWN_BUSTYPE, "---"},
704 {UNKNOWN_BUSTYPE, "---"},
705 {UNKNOWN_BUSTYPE, "---"},
706 {UNKNOWN_BUSTYPE, "---"},
707 {UNKNOWN_BUSTYPE, "---"},
708 {UNKNOWN_BUSTYPE, "---"},
710 {UNKNOWN_BUSTYPE, "---"},
711 {UNKNOWN_BUSTYPE, "---"},
712 {UNKNOWN_BUSTYPE, "---"},
713 {UNKNOWN_BUSTYPE, "---"},
715 {UNKNOWN_BUSTYPE, "---"}
717 /* from MP spec v1.4, table 5-1 */
718 static int default_data[7][5] =
720 /* nbus, id0, type0, id1, type1 */
721 {1, 0, ISA, 255, 255},
722 {1, 0, EISA, 255, 255},
723 {1, 0, EISA, 255, 255},
724 {0, 255, 255, 255, 255},/* MCA not supported */
726 {2, 0, EISA, 1, PCI},
727 {0, 255, 255, 255, 255} /* MCA not supported */
732 static bus_datum bus_data[NBUS];
734 /* the IO INT data, one entry per possible APIC INTerrupt */
735 static io_int io_apic_ints[NINTR];
739 static int processor_entry __P((proc_entry_ptr entry, int cpu));
740 static int bus_entry __P((bus_entry_ptr entry, int bus));
741 static int io_apic_entry __P((io_apic_entry_ptr entry, int apic));
742 static int int_entry __P((int_entry_ptr entry, int intr));
743 static int lookup_bus_type __P((char *name));
747 * 1st pass on motherboard's Intel MP specification table.
753 * cpu_apic_address (common to all CPUs)
771 POSTCODE(MPTABLE_PASS1_POST);
775 /* clear various tables */
776 for (x = 0; x < NAPICID; ++x) {
777 io_apic_address[x] = ~0; /* IO APIC address table */
780 /* init everything to empty */
786 /* check for use of 'default' configuration */
787 if (MPFPS_MPFB1 != 0) {
788 /* use default addresses */
789 cpu_apic_address = DEFAULT_APIC_BASE;
790 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
792 /* fill in with defaults */
793 mp_naps = 2; /* includes BSP */
794 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0];
801 if ((cth = mpfps->pap) == 0)
802 panic("MP Configuration Table Header MISSING!");
804 cpu_apic_address = (vm_offset_t) cth->apic_address;
806 /* walk the table, recording info of interest */
807 totalSize = cth->base_table_length - sizeof(struct MPCTH);
808 position = (u_char *) cth + sizeof(struct MPCTH);
809 count = cth->entry_count;
812 switch (type = *(u_char *) position) {
813 case 0: /* processor_entry */
814 if (((proc_entry_ptr)position)->cpu_flags
818 case 1: /* bus_entry */
821 case 2: /* io_apic_entry */
822 if (((io_apic_entry_ptr)position)->apic_flags
823 & IOAPICENTRY_FLAG_EN)
824 io_apic_address[mp_napics++] =
825 (vm_offset_t)((io_apic_entry_ptr)
826 position)->apic_address;
828 case 3: /* int_entry */
831 case 4: /* int_entry */
834 panic("mpfps Base Table HOSED!");
838 totalSize -= basetable_entry_types[type].length;
839 (u_char*)position += basetable_entry_types[type].length;
843 /* qualify the numbers */
845 #if 0 /* XXX FIXME: kern/4255 */
846 printf("Warning: only using %d of %d available CPUs!\n",
850 printf("NCPU cannot be different than actual CPU count.\n");
851 printf(" add 'options NCPU=%d' to your kernel config file,\n",
853 printf(" then rerun config & rebuild your SMP kernel\n");
856 #endif /* XXX FIXME: kern/4255 */
857 if (mp_nbusses > NBUS) {
858 printf("found %d busses, increase NBUS\n", mp_nbusses);
861 if (mp_napics > NAPIC) {
862 printf("found %d apics, increase NAPIC\n", mp_napics);
865 if (nintrs > NINTR) {
866 printf("found %d intrs, increase NINTR\n", nintrs);
872 * This is also used as a counter while starting the APs.
876 --mp_naps; /* subtract the BSP */
883 * 2nd pass on motherboard's Intel MP specification table.
887 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
888 * CPU_TO_ID(N), logical CPU to APIC ID table
889 * IO_TO_ID(N), logical IO to APIC ID table
902 int apic, bus, cpu, intr;
904 POSTCODE(MPTABLE_PASS2_POST);
906 /* clear various tables */
907 for (x = 0; x < NAPICID; ++x) {
908 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
909 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
910 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
913 /* clear bus data table */
914 for (x = 0; x < NBUS; ++x)
915 bus_data[x].bus_id = 0xff;
917 /* clear IO APIC INT table */
918 for (x = 0; x < NINTR; ++x) {
919 io_apic_ints[x].int_type = 0xff;
920 io_apic_ints[x].int_vector = 0xff;
923 /* setup the cpu/apic mapping arrays */
926 /* record whether PIC or virtual-wire mode */
927 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0;
929 /* check for use of 'default' configuration */
930 if (MPFPS_MPFB1 != 0)
931 return MPFPS_MPFB1; /* return default configuration type */
933 if ((cth = mpfps->pap) == 0)
934 panic("MP Configuration Table Header MISSING!");
936 /* walk the table, recording info of interest */
937 totalSize = cth->base_table_length - sizeof(struct MPCTH);
938 position = (u_char *) cth + sizeof(struct MPCTH);
939 count = cth->entry_count;
940 apic = bus = intr = 0;
941 cpu = 1; /* pre-count the BSP */
944 switch (type = *(u_char *) position) {
946 if (processor_entry(position, cpu))
950 if (bus_entry(position, bus))
954 if (io_apic_entry(position, apic))
958 if (int_entry(position, intr))
962 /* int_entry(position); */
965 panic("mpfps Base Table HOSED!");
969 totalSize -= basetable_entry_types[type].length;
970 (u_char *) position += basetable_entry_types[type].length;
973 if (boot_cpu_id == -1)
974 panic("NO BSP found!");
976 /* report fact that its NOT a default configuration */
982 assign_apic_irq(int apic, int intpin, int irq)
986 if (int_to_apicintpin[irq].ioapic != -1)
987 panic("assign_apic_irq: inconsistent table");
989 int_to_apicintpin[irq].ioapic = apic;
990 int_to_apicintpin[irq].int_pin = intpin;
991 int_to_apicintpin[irq].apic_address = ioapic[apic];
992 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
994 for (x = 0; x < nintrs; x++) {
995 if ((io_apic_ints[x].int_type == 0 ||
996 io_apic_ints[x].int_type == 3) &&
997 io_apic_ints[x].int_vector == 0xff &&
998 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
999 io_apic_ints[x].dst_apic_int == intpin)
1000 io_apic_ints[x].int_vector = irq;
1005 * parse an Intel MP specification table
1017 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1018 * did it wrong. The MP spec says that when more than 1 PCI bus
1019 * exists the BIOS must begin with bus entries for the PCI bus and use
1020 * actual PCI bus numbering. This implies that when only 1 PCI bus
1021 * exists the BIOS can choose to ignore this ordering, and indeed many
1022 * MP motherboards do ignore it. This causes a problem when the PCI
1023 * sub-system makes requests of the MP sub-system based on PCI bus
1024 * numbers. So here we look for the situation and renumber the
1025 * busses and associated INTs in an effort to "make it right".
1028 /* find bus 0, PCI bus, count the number of PCI busses */
1029 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1030 if (bus_data[x].bus_id == 0) {
1033 if (bus_data[x].bus_type == PCI) {
1039 * bus_0 == slot of bus with ID of 0
1040 * bus_pci == slot of last PCI bus encountered
1043 /* check the 1 PCI bus case for sanity */
1044 if (num_pci_bus == 1) {
1046 /* if it is number 0 all is well */
1047 if (bus_data[bus_pci].bus_id == 0)
1050 /* mis-numbered, swap with whichever bus uses slot 0 */
1052 /* swap the bus entry types */
1053 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1054 bus_data[bus_0].bus_type = PCI;
1056 /* swap each relavant INTerrupt entry */
1057 id = bus_data[bus_pci].bus_id;
1058 for (x = 0; x < nintrs; ++x) {
1059 if (io_apic_ints[x].src_bus_id == id) {
1060 io_apic_ints[x].src_bus_id = 0;
1062 else if (io_apic_ints[x].src_bus_id == 0) {
1063 io_apic_ints[x].src_bus_id = id;
1067 /* sanity check if more than 1 PCI bus */
1068 else if (num_pci_bus > 1) {
1069 for (x = 0; x < mp_nbusses; ++x) {
1070 if (bus_data[x].bus_type != PCI)
1072 if (bus_data[x].bus_id >= num_pci_bus)
1073 panic("bad PCI bus numbering");
1080 setup_apic_irq_mapping(void)
1085 /* Assign low level interrupt handlers */
1086 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1087 int_to_apicintpin[x].ioapic = -1;
1088 int_to_apicintpin[x].int_pin = 0;
1089 int_to_apicintpin[x].apic_address = NULL;
1090 int_to_apicintpin[x].redirindex = 0;
1092 for (x = 0; x < nintrs; x++) {
1093 if (io_apic_ints[x].dst_apic_int <= APIC_INTMAPSIZE &&
1094 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1095 io_apic_ints[x].int_vector == 0xff &&
1096 (io_apic_ints[x].int_type == 0 ||
1097 io_apic_ints[x].int_type == 3)) {
1099 io_apic_ints[x].dst_apic_int,
1100 io_apic_ints[x].dst_apic_int);
1104 while (int_vector < APIC_INTMAPSIZE &&
1105 int_to_apicintpin[int_vector].ioapic != -1)
1107 for (x = 0; x < nintrs && int_vector < APIC_INTMAPSIZE; x++) {
1108 if ((io_apic_ints[x].int_type == 0 ||
1109 io_apic_ints[x].int_type == 3) &&
1110 io_apic_ints[x].int_vector == 0xff) {
1111 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1112 io_apic_ints[x].dst_apic_int,
1115 while (int_vector < APIC_INTMAPSIZE &&
1116 int_to_apicintpin[int_vector].ioapic != -1)
1124 processor_entry(proc_entry_ptr entry, int cpu)
1126 /* check for usability */
1127 if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN))
1130 /* check for BSP flag */
1131 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1132 boot_cpu_id = entry->apic_id;
1133 CPU_TO_ID(0) = entry->apic_id;
1134 ID_TO_CPU(entry->apic_id) = 0;
1135 return 0; /* its already been counted */
1138 /* add another AP to list, if less than max number of CPUs */
1140 CPU_TO_ID(cpu) = entry->apic_id;
1141 ID_TO_CPU(entry->apic_id) = cpu;
1148 bus_entry(bus_entry_ptr entry, int bus)
1153 /* encode the name into an index */
1154 for (x = 0; x < 6; ++x) {
1155 if ((c = entry->bus_type[x]) == ' ')
1161 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1162 panic("unknown bus type: '%s'", name);
1164 bus_data[bus].bus_id = entry->bus_id;
1165 bus_data[bus].bus_type = x;
1172 io_apic_entry(io_apic_entry_ptr entry, int apic)
1174 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1177 IO_TO_ID(apic) = entry->apic_id;
1178 ID_TO_IO(entry->apic_id) = apic;
1185 lookup_bus_type(char *name)
1189 for (x = 0; x < MAX_BUSTYPE; ++x)
1190 if (strcmp(bus_type_table[x].name, name) == 0)
1191 return bus_type_table[x].type;
1193 return UNKNOWN_BUSTYPE;
1198 int_entry(int_entry_ptr entry, int intr)
1200 io_apic_ints[intr].int_type = entry->int_type;
1201 io_apic_ints[intr].int_flags = entry->int_flags;
1202 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1203 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1204 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1205 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1212 apic_int_is_bus_type(int intr, int bus_type)
1216 for (bus = 0; bus < mp_nbusses; ++bus)
1217 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1218 && ((int) bus_data[bus].bus_type == bus_type))
1226 * Given a traditional ISA INT mask, return an APIC mask.
1229 isa_apic_mask(u_int isa_mask)
1234 #if defined(SKIP_IRQ15_REDIRECT)
1235 if (isa_mask == (1 << 15)) {
1236 printf("skipping ISA IRQ15 redirect\n");
1239 #endif /* SKIP_IRQ15_REDIRECT */
1241 isa_irq = ffs(isa_mask); /* find its bit position */
1242 if (isa_irq == 0) /* doesn't exist */
1244 --isa_irq; /* make it zero based */
1246 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1250 return (1 << apic_pin); /* convert pin# to a mask */
1255 * Determine which APIC pin an ISA/EISA INT is attached to.
1257 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1258 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1259 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1260 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1262 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1264 isa_apic_irq(int isa_irq)
1268 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1269 if (INTTYPE(intr) == 0) { /* standard INT */
1270 if (SRCBUSIRQ(intr) == isa_irq) {
1271 if (apic_int_is_bus_type(intr, ISA) ||
1272 apic_int_is_bus_type(intr, EISA))
1273 return INTIRQ(intr); /* found */
1277 return -1; /* NOT found */
1282 * Determine which APIC pin a PCI INT is attached to.
1284 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1285 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1286 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1288 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1292 --pciInt; /* zero based */
1294 for (intr = 0; intr < nintrs; ++intr) /* check each record */
1295 if ((INTTYPE(intr) == 0) /* standard INT */
1296 && (SRCBUSID(intr) == pciBus)
1297 && (SRCBUSDEVICE(intr) == pciDevice)
1298 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */
1299 if (apic_int_is_bus_type(intr, PCI))
1300 return INTIRQ(intr); /* exact match */
1302 return -1; /* NOT found */
1306 next_apic_irq(int irq)
1313 for (intr = 0; intr < nintrs; intr++) {
1314 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1316 bus = SRCBUSID(intr);
1317 bustype = apic_bus_type(bus);
1318 if (bustype != ISA &&
1324 if (intr >= nintrs) {
1327 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1328 if (INTTYPE(ointr) != 0)
1330 if (bus != SRCBUSID(ointr))
1332 if (bustype == PCI) {
1333 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1335 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1338 if (bustype == ISA || bustype == EISA) {
1339 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1342 if (INTPIN(intr) == INTPIN(ointr))
1346 if (ointr >= nintrs) {
1349 return INTIRQ(ointr);
1363 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1366 * Exactly what this means is unclear at this point. It is a solution
1367 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1368 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1369 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1373 undirect_isa_irq(int rirq)
1376 printf("Freeing redirected ISA irq %d.\n", rirq);
1377 /** FIXME: tickle the MB redirector chip */
1380 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1387 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1390 undirect_pci_irq(int rirq)
1394 printf("Freeing redirected PCI irq %d.\n", rirq);
1396 /** FIXME: tickle the MB redirector chip */
1400 printf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1408 * given a bus ID, return:
1409 * the bus type if found
1413 apic_bus_type(int id)
1417 for (x = 0; x < mp_nbusses; ++x)
1418 if (bus_data[x].bus_id == id)
1419 return bus_data[x].bus_type;
1426 * given a LOGICAL APIC# and pin#, return:
1427 * the associated src bus ID if found
1431 apic_src_bus_id(int apic, int pin)
1435 /* search each of the possible INTerrupt sources */
1436 for (x = 0; x < nintrs; ++x)
1437 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1438 (pin == io_apic_ints[x].dst_apic_int))
1439 return (io_apic_ints[x].src_bus_id);
1441 return -1; /* NOT found */
1446 * given a LOGICAL APIC# and pin#, return:
1447 * the associated src bus IRQ if found
1451 apic_src_bus_irq(int apic, int pin)
1455 for (x = 0; x < nintrs; x++)
1456 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1457 (pin == io_apic_ints[x].dst_apic_int))
1458 return (io_apic_ints[x].src_bus_irq);
1460 return -1; /* NOT found */
1465 * given a LOGICAL APIC# and pin#, return:
1466 * the associated INTerrupt type if found
1470 apic_int_type(int apic, int pin)
1474 /* search each of the possible INTerrupt sources */
1475 for (x = 0; x < nintrs; ++x)
1476 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1477 (pin == io_apic_ints[x].dst_apic_int))
1478 return (io_apic_ints[x].int_type);
1480 return -1; /* NOT found */
1484 apic_irq(int apic, int pin)
1489 for (x = 0; x < nintrs; ++x)
1490 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1491 (pin == io_apic_ints[x].dst_apic_int)) {
1492 res = io_apic_ints[x].int_vector;
1495 if (apic != int_to_apicintpin[res].ioapic)
1496 panic("apic_irq: inconsistent table");
1497 if (pin != int_to_apicintpin[res].int_pin)
1498 panic("apic_irq inconsistent table (2)");
1506 * given a LOGICAL APIC# and pin#, return:
1507 * the associated trigger mode if found
1511 apic_trigger(int apic, int pin)
1515 /* search each of the possible INTerrupt sources */
1516 for (x = 0; x < nintrs; ++x)
1517 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1518 (pin == io_apic_ints[x].dst_apic_int))
1519 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1521 return -1; /* NOT found */
1526 * given a LOGICAL APIC# and pin#, return:
1527 * the associated 'active' level if found
1531 apic_polarity(int apic, int pin)
1535 /* search each of the possible INTerrupt sources */
1536 for (x = 0; x < nintrs; ++x)
1537 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1538 (pin == io_apic_ints[x].dst_apic_int))
1539 return (io_apic_ints[x].int_flags & 0x03);
1541 return -1; /* NOT found */
1546 * set data according to MP defaults
1547 * FIXME: probably not complete yet...
1550 default_mp_table(int type)
1553 #if defined(APIC_IO)
1557 #endif /* APIC_IO */
1560 printf(" MP default config type: %d\n", type);
1563 printf(" bus: ISA, APIC: 82489DX\n");
1566 printf(" bus: EISA, APIC: 82489DX\n");
1569 printf(" bus: EISA, APIC: 82489DX\n");
1572 printf(" bus: MCA, APIC: 82489DX\n");
1575 printf(" bus: ISA+PCI, APIC: Integrated\n");
1578 printf(" bus: EISA+PCI, APIC: Integrated\n");
1581 printf(" bus: MCA+PCI, APIC: Integrated\n");
1584 printf(" future type\n");
1590 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1591 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1594 CPU_TO_ID(0) = boot_cpu_id;
1595 ID_TO_CPU(boot_cpu_id) = 0;
1597 /* one and only AP */
1598 CPU_TO_ID(1) = ap_cpu_id;
1599 ID_TO_CPU(ap_cpu_id) = 1;
1601 #if defined(APIC_IO)
1602 /* one and only IO APIC */
1603 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1606 * sanity check, refer to MP spec section 3.6.6, last paragraph
1607 * necessary as some hardware isn't properly setting up the IO APIC
1609 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1610 if (io_apic_id != 2) {
1612 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1613 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1614 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */
1615 ux &= ~APIC_ID_MASK; /* clear the ID field */
1616 ux |= 0x02000000; /* set it to '2' */
1617 io_apic_write(0, IOAPIC_ID, ux); /* write new value */
1618 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */
1619 if ((ux & APIC_ID_MASK) != 0x02000000)
1620 panic("can't control IO APIC ID, reg: 0x%08x", ux);
1623 IO_TO_ID(0) = io_apic_id;
1624 ID_TO_IO(io_apic_id) = 0;
1625 #endif /* APIC_IO */
1627 /* fill out bus entries */
1634 bus_data[0].bus_id = default_data[type - 1][1];
1635 bus_data[0].bus_type = default_data[type - 1][2];
1636 bus_data[1].bus_id = default_data[type - 1][3];
1637 bus_data[1].bus_type = default_data[type - 1][4];
1640 /* case 4: case 7: MCA NOT supported */
1641 default: /* illegal/reserved */
1642 panic("BAD default MP config: %d", type);
1646 #if defined(APIC_IO)
1647 /* general cases from MP v1.4, table 5-2 */
1648 for (pin = 0; pin < 16; ++pin) {
1649 io_apic_ints[pin].int_type = 0;
1650 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
1651 io_apic_ints[pin].src_bus_id = 0;
1652 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
1653 io_apic_ints[pin].dst_apic_id = io_apic_id;
1654 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
1657 /* special cases from MP v1.4, table 5-2 */
1659 io_apic_ints[2].int_type = 0xff; /* N/C */
1660 io_apic_ints[13].int_type = 0xff; /* N/C */
1661 #if !defined(APIC_MIXED_MODE)
1663 panic("sorry, can't support type 2 default yet");
1664 #endif /* APIC_MIXED_MODE */
1667 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
1670 io_apic_ints[0].int_type = 0xff; /* N/C */
1672 io_apic_ints[0].int_type = 3; /* vectored 8259 */
1673 #endif /* APIC_IO */
1678 * initialize all the SMP locks
1681 /* critical region around IO APIC, apic_imen */
1682 struct simplelock imen_lock;
1684 /* critical region around splxx(), cpl, cml, cil, ipending */
1685 struct simplelock cpl_lock;
1687 /* Make FAST_INTR() routines sequential */
1688 struct simplelock fast_intr_lock;
1690 /* critical region around INTR() routines */
1691 struct simplelock intr_lock;
1693 /* lock regions protected in UP kernel via cli/sti */
1694 struct simplelock mpintr_lock;
1696 /* lock region used by kernel profiling */
1697 struct simplelock mcount_lock;
1700 /* locks com (tty) data/hardware accesses: a FASTINTR() */
1701 struct simplelock com_lock;
1702 #endif /* USE_COMLOCK */
1704 #ifdef USE_CLOCKLOCK
1705 /* lock regions around the clock hardware */
1706 struct simplelock clock_lock;
1707 #endif /* USE_CLOCKLOCK */
1713 * Get the initial mp_lock with a count of 1 for the BSP.
1714 * This uses a LOGICAL cpu ID, ie BSP == 0.
1716 mp_lock = 0x00000001;
1718 /* ISR uses its own "giant lock" */
1719 isr_lock = FREE_LOCK;
1721 #if defined(APIC_INTR_DIAGNOSTIC) && defined(APIC_INTR_DIAGNOSTIC_IRQ)
1722 s_lock_init((struct simplelock*)&apic_itrace_debuglock);
1725 s_lock_init((struct simplelock*)&mpintr_lock);
1727 s_lock_init((struct simplelock*)&mcount_lock);
1729 s_lock_init((struct simplelock*)&fast_intr_lock);
1730 s_lock_init((struct simplelock*)&intr_lock);
1731 s_lock_init((struct simplelock*)&imen_lock);
1732 s_lock_init((struct simplelock*)&cpl_lock);
1735 s_lock_init((struct simplelock*)&com_lock);
1736 #endif /* USE_COMLOCK */
1737 #ifdef USE_CLOCKLOCK
1738 s_lock_init((struct simplelock*)&clock_lock);
1739 #endif /* USE_CLOCKLOCK */
1744 * start each AP in our list
1747 start_all_aps(u_int boot_addr)
1750 u_char mpbiosreason;
1751 u_long mpbioswarmvec;
1754 struct globaldata *gd;
1758 POSTCODE(START_ALL_APS_POST);
1760 /* initialize BSP's local APIC */
1764 /* install the AP 1st level boot code */
1765 install_ap_tramp(boot_addr);
1768 /* save the current value of the warm-start vector */
1769 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
1771 outb(CMOS_REG, BIOS_RESET);
1772 mpbiosreason = inb(CMOS_DATA);
1775 /* record BSP in CPU map */
1779 for (x = 1; x <= mp_naps; ++x) {
1781 /* This is a bit verbose, it will go away soon. */
1783 /* alloc new page table directory */
1784 newptd = (pd_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE));
1786 /* Store the virtual PTD address for this CPU */
1787 IdlePTDS[x] = newptd;
1789 /* clone currently active one (ie: IdlePTD) */
1790 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */
1792 /* set up 0 -> 4MB P==V mapping for AP boot */
1793 newptd[0] = (void *)(uintptr_t)(PG_V | PG_RW |
1794 ((uintptr_t)(void *)KPTphys & PG_FRAME));
1796 /* store PTD for this AP's boot sequence */
1797 myPTD = (pd_entry_t *)vtophys(newptd);
1799 /* alloc new page table page */
1800 newpt = (pt_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE));
1802 /* set the new PTD's private page to point there */
1803 newptd[MPPTDI] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpt));
1805 /* install self referential entry */
1806 newptd[PTDPTDI] = (pd_entry_t)(PG_V | PG_RW | vtophys(newptd));
1808 /* allocate a new private data page */
1809 gd = (struct globaldata *)kmem_alloc(kernel_map, PAGE_SIZE);
1811 /* wire it into the private page table page */
1812 newpt[0] = (pt_entry_t)(PG_V | PG_RW | vtophys(gd));
1814 /* wire the ptp into itself for access */
1815 newpt[1] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpt));
1817 /* copy in the pointer to the local apic */
1818 newpt[2] = SMP_prvpt[2];
1820 /* and the IO apic mapping[s] */
1821 for (i = 16; i < 32; i++)
1822 newpt[i] = SMP_prvpt[i];
1824 /* allocate and set up an idle stack data page */
1825 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE);
1826 for (i = 0; i < UPAGES; i++)
1827 newpt[i + 3] = (pt_entry_t)(PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
1829 newpt[3 + UPAGES] = 0; /* *prv_CMAP1 */
1830 newpt[4 + UPAGES] = 0; /* *prv_CMAP2 */
1831 newpt[5 + UPAGES] = 0; /* *prv_CMAP3 */
1832 newpt[6 + UPAGES] = 0; /* *prv_PMAP1 */
1834 /* prime data page for it to use */
1836 gd->cpu_lockid = x << 24;
1837 gd->my_idlePTD = myPTD;
1838 gd->prv_CMAP1 = &newpt[3 + UPAGES];
1839 gd->prv_CMAP2 = &newpt[4 + UPAGES];
1840 gd->prv_CMAP3 = &newpt[5 + UPAGES];
1841 gd->prv_PMAP1 = &newpt[6 + UPAGES];
1843 /* setup a vector to our boot code */
1844 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
1845 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
1847 outb(CMOS_REG, BIOS_RESET);
1848 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
1852 /* attempt to start the Application Processor */
1853 CHECK_INIT(99); /* setup checkpoints */
1854 if (!start_ap(x, boot_addr)) {
1855 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
1856 CHECK_PRINT("trace"); /* show checkpoints */
1857 /* better panic as the AP may be running loose */
1858 printf("panic y/n? [y] ");
1859 if (cngetc() != 'n')
1862 CHECK_PRINT("trace"); /* show checkpoints */
1864 /* record its version info */
1865 cpu_apic_versions[x] = cpu_apic_versions[0];
1867 all_cpus |= (1 << x); /* record AP in CPU map */
1870 /* build our map of 'other' CPUs */
1871 other_cpus = all_cpus & ~(1 << cpuid);
1873 /* fill in our (BSP) APIC version */
1874 cpu_apic_versions[0] = lapic.version;
1876 /* restore the warmstart vector */
1877 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
1879 outb(CMOS_REG, BIOS_RESET);
1880 outb(CMOS_DATA, mpbiosreason);
1884 * Set up the idle context for the BSP. Similar to above except
1885 * that some was done by locore, some by pmap.c and some is implicit
1886 * because the BSP is cpu#0 and the page is initially zero, and also
1887 * because we can refer to variables by name on the BSP..
1889 newptd = (pd_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE));
1891 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */
1892 IdlePTDS[0] = newptd;
1894 /* Point PTD[] to this page instead of IdlePTD's physical page */
1895 newptd[PTDPTDI] = (pd_entry_t)(PG_V | PG_RW | vtophys(newptd));
1897 my_idlePTD = (pd_entry_t *)vtophys(newptd);
1899 /* Allocate and setup BSP idle stack */
1900 stack = (char *)kmem_alloc(kernel_map, UPAGES * PAGE_SIZE);
1901 for (i = 0; i < UPAGES; i++)
1902 SMP_prvpt[i + 3] = (pt_entry_t)(PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
1906 for (i = 0; i < mp_ncpus; i++) {
1907 bcopy( (int *) PTD + KPTDI, (int *) IdlePTDS[i] + KPTDI, NKPDE * sizeof (int));
1910 /* number of APs actually started */
1911 return mp_ncpus - 1;
1916 * load the 1st level AP boot code into base memory.
1919 /* targets for relocation */
1920 extern void bigJump(void);
1921 extern void bootCodeSeg(void);
1922 extern void bootDataSeg(void);
1923 extern void MPentry(void);
1924 extern u_int MP_GDT;
1925 extern u_int mp_gdtbase;
1928 install_ap_tramp(u_int boot_addr)
1931 int size = *(int *) ((u_long) & bootMP_size);
1932 u_char *src = (u_char *) ((u_long) bootMP);
1933 u_char *dst = (u_char *) boot_addr + KERNBASE;
1934 u_int boot_base = (u_int) bootMP;
1939 POSTCODE(INSTALL_AP_TRAMP_POST);
1941 for (x = 0; x < size; ++x)
1945 * modify addresses in code we just moved to basemem. unfortunately we
1946 * need fairly detailed info about mpboot.s for this to work. changes
1947 * to mpboot.s might require changes here.
1950 /* boot code is located in KERNEL space */
1951 dst = (u_char *) boot_addr + KERNBASE;
1953 /* modify the lgdt arg */
1954 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
1955 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
1957 /* modify the ljmp target for MPentry() */
1958 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
1959 *dst32 = ((u_int) MPentry - KERNBASE);
1961 /* modify the target for boot code segment */
1962 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
1963 dst8 = (u_int8_t *) (dst16 + 1);
1964 *dst16 = (u_int) boot_addr & 0xffff;
1965 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
1967 /* modify the target for boot data segment */
1968 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
1969 dst8 = (u_int8_t *) (dst16 + 1);
1970 *dst16 = (u_int) boot_addr & 0xffff;
1971 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
1976 * this function starts the AP (application processor) identified
1977 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
1978 * to accomplish this. This is necessary because of the nuances
1979 * of the different hardware we might encounter. It ain't pretty,
1980 * but it seems to work.
1983 start_ap(int logical_cpu, u_int boot_addr)
1988 u_long icr_lo, icr_hi;
1990 POSTCODE(START_AP_POST);
1992 /* get the PHYSICAL APIC ID# */
1993 physical_cpu = CPU_TO_ID(logical_cpu);
1995 /* calculate the vector */
1996 vector = (boot_addr >> 12) & 0xff;
1998 /* used as a watchpoint to signal AP startup */
2002 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2003 * and running the target CPU. OR this INIT IPI might be latched (P5
2004 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2008 /* setup the address for the target AP */
2009 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2010 icr_hi |= (physical_cpu << 24);
2011 lapic.icr_hi = icr_hi;
2013 /* do an INIT IPI: assert RESET */
2014 icr_lo = lapic.icr_lo & 0xfff00000;
2015 lapic.icr_lo = icr_lo | 0x0000c500;
2017 /* wait for pending status end */
2018 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2021 /* do an INIT IPI: deassert RESET */
2022 lapic.icr_lo = icr_lo | 0x00008500;
2024 /* wait for pending status end */
2025 u_sleep(10000); /* wait ~10mS */
2026 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2030 * next we do a STARTUP IPI: the previous INIT IPI might still be
2031 * latched, (P5 bug) this 1st STARTUP would then terminate
2032 * immediately, and the previously started INIT IPI would continue. OR
2033 * the previous INIT IPI has already run. and this STARTUP IPI will
2034 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2038 /* do a STARTUP IPI */
2039 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2040 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2042 u_sleep(200); /* wait ~200uS */
2045 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2046 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2047 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2048 * recognized after hardware RESET or INIT IPI.
2051 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2052 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2054 u_sleep(200); /* wait ~200uS */
2056 /* wait for it to start */
2057 set_apic_timer(5000000);/* == 5 seconds */
2058 while (read_apic_timer())
2059 if (mp_ncpus > cpus)
2060 return 1; /* return SUCCESS */
2062 return 0; /* return FAILURE */
2067 * Flush the TLB on all other CPU's
2069 * XXX: Needs to handshake and wait for completion before proceding.
2074 #if defined(APIC_IO)
2075 if (smp_started && invltlb_ok)
2076 all_but_self_ipi(XINVLTLB_OFFSET);
2077 #endif /* APIC_IO */
2083 __asm __volatile("invlpg (%0)"::"r"(addr):"memory");
2085 /* send a message to the other CPUs */
2095 * This should be implemented as load_cr3(rcr3()) when load_cr3() is
2098 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory");
2100 /* send a message to the other CPUs */
2106 * When called the executing CPU will send an IPI to all other CPUs
2107 * requesting that they halt execution.
2109 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2111 * - Signals all CPUs in map to stop.
2112 * - Waits for each to stop.
2119 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2120 * from executing at same time.
2123 stop_cpus(u_int map)
2128 /* send the Xcpustop IPI to all CPUs in map */
2129 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2131 while ((stopped_cpus & map) != map)
2139 * Called by a CPU to restart stopped CPUs.
2141 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2143 * - Signals all CPUs in map to restart.
2144 * - Waits for each to restart.
2152 restart_cpus(u_int map)
2157 started_cpus = map; /* signal other cpus to restart */
2159 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2165 int smp_active = 0; /* are the APs allowed to run? */
2166 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RW, &smp_active, 0, "");
2168 /* XXX maybe should be hw.ncpu */
2169 static int smp_cpus = 1; /* how many cpu's running */
2170 SYSCTL_INT(_machdep, OID_AUTO, smp_cpus, CTLFLAG_RD, &smp_cpus, 0, "");
2172 int invltlb_ok = 0; /* throttle smp_invltlb() till safe */
2173 SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, "");
2175 /* Warning: Do not staticize. Used from swtch.s */
2176 int do_page_zero_idle = 1; /* bzero pages for fun and profit in idleloop */
2177 SYSCTL_INT(_machdep, OID_AUTO, do_page_zero_idle, CTLFLAG_RW,
2178 &do_page_zero_idle, 0, "");
2180 /* Is forwarding of a interrupt to the CPU holding the ISR lock enabled ? */
2181 int forward_irq_enabled = 1;
2182 SYSCTL_INT(_machdep, OID_AUTO, forward_irq_enabled, CTLFLAG_RW,
2183 &forward_irq_enabled, 0, "");
2185 /* Enable forwarding of a signal to a process running on a different CPU */
2186 int forward_signal_enabled = 1;
2187 SYSCTL_INT(_machdep, OID_AUTO, forward_signal_enabled, CTLFLAG_RW,
2188 &forward_signal_enabled, 0, "");
2190 /* Enable forwarding of roundrobin to all other cpus */
2191 int forward_roundrobin_enabled = 1;
2192 SYSCTL_INT(_machdep, OID_AUTO, forward_roundrobin_enabled, CTLFLAG_RW,
2193 &forward_roundrobin_enabled, 0, "");
2196 * This is called once the rest of the system is up and running and we're
2197 * ready to let the AP's out of the pen.
2209 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2213 /* Build our map of 'other' CPUs. */
2214 other_cpus = all_cpus & ~(1 << cpuid);
2216 printf("SMP: AP CPU #%d Launched!\n", cpuid);
2218 /* XXX FIXME: i386 specific, and redundant: Setup the FPU. */
2219 load_cr0((rcr0() & ~CR0_EM) | CR0_MP | CR0_NE | CR0_TS);
2221 /* A quick check from sanity claus */
2222 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2223 if (cpuid != apic_id) {
2224 printf("SMP: cpuid = %d\n", cpuid);
2225 printf("SMP: apic_id = %d\n", apic_id);
2226 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2227 panic("cpuid mismatch! boom!!");
2232 /* Init local apic for irq's */
2236 * Activate smp_invltlb, although strictly speaking, this isn't
2237 * quite correct yet. We should have a bitfield for cpus willing
2238 * to accept TLB flush IPI's or something and sync them.
2240 if (smp_cpus == mp_ncpus) {
2242 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */
2243 smp_active = 1; /* historic */
2246 curproc = NULL; /* make sure */
2251 #define CHECKSTATE_USER 0
2252 #define CHECKSTATE_SYS 1
2253 #define CHECKSTATE_INTR 2
2255 /* Do not staticize. Used from apic_vector.s */
2256 struct proc* checkstate_curproc[NCPU];
2257 int checkstate_cpustate[NCPU];
2258 u_long checkstate_pc[NCPU];
2260 extern long cp_time[CPUSTATES];
2262 #define PC_TO_INDEX(pc, prof) \
2263 ((int)(((u_quad_t)((pc) - (prof)->pr_off) * \
2264 (u_quad_t)((prof)->pr_scale)) >> 16) & ~1)
2267 addupc_intr_forwarded(struct proc *p, int id, int *astmap)
2273 pc = checkstate_pc[id];
2274 prof = &p->p_stats->p_prof;
2275 if (pc >= prof->pr_off &&
2276 (i = PC_TO_INDEX(pc, prof)) < prof->pr_size) {
2277 if ((p->p_flag & P_OWEUPC) == 0) {
2280 p->p_flag |= P_OWEUPC;
2282 *astmap |= (1 << id);
2287 forwarded_statclock(int id, int pscnt, int *astmap)
2289 struct pstats *pstats;
2296 register struct gmonparam *g;
2300 p = checkstate_curproc[id];
2301 cpustate = checkstate_cpustate[id];
2304 case CHECKSTATE_USER:
2305 if (p->p_flag & P_PROFIL)
2306 addupc_intr_forwarded(p, id, astmap);
2310 if (p->p_nice > NZERO)
2315 case CHECKSTATE_SYS:
2318 * Kernel statistics are just like addupc_intr, only easier.
2321 if (g->state == GMON_PROF_ON) {
2322 i = checkstate_pc[id] - g->lowpc;
2323 if (i < g->textsize) {
2324 i /= HISTFRACTION * sizeof(*g->kcount);
2339 case CHECKSTATE_INTR:
2343 * Kernel statistics are just like addupc_intr, only easier.
2346 if (g->state == GMON_PROF_ON) {
2347 i = checkstate_pc[id] - g->lowpc;
2348 if (i < g->textsize) {
2349 i /= HISTFRACTION * sizeof(*g->kcount);
2362 if (++p->p_estcpu == 0)
2364 if ((p->p_estcpu & 3) == 0) {
2366 if (p->p_priority >= PUSER)
2367 p->p_priority = p->p_usrpri;
2370 /* Update resource usage integrals and maximums. */
2371 if ((pstats = p->p_stats) != NULL &&
2372 (ru = &pstats->p_ru) != NULL &&
2373 (vm = p->p_vmspace) != NULL) {
2374 ru->ru_ixrss += vm->vm_tsize * PAGE_SIZE / 1024;
2375 ru->ru_idrss += vm->vm_dsize * PAGE_SIZE / 1024;
2376 ru->ru_isrss += vm->vm_ssize * PAGE_SIZE / 1024;
2377 rss = vm->vm_pmap.pm_stats.resident_count *
2379 if (ru->ru_maxrss < rss)
2380 ru->ru_maxrss = rss;
2386 forward_statclock(int pscnt)
2392 /* Kludge. We don't yet have separate locks for the interrupts
2393 * and the kernel. This means that we cannot let the other processors
2394 * handle complex interrupts while inhibiting them from entering
2395 * the kernel in a non-interrupt context.
2397 * What we can do, without changing the locking mechanisms yet,
2398 * is letting the other processors handle a very simple interrupt
2399 * (wich determines the processor states), and do the main
2403 if (!smp_started || !invltlb_ok || cold || panicstr)
2406 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle ) */
2408 map = other_cpus & ~stopped_cpus ;
2409 checkstate_probed_cpus = 0;
2411 selected_apic_ipi(map,
2412 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2415 while (checkstate_probed_cpus != map) {
2419 #ifdef BETTER_CLOCK_DIAGNOSTIC
2420 printf("forward_statclock: checkstate %x\n",
2421 checkstate_probed_cpus);
2428 * Step 2: walk through other processors processes, update ticks and
2433 for (id = 0; id < mp_ncpus; id++) {
2436 if (((1 << id) & checkstate_probed_cpus) == 0)
2438 forwarded_statclock(id, pscnt, &map);
2441 checkstate_need_ast |= map;
2442 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2444 while ((checkstate_need_ast & map) != 0) {
2448 #ifdef BETTER_CLOCK_DIAGNOSTIC
2449 printf("forward_statclock: dropped ast 0x%x\n",
2450 checkstate_need_ast & map);
2459 forward_hardclock(int pscnt)
2464 struct pstats *pstats;
2467 /* Kludge. We don't yet have separate locks for the interrupts
2468 * and the kernel. This means that we cannot let the other processors
2469 * handle complex interrupts while inhibiting them from entering
2470 * the kernel in a non-interrupt context.
2472 * What we can do, without changing the locking mechanisms yet,
2473 * is letting the other processors handle a very simple interrupt
2474 * (wich determines the processor states), and do the main
2478 if (!smp_started || !invltlb_ok || cold || panicstr)
2481 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle) */
2483 map = other_cpus & ~stopped_cpus ;
2484 checkstate_probed_cpus = 0;
2486 selected_apic_ipi(map,
2487 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2490 while (checkstate_probed_cpus != map) {
2494 #ifdef BETTER_CLOCK_DIAGNOSTIC
2495 printf("forward_hardclock: checkstate %x\n",
2496 checkstate_probed_cpus);
2503 * Step 2: walk through other processors processes, update virtual
2504 * timer and profiling timer. If stathz == 0, also update ticks and
2509 for (id = 0; id < mp_ncpus; id++) {
2512 if (((1 << id) & checkstate_probed_cpus) == 0)
2514 p = checkstate_curproc[id];
2516 pstats = p->p_stats;
2517 if (checkstate_cpustate[id] == CHECKSTATE_USER &&
2518 timevalisset(&pstats->p_timer[ITIMER_VIRTUAL].it_value) &&
2519 itimerdecr(&pstats->p_timer[ITIMER_VIRTUAL], tick) == 0) {
2520 psignal(p, SIGVTALRM);
2523 if (timevalisset(&pstats->p_timer[ITIMER_PROF].it_value) &&
2524 itimerdecr(&pstats->p_timer[ITIMER_PROF], tick) == 0) {
2525 psignal(p, SIGPROF);
2530 forwarded_statclock( id, pscnt, &map);
2534 checkstate_need_ast |= map;
2535 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2537 while ((checkstate_need_ast & map) != 0) {
2541 #ifdef BETTER_CLOCK_DIAGNOSTIC
2542 printf("forward_hardclock: dropped ast 0x%x\n",
2543 checkstate_need_ast & map);
2551 #endif /* BETTER_CLOCK */
2554 forward_signal(struct proc *p)
2560 /* Kludge. We don't yet have separate locks for the interrupts
2561 * and the kernel. This means that we cannot let the other processors
2562 * handle complex interrupts while inhibiting them from entering
2563 * the kernel in a non-interrupt context.
2565 * What we can do, without changing the locking mechanisms yet,
2566 * is letting the other processors handle a very simple interrupt
2567 * (wich determines the processor states), and do the main
2571 if (!smp_started || !invltlb_ok || cold || panicstr)
2573 if (!forward_signal_enabled)
2576 if (p->p_stat != SRUN)
2578 id = (u_char) p->p_oncpu;
2582 checkstate_need_ast |= map;
2583 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2585 while ((checkstate_need_ast & map) != 0) {
2590 printf("forward_signal: dropped ast 0x%x\n",
2591 checkstate_need_ast & map);
2596 if (id == (u_char) p->p_oncpu)
2602 forward_roundrobin(void)
2607 if (!smp_started || !invltlb_ok || cold || panicstr)
2609 if (!forward_roundrobin_enabled)
2611 resched_cpus |= other_cpus;
2612 map = other_cpus & ~stopped_cpus ;
2614 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2616 (void) all_but_self_ipi(XCPUAST_OFFSET);
2619 while ((checkstate_need_ast & map) != 0) {
2624 printf("forward_roundrobin: dropped ast 0x%x\n",
2625 checkstate_need_ast & map);
2633 #ifdef APIC_INTR_REORDER
2635 * Maintain mapping from softintr vector to isr bit in local apic.
2638 set_lapic_isrloc(int intr, int vector)
2640 if (intr < 0 || intr > 32)
2641 panic("set_apic_isrloc: bad intr argument: %d",intr);
2642 if (vector < ICU_OFFSET || vector > 255)
2643 panic("set_apic_isrloc: bad vector argument: %d",vector);
2644 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2);
2645 apic_isrbit_location[intr].bit = (1<<(vector & 31));