2 * Copyright (c) 1990 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
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9 * modification, are permitted provided that the following conditions
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18 * This product includes software developed by the University of
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21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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36 * from: @(#)npx.h 5.3 (Berkeley) 1/18/91
41 * 287/387 NPX Coprocessor Data Structures and Constants
48 /* Environment information of floating point unit */
50 long en_cw; /* control word (16bits) */
51 long en_sw; /* status word (16bits) */
52 long en_tw; /* tag word (16bits) */
53 long en_fip; /* floating point instruction pointer */
54 u_short en_fcs; /* floating code segment selector */
55 u_short en_opcode; /* opcode last executed (11 bits ) */
56 long en_foo; /* floating operand offset */
57 long en_fos; /* floating operand segment selector */
60 /* Contents of each floating point accumulator */
62 #ifdef dontdef /* too unportable */
63 u_long fp_mantlo; /* mantissa low (31:0) */
64 u_long fp_manthi; /* mantissa high (63:32) */
65 int fp_exp:15; /* exponent */
66 int fp_sgn:1; /* mantissa sign */
72 /* Floating point context */
74 struct env87 sv_env; /* floating point control/status */
75 struct fpacc87 sv_ac[8]; /* accumulator contents, 0-7 */
77 u_long sv_ex_sw; /* status word for last exception (was pad) */
78 u_long sv_ex_tw; /* tag word for last exception (was pad) */
79 u_char sv_pad[8 * 2 - 2 * 4]; /* bogus historical padding */
83 /* Cyrix EMC memory - mapped coprocessor context switch information */
85 long em_msw; /* memory mapped status register when swtched */
86 long em_tar; /* memory mapped temp A register when swtched */
87 long em_dl; /* memory mapped D low register when swtched */
90 /* Intel prefers long real (53 bit) precision */
91 #define __iBCS_NPXCW__ 0x262
92 /* wfj prefers temporary real (64 bit) precision */
93 #define __386BSD_NPXCW__ 0x362
95 * bde prefers 53 bit precision and all exceptions masked.
97 * The standard control word from finit is 0x37F, giving:
101 * all exceptions masked.
105 * affine mode for 287's (if they work at all) (1 in bitfield 1<<12)
106 * 53-bit precision (2 in bitfield 3<<8)
107 * overflow exception unmasked (0 in bitfield 1<<3)
108 * zero divide exception unmasked (0 in bitfield 1<<2)
109 * invalid-operand exception unmasked (0 in bitfield 1<<0).
111 * 64-bit precision often gives bad results with high level languages
112 * because it makes the results of calculations depend on whether
113 * intermediate values are stored in memory or in FPU registers.
115 * The "Intel" and wfj control words have:
117 * underflow exception unmasked (0 in bitfield 1<<4)
119 * but that causes an unexpected exception in the test program 'paranoia'
120 * and makes denormals useless (DBL_MIN / 2 underflows). It doesn't make
121 * a lot of sense to trap underflow without trapping denormals.
123 * Later I will want the IEEE default of all exceptions masked. See the
124 * 0.0 math manpage for why this is better. The 0.1 math manpage is empty.
126 #define __BDE_NPXCW__ 0x1272
127 #define __BETTER_BDE_NPXCW__ 0x127f
129 #ifdef __BROKEN_NPXCW__
131 #define __INITIAL_NPXCW__ __386BSD_NPXCW__
133 #define __INITIAL_NPXCW__ __iBCS_NPXCW__
136 #define __INITIAL_NPXCW__ __BDE_NPXCW__