2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2003-2005,2008 Joseph Koshy
5 * Copyright (c) 2007 The FreeBSD Foundation
8 * Portions of this software were developed by A. Joseph Koshy under
9 * sponsorship from the FreeBSD Foundation and Google, Inc.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #ifndef _MACHINE_PMC_MDEP_H
36 #define _MACHINE_PMC_MDEP_H 1
43 * On the i386 platform we support the following PMCs.
45 * TSC The timestamp counter
46 * K7 AMD Athlon XP/MP and other 32 bit processors.
47 * K8 AMD Athlon64 and Opteron PMCs in 32 bit mode.
48 * PIV Intel P4/HTT and P4/EMT64
49 * PPRO Intel Pentium Pro, Pentium-II, Pentium-III, Celeron and
50 * Pentium-M processors
51 * PENTIUM Intel Pentium MMX.
52 * IAP Intel Core/Core2/Atom programmable PMCs.
53 * IAF Intel fixed-function PMCs.
54 * UCP Intel Uncore programmable PMCs.
55 * UCF Intel Uncore fixed-function PMCs.
58 #include <dev/hwpmc/hwpmc_amd.h> /* K7 and K8 */
59 #include <dev/hwpmc/hwpmc_core.h>
60 #include <dev/hwpmc/hwpmc_tsc.h>
61 #include <dev/hwpmc/hwpmc_uncore.h>
64 * Intel processors implementing V2 and later of the Intel performance
65 * measurement architecture have PMCs of the following classes: TSC,
66 * IAF, IAP, UCF and UCP.
68 #define PMC_MDEP_CLASS_INDEX_TSC 1
69 #define PMC_MDEP_CLASS_INDEX_K7 2
70 #define PMC_MDEP_CLASS_INDEX_K8 2
71 #define PMC_MDEP_CLASS_INDEX_IAP 2
72 #define PMC_MDEP_CLASS_INDEX_IAF 3
73 #define PMC_MDEP_CLASS_INDEX_UCP 4
74 #define PMC_MDEP_CLASS_INDEX_UCF 5
77 * Architecture specific extensions to <sys/pmc.h> structures.
80 union pmc_md_op_pmcallocate {
81 struct pmc_md_amd_op_pmcallocate pm_amd;
82 struct pmc_md_iap_op_pmcallocate pm_iap;
83 struct pmc_md_ucf_op_pmcallocate pm_ucf;
84 struct pmc_md_ucp_op_pmcallocate pm_ucp;
89 #define PMCLOG_READADDR PMCLOG_READ32
90 #define PMCLOG_EMITADDR PMCLOG_EMIT32
94 /* MD extension for 'struct pmc' */
96 struct pmc_md_amd_pmc pm_amd;
97 struct pmc_md_iaf_pmc pm_iaf;
98 struct pmc_md_iap_pmc pm_iap;
99 struct pmc_md_ucf_pmc pm_ucf;
100 struct pmc_md_ucp_pmc pm_ucp;
106 #define PMC_TRAPFRAME_TO_PC(TF) ((TF)->tf_eip)
107 #define PMC_TRAPFRAME_TO_FP(TF) ((TF)->tf_ebp)
110 * The layout of the stack frame on entry into the NMI handler depends on
111 * whether a privilege level change (and consequent stack switch) was
112 * required for entry.
114 * When processing an interrupt when in user mode, the processor switches
115 * stacks, and saves the user mode stack pointer on the kernel stack. The
116 * user mode stack pointer is then available to the interrupt handler
119 * When processing an interrupt while in kernel mode, the processor
120 * continues to use the existing (kernel) stack. Therefore we determine
121 * the stack pointer for the interrupted kernel procedure by adding an
122 * offset to the current frame pointer.
125 #define PMC_TRAPFRAME_TO_USER_SP(TF) ((TF)->tf_esp)
126 #define PMC_TRAPFRAME_TO_KERNEL_SP(TF) ((uintptr_t) &((TF)->tf_esp))
128 #define PMC_IN_KERNEL_STACK(S,START,END) \
129 ((S) >= (START) && (S) < (END))
130 #define PMC_IN_KERNEL(va) INKERNEL(va)
132 #define PMC_IN_USERSPACE(va) ((va) <= VM_MAXUSER_ADDRESS)
134 #define PMC_IN_TRAP_HANDLER(PC) \
135 ((PC) >= (uintptr_t)start_exceptions + setidt_disp && \
136 (PC) < (uintptr_t) end_exceptions + setidt_disp)
138 #define PMC_AT_FUNCTION_PROLOGUE_PUSH_BP(I) \
139 (((I) & 0x00ffffff) == 0xe58955) /* pushl %ebp; movl %esp,%ebp */
140 #define PMC_AT_FUNCTION_PROLOGUE_MOV_SP_BP(I) \
141 (((I) & 0x0000ffff) == 0xe589) /* movl %esp,%ebp */
142 #define PMC_AT_FUNCTION_EPILOGUE_RET(I) \
143 (((I) & 0xFF) == 0xC3) /* ret */
145 /* Build a fake kernel trapframe from current instruction pointer. */
146 #define PMC_FAKE_TRAPFRAME(TF) \
148 (TF)->tf_cs = 0; (TF)->tf_eflags = 0; \
149 __asm __volatile("movl %%ebp,%0" : "=r" ((TF)->tf_ebp)); \
150 __asm __volatile("movl %%esp,%0" : "=r" ((TF)->tf_esp)); \
151 __asm __volatile("call 1f \n\t1: pop %0" : "=r"((TF)->tf_eip)); \
158 void start_exceptions(void), end_exceptions(void);
160 struct pmc_mdep *pmc_amd_initialize(void);
161 void pmc_amd_finalize(struct pmc_mdep *_md);
162 struct pmc_mdep *pmc_intel_initialize(void);
163 void pmc_intel_finalize(struct pmc_mdep *_md);
166 #endif /* _MACHINE_PMC_MDEP_H */