2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2003-2005,2008 Joseph Koshy
5 * Copyright (c) 2007 The FreeBSD Foundation
8 * Portions of this software were developed by A. Joseph Koshy under
9 * sponsorship from the FreeBSD Foundation and Google, Inc.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #ifndef _MACHINE_PMC_MDEP_H
36 #define _MACHINE_PMC_MDEP_H 1
43 * On the i386 platform we support the following PMCs.
45 * TSC The timestamp counter
46 * K7 AMD Athlon XP/MP and other 32 bit processors.
47 * K8 AMD Athlon64 and Opteron PMCs in 32 bit mode.
48 * IAP Intel Core/Core2/Atom programmable PMCs.
49 * IAF Intel fixed-function PMCs.
50 * UCP Intel Uncore programmable PMCs.
51 * UCF Intel Uncore fixed-function PMCs.
54 #include <dev/hwpmc/hwpmc_amd.h> /* K7 and K8 */
55 #include <dev/hwpmc/hwpmc_core.h>
56 #include <dev/hwpmc/hwpmc_tsc.h>
57 #include <dev/hwpmc/hwpmc_uncore.h>
60 * Intel processors implementing V2 and later of the Intel performance
61 * measurement architecture have PMCs of the following classes: TSC,
62 * IAF, IAP, UCF and UCP.
64 #define PMC_MDEP_CLASS_INDEX_TSC 1
65 #define PMC_MDEP_CLASS_INDEX_K7 2
66 #define PMC_MDEP_CLASS_INDEX_K8 2
67 #define PMC_MDEP_CLASS_INDEX_IAP 2
68 #define PMC_MDEP_CLASS_INDEX_IAF 3
69 #define PMC_MDEP_CLASS_INDEX_UCP 4
70 #define PMC_MDEP_CLASS_INDEX_UCF 5
73 * Architecture specific extensions to <sys/pmc.h> structures.
76 union pmc_md_op_pmcallocate {
77 struct pmc_md_amd_op_pmcallocate pm_amd;
78 struct pmc_md_iap_op_pmcallocate pm_iap;
79 struct pmc_md_ucf_op_pmcallocate pm_ucf;
80 struct pmc_md_ucp_op_pmcallocate pm_ucp;
85 #define PMCLOG_READADDR PMCLOG_READ32
86 #define PMCLOG_EMITADDR PMCLOG_EMIT32
90 /* MD extension for 'struct pmc' */
92 struct pmc_md_amd_pmc pm_amd;
93 struct pmc_md_iaf_pmc pm_iaf;
94 struct pmc_md_iap_pmc pm_iap;
95 struct pmc_md_ucf_pmc pm_ucf;
96 struct pmc_md_ucp_pmc pm_ucp;
102 #define PMC_TRAPFRAME_TO_PC(TF) ((TF)->tf_eip)
103 #define PMC_TRAPFRAME_TO_FP(TF) ((TF)->tf_ebp)
106 * The layout of the stack frame on entry into the NMI handler depends on
107 * whether a privilege level change (and consequent stack switch) was
108 * required for entry.
110 * When processing an interrupt when in user mode, the processor switches
111 * stacks, and saves the user mode stack pointer on the kernel stack. The
112 * user mode stack pointer is then available to the interrupt handler
115 * When processing an interrupt while in kernel mode, the processor
116 * continues to use the existing (kernel) stack. Therefore we determine
117 * the stack pointer for the interrupted kernel procedure by adding an
118 * offset to the current frame pointer.
121 #define PMC_TRAPFRAME_TO_USER_SP(TF) ((TF)->tf_esp)
122 #define PMC_TRAPFRAME_TO_KERNEL_SP(TF) ((uintptr_t) &((TF)->tf_esp))
124 #define PMC_IN_KERNEL_STACK(va) kstack_contains(curthread, (va), sizeof(va))
125 #define PMC_IN_KERNEL(va) INKERNEL(va)
126 #define PMC_IN_USERSPACE(va) ((va) <= VM_MAXUSER_ADDRESS)
128 #define PMC_IN_TRAP_HANDLER(PC) \
129 ((PC) >= (uintptr_t)start_exceptions + setidt_disp && \
130 (PC) < (uintptr_t) end_exceptions + setidt_disp)
132 #define PMC_AT_FUNCTION_PROLOGUE_PUSH_BP(I) \
133 (((I) & 0x00ffffff) == 0xe58955) /* pushl %ebp; movl %esp,%ebp */
134 #define PMC_AT_FUNCTION_PROLOGUE_MOV_SP_BP(I) \
135 (((I) & 0x0000ffff) == 0xe589) /* movl %esp,%ebp */
136 #define PMC_AT_FUNCTION_EPILOGUE_RET(I) \
137 (((I) & 0xFF) == 0xC3) /* ret */
139 /* Build a fake kernel trapframe from current instruction pointer. */
140 #define PMC_FAKE_TRAPFRAME(TF) \
142 (TF)->tf_cs = 0; (TF)->tf_eflags = 0; \
143 __asm __volatile("movl %%ebp,%0" : "=r" ((TF)->tf_ebp)); \
144 __asm __volatile("movl %%esp,%0" : "=r" ((TF)->tf_esp)); \
145 __asm __volatile("call 1f \n\t1: pop %0" : "=r"((TF)->tf_eip)); \
152 void start_exceptions(void), end_exceptions(void);
154 struct pmc_mdep *pmc_amd_initialize(void);
155 void pmc_amd_finalize(struct pmc_mdep *_md);
156 struct pmc_mdep *pmc_intel_initialize(void);
157 void pmc_intel_finalize(struct pmc_mdep *_md);
160 #endif /* _MACHINE_PMC_MDEP_H */