2 * from: vector.s, 386BSD 0.1 unknown origin
7 #include <machine/apic.h>
8 #include <machine/smp.h>
10 #include "i386/isa/intr_machdep.h"
13 #ifdef FAST_SIMPLELOCK
15 #define GET_FAST_INTR_LOCK \
16 pushl $_fast_intr_lock ; /* address of lock */ \
17 call _s_lock ; /* MP-safe */ \
20 #define REL_FAST_INTR_LOCK \
21 movl $0, _fast_intr_lock
23 #else /* FAST_SIMPLELOCK */
25 #define GET_FAST_INTR_LOCK \
28 #define REL_FAST_INTR_LOCK \
29 pushl $_mp_lock ; /* GIANT_LOCK */ \
33 #endif /* FAST_SIMPLELOCK */
35 /* convert an absolute IRQ# into a bitmask */
36 #define IRQ_BIT(irq_num) (1 << (irq_num))
38 /* make an index into the IO APIC from the IRQ# */
39 #define REDTBL_IDX(irq_num) (0x10 + ((irq_num) * 2))
43 * Macros for interrupt interrupt entry, call to handler, and exit.
46 #ifdef FAST_WITHOUTCPL
50 #define FAST_INTR(irq_num, vec_name) \
54 pushl %eax ; /* save only call-used registers */ \
65 FAKE_MCOUNT((5+ACTUALLY_PUSHED)*4(%esp)) ; \
66 pushl _intr_unit + (irq_num) * 4 ; \
67 GET_FAST_INTR_LOCK ; \
68 call *_intr_handler + (irq_num) * 4 ; /* do the work ASAP */ \
69 REL_FAST_INTR_LOCK ; \
71 movl $0, lapic_eoi ; \
73 incl _cnt+V_INTR ; /* book-keeping can wait */ \
74 movl _intr_countp + (irq_num) * 4, %eax ; \
86 #else /* FAST_WITHOUTCPL */
88 #define FAST_INTR(irq_num, vec_name) \
92 pushl %eax ; /* save only call-used registers */ \
101 movl $KPSEL, %eax ; \
103 FAKE_MCOUNT((5+ACTUALLY_PUSHED)*4(%esp)) ; \
104 GET_FAST_INTR_LOCK ; \
105 pushl _intr_unit + (irq_num) * 4 ; \
106 call *_intr_handler + (irq_num) * 4 ; /* do the work ASAP */ \
108 movl $0, lapic_eoi ; \
110 incl _cnt+V_INTR ; /* book-keeping can wait */ \
111 movl _intr_countp + (irq_num) * 4,%eax ; \
114 movl _cpl, %eax ; /* unmasking pending HWIs or SWIs? */ \
116 andl _ipending, %eax ; \
117 jne 2f ; /* yes, maybe handle them */ \
120 REL_FAST_INTR_LOCK ; \
131 cmpb $3, _intr_nesting_level ; /* enough stack? */ \
132 jae 1b ; /* no, return */ \
134 /* XXX next line is probably unnecessary now. */ \
135 movl $HWI_MASK|SWI_MASK, _cpl ; /* limit nesting ... */ \
137 incb _intr_nesting_level ; /* ... really limit it ... */ \
138 sti ; /* to do this as early as possible */ \
139 popl %fs ; /* discard most of thin frame ... */ \
140 MAYBE_POPL_ES ; /* discard most of thin frame ... */ \
141 popl %ecx ; /* ... original %ds ... */ \
143 xchgl %eax, 4(%esp) ; /* orig %eax; save cpl */ \
144 pushal ; /* build fat frame (grrr) ... */ \
145 pushl %ecx ; /* ... actually %ds ... */ \
148 movl $KDSEL, %eax ; \
152 movl (3+8+0)*4(%esp), %ecx ; /* %ecx from thin frame ... */ \
153 movl %ecx, (3+6)*4(%esp) ; /* ... to fat frame ... */ \
154 movl (3+8+1)*4(%esp), %eax ; /* ... cpl from thin frame */ \
156 subl $4, %esp ; /* junk for unit number */ \
160 #endif /** FAST_WITHOUTCPL */
167 pushl $0 ; /* dummy error code */ \
168 pushl $0 ; /* dummy trap type */ \
170 pushl %ds ; /* save data and extra segments ... */ \
181 #define IOAPICADDR(irq_num) CNAME(int_to_apicintpin) + 16 * (irq_num) + 8
182 #define REDIRIDX(irq_num) CNAME(int_to_apicintpin) + 16 * (irq_num) + 12
184 #define MASK_IRQ(irq_num) \
185 IMASK_LOCK ; /* into critical reg */ \
186 testl $IRQ_BIT(irq_num), _apic_imen ; \
187 jne 7f ; /* masked, don't mask */ \
188 orl $IRQ_BIT(irq_num), _apic_imen ; /* set the mask bit */ \
189 movl IOAPICADDR(irq_num), %ecx ; /* ioapic addr */ \
190 movl REDIRIDX(irq_num), %eax ; /* get the index */ \
191 movl %eax, (%ecx) ; /* write the index */ \
192 movl IOAPIC_WINDOW(%ecx), %eax ; /* current value */ \
193 orl $IOART_INTMASK, %eax ; /* set the mask */ \
194 movl %eax, IOAPIC_WINDOW(%ecx) ; /* new value */ \
195 7: ; /* already masked */ \
198 * Test to see whether we are handling an edge or level triggered INT.
199 * Level-triggered INTs must still be masked as we don't clear the source,
200 * and the EOI cycle would cause redundant INTs to occur.
202 #define MASK_LEVEL_IRQ(irq_num) \
203 testl $IRQ_BIT(irq_num), _apic_pin_trigger ; \
204 jz 9f ; /* edge, don't mask */ \
205 MASK_IRQ(irq_num) ; \
209 #ifdef APIC_INTR_REORDER
210 #define EOI_IRQ(irq_num) \
211 movl _apic_isrbit_location + 8 * (irq_num), %eax ; \
212 movl (%eax), %eax ; \
213 testl _apic_isrbit_location + 4 + 8 * (irq_num), %eax ; \
214 jz 9f ; /* not active */ \
215 movl $0, lapic_eoi ; \
216 APIC_ITRACE(apic_itrace_eoi, irq_num, APIC_ITRACE_EOI) ; \
220 #define EOI_IRQ(irq_num) \
221 testl $IRQ_BIT(irq_num), lapic_isr1; \
222 jz 9f ; /* not active */ \
223 movl $0, lapic_eoi; \
224 APIC_ITRACE(apic_itrace_eoi, irq_num, APIC_ITRACE_EOI) ; \
230 * Test to see if the source is currntly masked, clear if so.
232 #define UNMASK_IRQ(irq_num) \
233 IMASK_LOCK ; /* into critical reg */ \
234 testl $IRQ_BIT(irq_num), _apic_imen ; \
235 je 7f ; /* bit clear, not masked */ \
236 andl $~IRQ_BIT(irq_num), _apic_imen ;/* clear mask bit */ \
237 movl IOAPICADDR(irq_num),%ecx ; /* ioapic addr */ \
238 movl REDIRIDX(irq_num), %eax ; /* get the index */ \
239 movl %eax,(%ecx) ; /* write the index */ \
240 movl IOAPIC_WINDOW(%ecx),%eax ; /* current value */ \
241 andl $~IOART_INTMASK,%eax ; /* clear the mask */ \
242 movl %eax,IOAPIC_WINDOW(%ecx) ; /* new value */ \
246 #ifdef INTR_SIMPLELOCK
249 #define LATELOCK call _get_isrlock
252 ISR_TRYLOCK ; /* XXX this is going away... */ \
253 testl %eax, %eax ; /* did we get it? */ \
255 #define DELOCK ISR_RELLOCK
259 #ifdef APIC_INTR_DIAGNOSTIC
260 #ifdef APIC_INTR_DIAGNOSTIC_IRQ
264 pushl $CNAME(apic_itrace_debuglock)
265 call CNAME(s_lock_np)
267 movl CNAME(apic_itrace_debugbuffer_idx), %ecx
272 movw %ax, CNAME(apic_itrace_debugbuffer)(,%ecx,2)
275 movl %ecx, CNAME(apic_itrace_debugbuffer_idx)
276 pushl $CNAME(apic_itrace_debuglock)
277 call CNAME(s_unlock_np)
283 #define APIC_ITRACE(name, irq_num, id) \
284 lock ; /* MP-safe */ \
285 incl CNAME(name) + (irq_num) * 4 ; \
289 movl $(irq_num), %eax ; \
290 cmpl $APIC_INTR_DIAGNOSTIC_IRQ, %eax ; \
293 call log_intr_event ; \
300 #define APIC_ITRACE(name, irq_num, id) \
301 lock ; /* MP-safe */ \
302 incl CNAME(name) + (irq_num) * 4
305 #define APIC_ITRACE_ENTER 1
306 #define APIC_ITRACE_EOI 2
307 #define APIC_ITRACE_TRYISRLOCK 3
308 #define APIC_ITRACE_GOTISRLOCK 4
309 #define APIC_ITRACE_ENTER2 5
310 #define APIC_ITRACE_LEAVE 6
311 #define APIC_ITRACE_UNMASK 7
312 #define APIC_ITRACE_ACTIVE 8
313 #define APIC_ITRACE_MASKED 9
314 #define APIC_ITRACE_NOISRLOCK 10
315 #define APIC_ITRACE_MASKED2 11
316 #define APIC_ITRACE_SPLZ 12
317 #define APIC_ITRACE_DORETI 13
320 #define APIC_ITRACE(name, irq_num, id)
325 #define INTR(irq_num, vec_name, maybe_extra_ipending) \
328 /* _XintrNN: entry point used by IDT/HWIs & splz_unpend via _vec[]. */ \
331 movl $KDSEL, %eax ; /* reload with kernel's data segment */ \
334 movl $KPSEL, %eax ; \
337 maybe_extra_ipending ; \
339 APIC_ITRACE(apic_itrace_enter, irq_num, APIC_ITRACE_ENTER) ; \
340 lock ; /* MP-safe */ \
341 btsl $(irq_num), iactive ; /* lazy masking */ \
342 jc 1f ; /* already active */ \
344 MASK_LEVEL_IRQ(irq_num) ; \
347 APIC_ITRACE(apic_itrace_tryisrlock, irq_num, APIC_ITRACE_TRYISRLOCK) ;\
350 APIC_ITRACE(apic_itrace_gotisrlock, irq_num, APIC_ITRACE_GOTISRLOCK) ;\
351 AVCPL_LOCK ; /* MP-safe */ \
352 testl $IRQ_BIT(irq_num), _cpl ; \
353 jne 2f ; /* this INT masked */ \
354 testl $IRQ_BIT(irq_num), _cml ; \
355 jne 2f ; /* this INT masked */ \
356 orl $IRQ_BIT(irq_num), _cil ; \
359 incb _intr_nesting_level ; \
361 /* entry point used by doreti_unpend for HWIs. */ \
362 __CONCAT(Xresume,irq_num): ; \
363 FAKE_MCOUNT(13*4(%esp)) ; /* XXX avoid dbl cnt */ \
364 lock ; incl _cnt+V_INTR ; /* tally interrupts */ \
365 movl _intr_countp + (irq_num) * 4, %eax ; \
366 lock ; incl (%eax) ; \
368 AVCPL_LOCK ; /* MP-safe */ \
371 orl _intr_mask + (irq_num) * 4, %eax ; \
375 pushl _intr_unit + (irq_num) * 4 ; \
376 incl _inside_intr ; \
377 APIC_ITRACE(apic_itrace_enter2, irq_num, APIC_ITRACE_ENTER2) ; \
379 call *_intr_handler + (irq_num) * 4 ; \
381 APIC_ITRACE(apic_itrace_leave, irq_num, APIC_ITRACE_LEAVE) ; \
382 decl _inside_intr ; \
384 lock ; andl $~IRQ_BIT(irq_num), iactive ; \
385 lock ; andl $~IRQ_BIT(irq_num), _cil ; \
386 UNMASK_IRQ(irq_num) ; \
387 APIC_ITRACE(apic_itrace_unmask, irq_num, APIC_ITRACE_UNMASK) ; \
388 sti ; /* doreti repeats cli/sti */ \
395 APIC_ITRACE(apic_itrace_active, irq_num, APIC_ITRACE_ACTIVE) ; \
396 MASK_IRQ(irq_num) ; \
398 AVCPL_LOCK ; /* MP-safe */ \
400 orl $IRQ_BIT(irq_num), _ipending ; \
403 btsl $(irq_num), iactive ; /* still active */ \
404 jnc 0b ; /* retry */ \
409 2: ; /* masked by cpl|cml */ \
410 APIC_ITRACE(apic_itrace_masked, irq_num, APIC_ITRACE_MASKED) ; \
412 orl $IRQ_BIT(irq_num), _ipending ; \
414 DELOCK ; /* XXX this is going away... */ \
418 3: ; /* other cpu has isr lock */ \
419 APIC_ITRACE(apic_itrace_noisrlock, irq_num, APIC_ITRACE_NOISRLOCK) ;\
420 AVCPL_LOCK ; /* MP-safe */ \
422 orl $IRQ_BIT(irq_num), _ipending ; \
423 testl $IRQ_BIT(irq_num), _cpl ; \
424 jne 4f ; /* this INT masked */ \
425 testl $IRQ_BIT(irq_num), _cml ; \
426 jne 4f ; /* this INT masked */ \
427 orl $IRQ_BIT(irq_num), _cil ; \
429 call forward_irq ; /* forward irq to lock holder */ \
430 POP_FRAME ; /* and return */ \
434 APIC_ITRACE(apic_itrace_masked2, irq_num, APIC_ITRACE_MASKED2) ;\
436 POP_FRAME ; /* and return */ \
439 #else /* CPL_AND_CML */
442 #define INTR(irq_num, vec_name, maybe_extra_ipending) \
445 /* _XintrNN: entry point used by IDT/HWIs & splz_unpend via _vec[]. */ \
448 movl $KDSEL, %eax ; /* reload with kernel's data segment */ \
451 movl $KPSEL, %eax ; \
454 maybe_extra_ipending ; \
456 APIC_ITRACE(apic_itrace_enter, irq_num, APIC_ITRACE_ENTER) ; \
457 lock ; /* MP-safe */ \
458 btsl $(irq_num), iactive ; /* lazy masking */ \
459 jc 1f ; /* already active */ \
461 MASK_LEVEL_IRQ(irq_num) ; \
464 APIC_ITRACE(apic_itrace_tryisrlock, irq_num, APIC_ITRACE_TRYISRLOCK) ;\
465 ISR_TRYLOCK ; /* XXX this is going away... */ \
466 testl %eax, %eax ; /* did we get it? */ \
469 APIC_ITRACE(apic_itrace_gotisrlock, irq_num, APIC_ITRACE_GOTISRLOCK) ;\
470 AVCPL_LOCK ; /* MP-safe */ \
471 testl $IRQ_BIT(irq_num), _cpl ; \
472 jne 2f ; /* this INT masked */ \
475 incb _intr_nesting_level ; \
477 /* entry point used by doreti_unpend for HWIs. */ \
478 __CONCAT(Xresume,irq_num): ; \
479 FAKE_MCOUNT(13*4(%esp)) ; /* XXX avoid dbl cnt */ \
480 lock ; incl _cnt+V_INTR ; /* tally interrupts */ \
481 movl _intr_countp + (irq_num) * 4, %eax ; \
482 lock ; incl (%eax) ; \
484 AVCPL_LOCK ; /* MP-safe */ \
487 orl _intr_mask + (irq_num) * 4, %eax ; \
490 andl $~IRQ_BIT(irq_num), _ipending ; \
493 pushl _intr_unit + (irq_num) * 4 ; \
494 APIC_ITRACE(apic_itrace_enter2, irq_num, APIC_ITRACE_ENTER2) ; \
496 call *_intr_handler + (irq_num) * 4 ; \
498 APIC_ITRACE(apic_itrace_leave, irq_num, APIC_ITRACE_LEAVE) ; \
500 lock ; andl $~IRQ_BIT(irq_num), iactive ; \
501 UNMASK_IRQ(irq_num) ; \
502 APIC_ITRACE(apic_itrace_unmask, irq_num, APIC_ITRACE_UNMASK) ; \
503 sti ; /* doreti repeats cli/sti */ \
509 APIC_ITRACE(apic_itrace_active, irq_num, APIC_ITRACE_ACTIVE) ; \
510 MASK_IRQ(irq_num) ; \
512 AVCPL_LOCK ; /* MP-safe */ \
514 orl $IRQ_BIT(irq_num), _ipending ; \
517 btsl $(irq_num), iactive ; /* still active */ \
518 jnc 0b ; /* retry */ \
520 iret ; /* XXX: iactive bit might be 0 now */ \
522 2: ; /* masked by cpl, leave iactive set */ \
523 APIC_ITRACE(apic_itrace_masked, irq_num, APIC_ITRACE_MASKED) ; \
525 orl $IRQ_BIT(irq_num), _ipending ; \
527 ISR_RELLOCK ; /* XXX this is going away... */ \
531 3: ; /* other cpu has isr lock */ \
532 APIC_ITRACE(apic_itrace_noisrlock, irq_num, APIC_ITRACE_NOISRLOCK) ;\
533 AVCPL_LOCK ; /* MP-safe */ \
535 orl $IRQ_BIT(irq_num), _ipending ; \
536 testl $IRQ_BIT(irq_num), _cpl ; \
537 jne 4f ; /* this INT masked */ \
539 call forward_irq ; /* forward irq to lock holder */ \
540 POP_FRAME ; /* and return */ \
544 APIC_ITRACE(apic_itrace_masked2, irq_num, APIC_ITRACE_MASKED2) ;\
546 POP_FRAME ; /* and return */ \
549 #endif /* CPL_AND_CML */
553 * Handle "spurious INTerrupts".
555 * This is different than the "spurious INTerrupt" generated by an
556 * 8259 PIC for missing INTs. See the APIC documentation for details.
557 * This routine should NOT do an 'EOI' cycle.
564 /* No EOI cycle used here */
570 * Handle TLB shootdowns.
578 #ifdef COUNT_XINVLTLB_HITS
586 #endif /* COUNT_XINVLTLB_HITS */
588 movl %cr3, %eax /* invalidate the TLB */
591 ss /* stack segment, avoid %ds load */
592 movl $0, lapic_eoi /* End Of Interrupt to APIC */
601 * Executed by a CPU when it receives an Xcpucheckstate IPI from another CPU,
603 * - Stores current cpu state in checkstate_cpustate[cpuid]
604 * 0 == user, 1 == sys, 2 == intr
605 * - Stores current process in checkstate_curproc[cpuid]
607 * - Signals its receipt by setting bit cpuid in checkstate_probed_cpus.
609 * stack: 0->ds, 4->fs, 8->ebx, 12->eax, 16->eip, 20->cs, 24->eflags
614 .globl _Xcpucheckstate
615 .globl _checkstate_cpustate
616 .globl _checkstate_curproc
617 .globl _checkstate_pc
621 pushl %ds /* save current data segment */
625 movl %ax, %ds /* use KERNEL data segment */
629 movl $0, lapic_eoi /* End Of Interrupt to APIC */
636 testl $PSL_VM, 24(%esp)
638 incl %ebx /* system or interrupt */
640 cmpl $0, _inside_intr
642 incl %ebx /* interrupt */
646 movl %ebx, _checkstate_cpustate(,%eax,4)
648 movl %ebx, _checkstate_curproc(,%eax,4)
650 movl %ebx, _checkstate_pc(,%eax,4)
652 lock /* checkstate_probed_cpus |= (1<<id) */
653 btsl %eax, _checkstate_probed_cpus
656 popl %ds /* restore previous data segment */
661 #endif /* BETTER_CLOCK */
664 * Executed by a CPU when it receives an Xcpuast IPI from another CPU,
666 * - Signals its receipt by clearing bit cpuid in checkstate_need_ast.
668 * - We need a better method of triggering asts on other cpus.
677 movl %ax, %ds /* use KERNEL data segment */
683 lock /* checkstate_need_ast &= ~(1<<id) */
684 btrl %eax, _checkstate_need_ast
685 movl $0, lapic_eoi /* End Of Interrupt to APIC */
688 btsl %eax, _checkstate_pending_ast
691 FAKE_MCOUNT(13*4(%esp))
694 * Giant locks do not come cheap.
695 * A lot of cycles are going to be wasted here.
706 movl $1, _astpending /* XXX */
709 incb _intr_nesting_level
716 btrl %eax, _checkstate_pending_ast
718 btrl %eax, CNAME(resched_cpus)
720 movl $1, CNAME(want_resched)
722 incl CNAME(want_resched_cnt)
725 incl CNAME(cpuast_cnt)
729 /* We are already in the process of delivering an ast for this CPU */
735 * Executed by a CPU when it receives an XFORWARD_IRQ IPI.
744 movl %ax, %ds /* use KERNEL data segment */
749 movl $0, lapic_eoi /* End Of Interrupt to APIC */
751 FAKE_MCOUNT(13*4(%esp))
754 testl %eax,%eax /* Did we get the lock ? */
758 incl CNAME(forward_irq_hitcnt)
759 cmpb $4, _intr_nesting_level
771 incb _intr_nesting_level
777 jmp _doreti /* Handle forwarded interrupt */
780 incl CNAME(forward_irq_misscnt)
781 call forward_irq /* Oops, we've lost the isr lock */
787 incl CNAME(forward_irq_toodeepcnt)
802 cmpl $0, CNAME(forward_irq_enabled)
808 movl $0, %eax /* Pick CPU #0 if noone has lock */
811 movl _cpu_num_to_apic_id(,%eax,4),%ecx
813 movl lapic_icr_hi, %eax
814 andl $~APIC_ID_MASK, %eax
816 movl %eax, lapic_icr_hi
819 movl lapic_icr_lo, %eax
820 andl $APIC_DELSTAT_MASK,%eax
822 movl lapic_icr_lo, %eax
823 andl $APIC_RESV2_MASK, %eax
824 orl $(APIC_DEST_DESTFLD|APIC_DELMODE_FIXED|XFORWARD_IRQ_OFFSET), %eax
825 movl %eax, lapic_icr_lo
827 movl lapic_icr_lo, %eax
828 andl $APIC_DELSTAT_MASK,%eax
834 * Executed by a CPU when it receives an Xcpustop IPI from another CPU,
836 * - Signals its receipt.
837 * - Waits for permission to restart.
838 * - Signals its restart.
850 pushl %ds /* save current data segment */
854 movl %ax, %ds /* use KERNEL data segment */
858 movl $0, lapic_eoi /* End Of Interrupt to APIC */
861 imull $PCB_SIZE, %eax
862 leal CNAME(stoppcbs)(%eax), %eax
864 call CNAME(savectx) /* Save process context */
871 btsl %eax, _stopped_cpus /* stopped_cpus |= (1<<id) */
873 btl %eax, _started_cpus /* while (!(started_cpus & (1<<id))) */
877 btrl %eax, _started_cpus /* started_cpus &= ~(1<<id) */
879 btrl %eax, _stopped_cpus /* stopped_cpus &= ~(1<<id) */
884 movl CNAME(cpustop_restartfunc), %eax
887 movl $0, CNAME(cpustop_restartfunc) /* One-shot */
892 popl %ds /* restore previous data segment */
902 FAST_INTR(0,fastintr0)
903 FAST_INTR(1,fastintr1)
904 FAST_INTR(2,fastintr2)
905 FAST_INTR(3,fastintr3)
906 FAST_INTR(4,fastintr4)
907 FAST_INTR(5,fastintr5)
908 FAST_INTR(6,fastintr6)
909 FAST_INTR(7,fastintr7)
910 FAST_INTR(8,fastintr8)
911 FAST_INTR(9,fastintr9)
912 FAST_INTR(10,fastintr10)
913 FAST_INTR(11,fastintr11)
914 FAST_INTR(12,fastintr12)
915 FAST_INTR(13,fastintr13)
916 FAST_INTR(14,fastintr14)
917 FAST_INTR(15,fastintr15)
918 FAST_INTR(16,fastintr16)
919 FAST_INTR(17,fastintr17)
920 FAST_INTR(18,fastintr18)
921 FAST_INTR(19,fastintr19)
922 FAST_INTR(20,fastintr20)
923 FAST_INTR(21,fastintr21)
924 FAST_INTR(22,fastintr22)
925 FAST_INTR(23,fastintr23)
926 #define CLKINTR_PENDING movl $1,CNAME(clkintr_pending)
927 INTR(0,intr0, CLKINTR_PENDING)
954 * Executed by a CPU when it receives a RENDEZVOUS IPI from another CPU.
956 * - Calls the generic rendezvous action function.
964 movl %ax, %ds /* use KERNEL data segment */
969 call _smp_rendezvous_action
971 movl $0, lapic_eoi /* End Of Interrupt to APIC */
978 * Addresses of interrupt handlers.
979 * XresumeNN: Resumption addresses for HWIs.
985 * ipl.s: doreti_unpend
987 .long Xresume0, Xresume1, Xresume2, Xresume3
988 .long Xresume4, Xresume5, Xresume6, Xresume7
989 .long Xresume8, Xresume9, Xresume10, Xresume11
990 .long Xresume12, Xresume13, Xresume14, Xresume15
991 .long Xresume16, Xresume17, Xresume18, Xresume19
992 .long Xresume20, Xresume21, Xresume22, Xresume23
995 * ipl.s: doreti_unpend
996 * apic_ipl.s: splz_unpend
998 .long _swi_null, swi_net, _swi_null, _swi_null
999 .long _swi_vm, _swi_null, _softclock, _swi_null
1001 imasks: /* masks for interrupt handlers */
1002 .space NHWI*4 /* padding; HWI masks are elsewhere */
1004 .long SWI_TTY_MASK, SWI_NET_MASK, SWI_CAMNET_MASK, SWI_CAMBIO_MASK
1005 .long SWI_VM_MASK, 0, SWI_CLOCK_MASK, 0
1007 /* active flag for lazy masking */
1011 #ifdef COUNT_XINVLTLB_HITS
1014 .space (NCPU * 4), 0
1015 #endif /* COUNT_XINVLTLB_HITS */
1017 /* variables used by stop_cpus()/restart_cpus()/Xcpustop */
1018 .globl _stopped_cpus, _started_cpus
1025 .globl _checkstate_probed_cpus
1026 _checkstate_probed_cpus:
1028 #endif /* BETTER_CLOCK */
1029 .globl _checkstate_need_ast
1030 _checkstate_need_ast:
1032 _checkstate_pending_ast:
1034 .globl CNAME(forward_irq_misscnt)
1035 .globl CNAME(forward_irq_toodeepcnt)
1036 .globl CNAME(forward_irq_hitcnt)
1037 .globl CNAME(resched_cpus)
1038 .globl CNAME(want_resched_cnt)
1039 .globl CNAME(cpuast_cnt)
1040 .globl CNAME(cpustop_restartfunc)
1041 CNAME(forward_irq_misscnt):
1043 CNAME(forward_irq_hitcnt):
1045 CNAME(forward_irq_toodeepcnt):
1047 CNAME(resched_cpus):
1049 CNAME(want_resched_cnt):
1053 CNAME(cpustop_restartfunc):
1058 .globl _apic_pin_trigger