2 * from: vector.s, 386BSD 0.1 unknown origin
7 * modified for PC98 by Kakefuda
11 #define ICU_IMR_OFFSET 2 /* IO_ICU{1,2} + 2 */
13 #define ICU_IMR_OFFSET 1 /* IO_ICU{1,2} + 1 */
16 #define ICU_EOI 0x20 /* XXX - define elsewhere */
18 #define IRQ_BIT(irq_num) (1 << ((irq_num) % 8))
19 #define IRQ_BYTE(irq_num) ((irq_num) >> 3)
22 #define ENABLE_ICU1 /* use auto-EOI to reduce i/o */
26 movb $ICU_EOI,%al ; /* as soon as possible send EOI ... */ \
27 OUTB_ICU1 /* ... to clear in service bit */
34 * The data sheet says no auto-EOI on slave, but it sometimes works.
36 #define ENABLE_ICU1_AND_2 ENABLE_ICU1
38 #define ENABLE_ICU1_AND_2 \
39 movb $ICU_EOI,%al ; /* as above */ \
40 outb %al,$IO_ICU2 ; /* but do second icu first ... */ \
41 OUTB_ICU1 /* ... then first icu (if !AUTO_EOI_1) */
45 * Macros for interrupt interrupt entry, call to handler, and exit.
48 #define FAST_INTR(irq_num, vec_name, enable_icus) \
52 pushl $0 ; /* dummy error code */ \
53 pushl $0 ; /* dummy trap type */ \
63 FAKE_MCOUNT((12+ACTUALLY_PUSHED)*4(%esp)) ; \
64 movl PCPU(CURPROC),%ebx ; \
65 incl P_INTR_NESTING_LEVEL(%ebx) ; \
66 pushl intr_unit + (irq_num) * 4 ; \
67 call *intr_handler + (irq_num) * 4 ; /* do the work ASAP */ \
68 enable_icus ; /* (re)enable ASAP (helps edge trigger?) */ \
70 incl cnt+V_INTR ; /* book-keeping can wait */ \
71 movl intr_countp + (irq_num) * 4,%eax ; \
73 decl P_INTR_NESTING_LEVEL(%ebx) ; \
78 * Slow, threaded interrupts.
80 * XXX Most of the parameters here are obsolete. Fix this when we're
82 * XXX we really shouldn't return via doreti if we just schedule the
83 * interrupt handler and don't run anything. We could just do an
86 #define INTR(irq_num, vec_name, icu, enable_icus, reg, maybe_extra_ipending) \
90 pushl $0 ; /* dummy error code */ \
91 pushl $0 ; /* dummy trap type */ \
93 pushl %ds ; /* save our data and extra segments ... */ \
96 mov $KDSEL,%ax ; /* load kernel ds, es and fs */ \
101 maybe_extra_ipending ; \
102 movb imen + IRQ_BYTE(irq_num),%al ; \
103 orb $IRQ_BIT(irq_num),%al ; \
104 movb %al,imen + IRQ_BYTE(irq_num) ; \
105 outb %al,$icu+ICU_IMR_OFFSET ; \
107 movl PCPU(CURPROC),%ebx ; \
108 incl P_INTR_NESTING_LEVEL(%ebx) ; \
109 __CONCAT(Xresume,irq_num): ; \
110 FAKE_MCOUNT(13*4(%esp)) ; /* XXX late to avoid double count */ \
111 pushl $irq_num; /* pass the IRQ */ \
113 addl $4, %esp ; /* discard the parameter */ \
114 decl P_INTR_NESTING_LEVEL(%ebx) ; \
116 /* We could usually avoid the following jmp by inlining some of */ \
117 /* doreti, but it's probably better to use less cache. */ \
118 jmp doreti /* and catch up inside doreti */
121 FAST_INTR(0,fastintr0, ENABLE_ICU1)
122 FAST_INTR(1,fastintr1, ENABLE_ICU1)
123 FAST_INTR(2,fastintr2, ENABLE_ICU1)
124 FAST_INTR(3,fastintr3, ENABLE_ICU1)
125 FAST_INTR(4,fastintr4, ENABLE_ICU1)
126 FAST_INTR(5,fastintr5, ENABLE_ICU1)
127 FAST_INTR(6,fastintr6, ENABLE_ICU1)
128 FAST_INTR(7,fastintr7, ENABLE_ICU1)
129 FAST_INTR(8,fastintr8, ENABLE_ICU1_AND_2)
130 FAST_INTR(9,fastintr9, ENABLE_ICU1_AND_2)
131 FAST_INTR(10,fastintr10, ENABLE_ICU1_AND_2)
132 FAST_INTR(11,fastintr11, ENABLE_ICU1_AND_2)
133 FAST_INTR(12,fastintr12, ENABLE_ICU1_AND_2)
134 FAST_INTR(13,fastintr13, ENABLE_ICU1_AND_2)
135 FAST_INTR(14,fastintr14, ENABLE_ICU1_AND_2)
136 FAST_INTR(15,fastintr15, ENABLE_ICU1_AND_2)
138 #define CLKINTR_PENDING movl $1,CNAME(clkintr_pending)
139 /* Threaded interrupts */
140 INTR(0,intr0, IO_ICU1, ENABLE_ICU1, al, CLKINTR_PENDING)
141 INTR(1,intr1, IO_ICU1, ENABLE_ICU1, al,)
142 INTR(2,intr2, IO_ICU1, ENABLE_ICU1, al,)
143 INTR(3,intr3, IO_ICU1, ENABLE_ICU1, al,)
144 INTR(4,intr4, IO_ICU1, ENABLE_ICU1, al,)
145 INTR(5,intr5, IO_ICU1, ENABLE_ICU1, al,)
146 INTR(6,intr6, IO_ICU1, ENABLE_ICU1, al,)
147 INTR(7,intr7, IO_ICU1, ENABLE_ICU1, al,)
148 INTR(8,intr8, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
149 INTR(9,intr9, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
150 INTR(10,intr10, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
151 INTR(11,intr11, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
152 INTR(12,intr12, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
153 INTR(13,intr13, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
154 INTR(14,intr14, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
155 INTR(15,intr15, IO_ICU2, ENABLE_ICU1_AND_2, ah,)