2 * Copyright (c) 1990 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
41 * Routines to handle clock hardware.
45 * inittodr, settodr and support routines written
46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
51 #include "opt_clock.h"
55 #include <sys/param.h>
56 #include <sys/systm.h>
59 #include <sys/mutex.h>
62 #include <sys/timetc.h>
63 #include <sys/kernel.h>
67 #include <sys/sysctl.h>
70 #include <machine/clock.h>
71 #ifdef CLK_CALIBRATION_LOOP
73 #include <machine/cputypes.h>
74 #include <machine/frame.h>
75 #include <machine/limits.h>
76 #include <machine/md_var.h>
77 #include <machine/psl.h>
79 #include <machine/segments.h>
81 #if defined(SMP) || defined(APIC_IO)
82 #include <machine/smp.h>
83 #endif /* SMP || APIC_IO */
84 #include <machine/specialreg.h>
86 #include <i386/isa/icu.h>
87 #include <i386/isa/isa.h>
89 #include <isa/isavar.h>
90 #include <i386/isa/timerreg.h>
92 #include <i386/isa/intr_machdep.h>
95 #include <i386/isa/mca_machdep.h>
99 #include <i386/isa/intr_machdep.h>
100 /* The interrupt triggered by the 8254 (timer) chip */
102 static u_long read_intr_count __P((int vec));
103 static void setup_8254_mixed_mode __P((void));
107 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
108 * can use a simple formula for leap years.
110 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
111 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
113 #define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x))
116 * Time in timer cycles that it takes for microtime() to disable interrupts
117 * and latch the count. microtime() currently uses "cli; outb ..." so it
118 * normally takes less than 2 timer cycles. Add a few for cache misses.
119 * Add a few more to allow for latency in bogus calls to microtime() with
120 * interrupts already disabled.
122 #define TIMER0_LATCH_COUNT 20
125 * Maximum frequency that we are willing to allow for timer0. Must be
126 * low enough to guarantee that the timer interrupt handler returns
127 * before the next timer interrupt.
129 #define TIMER0_MAX_FREQ 20000
131 int adjkerntz; /* local offset from GMT in seconds */
133 int disable_rtc_set; /* disable resettodr() if != 0 */
134 int statclock_disable;
136 #define TIMER_FREQ 1193182
138 u_int timer_freq = TIMER_FREQ;
139 int timer0_max_count;
143 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
144 struct mtx clock_lock;
146 static int beeping = 0;
147 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
148 static u_int hardclock_max_count;
149 static u_int32_t i8254_lastcount;
150 static u_int32_t i8254_offset;
151 static int i8254_ticked;
153 * XXX new_function and timer_func should not handle clockframes, but
154 * timer_func currently needs to hold hardclock to handle the
155 * timer0_state == 0 case. We should use inthand_add()/inthand_remove()
156 * to switch between clkintr() and a slightly different timerintr().
158 static void (*new_function) __P((struct clockframe *frame));
159 static u_int new_rate;
160 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
161 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
162 static u_int timer0_prescaler_count;
164 /* Values for timerX_state: */
166 #define RELEASE_PENDING 1
168 #define ACQUIRE_PENDING 3
170 static u_char timer0_state;
171 static u_char timer2_state;
172 static void (*timer_func) __P((struct clockframe *frame)) = hardclock;
174 static unsigned i8254_get_timecount __P((struct timecounter *tc));
175 static unsigned tsc_get_timecount __P((struct timecounter *tc));
176 static void set_timer_freq(u_int freq, int intr_freq);
178 static struct timecounter tsc_timecounter = {
179 tsc_get_timecount, /* get_timecount */
181 ~0u, /* counter_mask */
186 SYSCTL_OPAQUE(_debug, OID_AUTO, tsc_timecounter, CTLFLAG_RD,
187 &tsc_timecounter, sizeof(tsc_timecounter), "S,timecounter", "");
189 static struct timecounter i8254_timecounter = {
190 i8254_get_timecount, /* get_timecount */
192 ~0u, /* counter_mask */
197 SYSCTL_OPAQUE(_debug, OID_AUTO, i8254_timecounter, CTLFLAG_RD,
198 &i8254_timecounter, sizeof(i8254_timecounter), "S,timecounter", "");
201 clkintr(struct clockframe frame)
204 if (timecounter->tc_get_timecount == i8254_get_timecount) {
205 mtx_lock_spin(&clock_lock);
209 i8254_offset += timer0_max_count;
213 mtx_unlock_spin(&clock_lock);
216 switch (timer0_state) {
222 if ((timer0_prescaler_count += timer0_max_count)
223 >= hardclock_max_count) {
224 timer0_prescaler_count -= hardclock_max_count;
229 case ACQUIRE_PENDING:
230 mtx_lock_spin(&clock_lock);
231 i8254_offset = i8254_get_timecount(NULL);
233 timer0_max_count = TIMER_DIV(new_rate);
234 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
235 outb(TIMER_CNTR0, timer0_max_count & 0xff);
236 outb(TIMER_CNTR0, timer0_max_count >> 8);
237 mtx_unlock_spin(&clock_lock);
238 timer_func = new_function;
239 timer0_state = ACQUIRED;
242 case RELEASE_PENDING:
243 if ((timer0_prescaler_count += timer0_max_count)
244 >= hardclock_max_count) {
245 mtx_lock_spin(&clock_lock);
246 i8254_offset = i8254_get_timecount(NULL);
248 timer0_max_count = hardclock_max_count;
250 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
251 outb(TIMER_CNTR0, timer0_max_count & 0xff);
252 outb(TIMER_CNTR0, timer0_max_count >> 8);
253 mtx_unlock_spin(&clock_lock);
254 timer0_prescaler_count = 0;
255 timer_func = hardclock;
256 timer0_state = RELEASED;
262 /* Reset clock interrupt by asserting bit 7 of port 0x61 */
264 outb(0x61, inb(0x61) | 0x80);
269 * The acquire and release functions must be called at ipl >= splclock().
272 acquire_timer0(int rate, void (*function) __P((struct clockframe *frame)))
276 if (rate <= 0 || rate > TIMER0_MAX_FREQ)
278 switch (timer0_state) {
281 timer0_state = ACQUIRE_PENDING;
284 case RELEASE_PENDING:
285 if (rate != old_rate)
288 * The timer has been released recently, but is being
289 * re-acquired before the release completed. In this
290 * case, we simply reclaim it as if it had not been
293 timer0_state = ACQUIRED;
297 return (-1); /* busy */
299 new_function = function;
300 old_rate = new_rate = rate;
305 acquire_timer2(int mode)
308 if (timer2_state != RELEASED)
310 timer2_state = ACQUIRED;
313 * This access to the timer registers is as atomic as possible
314 * because it is a single instruction. We could do better if we
315 * knew the rate. Use of splclock() limits glitches to 10-100us,
316 * and this is probably good enough for timer2, so we aren't as
317 * careful with it as with timer0.
319 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
327 switch (timer0_state) {
330 timer0_state = RELEASE_PENDING;
333 case ACQUIRE_PENDING:
334 /* Nothing happened yet, release quickly. */
335 timer0_state = RELEASED;
348 if (timer2_state != ACQUIRED)
350 timer2_state = RELEASED;
351 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
356 * This routine receives statistical clock interrupts from the RTC.
357 * As explained above, these occur at 128 interrupts per second.
358 * When profiling, we receive interrupts at a rate of 1024 Hz.
360 * This does not actually add as much overhead as it sounds, because
361 * when the statistical clock is active, the hardclock driver no longer
362 * needs to keep (inaccurate) statistics on its own. This decouples
363 * statistics gathering from scheduling interrupts.
365 * The RTC chip requires that we read status register C (RTC_INTR)
366 * to acknowledge an interrupt, before it will generate the next one.
367 * Under high interrupt load, rtcintr() can be indefinitely delayed and
368 * the clock can tick immediately after the read from RTC_INTR. In this
369 * case, the mc146818A interrupt signal will not drop for long enough
370 * to register with the 8259 PIC. If an interrupt is missed, the stat
371 * clock will halt, considerably degrading system performance. This is
372 * why we use 'while' rather than a more straightforward 'if' below.
373 * Stat clock ticks can still be lost, causing minor loss of accuracy
374 * in the statistics, but the stat clock will no longer stop.
377 rtcintr(struct clockframe frame)
379 while (rtcin(RTC_INTR) & RTCIR_PERIOD)
387 DB_SHOW_COMMAND(rtc, rtc)
389 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
390 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
391 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
392 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
401 mtx_lock_spin(&clock_lock);
403 /* Select timer0 and latch counter value. */
404 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
406 low = inb(TIMER_CNTR0);
407 high = inb(TIMER_CNTR0);
409 mtx_unlock_spin(&clock_lock);
410 return ((high << 8) | low);
414 * Wait "n" microseconds.
415 * Relies on timer 1 counting down from (timer_freq / hz)
416 * Note: timer had better have been programmed before this is first used!
421 int delta, prev_tick, tick, ticks_left;
426 static int state = 0;
430 for (n1 = 1; n1 <= 10000000; n1 *= 10)
435 printf("DELAY(%d)...", n);
438 * Guard against the timer being uninitialized if we are called
439 * early for console i/o.
441 if (timer0_max_count == 0)
442 set_timer_freq(timer_freq, hz);
445 * Read the counter first, so that the rest of the setup overhead is
446 * counted. Guess the initial overhead is 20 usec (on most systems it
447 * takes about 1.5 usec for each of the i/o's in getit(). The loop
448 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The
449 * multiplications and divisions to scale the count take a while).
452 n -= 0; /* XXX actually guess no initial overhead */
454 * Calculate (n * (timer_freq / 1e6)) without using floating point
455 * and without any avoidable overflows.
461 * Use fixed point to avoid a slow division by 1000000.
462 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest.
463 * 2^15 is the first power of 2 that gives exact results
464 * for n between 0 and 256.
466 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15;
469 * Don't bother using fixed point, although gcc-2.7.2
470 * generates particularly poor code for the long long
471 * division, since even the slow way will complete long
472 * before the delay is up (unless we're interrupted).
474 ticks_left = ((u_int)n * (long long)timer_freq + 999999)
477 while (ticks_left > 0) {
482 delta = prev_tick - tick;
485 delta += timer0_max_count;
487 * Guard against timer0_max_count being wrong.
488 * This shouldn't happen in normal operation,
489 * but it may happen if set_timer_freq() is
499 printf(" %d calls to getit() at %d usec each\n",
500 getit_calls, (n + 5) / getit_calls);
505 sysbeepstop(void *chan)
507 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
513 sysbeep(int pitch, int period)
517 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
519 /* Something else owns it. */
521 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */
523 mtx_lock_spin(&clock_lock);
524 outb(TIMER_CNTR2, pitch);
525 outb(TIMER_CNTR2, (pitch>>8));
526 mtx_unlock_spin(&clock_lock);
528 /* enable counter2 output to speaker */
529 outb(IO_PPI, inb(IO_PPI) | 3);
531 timeout(sysbeepstop, (void *)NULL, period);
538 * RTC support routines
551 val = inb(IO_RTC + 1);
558 writertc(u_char reg, u_char val)
566 outb(IO_RTC + 1, val);
567 inb(0x84); /* XXX work around wrong order in rtcin() */
574 return(bcd2bin(rtcin(port)));
578 calibrate_clocks(void)
581 u_int count, prev_count, tot_count;
582 int sec, start_sec, timeout;
585 printf("Calibrating clock(s) ... ");
586 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
590 /* Read the mc146818A seconds counter. */
592 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
593 sec = rtcin(RTC_SEC);
600 /* Wait for the mC146818A seconds counter to change. */
603 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
604 sec = rtcin(RTC_SEC);
605 if (sec != start_sec)
612 /* Start keeping track of the i8254 counter. */
613 prev_count = getit();
614 if (prev_count == 0 || prev_count > timer0_max_count)
621 old_tsc = 0; /* shut up gcc */
624 * Wait for the mc146818A seconds counter to change. Read the i8254
625 * counter for each iteration since this is convenient and only
626 * costs a few usec of inaccuracy. The timing of the final reads
627 * of the counters almost matches the timing of the initial reads,
628 * so the main cause of inaccuracy is the varying latency from
629 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
630 * rtcin(RTC_SEC) that returns a changed seconds count. The
631 * maximum inaccuracy from this cause is < 10 usec on 486's.
635 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
636 sec = rtcin(RTC_SEC);
638 if (count == 0 || count > timer0_max_count)
640 if (count > prev_count)
641 tot_count += prev_count - (count - timer0_max_count);
643 tot_count += prev_count - count;
645 if (sec != start_sec)
652 * Read the cpu cycle counter. The timing considerations are
653 * similar to those for the i8254 clock.
656 tsc_freq = rdtsc() - old_tsc;
660 printf("TSC clock: %u Hz, ", tsc_freq);
661 printf("i8254 clock: %u Hz\n", tot_count);
667 printf("failed, using default i8254 clock of %u Hz\n",
673 set_timer_freq(u_int freq, int intr_freq)
675 int new_timer0_max_count;
677 mtx_lock_spin(&clock_lock);
679 new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq);
680 if (new_timer0_max_count != timer0_max_count) {
681 timer0_max_count = new_timer0_max_count;
682 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
683 outb(TIMER_CNTR0, timer0_max_count & 0xff);
684 outb(TIMER_CNTR0, timer0_max_count >> 8);
686 mtx_unlock_spin(&clock_lock);
690 * i8254_restore is called from apm_default_resume() to reload
691 * the countdown register.
692 * this should not be necessary but there are broken laptops that
693 * do not restore the countdown register on resume.
694 * when it happnes, it messes up the hardclock interval and system clock,
695 * which leads to the infamous "calcru: negative time" problem.
701 mtx_lock_spin(&clock_lock);
702 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
703 outb(TIMER_CNTR0, timer0_max_count & 0xff);
704 outb(TIMER_CNTR0, timer0_max_count >> 8);
705 mtx_unlock_spin(&clock_lock);
709 * Initialize 8254 timer 0 early so that it can be used in DELAY().
710 * XXX initialization of other timers is unintentionally left blank.
717 if (cpu_feature & CPUID_TSC)
722 writertc(RTC_STATUSA, rtc_statusa);
723 writertc(RTC_STATUSB, RTCSB_24HR);
725 set_timer_freq(timer_freq, hz);
726 freq = calibrate_clocks();
727 #ifdef CLK_CALIBRATION_LOOP
730 "Press a key on the console to abort clock calibration\n");
731 while (cncheckc() == -1)
737 * Use the calibrated i8254 frequency if it seems reasonable.
738 * Otherwise use the default, and don't use the calibrated i586
741 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq;
742 if (delta < timer_freq / 100) {
743 #ifndef CLK_USE_I8254_CALIBRATION
746 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
753 "%d Hz differs from default of %d Hz by more than 1%%\n",
758 set_timer_freq(timer_freq, hz);
759 i8254_timecounter.tc_frequency = timer_freq;
760 tc_init(&i8254_timecounter);
762 #ifndef CLK_USE_TSC_CALIBRATION
766 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
770 if (tsc_present && tsc_freq == 0) {
772 * Calibration of the i586 clock relative to the mc146818A
773 * clock failed. Do a less accurate calibration relative
774 * to the i8254 clock.
776 u_int64_t old_tsc = rdtsc();
779 tsc_freq = rdtsc() - old_tsc;
780 #ifdef CLK_USE_TSC_CALIBRATION
782 printf("TSC clock: %u Hz (Method B)\n", tsc_freq);
788 * We can not use the TSC in SMP mode, until we figure out a
789 * cheap (impossible), reliable and precise (yeah right!) way
790 * to synchronize the TSCs of all the CPUs.
791 * Curse Intel for leaving the counter out of the I/O APIC.
796 * We can not use the TSC if we support APM. Precise timekeeping
797 * on an APM'ed machine is at best a fools pursuit, since
798 * any and all of the time spent in various SMM code can't
799 * be reliably accounted for. Reading the RTC is your only
800 * source of reliable time info. The i8254 looses too of course
801 * but we need to have some kind of time...
802 * We don't know at this point whether APM is going to be used
803 * or not, nor when it might be activated. Play it safe.
807 resource_int_value("apm", 0, "disabled", &disabled);
813 if (tsc_present && tsc_freq != 0 && !tsc_is_broken) {
814 tsc_timecounter.tc_frequency = tsc_freq;
815 tc_init(&tsc_timecounter);
818 #endif /* !defined(SMP) */
822 * Initialize the time of day register, based on the time base which is, e.g.
826 inittodr(time_t base)
828 unsigned long sec, days;
842 /* Look if we have a RTC present and the time is valid */
843 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
846 /* wait for time update to complete */
847 /* If RTCSA_TUP is zero, we have at least 244us before next update */
849 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
855 #ifdef USE_RTC_CENTURY
856 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
858 year = readrtc(RTC_YEAR) + 1900;
866 month = readrtc(RTC_MONTH);
867 for (m = 1; m < month; m++)
868 days += daysinmonth[m-1];
869 if ((month > 2) && LEAPYEAR(year))
871 days += readrtc(RTC_DAY) - 1;
873 for (y = 1970; y < year; y++)
874 days += DAYSPERYEAR + LEAPYEAR(y);
875 sec = ((( days * 24 +
876 readrtc(RTC_HRS)) * 60 +
877 readrtc(RTC_MIN)) * 60 +
879 /* sec now contains the number of seconds, since Jan 1 1970,
880 in the local time zone */
882 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
884 y = time_second - sec;
885 if (y <= -2 || y >= 2) {
886 /* badly off, adjust it */
895 printf("Invalid time in real time clock.\n");
896 printf("Check and reset the date immediately!\n");
900 * Write system time back to RTC
915 /* Disable RTC updates and interrupts. */
916 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
918 /* Calculate local time to put in RTC */
920 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
922 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
923 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
924 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
926 /* We have now the days since 01-01-1970 in tm */
927 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
928 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
930 y++, m = DAYSPERYEAR + LEAPYEAR(y))
933 /* Now we have the years in y and the day-of-the-year in tm */
934 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
935 #ifdef USE_RTC_CENTURY
936 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
942 if (m == 1 && LEAPYEAR(y))
949 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
950 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
952 /* Reenable RTC updates and interrupts. */
953 writertc(RTC_STATUSB, rtc_statusb);
958 * Start both clocks running.
969 if (statclock_disable) {
971 * The stat interrupt mask is different without the
972 * statistics clock. Also, don't set the interrupt
973 * flag which would normally cause the RTC to generate
976 rtc_statusb = RTCSB_24HR;
978 /* Setting stathz to nonzero early helps avoid races. */
979 stathz = RTC_NOPROFRATE;
980 profhz = RTC_PROFRATE;
983 /* Finish initializing 8253 timer 0. */
986 apic_8254_intr = isa_apic_irq(0);
988 if (apic_8254_intr >= 0 ) {
989 if (apic_int_type(0, 0) == 3)
992 /* look for ExtInt on pin 0 */
993 if (apic_int_type(0, 0) == 3) {
994 apic_8254_intr = apic_irq(0, 0);
995 setup_8254_mixed_mode();
997 panic("APIC_IO: Cannot route 8254 interrupt to CPU");
1000 inthand_add("clk", apic_8254_intr, (driver_intr_t *)clkintr, NULL,
1001 INTR_TYPE_CLK | INTR_FAST, &clkdesc);
1002 INTREN(1 << apic_8254_intr);
1007 * XXX Check the priority of this interrupt handler. I
1008 * couldn't find anything suitable in the BSD/OS code (grog,
1011 inthand_add("clk", 0, (driver_intr_t *)clkintr, NULL,
1012 INTR_TYPE_CLK | INTR_FAST, NULL);
1015 #endif /* APIC_IO */
1017 /* Initialize RTC. */
1018 writertc(RTC_STATUSA, rtc_statusa);
1019 writertc(RTC_STATUSB, RTCSB_24HR);
1021 /* Don't bother enabling the statistics clock. */
1022 if (statclock_disable)
1024 diag = rtcin(RTC_DIAG);
1026 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
1029 if (isa_apic_irq(8) != 8)
1030 panic("APIC RTC != 8");
1031 #endif /* APIC_IO */
1033 inthand_add("rtc", 8, (driver_intr_t *)rtcintr, NULL,
1034 INTR_TYPE_CLK | INTR_FAST, NULL);
1040 #endif /* APIC_IO */
1042 writertc(RTC_STATUSB, rtc_statusb);
1045 if (apic_8254_trial) {
1047 printf("APIC_IO: Testing 8254 interrupt delivery\n");
1048 while (read_intr_count(8) < 6)
1050 if (read_intr_count(apic_8254_intr) < 3) {
1052 * The MP table is broken.
1053 * The 8254 was not connected to the specified pin
1055 * Workaround: Limited variant of mixed mode.
1057 INTRDIS(1 << apic_8254_intr);
1058 inthand_remove(clkdesc);
1059 printf("APIC_IO: Broken MP table detected: "
1060 "8254 is not connected to "
1061 "IOAPIC #%d intpin %d\n",
1062 int_to_apicintpin[apic_8254_intr].ioapic,
1063 int_to_apicintpin[apic_8254_intr].int_pin);
1065 * Revoke current ISA IRQ 0 assignment and
1066 * configure a fallback interrupt routing from
1067 * the 8254 Timer via the 8259 PIC to the
1068 * an ExtInt interrupt line on IOAPIC #0 intpin 0.
1069 * We reuse the low level interrupt handler number.
1071 if (apic_irq(0, 0) < 0) {
1072 revoke_apic_irq(apic_8254_intr);
1073 assign_apic_irq(0, 0, apic_8254_intr);
1075 apic_8254_intr = apic_irq(0, 0);
1076 setup_8254_mixed_mode();
1077 inthand_add("clk", apic_8254_intr,
1078 (driver_intr_t *)clkintr, NULL,
1079 INTR_TYPE_CLK | INTR_FAST, NULL);
1080 INTREN(1 << apic_8254_intr);
1084 if (apic_int_type(0, 0) != 3 ||
1085 int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
1086 int_to_apicintpin[apic_8254_intr].int_pin != 0)
1087 printf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
1088 int_to_apicintpin[apic_8254_intr].ioapic,
1089 int_to_apicintpin[apic_8254_intr].int_pin);
1092 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
1099 read_intr_count(int vec)
1102 up = intr_countp[vec];
1109 setup_8254_mixed_mode()
1112 * Allow 8254 timer to INTerrupt 8259:
1113 * re-initialize master 8259:
1114 * reset; prog 4 bytes, single ICU, edge triggered
1116 outb(IO_ICU1, 0x13);
1117 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */
1118 outb(IO_ICU1 + 1, 0x00); /* ignore slave */
1119 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
1120 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
1122 /* program IO APIC for type 3 INT on INT0 */
1123 if (ext_int_setup(0, 0) < 0)
1124 panic("8254 redirect via APIC pin0 impossible!");
1129 setstatclockrate(int newhz)
1131 if (newhz == RTC_PROFRATE)
1132 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1134 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1135 writertc(RTC_STATUSA, rtc_statusa);
1139 sysctl_machdep_i8254_freq(SYSCTL_HANDLER_ARGS)
1145 * Use `i8254' instead of `timer' in external names because `timer'
1146 * is is too generic. Should use it everywhere.
1149 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
1150 if (error == 0 && req->newptr != NULL) {
1151 if (timer0_state != RELEASED)
1152 return (EBUSY); /* too much trouble to handle */
1153 set_timer_freq(freq, hz);
1154 i8254_timecounter.tc_frequency = freq;
1155 tc_update(&i8254_timecounter);
1160 SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW,
1161 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", "");
1164 sysctl_machdep_tsc_freq(SYSCTL_HANDLER_ARGS)
1169 if (tsc_timecounter.tc_frequency == 0)
1170 return (EOPNOTSUPP);
1172 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
1173 if (error == 0 && req->newptr != NULL) {
1175 tsc_timecounter.tc_frequency = tsc_freq;
1176 tc_update(&tsc_timecounter);
1181 SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_INT | CTLFLAG_RW,
1182 0, sizeof(u_int), sysctl_machdep_tsc_freq, "I", "");
1185 i8254_get_timecount(struct timecounter *tc)
1191 eflags = read_eflags();
1192 mtx_lock_spin(&clock_lock);
1194 /* Select timer0 and latch counter value. */
1195 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
1197 low = inb(TIMER_CNTR0);
1198 high = inb(TIMER_CNTR0);
1199 count = timer0_max_count - ((high << 8) | low);
1200 if (count < i8254_lastcount ||
1201 (!i8254_ticked && (clkintr_pending ||
1202 ((count < 20 || (!(eflags & PSL_I) && count < timer0_max_count / 2u)) &&
1204 #define lapic_irr1 ((volatile u_int *)&lapic)[0x210 / 4] /* XXX XXX */
1205 /* XXX this assumes that apic_8254_intr is < 24. */
1206 (lapic_irr1 & (1 << apic_8254_intr))))
1208 (inb(IO_ICU1) & 1)))
1212 i8254_offset += timer0_max_count;
1214 i8254_lastcount = count;
1215 count += i8254_offset;
1216 mtx_unlock_spin(&clock_lock);
1221 tsc_get_timecount(struct timecounter *tc)
1227 * Attach to the ISA PnP descriptors for the timer and realtime clock.
1229 static struct isa_pnp_id attimer_ids[] = {
1230 { 0x0001d041 /* PNP0100 */, "AT timer" },
1231 { 0x000bd041 /* PNP0B00 */, "AT realtime clock" },
1236 attimer_probe(device_t dev)
1240 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, attimer_ids)) <= 0)
1246 attimer_attach(device_t dev)
1251 static device_method_t attimer_methods[] = {
1252 /* Device interface */
1253 DEVMETHOD(device_probe, attimer_probe),
1254 DEVMETHOD(device_attach, attimer_attach),
1255 DEVMETHOD(device_detach, bus_generic_detach),
1256 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1257 DEVMETHOD(device_suspend, bus_generic_suspend), /* XXX stop statclock? */
1258 DEVMETHOD(device_resume, bus_generic_resume), /* XXX restart statclock? */
1262 static driver_t attimer_driver = {
1268 static devclass_t attimer_devclass;
1270 DRIVER_MODULE(attimer, isa, attimer_driver, attimer_devclass, 0, 0);