2 * Defines for Cronyx-Sigma adapter, based on Cirrus Logic multiprotocol
3 * controller RISC processor CL-CD2400/2401.
5 * Copyright (C) 1994 Cronyx Ltd.
6 * Author: Serge Vakulenko, <vak@zebub.msk.su>
8 * This software is distributed with NO WARRANTIES, not even the implied
9 * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
11 * Authors grant any other persons or organizations permission to use
12 * or modify this software as long as this message is kept with the software,
13 * all derivative works or modified versions.
15 * Version 1.0, Fri Oct 7 19:34:06 MSD 1994
17 #define NBRD 3 /* the maximum number of installed boards */
18 #define NPORT 16 /* the number of i/o ports per board */
20 #define REVCL_MIN 7 /* CD2400 min. revision number G */
21 #define REVCL_MAX 11 /* CD2400 max. revision number K */
23 #define BRD_INTR_LEVEL 0x5a /* interrupt level (arbitrary PILR value) */
25 #define CS0(p) ((p) | 0x8000) /* chip select 0 */
26 #define CS1(p) ((p) | 0xc000) /* chip select 1 */
27 #define BSR(p) (p) /* board status register, read only */
28 #define BCR0(p) (p) /* board command register 0, write only */
29 #define BCR1(p) ((p) | 0x2000) /* board command register 1, write only */
32 * Chip register address, B is chip base port, R is chip register number.
34 #define R(b,r) ((b) | (((r)<<6 & 0x3c00) | ((r) & 0xf)))
37 * Interrupt acknowledge register, P is board port, L is interrupt level,
38 * as programmed in PILR.
40 #define IACK(p,l) (R(p,l) | 0x4000)
45 #define GFRCR(b) R(b,0x82) /* global firmware revision code register */
46 #define CAR(b) R(b,0xec) /* channel access register */
51 #define CMR(b) R(b,0x18) /* channel mode register */
52 #define COR1(b) R(b,0x13) /* channel option register 1 */
53 #define COR2(b) R(b,0x14) /* channel option register 2 */
54 #define COR3(b) R(b,0x15) /* channel option register 3 */
55 #define COR4(b) R(b,0x16) /* channel option register 4 */
56 #define COR5(b) R(b,0x17) /* channel option register 5 */
57 #define COR6(b) R(b,0x1b) /* channel option register 6 */
58 #define COR7(b) R(b,0x04) /* channel option register 7 */
59 #define SCHR1(b) R(b,0x1c) /* special character register 1 */
60 #define SCHR2(b) R(b,0x1d) /* special character register 2 */
61 #define SCHR3(b) R(b,0x1e) /* special character register 3 */
62 #define SCHR4(b) R(b,0x1f) /* special character register 4 */
63 #define SCRL(b) R(b,0x20) /* special character range low */
64 #define SCRH(b) R(b,0x21) /* special character range high */
65 #define LNXT(b) R(b,0x2d) /* LNext character */
66 #define RFAR1(b) R(b,0x1c) /* receive frame address register 1 */
67 #define RFAR2(b) R(b,0x1d) /* receive frame address register 2 */
68 #define RFAR3(b) R(b,0x1e) /* receive frame address register 3 */
69 #define RFAR4(b) R(b,0x1f) /* receive frame address register 4 */
70 #define CPSR(b) R(b,0xd4) /* CRC polynomial select register */
73 * Bit rate and clock option registers.
75 #define RBPR(b) R(b,0xc9) /* receive baud rate period register */
76 #define RCOR(b) R(b,0xca) /* receive clock option register */
77 #define TBPR(b) R(b,0xc1) /* transmit baud rate period register */
78 #define TCOR(b) R(b,0xc2) /* receive clock option register */
81 * Channel command and status registers.
83 #define CCR(b) R(b,0x10) /* channel command register */
84 #define STCR(b) R(b,0x11) /* special transmit command register */
85 #define CSR(b) R(b,0x19) /* channel status register */
86 #define MSVR(b) R(b,0xdc) /* modem signal value register */
87 #define MSVR_RTS(b) R(b,0xdc) /* modem RTS setup register */
88 #define MSVR_DTR(b) R(b,0xdd) /* modem DTR setup register */
91 * Interrupt registers.
93 #define LIVR(b) R(b,0x0a) /* local interrupt vector register */
94 #define IER(b) R(b,0x12) /* interrupt enable register */
95 #define LICR(b) R(b,0x25) /* local interrupting channel register */
96 #define STK(b) R(b,0xe0) /* stack register */
99 * Receive interrupt registers.
101 #define RPILR(b) R(b,0xe3) /* receive priority interrupt level register */
102 #define RIR(b) R(b,0xef) /* receive interrupt register */
103 #define RISR(b) R(b,0x8a) /* receive interrupt status register */
104 #define RISRL(b) R(b,0x8a) /* receive interrupt status register low */
105 #define RISRH(b) R(b,0x8b) /* receive interrupt status register high */
106 #define RFOC(b) R(b,0x33) /* receive FIFO output count */
107 #define RDR(b) R(b,0xf8) /* receive data register */
108 #define REOIR(b) R(b,0x87) /* receive end of interrupt register */
111 * Transmit interrupt registers.
113 #define TPILR(b) R(b,0xe2) /* transmit priority interrupt level reg */
114 #define TIR(b) R(b,0xee) /* transmit interrupt register */
115 #define TISR(b) R(b,0x89) /* transmit interrupt status register */
116 #define TFTC(b) R(b,0x83) /* transmit FIFO transfer count */
117 #define TDR(b) R(b,0xf8) /* transmit data register */
118 #define TEOIR(b) R(b,0x86) /* transmit end of interrupt register */
121 * Modem interrupt registers.
123 #define MPILR(b) R(b,0xe1) /* modem priority interrupt level register */
124 #define MIR(b) R(b,0xed) /* modem interrupt register */
125 #define MISR(b) R(b,0x88) /* modem/timer interrupt status register */
126 #define MEOIR(b) R(b,0x85) /* modem end of interrupt register */
131 #define DMR(b) R(b,0xf4) /* DMA mode register */
132 #define BERCNT(b) R(b,0x8d) /* bus error retry count */
133 #define DMABSTS(b) R(b,0x1a) /* DMA buffer status */
136 * DMA receive registers.
138 #define ARBADRL(b) R(b,0x40) /* A receive buffer address lower */
139 #define ARBADRU(b) R(b,0x42) /* A receive buffer address upper */
140 #define BRBADRL(b) R(b,0x44) /* B receive buffer address lower */
141 #define BRBADRU(b) R(b,0x46) /* B receive buffer address upper */
142 #define ARBCNT(b) R(b,0x48) /* A receive buffer byte count */
143 #define BRBCNT(b) R(b,0x4a) /* B receive buffer byte count */
144 #define ARBSTS(b) R(b,0x4c) /* A receive buffer status */
145 #define BRBSTS(b) R(b,0x4d) /* B receive buffer status */
146 #define RCBADRL(b) R(b,0x3c) /* receive current buffer address lower */
147 #define RCBADRU(b) R(b,0x3e) /* receive current buffer address upper */
150 * DMA transmit registers.
152 #define ATBADRL(b) R(b,0x50) /* A transmit buffer address lower */
153 #define ATBADRU(b) R(b,0x52) /* A transmit buffer address upper */
154 #define BTBADRL(b) R(b,0x54) /* B transmit buffer address lower */
155 #define BTBADRU(b) R(b,0x56) /* B transmit buffer address upper */
156 #define ATBCNT(b) R(b,0x58) /* A transmit buffer byte count */
157 #define BTBCNT(b) R(b,0x5a) /* B transmit buffer byte count */
158 #define ATBSTS(b) R(b,0x5c) /* A transmit buffer status */
159 #define BTBSTS(b) R(b,0x5d) /* B transmit buffer status */
160 #define TCBADRL(b) R(b,0x38) /* transmit current buffer address lower */
161 #define TCBADRU(b) R(b,0x3a) /* transmit current buffer address upper */
166 #define TPR(b) R(b,0xd8) /* timer period register */
167 #define RTPR(b) R(b,0x26) /* receive timeout period register */
168 #define RTPRL(b) R(b,0x26) /* receive timeout period register low */
169 #define RTPTH(b) R(b,0x27) /* receive timeout period register high */
170 #define GT1(b) R(b,0x28) /* general timer 1 */
171 #define GT1L(b) R(b,0x28) /* general timer 1 low */
172 #define GT1H(b) R(b,0x29) /* general timer 1 high */
173 #define GT2(b) R(b,0x2a) /* general timer 2 */
174 #define TTR(b) R(b,0x2a) /* transmit timer register */
177 * Board status register bits.
179 #define BSR_NOINTR 0x01 /* no interrupt pending flag */
181 #define BSR_VAR_MASK 0x66 /* adapter variant mask */
183 #define BSR_OSC_MASK 0x18 /* oscillator frequency mask */
184 #define BSR_OSC_20 0x18 /* 20 MHz */
185 #define BSR_OSC_18432 0x10 /* 18.432 MHz */
187 #define BSR_NOCHAIN 0x80 /* no daisy chained board */
189 #define BSR_NODSR(n) (0x100 << (n)) /* DSR from channels 0-3, inverted */
190 #define BSR_NOCD(n) (0x1000 << (n)) /* CD from channels 0-3, inverted */
193 * Board revision mask.
195 #define BSR_REV_MASK (BSR_OSC_MASK|BSR_VAR_MASK|BSR_NOCHAIN)
198 * Board control register 0 bits.
200 #define BCR0_IRQ_DIS 0x00 /* no interrupt generated */
201 #define BCR0_IRQ_3 0x01 /* select IRQ number 3 */
202 #define BCR0_IRQ_5 0x02 /* select IRQ number 5 */
203 #define BCR0_IRQ_7 0x03 /* select IRQ number 7 */
204 #define BCR0_IRQ_10 0x04 /* select IRQ number 10 */
205 #define BCR0_IRQ_11 0x05 /* select IRQ number 11 */
206 #define BCR0_IRQ_12 0x06 /* select IRQ number 12 */
207 #define BCR0_IRQ_15 0x07 /* select IRQ number 15 */
209 #define BCR0_NORESET 0x08 /* CD2400 reset flag (inverted) */
211 #define BCR0_DMA_DIS 0x00 /* no interrupt generated */
212 #define BCR0_DMA_5 0x10 /* select DMA channel 5 */
213 #define BCR0_DMA_6 0x20 /* select DMA channel 6 */
214 #define BCR0_DMA_7 0x30 /* select DMA channel 7 */
216 #define BCR0_UM_ASYNC 0x00 /* channel 0 mode - async */
217 #define BCR0_UM_SYNC 0x80 /* channel 0 mode - sync */
218 #define BCR0_UI_RS232 0x00 /* channel 0 interface - RS-232 */
219 #define BCR0_UI_RS449 0x40 /* channel 0 interface - RS-449/V.35 */
220 #define BCR0_UMASK 0xc0 /* channel 0 interface mask */
223 * Board control register 1 bits.
225 #define BCR1_DTR(n) (0x100 << (n)) /* DTR for channels 0-3 sync */
228 * Cronyx board variants.
230 #define CRONYX_100 0x64
231 #define CRONYX_400 0x62
232 #define CRONYX_500 0x60
233 #define CRONYX_410 0x24
234 #define CRONYX_810 0x20
235 #define CRONYX_410s 0x04
236 #define CRONYX_810s 0x00
237 #define CRONYX_440 0x44
238 #define CRONYX_840 0x40
239 #define CRONYX_401 0x26
240 #define CRONYX_801 0x22
241 #define CRONYX_401s 0x06
242 #define CRONYX_801s 0x02
243 #define CRONYX_404 0x46
244 #define CRONYX_703 0x42
247 * Channel commands (CCR).
249 #define CCR_CLRCH 0x40 /* clear channel */
250 #define CCR_INITCH 0x20 /* initialize channel */
251 #define CCR_RSTALL 0x10 /* reset all channels */
252 #define CCR_ENTX 0x08 /* enable transmitter */
253 #define CCR_DISTX 0x04 /* disable transmitter */
254 #define CCR_ENRX 0x02 /* enable receiver */
255 #define CCR_DISRX 0x01 /* disable receiver */
256 #define CCR_CLRT1 0xc0 /* clear timer 1 */
257 #define CCR_CLRT2 0xa0 /* clear timer 2 */
258 #define CCR_CLRRCV 0x90 /* clear receiver */
261 * Interrupt enable register (IER) bits.
263 #define IER_MDM 0x80 /* modem status changed */
264 #define IER_RET 0x20 /* receive exception timeout */
265 #define IER_RXD 0x08 /* data received */
266 #define IER_TIMER 0x04 /* timer expired */
267 #define IER_TXMPTY 0x02 /* transmitter empty */
268 #define IER_TXD 0x01 /* data transmitted */
271 * Modem signal values register bits (MSVR).
273 #define MSV_DSR 0x80 /* state of Data Set Ready input */
274 #define MSV_CD 0x40 /* state of Carrier Detect input */
275 #define MSV_CTS 0x20 /* state of Clear to Send input */
276 #define MSV_TXCOUT 0x10 /* TXCout/DTR pin output flag */
277 #define MSV_PORTID 0x04 /* device is CL-CD2401 (not 2400) */
278 #define MSV_DTR 0x02 /* state of Data Terminal Ready output */
279 #define MSV_RTS 0x01 /* state of Request to Send output */
280 #define MSV_BITS "\20\1rts\2dtr\3cd2400\5txcout\6cts\7cd\10dsr"
283 * DMA buffer status register bits (DMABSTS).
285 #define DMABSTS_TDALIGN 0x80 /* internal data alignment in transmit FIFO */
286 #define DMABSTS_RSTAPD 0x40 /* reset append mode */
287 #define DMABSTS_CRTTBUF 0x20 /* internal current transmit buffer in use */
288 #define DMABSTS_APPEND 0x10 /* append buffer is in use */
289 #define DMABSTS_NTBUF 0x08 /* next transmit buffer is B (not A) */
290 #define DMABSTS_TBUSY 0x04 /* current transmit buffer is in use */
291 #define DMABSTS_NRBUF 0x02 /* next receive buffer is B (not A) */
292 #define DMABSTS_RBUSY 0x01 /* current receive buffer is in use */
295 * Buffer status register bits ([AB][RT]BSTS).
297 #define BSTS_BUSERR 0x80 /* bus error */
298 #define BSTS_EOFR 0x40 /* end of frame */
299 #define BSTS_EOBUF 0x20 /* end of buffer */
300 #define BSTS_APPEND 0x08 /* append mode */
301 #define BSTS_INTR 0x02 /* interrupt required */
302 #define BSTS_OWN24 0x01 /* buffer is (free to be) used by CD2400 */
303 #define BSTS_BITS "\20\1own24\2intr\4append\6eobuf\7eofr\10buserr"
306 * Receive interrupt status register (RISR) bits.
308 #define RIS_OVERRUN 0x0008 /* overrun error */
309 #define RIS_BB 0x0800 /* buffer B status (not A) */
310 #define RIS_EOBUF 0x2000 /* end of buffer reached */
311 #define RIS_EOFR 0x4000 /* frame reception complete */
312 #define RIS_BUSERR 0x8000 /* bus error */
314 #define RISH_CLRDCT 0x0001 /* X.21 clear detect */
315 #define RISH_RESIND 0x0004 /* residual indication */
316 #define RISH_CRCERR 0x0010 /* CRC error */
317 #define RISH_RXABORT 0x0020 /* abort sequence received */
318 #define RISH_EOFR 0x0040 /* complete frame received */
319 #define RISH_BITS "\20\1clrdct\3resind\4overrun\5crcerr\6rxabort\7eofr\14bb\16eobuf\17eofr\20buserr"
321 #define RISA_BREAK 0x0001 /* break signal detected */
322 #define RISA_FRERR 0x0002 /* frame error (bad stop bits) */
323 #define RISA_PARERR 0x0004 /* parity error */
324 #define RISA_SCMASK 0x0070 /* special character detect mask */
325 #define RISA_SCHR1 0x0010 /* special character 1 detected */
326 #define RISA_SCHR2 0x0020 /* special character 2 detected */
327 #define RISA_SCHR3 0x0030 /* special character 3 detected */
328 #define RISA_SCHR4 0x0040 /* special character 4 detected */
329 #define RISA_SCRANGE 0x0070 /* special character in range detected */
330 #define RISA_TIMEOUT 0x0080 /* receive timeout, no data */
331 #define RISA_BITS "\20\1break\2frerr\3parerr\4overrun\5schr1\6schr2\7schr4\10timeout\14bb\16eobuf\17eofr\20buserr"
333 #define RISB_CRCERR 0x0010 /* CRC error */
334 #define RISB_RXABORT 0x0020 /* abort sequence received */
335 #define RISB_EOFR 0x0040 /* complete frame received */
337 #define RISX_LEADCHG 0x0001 /* CTS lead change */
338 #define RISX_PARERR 0x0004 /* parity error */
339 #define RISX_SCMASK 0x0070 /* special character detect mask */
340 #define RISX_SCHR1 0x0010 /* special character 1 detected */
341 #define RISX_SCHR2 0x0020 /* special character 2 detected */
342 #define RISX_SCHR3 0x0030 /* special character 3 detected */
343 #define RISX_ALLZERO 0x0040 /* all 0 condition detected */
344 #define RISX_ALLONE 0x0050 /* all 1 condition detected */
345 #define RISX_ALTOZ 0x0060 /* alternating 1 0 condition detected */
346 #define RISX_SYN 0x0070 /* SYN detected */
347 #define RISX_LEAD 0x0080 /* leading value */
350 * Channel mode register (CMR) bits.
352 #define CMR_RXDMA 0x80 /* DMA receive transfer mode */
353 #define CMR_TXDMA 0x40 /* DMA transmit transfer mode */
354 #define CMR_HDLC 0x00 /* HDLC protocol mode */
355 #define CMR_BISYNC 0x01 /* BISYNC protocol mode */
356 #define CMR_ASYNC 0x02 /* ASYNC protocol mode */
357 #define CMR_X21 0x03 /* X.21 protocol mode */
360 * Modem interrupt status register (MISR) bits.
362 #define MIS_CDSR 0x80 /* DSR changed */
363 #define MIS_CCD 0x40 /* CD changed */
364 #define MIS_CCTS 0x20 /* CTS changed */
365 #define MIS_CGT2 0x02 /* GT2 timer expired */
366 #define MIS_CGT1 0x01 /* GT1 timer expired */
367 #define MIS_BITS "\20\1gt1\2gt2\6ccts\7ccd\10cdsr"
370 * Transmit interrupt status register (TISR) bits.
372 #define TIS_BUSERR 0x80 /* Bus error */
373 #define TIS_EOFR 0x40 /* End of frame */
374 #define TIS_EOBUF 0x20 /* end of transmit buffer reached */
375 #define TIS_UNDERRUN 0x10 /* transmit underrun */
376 #define TIS_BB 0x08 /* buffer B status (not A) */
377 #define TIS_TXEMPTY 0x02 /* transmitter empty */
378 #define TIS_TXDATA 0x01 /* transmit data below threshold */
379 #define TIS_BITS "\20\1txdata\2txempty\4bb\5underrun\6eobuf\7eofr\10buserr"
382 * Local interrupt vector register (LIVR) bits.
390 * Transmit end of interrupt registers (TEOIR) bits.
392 #define TEOI_TERMBUFF 0x80 /* force current buffer to be discarded */
393 #define TEOI_EOFR 0x40 /* end of frame in interrupt mode */
394 #define TEOI_SETTM2 0x20 /* set general timer 2 in sync mode */
395 #define TEOI_SETTM1 0x10 /* set general timer 1 in sync mode */
396 #define TEOI_NOTRANSF 0x08 /* no transfer of data on this interrupt */
399 * Receive end of interrupt registers (REOIR) bits.
401 #define REOI_TERMBUFF 0x80 /* force current buffer to be terminated */
402 #define REOI_DISCEXC 0x40 /* discard exception character */
403 #define REOI_SETTM2 0x20 /* set general timer 2 */
404 #define REOI_SETTM1 0x10 /* set general timer 1 */
405 #define REOI_NOTRANSF 0x08 /* no transfer of data */
406 #define REOI_GAP_MASK 0x07 /* optional gap size to leave in buffer */
409 * Special transmit command register (STCR) bits.
411 #define STC_ABORTTX 0x40 /* abort transmission (HDLC mode) */
412 #define STC_APPDCMP 0x20 /* append complete (async DMA mode) */
413 #define STC_SNDSPC 0x08 /* send special characters (async mode) */
414 #define STC_SSPC_MASK 0x07 /* special character select */
415 #define STC_SSPC_1 0x01 /* send special character #1 */
416 #define STC_SSPC_2 0x02 /* send special character #2 */
417 #define STC_SSPC_3 0x03 /* send special character #3 */
418 #define STC_SSPC_4 0x04 /* send special character #4 */
421 * Channel status register (CSR) bits, asynchronous mode.
423 #define CSRA_RXEN 0x80 /* receiver enable */
424 #define CSRA_RXFLOFF 0x40 /* receiver flow off */
425 #define CSRA_RXFLON 0x20 /* receiver flow on */
426 #define CSRA_TXEN 0x08 /* transmitter enable */
427 #define CSRA_TXFLOFF 0x04 /* transmitter flow off */
428 #define CSRA_TXFLON 0x02 /* transmitter flow on */
429 #define CSRA_BITS "\20\2txflon\3txfloff\4txen\6rxflon\7rxfloff\10rxen"