1 /* gscreg.h - port and bit definitions for the Genius GS-4500 interface
4 * Copyright (c) 1995 Gunther Schadow. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Gunther Schadow.
17 * 4. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 /* the DMA/IRQ jumper configuration */
38 #define GSC_CNF_MASK 0x5a
40 #define GSC_CNF_DMA1 (~0x02 & GSC_CNF_MASK)
41 #define GSC_CNF_DMA3 (~0x08 & GSC_CNF_MASK)
42 #define GSC_CNF_IRQ3 (~0x10 & GSC_CNF_MASK)
43 #define GSC_CNF_IRQ5 (~0x40 & GSC_CNF_MASK)
45 /* the resolution switch setting */
47 #define GSC_RES_MASK 0x24
49 #define GSC_RES_400 0x00
50 #define GSC_RES_300 0x04
51 #define GSC_RES_200 0x20
52 #define GSC_RES_100 0x24
56 #define GSC_RDY_FLAG 0x80
58 #define GSC_IRQ_FLAG 0x01
61 * control register (w)
66 #define GSC_POWER_ON 0x01
68 /* pixel per line count */
70 #define GSC_CNT_MASK 0xf0
72 #define GSC_CNT_3648 0x30
73 #define GSC_CNT_2544 0x90
74 #define GSC_CNT_1696 0xb0
75 #define GSC_CNT_1648 0xe0
76 #define GSC_CNT_1264 0x80
77 #define GSC_CNT_840 0xa0
78 #define GSC_CNT_424 0xf0
84 #define GSC_DATA(iob) (iob + (iob == 0x270 ? 0x02 : 0x01))
85 #define GSC_STAT(iob) (iob + (iob == 0x270 ? 0x03 : 0x02))
86 #define GSC_CTRL(iob) (iob + (iob == 0x270 ? 0x0a : 0x03))
87 #define GSC_CLRP(iob) (iob + (iob == 0x270 ? 0x0b : 0x04))