2 * Copyright (c) 1994 Matt Thomas (thomas@lkg.dec.com)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the author may not be used to endorse or promote products
11 * derived from this software withough specific prior written permission
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * DEC EtherWORKS 2 Ethernet Controllers
29 * DEC EtherWORKS 3 Ethernet Controllers
31 * Written by Matt Thomas
32 * BPF support code stolen directly from if_ec.c
34 * This driver supports the DEPCA, DE100, DE101, DE200, DE201,
35 * DE2002, DE203, DE204, DE205, and DE422 cards.
42 #include <sys/param.h>
43 #include <sys/systm.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/malloc.h>
50 #include <net/ethernet.h>
52 #include <net/if_types.h>
53 #include <net/if_dl.h>
55 #include <netinet/in.h>
56 #include <netinet/if_ether.h>
59 #include <machine/clock.h>
61 #include <i386/isa/isa_device.h>
62 #include <i386/isa/icu.h>
69 /* Forward declarations */
70 typedef struct le_softc le_softc_t;
71 typedef struct le_board le_board_t;
73 typedef u_short le_mcbits_t;
74 #define LE_MC_NBPW_LOG2 4
75 #define LE_MC_NBPW (1 << LE_MC_NBPW_LOG2)
76 #define IF_RESET_ARGS int unit
77 #define LE_RESET(ifp) (((sc)->if_reset)((sc)->le_if.if_unit))
79 #if !defined(LE_NOLEMAC)
81 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
83 * Start of DEC EtherWORKS III (LEMAC) dependent structures
86 #include <i386/isa/ic/lemac.h> /* Include LEMAC definitions */
88 static int lemac_probe(le_softc_t *sc, const le_board_t *bd, int *msize);
90 struct le_lemac_info {
91 u_int lemac__lastpage; /* last 2K page */
92 u_int lemac__memmode; /* Are we in 2K, 32K, or 64K mode */
93 u_int lemac__membase; /* Physical address of start of RAM */
94 u_int lemac__txctl; /* Transmit Control Byte */
95 u_int lemac__txmax; /* Maximum # of outstanding transmits */
96 le_mcbits_t lemac__mctbl[LEMAC_MCTBL_SIZE/sizeof(le_mcbits_t)];
97 /* local copy of multicast table */
98 u_char lemac__eeprom[LEMAC_EEP_SIZE]; /* local copy eeprom */
99 char lemac__prodname[LEMAC_EEP_PRDNMSZ+1]; /* prodname name */
100 #define lemac_lastpage le_un.un_lemac.lemac__lastpage
101 #define lemac_memmode le_un.un_lemac.lemac__memmode
102 #define lemac_membase le_un.un_lemac.lemac__membase
103 #define lemac_txctl le_un.un_lemac.lemac__txctl
104 #define lemac_txmax le_un.un_lemac.lemac__txmax
105 #define lemac_mctbl le_un.un_lemac.lemac__mctbl
106 #define lemac_eeprom le_un.un_lemac.lemac__eeprom
107 #define lemac_prodname le_un.un_lemac.lemac__prodname
109 #endif /* !defined(LE_NOLEMAC) */
111 #if !defined(LE_NOLANCE)
113 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
115 * Start of DEC EtherWORKS II (LANCE) dependent structures
119 #include <i386/isa/ic/am7990.h>
125 static int depca_probe(le_softc_t *sc, const le_board_t *bd, int *msize);
127 typedef struct lance_descinfo lance_descinfo_t;
128 typedef struct lance_ring lance_ring_t;
130 typedef unsigned lance_addr_t;
132 struct lance_descinfo {
133 caddr_t di_addr; /* address of descriptor */
134 lance_addr_t di_bufaddr; /* LANCE address of buffer owned by descriptor */
135 unsigned di_buflen; /* size of buffer owned by descriptor */
136 struct mbuf *di_mbuf; /* mbuf being transmitted/received */
140 lance_descinfo_t *ri_first; /* Pointer to first descriptor in ring */
141 lance_descinfo_t *ri_last; /* Pointer to last + 1 descriptor in ring */
142 lance_descinfo_t *ri_nextin; /* Pointer to next one to be given to HOST */
143 lance_descinfo_t *ri_nextout; /* Pointer to next one to be given to LANCE */
144 unsigned ri_max; /* Size of Ring - 1 */
145 unsigned ri_free; /* Number of free rings entires (owned by HOST) */
146 lance_addr_t ri_heap; /* Start of RAM for this ring */
147 lance_addr_t ri_heapend; /* End + 1 of RAM for this ring */
148 lance_addr_t ri_outptr; /* Pointer to first output byte */
149 unsigned ri_outsize; /* Space remaining for output */
152 struct le_lance_info {
153 unsigned lance__csr1; /* LANCE Address of init block (low 16) */
154 unsigned lance__csr2; /* LANCE Address of init block (high 8) */
155 unsigned lance__csr3; /* Copy of CSR3 */
156 unsigned lance__rap; /* IO Port Offset of RAP */
157 unsigned lance__rdp; /* IO Port Offset of RDP */
158 unsigned lance__ramoffset; /* Offset to valid LANCE RAM */
159 unsigned lance__ramsize; /* Amount of RAM shared by LANCE */
160 unsigned lance__rxbufsize; /* Size of a receive buffer */
161 ln_initb_t lance__initb; /* local copy of LANCE initblock */
162 ln_initb_t *lance__raminitb; /* copy to board's LANCE initblock (debugging) */
163 ln_desc_t *lance__ramdesc; /* copy to board's LANCE descriptors (debugging) */
164 lance_ring_t lance__rxinfo; /* Receive ring information */
165 lance_ring_t lance__txinfo; /* Transmit ring information */
166 #define lance_csr1 le_un.un_lance.lance__csr1
167 #define lance_csr2 le_un.un_lance.lance__csr2
168 #define lance_csr3 le_un.un_lance.lance__csr3
169 #define lance_rap le_un.un_lance.lance__rap
170 #define lance_rdp le_un.un_lance.lance__rdp
171 #define lance_ramoffset le_un.un_lance.lance__ramoffset
172 #define lance_ramsize le_un.un_lance.lance__ramsize
173 #define lance_rxbufsize le_un.un_lance.lance__rxbufsize
174 #define lance_initb le_un.un_lance.lance__initb
175 #define lance_raminitb le_un.un_lance.lance__raminitb
176 #define lance_ramdesc le_un.un_lance.lance__ramdesc
177 #define lance_rxinfo le_un.un_lance.lance__rxinfo
178 #define lance_txinfo le_un.un_lance.lance__txinfo
180 #endif /* !defined(LE_NOLANCE) */
183 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
185 * Start of Common Code
189 static void (*le_intrvec[NLE])(le_softc_t *sc);
192 * Ethernet status, per interface.
195 struct arpcom le_ac; /* Common Ethernet/ARP Structure */
196 void (*if_init) __P((int)); /* Interface init routine */
197 void (*if_reset) __P((int)); /* Interface reset routine */
198 caddr_t le_membase; /* Starting memory address (virtual) */
199 unsigned le_iobase; /* Starting I/O base address */
200 unsigned le_irq; /* Interrupt Request Value */
201 unsigned le_flags; /* local copy of if_flags */
202 #define LE_BRDCSTONLY 0x01000000 /* If only broadcast is enabled */
203 u_int le_mcmask; /* bit mask for CRC-32 for multicast hash */
204 le_mcbits_t *le_mctbl; /* pointer to multicast table */
205 const char *le_prodname; /* product name DE20x-xx */
206 u_char le_hwaddr[6]; /* local copy of hwaddr */
207 unsigned le_scast_drops; /* singlecast drops */
208 unsigned le_mcast_drops; /* multicast drops */
209 unsigned le_bcast_drops; /* broadcast drops */
211 #if !defined(LE_NOLEMAC)
212 struct le_lemac_info un_lemac; /* LEMAC specific information */
214 #if !defined(LE_NOLANCE)
215 struct le_lance_info un_lance; /* Am7990 specific information */
219 #define le_if le_ac.ac_if
222 static int le_probe(struct isa_device *dvp);
223 static int le_attach(struct isa_device *dvp);
224 static ointhand2_t le_intr;
225 static int le_ioctl(struct ifnet *ifp, u_long command, caddr_t data);
226 static void le_input(le_softc_t *sc, caddr_t seg1, size_t total_len,
227 size_t len2, caddr_t seg2);
228 static void le_multi_filter(le_softc_t *sc);
229 static void le_multi_op(le_softc_t *sc, const u_char *mca, int oper_flg);
230 static int le_read_macaddr(le_softc_t *sc, int ioreg, int skippat);
232 #define LE_CRC32_POLY 0xEDB88320UL /* CRC-32 Poly -- Little Endian */
235 int (*bd_probe)(le_softc_t *sc, const le_board_t *bd, int *msize);
239 static le_softc_t le_softc[NLE];
241 static const le_board_t le_boards[] = {
242 #if !defined(LE_NOLEMAC)
243 { lemac_probe }, /* DE20[345] */
245 #if !defined(LE_NOLANCE)
246 { depca_probe }, /* DE{20[012],422} */
248 { NULL } /* Must Be Last! */
252 * This tells the autoconf code how to set us up.
254 struct isa_driver ledriver = {
255 le_probe, le_attach, "le",
258 static unsigned le_intrs[NLE];
260 #define LE_ADDREQUAL(a1, a2) \
261 (((u_short *)a1)[0] == ((u_short *)a2)[0] \
262 || ((u_short *)a1)[1] == ((u_short *)a2)[1] \
263 || ((u_short *)a1)[2] == ((u_short *)a2)[2])
264 #define LE_ADDRBRDCST(a1) \
265 (((u_short *)a1)[0] == 0xFFFFU \
266 || ((u_short *)a1)[1] == 0xFFFFU \
267 || ((u_short *)a1)[2] == 0xFFFFU)
269 #define LE_INL(sc, reg) \
271 __asm __volatile("inl %1, %0": "=a" (data): "d" ((u_short)((sc)->le_iobase + (reg)))); \
275 #define LE_OUTL(sc, reg, data) \
276 ({__asm __volatile("outl %0, %1"::"a" ((u_int)(data)), "d" ((u_short)((sc)->le_iobase + (reg))));})
278 #define LE_INW(sc, reg) \
280 __asm __volatile("inw %1, %0": "=a" (data): "d" ((u_short)((sc)->le_iobase + (reg)))); \
284 #define LE_OUTW(sc, reg, data) \
285 ({__asm __volatile("outw %0, %1"::"a" ((u_short)(data)), "d" ((u_short)((sc)->le_iobase + (reg))));})
287 #define LE_INB(sc, reg) \
289 __asm __volatile("inb %1, %0": "=a" (data): "d" ((u_short)((sc)->le_iobase + (reg)))); \
293 #define LE_OUTB(sc, reg, data) \
294 ({__asm __volatile("outb %0, %1"::"a" ((u_char)(data)), "d" ((u_short)((sc)->le_iobase + (reg))));})
296 #define MEMCPY(to, from, len) bcopy(from, to, len)
297 #define MEMSET(where, what, howmuch) bzero(where, howmuch)
298 #define MEMCMP(l, r, len) bcmp(l, r, len)
303 struct isa_device *dvp)
305 le_softc_t *sc = &le_softc[dvp->id_unit];
306 const le_board_t *bd;
309 if (dvp->id_unit >= NLE) {
310 printf("%s%d not configured -- too many devices\n",
311 ledriver.name, dvp->id_unit);
315 sc->le_iobase = dvp->id_iobase;
316 sc->le_membase = (u_char *) dvp->id_maddr;
317 sc->le_irq = dvp->id_irq;
318 sc->le_if.if_name = ledriver.name;
319 sc->le_if.if_unit = dvp->id_unit;
322 * Find and Initialize board..
325 sc->le_flags &= ~(IFF_UP|IFF_ALLMULTI);
327 for (bd = le_boards; bd->bd_probe != NULL; bd++) {
328 if ((iospace = (*bd->bd_probe)(sc, bd, &dvp->id_msize)) != 0) {
338 struct isa_device *dvp)
340 le_softc_t *sc = &le_softc[dvp->id_unit];
341 struct ifnet *ifp = &sc->le_if;
343 dvp->id_ointr = le_intr;
345 ifp->if_mtu = ETHERMTU;
346 printf("%s%d: %s ethernet address %6D\n",
347 ifp->if_name, ifp->if_unit,
349 sc->le_ac.ac_enaddr, ":");
351 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
352 ifp->if_output = ether_output;
353 ifp->if_ioctl = le_ioctl;
354 ifp->if_type = IFT_ETHER;
358 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
373 (*le_intrvec[unit])(&le_softc[unit]);
388 struct ether_header eh;
391 if (total_len - sizeof(eh) > ETHERMTU
392 || total_len - sizeof(eh) < ETHERMIN) {
393 sc->le_if.if_ierrors++;
396 MEMCPY(&eh, seg1, sizeof(eh));
398 if (sc->le_if.if_bpf != NULL && seg2 == NULL) {
399 bpf_tap(&sc->le_if, seg1, total_len);
401 * If this is single cast but not to us
404 if ((eh.ether_dhost[0] & 1) == 0) {
405 if (!LE_ADDREQUAL(eh.ether_dhost, sc->le_ac.ac_enaddr)) {
406 sc->le_scast_drops++;
409 } else if ((sc->le_flags & IFF_MULTICAST) == 0) {
410 sc->le_mcast_drops++;
412 } else if (sc->le_flags & LE_BRDCSTONLY) {
413 if (!LE_ADDRBRDCST(eh.ether_dhost)) {
414 sc->le_bcast_drops++;
419 seg1 += sizeof(eh); total_len -= sizeof(eh); len1 -= sizeof(eh);
421 MGETHDR(m, M_DONTWAIT, MT_DATA);
423 sc->le_if.if_ierrors++;
426 m->m_pkthdr.len = total_len;
427 m->m_pkthdr.rcvif = &sc->le_if;
428 if (total_len + LE_XTRA > MHLEN /* >= MINCLSIZE */) {
429 MCLGET(m, M_DONTWAIT);
430 if ((m->m_flags & M_EXT) == 0) {
432 sc->le_if.if_ierrors++;
435 } else if (total_len + LE_XTRA > MHLEN && MINCLSIZE == (MHLEN+MLEN)) {
436 MGET(m->m_next, M_DONTWAIT, MT_DATA);
437 if (m->m_next == NULL) {
439 sc->le_if.if_ierrors++;
442 m->m_next->m_len = total_len - MHLEN - LE_XTRA;
443 len1 = total_len = MHLEN - LE_XTRA;
444 MEMCPY(mtod(m->m_next, caddr_t), &seg1[MHLEN-LE_XTRA], m->m_next->m_len);
445 } else if (total_len + LE_XTRA > MHLEN) {
446 panic("le_input: pkt of unknown length");
448 m->m_data += LE_XTRA;
449 m->m_len = total_len;
450 MEMCPY(mtod(m, caddr_t), seg1, len1);
452 MEMCPY(mtod(m, caddr_t) + len1, seg2, total_len - len1);
453 if (sc->le_if.if_bpf != NULL && seg2 != NULL) {
454 bpf_mtap(&sc->le_if, m);
456 * If this is single cast but not to us
459 if ((eh.ether_dhost[0] & 1) == 0) {
460 if (!LE_ADDREQUAL(eh.ether_dhost, sc->le_ac.ac_enaddr)) {
461 sc->le_scast_drops++;
465 } else if ((sc->le_flags & IFF_MULTICAST) == 0) {
466 sc->le_mcast_drops++;
469 } else if (sc->le_flags & LE_BRDCSTONLY) {
470 if (!LE_ADDRBRDCST(eh.ether_dhost)) {
471 sc->le_bcast_drops++;
477 ether_input(&sc->le_if, &eh, m);
486 le_softc_t *sc = ifp->if_softc;
489 if ((sc->le_flags & IFF_UP) == 0)
498 error = ether_ioctl(ifp, cmd, data);
502 (*sc->if_init)(ifp->if_unit);
509 * Update multicast listeners
511 (*sc->if_init)(ifp->if_unit);
525 * This is the standard method of reading the DEC Address ROMS.
526 * I don't understand it but it does work.
534 int cksum, rom_cksum;
537 int idx, idx2, found, octet;
538 static u_char testpat[] = { 0xFF, 0, 0x55, 0xAA, 0xFF, 0, 0x55, 0xAA };
541 for (idx = 0; idx < 32; idx++) {
542 octet = LE_INB(sc, ioreg);
544 if (octet == testpat[idx2]) {
545 if (++idx2 == sizeof testpat) {
559 sc->le_hwaddr[0] = LE_INB(sc, ioreg);
560 sc->le_hwaddr[1] = LE_INB(sc, ioreg);
562 cksum = *(u_short *) &sc->le_hwaddr[0];
564 sc->le_hwaddr[2] = LE_INB(sc, ioreg);
565 sc->le_hwaddr[3] = LE_INB(sc, ioreg);
567 if (cksum > 65535) cksum -= 65535;
568 cksum += *(u_short *) &sc->le_hwaddr[2];
569 if (cksum > 65535) cksum -= 65535;
571 sc->le_hwaddr[4] = LE_INB(sc, ioreg);
572 sc->le_hwaddr[5] = LE_INB(sc, ioreg);
574 if (cksum > 65535) cksum -= 65535;
575 cksum += *(u_short *) &sc->le_hwaddr[4];
576 if (cksum >= 65535) cksum -= 65535;
578 rom_cksum = LE_INB(sc, ioreg);
579 rom_cksum |= LE_INB(sc, ioreg) << 8;
581 if (cksum != rom_cksum)
590 struct ifmultiaddr *ifma;
592 MEMSET(sc->le_mctbl, 0, (sc->le_mcmask + 1) / 8);
594 if (sc->le_if.if_flags & IFF_ALLMULTI) {
595 sc->le_flags |= IFF_MULTICAST|IFF_ALLMULTI;
598 sc->le_flags &= ~IFF_MULTICAST;
599 /* if (interface has had an address assigned) { */
600 le_multi_op(sc, etherbroadcastaddr, TRUE);
601 sc->le_flags |= LE_BRDCSTONLY|IFF_MULTICAST;
604 sc->le_flags |= IFF_MULTICAST;
606 for (ifma = sc->le_ac.ac_if.if_multiaddrs.lh_first; ifma;
607 ifma = ifma->ifma_link.le_next) {
608 if (ifma->ifma_addr->sa_family != AF_LINK)
611 le_multi_op(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1);
612 sc->le_flags &= ~LE_BRDCSTONLY;
622 u_int idx, bit, data, crc = 0xFFFFFFFFUL;
625 for (data = *(__unaligned u_long *) mca, bit = 0; bit < 48; bit++, data >>=
627 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LE_CRC32_POLY : 0);
629 for (idx = 0; idx < 6; idx++)
630 for (data = *mca++, bit = 0; bit < 8; bit++, data >>= 1)
631 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LE_CRC32_POLY : 0);
634 * The following two line convert the N bit index into a longword index
635 * and a longword mask.
637 crc &= sc->le_mcmask;
638 bit = 1 << (crc & (LE_MC_NBPW -1));
639 idx = crc >> (LE_MC_NBPW_LOG2);
642 * Set or clear hash filter bit in our table.
645 sc->le_mctbl[idx] |= bit; /* Set Bit */
647 sc->le_mctbl[idx] &= ~bit; /* Clear Bit */
651 #if !defined(LE_NOLEMAC)
653 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
655 * Start of DEC EtherWORKS III (LEMAC) dependent code
659 #define LEMAC_INTR_ENABLE(sc) \
660 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) | LEMAC_IC_ALL)
662 #define LEMAC_INTR_DISABLE(sc) \
663 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) & ~LEMAC_IC_ALL)
665 #define LEMAC_64K_MODE(mbase) (((mbase) >= 0x0A) && ((mbase) <= 0x0F))
666 #define LEMAC_32K_MODE(mbase) (((mbase) >= 0x14) && ((mbase) <= 0x1F))
667 #define LEMAC_2K_MODE(mbase) ( (mbase) >= 0x40)
669 static void lemac_init(int unit);
670 static void lemac_start(struct ifnet *ifp);
671 static void lemac_reset(IF_RESET_ARGS);
672 static void lemac_intr(le_softc_t *sc);
673 static void lemac_rne_intr(le_softc_t *sc);
674 static void lemac_tne_intr(le_softc_t *sc);
675 static void lemac_txd_intr(le_softc_t *sc, unsigned cs_value);
676 static void lemac_rxd_intr(le_softc_t *sc, unsigned cs_value);
677 static int lemac_read_eeprom(le_softc_t *sc);
678 static void lemac_init_adapmem(le_softc_t *sc);
680 #define LE_MCBITS_ALL_1S ((le_mcbits_t)~(le_mcbits_t)0)
682 static const le_mcbits_t lemac_allmulti_mctbl[16] = {
683 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
684 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
685 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
686 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
689 * An IRQ mapping table. Less space than switch statement.
691 static const int lemac_irqs[] = { IRQ5, IRQ10, IRQ11, IRQ15 };
694 * Some tuning/monitoring variables.
696 static unsigned lemac_deftxmax = 16; /* see lemac_max above */
697 static unsigned lemac_txnospc = 0; /* total # of tranmit starvations */
699 static unsigned lemac_tne_intrs = 0; /* total # of tranmit done intrs */
700 static unsigned lemac_rne_intrs = 0; /* total # of receive done intrs */
701 static unsigned lemac_txd_intrs = 0; /* total # of tranmit error intrs */
702 static unsigned lemac_rxd_intrs = 0; /* total # of receive error intrs */
708 const le_board_t *bd,
713 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEINIT);
714 DELAY(LEMAC_EEP_DELAY);
717 * Read Ethernet address if card is present.
719 if (le_read_macaddr(sc, LEMAC_REG_APD, 0) < 0)
722 MEMCPY(sc->le_ac.ac_enaddr, sc->le_hwaddr, 6);
724 * Clear interrupts and set IRQ.
727 portval = LE_INB(sc, LEMAC_REG_IC) & LEMAC_IC_IRQMSK;
728 irq = lemac_irqs[portval >> 5];
729 LE_OUTB(sc, LEMAC_REG_IC, portval);
732 * Make sure settings match.
735 if (irq != sc->le_irq) {
736 printf("%s%d: lemac configuration error: expected IRQ 0x%x actual 0x%x\n",
737 sc->le_if.if_name, sc->le_if.if_unit, sc->le_irq, irq);
742 * Try to reset the unit
744 sc->if_init = lemac_init;
745 sc->le_if.if_start = lemac_start;
746 sc->if_reset = lemac_reset;
747 sc->lemac_memmode = 2;
749 if ((sc->le_flags & IFF_UP) == 0)
753 * Check for correct memory base configuration.
755 if (vtophys(sc->le_membase) != sc->lemac_membase) {
756 printf("%s%d: lemac configuration error: expected iomem 0x%x actual 0x%x\n",
757 sc->le_if.if_name, sc->le_if.if_unit,
758 vtophys(sc->le_membase), sc->lemac_membase);
762 sc->le_prodname = sc->lemac_prodname;
763 sc->le_mctbl = sc->lemac_mctbl;
764 sc->le_mcmask = (1 << LEMAC_MCTBL_BITS) - 1;
765 sc->lemac_txmax = lemac_deftxmax;
767 le_intrvec[sc->le_if.if_unit] = lemac_intr;
769 return LEMAC_IOSPACE;
773 * Do a hard reset of the board;
779 le_softc_t *sc = &le_softc[unit];
786 sc->le_flags &= IFF_UP;
787 sc->le_if.if_flags &= ~IFF_OACTIVE;
788 LEMAC_INTR_DISABLE(sc);
790 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEINIT);
791 DELAY(LEMAC_EEP_DELAY);
793 /* Disable Interrupts */
794 /* LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) & ICR_IRQ_SEL); */
797 * Read EEPROM information. NOTE - the placement of this function
798 * is important because functions hereafter may rely on information
799 * read from the EEPROM.
801 if ((cksum = lemac_read_eeprom(sc)) != LEMAC_EEP_CKSUM) {
802 printf("%s%d: reset: EEPROM checksum failed (0x%x)\n",
803 sc->le_if.if_name, sc->le_if.if_unit, cksum);
808 * Force to 2K mode if not already configured.
811 portval = LE_INB(sc, LEMAC_REG_MBR);
812 if (!LEMAC_2K_MODE(portval)) {
813 if (LEMAC_64K_MODE(portval)) {
814 portval = (((portval * 2) & 0xF) << 4);
815 sc->lemac_memmode = 64;
816 } else if (LEMAC_32K_MODE(portval)) {
817 portval = ((portval & 0xF) << 4);
818 sc->lemac_memmode = 32;
820 LE_OUTB(sc, LEMAC_REG_MBR, portval);
822 sc->lemac_membase = portval * (2 * 1024) + (512 * 1024);
825 * Initialize Free Memory Queue, Init mcast table with broadcast.
828 lemac_init_adapmem(sc);
829 sc->le_flags |= IFF_UP;
837 le_softc_t *sc = &le_softc[unit];
840 if ((sc->le_flags & IFF_UP) == 0)
846 * If the interface has the up flag
848 if (sc->le_if.if_flags & IFF_UP) {
849 int saved_cs = LE_INB(sc, LEMAC_REG_CS);
850 LE_OUTB(sc, LEMAC_REG_CS, saved_cs | (LEMAC_CS_TXD | LEMAC_CS_RXD));
851 LE_OUTB(sc, LEMAC_REG_PA0, sc->le_ac.ac_enaddr[0]);
852 LE_OUTB(sc, LEMAC_REG_PA1, sc->le_ac.ac_enaddr[1]);
853 LE_OUTB(sc, LEMAC_REG_PA2, sc->le_ac.ac_enaddr[2]);
854 LE_OUTB(sc, LEMAC_REG_PA3, sc->le_ac.ac_enaddr[3]);
855 LE_OUTB(sc, LEMAC_REG_PA4, sc->le_ac.ac_enaddr[4]);
856 LE_OUTB(sc, LEMAC_REG_PA5, sc->le_ac.ac_enaddr[5]);
858 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) | LEMAC_IC_IE);
860 if (sc->le_if.if_flags & IFF_PROMISC) {
861 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_MCE | LEMAC_CS_PME);
863 LEMAC_INTR_DISABLE(sc);
865 LE_OUTB(sc, LEMAC_REG_MPN, 0);
866 if ((sc->le_flags | sc->le_if.if_flags) & IFF_ALLMULTI) {
867 MEMCPY(&sc->le_membase[LEMAC_MCTBL_OFF], lemac_allmulti_mctbl, sizeof(lemac_allmulti_mctbl));
869 MEMCPY(&sc->le_membase[LEMAC_MCTBL_OFF], sc->lemac_mctbl, sizeof(sc->lemac_mctbl));
871 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_MCE);
874 LE_OUTB(sc, LEMAC_REG_CTL, LE_INB(sc, LEMAC_REG_CTL) ^ LEMAC_CTL_LED);
876 LEMAC_INTR_ENABLE(sc);
877 sc->le_if.if_flags |= IFF_RUNNING;
879 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_RXD|LEMAC_CS_TXD);
881 LEMAC_INTR_DISABLE(sc);
882 sc->le_if.if_flags &= ~IFF_RUNNING;
888 * What to do upon receipt of an interrupt.
896 LEMAC_INTR_DISABLE(sc); /* Mask interrupts */
899 * Determine cause of interrupt. Receive events take
900 * priority over Transmit.
903 cs_value = LE_INB(sc, LEMAC_REG_CS);
906 * Check for Receive Queue not being empty.
907 * Check for Transmit Done Queue not being empty.
910 if (cs_value & LEMAC_CS_RNE)
912 if (cs_value & LEMAC_CS_TNE)
916 * Check for Transmitter Disabled.
917 * Check for Receiver Disabled.
920 if (cs_value & LEMAC_CS_TXD)
921 lemac_txd_intr(sc, cs_value);
922 if (cs_value & LEMAC_CS_RXD)
923 lemac_rxd_intr(sc, cs_value);
926 * Toggle LED and unmask interrupts.
929 LE_OUTB(sc, LEMAC_REG_CTL, LE_INB(sc, LEMAC_REG_CTL) ^ LEMAC_CTL_LED);
930 LEMAC_INTR_ENABLE(sc); /* Unmask interrupts */
937 int rxcount, rxlen, rxpg;
941 rxcount = LE_INB(sc, LEMAC_REG_RQC);
943 rxpg = LE_INB(sc, LEMAC_REG_RQ);
944 LE_OUTB(sc, LEMAC_REG_MPN, rxpg);
946 rxptr = sc->le_membase;
947 sc->le_if.if_ipackets++;
948 if (*rxptr & LEMAC_RX_OK) {
951 * Get receive length - subtract out checksum.
954 rxlen = ((*(u_int *)rxptr >> 8) & 0x7FF) - 4;
955 le_input(sc, rxptr + sizeof(u_int), rxlen, rxlen, NULL);
956 } else { /* end if (*rxptr & LEMAC_RX_OK) */
957 sc->le_if.if_ierrors++;
959 LE_OUTB(sc, LEMAC_REG_FMQ, rxpg); /* Return this page to Free Memory Queue */
960 } /* end while (recv_count--) */
971 * Handle CS_RXD (Receiver disabled) here.
973 * Check Free Memory Queue Count. If not equal to zero
974 * then just turn Receiver back on. If it is equal to
975 * zero then check to see if transmitter is disabled.
976 * Process transmit TXD loop once more. If all else
977 * fails then do software init (0xC0 to EEPROM Init)
978 * and rebuild Free Memory Queue.
984 * Re-enable Receiver.
987 cs_value &= ~LEMAC_CS_RXD;
988 LE_OUTB(sc, LEMAC_REG_CS, cs_value);
990 if (LE_INB(sc, LEMAC_REG_FMC) > 0)
993 if (cs_value & LEMAC_CS_TXD)
994 lemac_txd_intr(sc, cs_value);
996 if ((LE_INB(sc, LEMAC_REG_CS) & LEMAC_CS_RXD) == 0)
999 printf("%s%d: fatal RXD error, attempting recovery\n",
1000 sc->le_if.if_name, sc->le_if.if_unit);
1003 if (sc->le_flags & IFF_UP) {
1004 lemac_init(sc->le_if.if_unit);
1009 * Error during initializion. Mark card as disabled.
1011 printf("%s%d: recovery failed -- board disabled\n",
1012 sc->le_if.if_name, sc->le_if.if_unit);
1020 le_softc_t *sc = (le_softc_t *) ifp;
1021 struct ifqueue *ifq = &ifp->if_snd;
1023 if ((ifp->if_flags & IFF_RUNNING) == 0)
1026 LEMAC_INTR_DISABLE(sc);
1028 while (ifq->ifq_head != NULL) {
1033 if (LE_INB(sc, LEMAC_REG_TQC) >= sc->lemac_txmax) {
1034 ifp->if_flags |= IFF_OACTIVE;
1038 tx_pg = LE_INB(sc, LEMAC_REG_FMQ); /* get free memory page */
1040 * Check for good transmit page.
1042 if (tx_pg == 0 || tx_pg > sc->lemac_lastpage) {
1044 ifp->if_flags |= IFF_OACTIVE;
1049 LE_OUTB(sc, LEMAC_REG_MPN, tx_pg); /* Shift 2K window. */
1052 * The first four bytes of each transmit buffer are for
1053 * control information. The first byte is the control
1054 * byte, then the length (why not word aligned?), then
1055 * the off to the buffer.
1058 txoff = (mtod(m, u_int) & (sizeof(u_long) - 1)) + LEMAC_TX_HDRSZ;
1059 txhdr = sc->lemac_txctl | (m->m_pkthdr.len << 8) | (txoff << 24);
1060 *(u_int *) sc->le_membase = txhdr;
1063 * Copy the packet to the board
1066 m_copydata(m, 0, m->m_pkthdr.len, sc->le_membase + txoff);
1068 LE_OUTB(sc, LEMAC_REG_TQ, tx_pg); /* tell chip to transmit this packet */
1070 if (sc->le_if.if_bpf)
1071 bpf_mtap(&sc->le_if, m);
1073 m_freem(m); /* free the mbuf */
1075 LEMAC_INTR_ENABLE(sc);
1082 int txsts, txcount = LE_INB(sc, LEMAC_REG_TDC);
1086 txsts = LE_INB(sc, LEMAC_REG_TDQ);
1087 sc->le_if.if_opackets++; /* another one done */
1088 if ((txsts & LEMAC_TDQ_COL) != LEMAC_TDQ_NOCOL)
1089 sc->le_if.if_collisions++;
1091 sc->le_if.if_flags &= ~IFF_OACTIVE;
1092 lemac_start(&sc->le_if);
1101 * Read transmit status, remove transmit buffer from
1102 * transmit queue and place on free memory queue,
1103 * then reset transmitter.
1104 * Increment appropriate counters.
1108 sc->le_if.if_oerrors++;
1109 if (LE_INB(sc, LEMAC_REG_TS) & LEMAC_TS_ECL)
1110 sc->le_if.if_collisions++;
1111 sc->le_if.if_flags &= ~IFF_OACTIVE;
1113 LE_OUTB(sc, LEMAC_REG_FMQ, LE_INB(sc, LEMAC_REG_TQ));
1114 /* Get Page number and write it back out */
1116 LE_OUTB(sc, LEMAC_REG_CS, cs_value & ~LEMAC_CS_TXD);
1117 /* Turn back on transmitter */
1125 int word_off, cksum;
1130 ep = sc->lemac_eeprom;
1131 for (word_off = 0; word_off < LEMAC_EEP_SIZE / 2; word_off++) {
1132 LE_OUTB(sc, LEMAC_REG_PI1, word_off);
1133 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEREAD);
1135 DELAY(LEMAC_EEP_DELAY);
1137 *ep = LE_INB(sc, LEMAC_REG_EE1); cksum += *ep++;
1138 *ep = LE_INB(sc, LEMAC_REG_EE2); cksum += *ep++;
1142 * Set up Transmit Control Byte for use later during transmit.
1145 sc->lemac_txctl |= LEMAC_TX_FLAGS;
1147 if ((sc->lemac_eeprom[LEMAC_EEP_SWFLAGS] & LEMAC_EEP_SW_SQE) == 0)
1148 sc->lemac_txctl &= ~LEMAC_TX_SQE;
1150 if (sc->lemac_eeprom[LEMAC_EEP_SWFLAGS] & LEMAC_EEP_SW_LAB)
1151 sc->lemac_txctl |= LEMAC_TX_LAB;
1153 MEMCPY(sc->lemac_prodname, &sc->lemac_eeprom[LEMAC_EEP_PRDNM], LEMAC_EEP_PRDNMSZ);
1154 sc->lemac_prodname[LEMAC_EEP_PRDNMSZ] = '\0';
1165 conf = LE_INB(sc, LEMAC_REG_CNF);
1167 if ((sc->lemac_eeprom[LEMAC_EEP_SETUP] & LEMAC_EEP_ST_DRAM) == 0) {
1168 sc->lemac_lastpage = 63;
1169 conf &= ~LEMAC_CNF_DRAM;
1171 sc->lemac_lastpage = 127;
1172 conf |= LEMAC_CNF_DRAM;
1175 LE_OUTB(sc, LEMAC_REG_CNF, conf);
1177 for (pg = 1; pg <= sc->lemac_lastpage; pg++)
1178 LE_OUTB(sc, LEMAC_REG_FMQ, pg);
1182 #endif /* !defined(LE_NOLEMAC) */
1184 #if !defined(LE_NOLANCE)
1186 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1188 * Start of DEPCA (DE200/DE201/DE202/DE422 etal) support.
1191 static void depca_intr(le_softc_t *sc);
1192 static int lance_init_adapmem(le_softc_t *sc);
1193 static int lance_init_ring(le_softc_t *sc, ln_ring_t *rp, lance_ring_t *ri,
1194 unsigned ndescs, unsigned bufoffset,
1195 unsigned descoffset);
1196 static void lance_init(int unit);
1197 static void lance_reset(IF_RESET_ARGS);
1198 static void lance_intr(le_softc_t *sc);
1199 static int lance_rx_intr(le_softc_t *sc);
1200 static void lance_start(struct ifnet *ifp);
1201 static int lance_tx_intr(le_softc_t *sc);
1203 #define LN_BUFSIZE /* 380 */ 304 /* 1520 / 4 */
1204 #define LN_TXDESC_RATIO 2048
1205 #define LN_DESC_MAX 128
1209 unsigned lance_rx_misses;
1210 unsigned lance_rx_badcrc;
1211 unsigned lance_rx_badalign;
1212 unsigned lance_rx_badframe;
1213 unsigned lance_rx_buferror;
1214 unsigned lance_tx_deferred;
1215 unsigned lance_tx_single_collisions;
1216 unsigned lance_tx_multiple_collisions;
1217 unsigned lance_tx_excessive_collisions;
1218 unsigned lance_tx_late_collisions;
1220 unsigned lance_memory_errors;
1221 unsigned lance_inits;
1222 unsigned lance_tx_intrs;
1223 unsigned lance_tx_nospc[2];
1224 unsigned lance_tx_drains[2];
1225 unsigned lance_tx_orphaned;
1226 unsigned lance_tx_adoptions;
1227 unsigned lance_tx_emptied;
1228 unsigned lance_tx_deftxint;
1229 unsigned lance_tx_buferror;
1230 unsigned lance_high_txoutptr;
1231 unsigned lance_low_txheapsize;
1232 unsigned lance_low_txfree;
1233 unsigned lance_tx_intr_hidescs;
1234 /* unsigned lance_tx_intr_descs[LN_DESC_MAX]; */
1236 unsigned lance_rx_intrs;
1237 unsigned lance_rx_badsop;
1238 unsigned lance_rx_contig;
1239 unsigned lance_rx_noncontig;
1240 unsigned lance_rx_intr_hidescs;
1241 unsigned lance_rx_ndescs[4096 / LN_BUFSIZE];
1242 /* unsigned lance_rx_intr_descs[LN_DESC_MAX]; */
1245 #define LN_STAT(stat) (lance_stats.lance_ ## stat)
1246 #define LN_MINSTAT(stat, val) (LN_STAT(stat > (val)) ? LN_STAT(stat = (val)) : 0)
1247 #define LN_MAXSTAT(stat, val) (LN_STAT(stat < (val)) ? LN_STAT(stat = (val)) : 0)
1250 #define LN_STAT(stat) 0
1251 #define LN_MINSTAT(stat, val) 0
1252 #define LN_MAXSTAT(stat, val) 0
1255 #define LN_SELCSR(sc, csrno) (LE_OUTW(sc, sc->lance_rap, csrno))
1256 #define LN_INQCSR(sc) (LE_INW(sc, sc->lance_rap))
1258 #define LN_WRCSR(sc, val) (LE_OUTW(sc, sc->lance_rdp, val))
1259 #define LN_RDCSR(sc) (LE_INW(sc, sc->lance_rdp))
1262 #define LN_ZERO(sc, vaddr, len) bzero(vaddr, len)
1263 #define LN_COPYTO(sc, from, to, len) bcopy(from, to, len)
1265 #define LN_SETFLAG(sc, vaddr, val) \
1266 (((volatile u_char *) vaddr)[3] = (val))
1268 #define LN_PUTDESC(sc, desc, vaddr) \
1269 (((volatile u_short *) vaddr)[0] = ((u_short *) desc)[0], \
1270 ((volatile u_short *) vaddr)[2] = ((u_short *) desc)[2], \
1271 ((volatile u_short *) vaddr)[1] = ((u_short *) desc)[1])
1274 * Only get the descriptor flags and length/status. All else
1277 #define LN_GETDESC(sc, desc, vaddr) \
1278 (((u_short *) desc)[1] = ((volatile u_short *) vaddr)[1], \
1279 ((u_short *) desc)[3] = ((volatile u_short *) vaddr)[3])
1283 * These definitions are specific to the DEC "DEPCA-style" NICs.
1284 * (DEPCA, DE10x, DE20[012], DE422)
1287 #define DEPCA_REG_NICSR 0 /* (RW;16) NI Control / Status */
1288 #define DEPCA_REG_RDP 4 /* (RW:16) LANCE RDP (data) register */
1289 #define DEPCA_REG_RAP 6 /* (RW:16) LANCE RAP (address) register */
1290 #define DEPCA_REG_ADDRROM 12 /* (R : 8) DEPCA Ethernet Address ROM */
1291 #define DEPCA_IOSPACE 16 /* DEPCAs use 16 bytes of IO space */
1293 #define DEPCA_NICSR_LED 0x0001 /* Light the LED on the back of the DEPCA */
1294 #define DEPCA_NICSR_ENABINTR 0x0002 /* Enable Interrupts */
1295 #define DEPCA_NICSR_MASKINTR 0x0004 /* Mask Interrupts */
1296 #define DEPCA_NICSR_AAC 0x0008 /* Address Counter Clear */
1297 #define DEPCA_NICSR_REMOTEBOOT 0x0010 /* Remote Boot Enabled (ignored) */
1298 #define DEPCA_NICSR_32KRAM 0x0020 /* DEPCA LANCE RAM size 64K (C) / 32K (S) */
1299 #define DEPCA_NICSR_LOW32K 0x0040 /* Bank Select (A15 = !This Bit) */
1300 #define DEPCA_NICSR_SHE 0x0080 /* Shared RAM Enabled (ie hide ROM) */
1301 #define DEPCA_NICSR_BOOTTMO 0x0100 /* Remote Boot Timeout (ignored) */
1303 #define DEPCA_RDNICSR(sc) (LE_INW(sc, DEPCA_REG_NICSR))
1304 #define DEPCA_WRNICSR(sc, val) (LE_OUTW(sc, DEPCA_REG_NICSR, val))
1306 #define DEPCA_IDSTR_OFFSET 0xC006 /* ID String Offset */
1308 #define DEPCA_REG_EISAID 0x80
1309 #define DEPCA_EISAID_MASK 0xf0ffffff
1310 #define DEPCA_EISAID_DE422 0x2042A310
1314 DEPCA_DE100, DEPCA_DE101,
1316 DEPCA_DE200, DEPCA_DE201, DEPCA_DE202,
1321 static const char *depca_signatures[] = {
1325 "DE200", "DE201", "DE202",
1333 const le_board_t *bd,
1336 unsigned nicsr, idx, idstr_offset = DEPCA_IDSTR_OFFSET;
1339 * Find out how memory we are dealing with. Adjust
1340 * the ID string offset approriately if we are at
1341 * 32K. Make sure the ROM is enabled.
1343 nicsr = DEPCA_RDNICSR(sc);
1344 nicsr &= ~(DEPCA_NICSR_SHE|DEPCA_NICSR_LED|DEPCA_NICSR_ENABINTR);
1346 if (nicsr & DEPCA_NICSR_32KRAM) {
1348 * Make we are going to read the upper
1349 * 32K so we do read the ROM.
1351 sc->lance_ramsize = 32 * 1024;
1352 nicsr &= ~DEPCA_NICSR_LOW32K;
1353 sc->lance_ramoffset = 32 * 1024;
1354 idstr_offset -= sc->lance_ramsize;
1356 sc->lance_ramsize = 64 * 1024;
1357 sc->lance_ramoffset = 0;
1359 DEPCA_WRNICSR(sc, nicsr);
1361 sc->le_prodname = NULL;
1362 for (idx = 0; depca_signatures[idx] != NULL; idx++) {
1363 if (bcmp(depca_signatures[idx], sc->le_membase + idstr_offset, 5) == 0) {
1364 sc->le_prodname = depca_signatures[idx];
1369 if (sc->le_prodname == NULL) {
1371 * Try to get the EISA device if it's a DE422.
1373 if (sc->le_iobase > 0x1000 && (sc->le_iobase & 0x0F00) == 0x0C00
1374 && (LE_INL(sc, DEPCA_REG_EISAID) & DEPCA_EISAID_MASK)
1375 == DEPCA_EISAID_DE422) {
1376 sc->le_prodname = "DE422";
1381 if (idx == DEPCA_CLASSIC)
1382 sc->lance_ramsize -= 16384; /* Can't use the ROM area on a DEPCA */
1385 * Try to read the address ROM.
1386 * Stop the LANCE, reset the Address ROM Counter (AAC),
1387 * read the NICSR to "clock" in the reset, and then
1388 * re-enable the Address ROM Counter. Now read the
1391 sc->lance_rdp = DEPCA_REG_RDP;
1392 sc->lance_rap = DEPCA_REG_RAP;
1393 sc->lance_csr3 = LN_CSR3_ALE;
1394 sc->le_mctbl = sc->lance_initb.ln_multi_mask;
1395 sc->le_mcmask = LN_MC_MASK;
1396 LN_SELCSR(sc, LN_CSR0);
1397 LN_WRCSR(sc, LN_CSR0_STOP);
1399 if (idx < DEPCA_DE200) {
1400 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) & ~DEPCA_NICSR_AAC);
1401 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) | DEPCA_NICSR_AAC);
1404 if (le_read_macaddr(sc, DEPCA_REG_ADDRROM, idx == DEPCA_CLASSIC) < 0)
1407 MEMCPY(sc->le_ac.ac_enaddr, sc->le_hwaddr, 6);
1409 * Renable shared RAM.
1411 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) | DEPCA_NICSR_SHE);
1413 le_intrvec[sc->le_if.if_unit] = depca_intr;
1414 if (!lance_init_adapmem(sc))
1417 sc->if_reset = lance_reset;
1418 sc->if_init = lance_init;
1419 sc->le_if.if_start = lance_start;
1420 DEPCA_WRNICSR(sc, DEPCA_NICSR_SHE | DEPCA_NICSR_ENABINTR);
1423 LN_STAT(low_txfree = sc->lance_txinfo.ri_max);
1424 LN_STAT(low_txheapsize = 0xFFFFFFFF);
1425 *msize = sc->lance_ramsize;
1426 return DEPCA_IOSPACE;
1433 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) ^ DEPCA_NICSR_LED);
1438 * Here's as good a place to describe our paritioning of the
1439 * LANCE shared RAM space. (NOTE: this driver does not yet support
1440 * the concept of a LANCE being able to DMA).
1442 * First is the 24 (00:23) bytes for LANCE Initialization Block
1443 * Next are the recieve descriptors. The number is calculated from
1444 * how many LN_BUFSIZE buffers we can allocate (this number must
1445 * be a power of 2). Next are the transmit descriptors. The amount
1446 * of transmit descriptors is derived from the size of the RAM
1447 * divided by 1K. Now come the receive buffers (one for each receive
1448 * descriptor). Finally is the transmit heap. (no fixed buffers are
1449 * allocated so as to make the most use of the limited space).
1455 lance_addr_t rxbufoffset;
1456 lance_addr_t rxdescoffset, txdescoffset;
1457 unsigned rxdescs, txdescs;
1460 * First calculate how many descriptors we heap.
1461 * Note this assumes the ramsize is a power of two.
1463 sc->lance_rxbufsize = LN_BUFSIZE;
1465 while (rxdescs * sc->lance_rxbufsize < sc->lance_ramsize)
1468 if (rxdescs > LN_DESC_MAX) {
1469 sc->lance_rxbufsize *= rxdescs / LN_DESC_MAX;
1470 rxdescs = LN_DESC_MAX;
1472 txdescs = sc->lance_ramsize / LN_TXDESC_RATIO;
1473 if (txdescs > LN_DESC_MAX)
1474 txdescs = LN_DESC_MAX;
1477 * Now calculate where everything goes in memory
1479 rxdescoffset = sizeof(ln_initb_t);
1480 txdescoffset = rxdescoffset + sizeof(ln_desc_t) * rxdescs;
1481 rxbufoffset = txdescoffset + sizeof(ln_desc_t) * txdescs;
1483 sc->le_mctbl = (le_mcbits_t *) sc->lance_initb.ln_multi_mask;
1485 * Remember these for debugging.
1487 sc->lance_raminitb = (ln_initb_t *) sc->le_membase;
1488 sc->lance_ramdesc = (ln_desc_t *) (sc->le_membase + rxdescoffset);
1491 * Initialize the rings.
1493 if (!lance_init_ring(sc, &sc->lance_initb.ln_rxring, &sc->lance_rxinfo,
1494 rxdescs, rxbufoffset, rxdescoffset))
1496 sc->lance_rxinfo.ri_heap = rxbufoffset;
1497 sc->lance_rxinfo.ri_heapend = rxbufoffset + sc->lance_rxbufsize * rxdescs;
1499 if (!lance_init_ring(sc, &sc->lance_initb.ln_txring, &sc->lance_txinfo,
1500 txdescs, 0, txdescoffset))
1502 sc->lance_txinfo.ri_heap = sc->lance_rxinfo.ri_heapend;
1503 sc->lance_txinfo.ri_heapend = sc->lance_ramsize;
1506 * Set CSR1 and CSR2 to the address of the init block (which
1507 * for us is always 0.
1509 sc->lance_csr1 = LN_ADDR_LO(0 + sc->lance_ramoffset);
1510 sc->lance_csr2 = LN_ADDR_HI(0 + sc->lance_ramoffset);
1520 lance_addr_t bufoffset,
1521 lance_addr_t descoffset)
1523 lance_descinfo_t *di;
1526 * Initialize the ring pointer in the LANCE InitBlock
1528 rp->r_addr_lo = LN_ADDR_LO(descoffset + sc->lance_ramoffset);
1529 rp->r_addr_hi = LN_ADDR_HI(descoffset + sc->lance_ramoffset);
1530 rp->r_log2_size = ffs(ndescs) - 1;
1533 * Allocate the ring entry descriptors and initialize
1534 * our ring information data structure. All these are
1535 * our copies and do not live in the LANCE RAM.
1537 ri->ri_first = (lance_descinfo_t *) malloc(ndescs * sizeof(*di), M_DEVBUF, M_NOWAIT);
1538 if (ri->ri_first == NULL) {
1539 printf("lance_init_ring: malloc(%d) failed\n", ndescs * sizeof(*di));
1542 ri->ri_free = ri->ri_max = ndescs;
1543 ri->ri_last = ri->ri_first + ri->ri_max;
1544 for (di = ri->ri_first; di < ri->ri_last; di++) {
1545 di->di_addr = sc->le_membase + descoffset;
1548 di->di_bufaddr = bufoffset;
1549 di->di_buflen = sc->lance_rxbufsize;
1550 bufoffset += sc->lance_rxbufsize;
1552 descoffset += sizeof(ln_desc_t);
1562 printf("%s%d: %s: nicsr=%04x",
1563 sc->le_if.if_name, sc->le_if.if_unit,
1564 id, DEPCA_RDNICSR(sc));
1565 LN_SELCSR(sc, LN_CSR0); printf(" csr0=%04x", LN_RDCSR(sc));
1566 LN_SELCSR(sc, LN_CSR1); printf(" csr1=%04x", LN_RDCSR(sc));
1567 LN_SELCSR(sc, LN_CSR2); printf(" csr2=%04x", LN_RDCSR(sc));
1568 LN_SELCSR(sc, LN_CSR3); printf(" csr3=%04x\n", LN_RDCSR(sc));
1569 LN_SELCSR(sc, LN_CSR0);
1576 le_softc_t *sc = &le_softc[unit];
1577 register int cnt, csr;
1579 /* lance_dumpcsrs(sc, "lance_reset: start"); */
1581 LN_WRCSR(sc, LN_RDCSR(sc) & ~LN_CSR0_ENABINTR);
1582 LN_WRCSR(sc, LN_CSR0_STOP);
1585 sc->le_flags &= ~IFF_UP;
1586 sc->le_if.if_flags &= ~(IFF_UP|IFF_RUNNING);
1588 le_multi_filter(sc); /* initialize the multicast table */
1589 if ((sc->le_flags | sc->le_if.if_flags) & IFF_ALLMULTI) {
1590 sc->lance_initb.ln_multi_mask[0] = 0xFFFFU;
1591 sc->lance_initb.ln_multi_mask[1] = 0xFFFFU;
1592 sc->lance_initb.ln_multi_mask[2] = 0xFFFFU;
1593 sc->lance_initb.ln_multi_mask[3] = 0xFFFFU;
1595 sc->lance_initb.ln_physaddr[0] = ((u_short *) sc->le_ac.ac_enaddr)[0];
1596 sc->lance_initb.ln_physaddr[1] = ((u_short *) sc->le_ac.ac_enaddr)[1];
1597 sc->lance_initb.ln_physaddr[2] = ((u_short *) sc->le_ac.ac_enaddr)[2];
1598 if (sc->le_if.if_flags & IFF_PROMISC) {
1599 sc->lance_initb.ln_mode |= LN_MODE_PROMISC;
1601 sc->lance_initb.ln_mode &= ~LN_MODE_PROMISC;
1604 * We force the init block to be at the start
1605 * of the LANCE's RAM buffer.
1607 LN_COPYTO(sc, &sc->lance_initb, sc->le_membase, sizeof(sc->lance_initb));
1608 LN_SELCSR(sc, LN_CSR1); LN_WRCSR(sc, sc->lance_csr1);
1609 LN_SELCSR(sc, LN_CSR2); LN_WRCSR(sc, sc->lance_csr2);
1610 LN_SELCSR(sc, LN_CSR3); LN_WRCSR(sc, sc->lance_csr3);
1612 /* lance_dumpcsrs(sc, "lance_reset: preinit"); */
1615 * clear INITDONE and INIT the chip
1617 LN_SELCSR(sc, LN_CSR0);
1618 LN_WRCSR(sc, LN_CSR0_INIT|LN_CSR0_INITDONE);
1623 if (((csr = LN_RDCSR(sc)) & LN_CSR0_INITDONE) != 0)
1628 if ((csr & LN_CSR0_INITDONE) == 0) { /* make sure we got out okay */
1629 lance_dumpcsrs(sc, "lance_reset: reset failure");
1631 /* lance_dumpcsrs(sc, "lance_reset: end"); */
1632 sc->le_if.if_flags |= IFF_UP;
1633 sc->le_flags |= IFF_UP;
1641 le_softc_t *sc = &le_softc[unit];
1643 lance_descinfo_t *di;
1647 if (sc->le_if.if_flags & IFF_RUNNING) {
1651 * If we were running, requeue any pending transmits.
1653 ri = &sc->lance_txinfo;
1654 di = ri->ri_nextout;
1655 while (ri->ri_free < ri->ri_max) {
1656 if (--di == ri->ri_first)
1657 di = ri->ri_nextout - 1;
1658 if (di->di_mbuf == NULL)
1660 IF_PREPEND(&sc->le_if.if_snd, di->di_mbuf);
1669 * Reset the transmit ring. Make sure we own all the buffers.
1670 * Also reset the transmit heap.
1672 sc->le_if.if_flags &= ~IFF_OACTIVE;
1673 ri = &sc->lance_txinfo;
1674 for (di = ri->ri_first; di < ri->ri_last; di++) {
1675 if (di->di_mbuf != NULL) {
1676 m_freem(di->di_mbuf);
1680 desc.d_addr_lo = LN_ADDR_LO(ri->ri_heap + sc->lance_ramoffset);
1681 desc.d_addr_hi = LN_ADDR_HI(ri->ri_heap + sc->lance_ramoffset);
1683 LN_PUTDESC(sc, &desc, di->di_addr);
1685 ri->ri_nextin = ri->ri_nextout = ri->ri_first;
1686 ri->ri_free = ri->ri_max;
1687 ri->ri_outptr = ri->ri_heap;
1688 ri->ri_outsize = ri->ri_heapend - ri->ri_heap;
1690 ri = &sc->lance_rxinfo;
1691 desc.d_flag = LN_DFLAG_OWNER;
1692 desc.d_buflen = 0 - sc->lance_rxbufsize;
1693 for (di = ri->ri_first; di < ri->ri_last; di++) {
1694 desc.d_addr_lo = LN_ADDR_LO(di->di_bufaddr + sc->lance_ramoffset);
1695 desc.d_addr_hi = LN_ADDR_HI(di->di_bufaddr + sc->lance_ramoffset);
1696 LN_PUTDESC(sc, &desc, di->di_addr);
1698 ri->ri_nextin = ri->ri_nextout = ri->ri_first;
1699 ri->ri_outptr = ri->ri_heap;
1700 ri->ri_outsize = ri->ri_heapend - ri->ri_heap;
1703 if (sc->le_if.if_flags & IFF_UP) {
1704 sc->le_if.if_flags |= IFF_RUNNING;
1705 LN_WRCSR(sc, LN_CSR0_START|LN_CSR0_INITDONE|LN_CSR0_ENABINTR);
1706 /* lance_dumpcsrs(sc, "lance_init: up"); */
1707 lance_start(&sc->le_if);
1709 /* lance_dumpcsrs(sc, "lance_init: down"); */
1710 sc->le_if.if_flags &= ~IFF_RUNNING;
1720 oldcsr = LN_RDCSR(sc);
1721 oldcsr &= ~LN_CSR0_ENABINTR;
1722 LN_WRCSR(sc, oldcsr);
1723 LN_WRCSR(sc, LN_CSR0_ENABINTR);
1725 if (oldcsr & LN_CSR0_ERRSUM) {
1726 if (oldcsr & LN_CSR0_MISS) {
1728 * LN_CSR0_MISS is signaled when the LANCE receiver
1729 * loses a packet because it doesn't own a receive
1730 * descriptor. Rev. D LANCE chips, which are no
1731 * longer used, require a chip reset as described
1734 LN_STAT(rx_misses++);
1736 if (oldcsr & LN_CSR0_MEMERROR) {
1737 LN_STAT(memory_errors++);
1738 if (oldcsr & (LN_CSR0_RXON|LN_CSR0_TXON)) {
1739 lance_init(sc->le_if.if_unit);
1745 if ((oldcsr & LN_CSR0_RXINT) && lance_rx_intr(sc)) {
1746 lance_init(sc->le_if.if_unit);
1750 if (oldcsr & LN_CSR0_TXINT) {
1751 if (lance_tx_intr(sc))
1752 lance_start(&sc->le_if);
1755 if (oldcsr == (LN_CSR0_PENDINTR|LN_CSR0_RXON|LN_CSR0_TXON))
1756 printf("%s%d: lance_intr: stray interrupt\n",
1757 sc->le_if.if_name, sc->le_if.if_unit);
1764 lance_ring_t *ri = &sc->lance_rxinfo;
1765 lance_descinfo_t *eop;
1767 int ndescs, total_len, rxdescs;
1769 LN_STAT(rx_intrs++);
1771 for (rxdescs = 0;;) {
1773 * Now to try to find the end of this packet chain.
1775 for (ndescs = 1, eop = ri->ri_nextin;; ndescs++) {
1777 * If we don't own this descriptor, the packet ain't
1778 * all here so return because we are done.
1780 LN_GETDESC(sc, &desc, eop->di_addr);
1781 if (desc.d_flag & LN_DFLAG_OWNER)
1784 * In case we have missed a packet and gotten the
1785 * LANCE confused, make sure we are pointing at the
1786 * start of a packet. If we aren't, something is really
1787 * strange so reinit the LANCE.
1789 if (desc.d_flag & LN_DFLAG_RxBUFERROR) {
1790 LN_STAT(rx_buferror++);
1793 if ((desc.d_flag & LN_DFLAG_SOP) && eop != ri->ri_nextin) {
1794 LN_STAT(rx_badsop++);
1797 if (desc.d_flag & LN_DFLAG_EOP)
1799 if (++eop == ri->ri_last)
1803 total_len = (desc.d_status & LN_DSTS_RxLENMASK) - 4;
1804 if ((desc.d_flag & LN_DFLAG_RxERRSUM) == 0) {
1806 * Valid Packet -- If the SOP is less than or equal to the EOP
1807 * or the length is less than the receive buffer size, then the
1808 * packet is contiguous in memory and can be copied in one shot.
1809 * Otherwise we need to copy two segments to get the entire
1812 if (ri->ri_nextin <= eop || total_len <= ri->ri_heapend - ri->ri_nextin->di_bufaddr) {
1813 le_input(sc, sc->le_membase + ri->ri_nextin->di_bufaddr,
1814 total_len, total_len, NULL);
1815 LN_STAT(rx_contig++);
1817 le_input(sc, sc->le_membase + ri->ri_nextin->di_bufaddr,
1819 ri->ri_heapend - ri->ri_nextin->di_bufaddr,
1820 sc->le_membase + ri->ri_first->di_bufaddr);
1821 LN_STAT(rx_noncontig++);
1825 * If the packet is bad, increment the
1828 sc->le_if.if_ierrors++;
1829 if (desc.d_flag & LN_DFLAG_RxBADCRC)
1830 LN_STAT(rx_badcrc++);
1831 if (desc.d_flag & LN_DFLAG_RxOVERFLOW)
1832 LN_STAT(rx_badalign++);
1833 if (desc.d_flag & LN_DFLAG_RxFRAMING)
1834 LN_STAT(rx_badframe++);
1836 sc->le_if.if_ipackets++;
1837 LN_STAT(rx_ndescs[ndescs-1]++);
1839 while (ndescs-- > 0) {
1840 LN_SETFLAG(sc, ri->ri_nextin->di_addr, LN_DFLAG_OWNER);
1841 if (++ri->ri_nextin == ri->ri_last)
1842 ri->ri_nextin = ri->ri_first;
1845 /* LN_STAT(rx_intr_descs[rxdescs]++); */
1846 LN_MAXSTAT(rx_intr_hidescs, rxdescs);
1855 le_softc_t *sc = (le_softc_t *) ifp;
1856 struct ifqueue *ifq = &ifp->if_snd;
1857 lance_ring_t *ri = &sc->lance_txinfo;
1858 lance_descinfo_t *di;
1861 struct mbuf *m, *m0;
1864 if ((ifp->if_flags & IFF_RUNNING) == 0)
1873 * Make the packet meets the minimum size for Ethernet.
1874 * The slop is so that we also use an even number of longwards.
1876 len = ETHERMIN + sizeof(struct ether_header);
1877 if (m->m_pkthdr.len > len)
1878 len = m->m_pkthdr.len;
1880 slop = (8 - len) & 3;
1882 * If there are no free ring entries (there must be always
1883 * one owned by the host), or there's not enough space for
1884 * this packet, or this packet would wrap around the end
1885 * of LANCE RAM then wait for the transmits to empty for
1886 * space and ring entries to become available.
1888 if (ri->ri_free == 1 || len + slop > ri->ri_outsize) {
1890 * Try to see if we can free up anything off the transit ring.
1892 if (lance_tx_intr(sc) > 0) {
1893 LN_STAT(tx_drains[0]++);
1897 LN_STAT(tx_nospc[0]++);
1901 if (len + slop > ri->ri_heapend - ri->ri_outptr) {
1903 * Since the packet won't fit in the end of the transmit
1904 * heap, see if there is space at the beginning of the transmit
1905 * heap. If not, try again when there is space.
1907 LN_STAT(tx_orphaned++);
1908 slop += ri->ri_heapend - ri->ri_outptr;
1909 if (len + slop > ri->ri_outsize) {
1910 LN_STAT(tx_nospc[1]++);
1914 * Point to the beginning of the heap
1916 ri->ri_outptr = ri->ri_heap;
1917 LN_STAT(tx_adoptions++);
1921 * Initialize the descriptor (saving the buffer address,
1922 * buffer length, and mbuf) and write the packet out
1925 di = ri->ri_nextout;
1926 di->di_bufaddr = ri->ri_outptr;
1927 di->di_buflen = len + slop;
1929 bp = sc->le_membase + di->di_bufaddr;
1930 for (m0 = m; m0 != NULL; m0 = m0->m_next) {
1931 LN_COPYTO(sc, mtod(m0, caddr_t), bp, m0->m_len);
1935 * Zero out the remainder if needed (< ETHERMIN).
1937 if (m->m_pkthdr.len < len)
1938 LN_ZERO(sc, bp, len - m->m_pkthdr.len);
1941 * Finally, copy out the descriptor and tell the
1942 * LANCE to transmit!.
1944 desc.d_buflen = 0 - len;
1945 desc.d_addr_lo = LN_ADDR_LO(di->di_bufaddr + sc->lance_ramoffset);
1946 desc.d_addr_hi = LN_ADDR_HI(di->di_bufaddr + sc->lance_ramoffset);
1947 desc.d_flag = LN_DFLAG_SOP|LN_DFLAG_EOP|LN_DFLAG_OWNER;
1948 LN_PUTDESC(sc, &desc, di->di_addr);
1949 LN_WRCSR(sc, LN_CSR0_TXDEMAND|LN_CSR0_ENABINTR);
1952 * Do our bookkeeping with our transmit heap.
1953 * (if we wrap, point back to the beginning).
1955 ri->ri_outptr += di->di_buflen;
1956 ri->ri_outsize -= di->di_buflen;
1957 LN_MAXSTAT(high_txoutptr, ri->ri_outptr);
1958 LN_MINSTAT(low_txheapsize, ri->ri_outsize);
1960 if (ri->ri_outptr == ri->ri_heapend)
1961 ri->ri_outptr = ri->ri_heap;
1964 if (++ri->ri_nextout == ri->ri_last)
1965 ri->ri_nextout = ri->ri_first;
1966 LN_MINSTAT(low_txfree, ri->ri_free);
1969 ifp->if_flags |= IFF_OACTIVE;
1978 lance_ring_t *ri = &sc->lance_txinfo;
1981 LN_STAT(tx_intrs++);
1982 for (xmits = 0; ri->ri_free < ri->ri_max; ) {
1985 LN_GETDESC(sc, &desc, ri->ri_nextin->di_addr);
1986 if (desc.d_flag & LN_DFLAG_OWNER)
1989 if (desc.d_flag & (LN_DFLAG_TxONECOLL|LN_DFLAG_TxMULTCOLL))
1990 sc->le_if.if_collisions++;
1991 if (desc.d_flag & LN_DFLAG_TxDEFERRED)
1992 LN_STAT(tx_deferred++);
1993 if (desc.d_flag & LN_DFLAG_TxONECOLL)
1994 LN_STAT(tx_single_collisions++);
1995 if (desc.d_flag & LN_DFLAG_TxMULTCOLL)
1996 LN_STAT(tx_multiple_collisions++);
1998 if (desc.d_flag & LN_DFLAG_TxERRSUM) {
1999 if (desc.d_status & (LN_DSTS_TxUNDERFLOW|LN_DSTS_TxBUFERROR|
2000 LN_DSTS_TxEXCCOLL|LN_DSTS_TxLATECOLL)) {
2001 if (desc.d_status & LN_DSTS_TxEXCCOLL) {
2003 LN_STAT(tx_excessive_collisions++);
2004 if ((tdr = (desc.d_status & LN_DSTS_TxTDRMASK)) > 0) {
2006 printf("%s%d: lance: warning: excessive collisions: TDR %dns (%d-%dm)\n",
2007 sc->le_if.if_name, sc->le_if.if_unit,
2008 tdr, (tdr*99)/1000, (tdr*117)/1000);
2011 if (desc.d_status & LN_DSTS_TxBUFERROR)
2012 LN_STAT(tx_buferror++);
2013 sc->le_if.if_oerrors++;
2014 if ((desc.d_status & LN_DSTS_TxLATECOLL) == 0) {
2015 lance_init(sc->le_if.if_unit);
2018 LN_STAT(tx_late_collisions++);
2022 m_freem(ri->ri_nextin->di_mbuf);
2023 ri->ri_nextin->di_mbuf = NULL;
2024 sc->le_if.if_opackets++;
2026 ri->ri_outsize += ri->ri_nextin->di_buflen;
2027 if (++ri->ri_nextin == ri->ri_last)
2028 ri->ri_nextin = ri->ri_first;
2029 sc->le_if.if_flags &= ~IFF_OACTIVE;
2032 if (ri->ri_free == ri->ri_max)
2033 LN_STAT(tx_emptied++);
2034 /* LN_STAT(tx_intr_descs[xmits]++); */
2035 LN_MAXSTAT(tx_intr_hidescs, xmits);
2038 #endif /* !defined(LE_NOLANCE) */