2 * Copyright (c) 1991 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91
40 #include "opt_auto_eoi.h"
44 #include <sys/param.h>
47 #include <machine/lock.h>
50 #include <sys/systm.h>
51 #include <sys/syslog.h>
53 #include <sys/kernel.h>
54 #include <sys/kthread.h>
55 #include <sys/malloc.h>
56 #include <sys/module.h>
57 #include <sys/mutex.h>
58 #include <sys/unistd.h>
59 #include <sys/errno.h>
60 #include <sys/interrupt.h>
61 #include <machine/md_var.h>
62 #include <machine/segments.h>
66 #include <machine/smptests.h> /** FAST_HI */
67 #include <machine/smp.h>
68 #include <machine/resource.h>
71 #include <pc98/pc98/pc98.h>
72 #include <pc98/pc98/pc98_machdep.h>
73 #include <pc98/pc98/epsonio.h>
75 #include <i386/isa/isa.h>
77 #include <i386/isa/icu.h>
80 #include <isa/isavar.h>
82 #include <i386/isa/intr_machdep.h>
83 #include <sys/interrupt.h>
85 #include <machine/clock.h>
89 #include <i386/isa/mca_machdep.h>
95 u_long *intr_countp[ICU_LEN]; /* pointers to interrupt counters */
96 driver_intr_t *intr_handler[ICU_LEN]; /* first level interrupt handler */
97 struct ithd *ithds[ICU_LEN]; /* real interrupt handler */
98 void *intr_unit[ICU_LEN];
100 static inthand_t *fastintr[ICU_LEN] = {
101 &IDTVEC(fastintr0), &IDTVEC(fastintr1),
102 &IDTVEC(fastintr2), &IDTVEC(fastintr3),
103 &IDTVEC(fastintr4), &IDTVEC(fastintr5),
104 &IDTVEC(fastintr6), &IDTVEC(fastintr7),
105 &IDTVEC(fastintr8), &IDTVEC(fastintr9),
106 &IDTVEC(fastintr10), &IDTVEC(fastintr11),
107 &IDTVEC(fastintr12), &IDTVEC(fastintr13),
108 &IDTVEC(fastintr14), &IDTVEC(fastintr15),
110 &IDTVEC(fastintr16), &IDTVEC(fastintr17),
111 &IDTVEC(fastintr18), &IDTVEC(fastintr19),
112 &IDTVEC(fastintr20), &IDTVEC(fastintr21),
113 &IDTVEC(fastintr22), &IDTVEC(fastintr23),
114 &IDTVEC(fastintr24), &IDTVEC(fastintr25),
115 &IDTVEC(fastintr26), &IDTVEC(fastintr27),
116 &IDTVEC(fastintr28), &IDTVEC(fastintr29),
117 &IDTVEC(fastintr30), &IDTVEC(fastintr31),
121 static inthand_t *slowintr[ICU_LEN] = {
122 &IDTVEC(intr0), &IDTVEC(intr1), &IDTVEC(intr2), &IDTVEC(intr3),
123 &IDTVEC(intr4), &IDTVEC(intr5), &IDTVEC(intr6), &IDTVEC(intr7),
124 &IDTVEC(intr8), &IDTVEC(intr9), &IDTVEC(intr10), &IDTVEC(intr11),
125 &IDTVEC(intr12), &IDTVEC(intr13), &IDTVEC(intr14), &IDTVEC(intr15),
127 &IDTVEC(intr16), &IDTVEC(intr17), &IDTVEC(intr18), &IDTVEC(intr19),
128 &IDTVEC(intr20), &IDTVEC(intr21), &IDTVEC(intr22), &IDTVEC(intr23),
129 &IDTVEC(intr24), &IDTVEC(intr25), &IDTVEC(intr26), &IDTVEC(intr27),
130 &IDTVEC(intr28), &IDTVEC(intr29), &IDTVEC(intr30), &IDTVEC(intr31),
134 static driver_intr_t isa_strayintr;
137 #define NMI_PARITY 0x04
138 #define NMI_EPARITY 0x02
140 #define NMI_PARITY (1 << 7)
141 #define NMI_IOCHAN (1 << 6)
142 #define ENMI_WATCHDOG (1 << 7)
143 #define ENMI_BUSTIMER (1 << 6)
144 #define ENMI_IOSTATUS (1 << 5)
148 * Bus attachment for the ISA PIC.
150 static struct isa_pnp_id atpic_ids[] = {
151 { 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
156 atpic_probe(device_t dev)
160 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids)) <= 0)
166 * In the APIC_IO case we might be granted IRQ 2, as this is typically
167 * consumed by chaining between the two PIC components. If we're using
168 * the APIC, however, this may not be the case, and as such we should
169 * free the resource. (XXX untested)
171 * The generic ISA attachment code will handle allocating any other resources
172 * that we don't explicitly claim here.
175 atpic_attach(device_t dev)
179 struct resource *res;
181 /* try to allocate our IRQ and then free it */
183 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 0);
185 bus_release_resource(dev, SYS_RES_IRQ, rid, res);
190 static device_method_t atpic_methods[] = {
191 /* Device interface */
192 DEVMETHOD(device_probe, atpic_probe),
193 DEVMETHOD(device_attach, atpic_attach),
194 DEVMETHOD(device_detach, bus_generic_detach),
195 DEVMETHOD(device_shutdown, bus_generic_shutdown),
196 DEVMETHOD(device_suspend, bus_generic_suspend),
197 DEVMETHOD(device_resume, bus_generic_resume),
201 static driver_t atpic_driver = {
207 static devclass_t atpic_devclass;
209 DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0);
212 * Handle a NMI, possibly a machine check.
213 * return true to panic system, false to ignore.
221 int port = inb(0x33);
223 log(LOG_CRIT, "NMI PC98 port = %x\n", port);
224 if (epson_machine_id == 0x20)
225 epson_outb(0xc16, epson_inb(0xc16) | 0x1);
226 if (port & NMI_PARITY) {
227 log(LOG_CRIT, "BASE RAM parity error, likely hardware failure.");
229 } else if (port & NMI_EPARITY) {
230 log(LOG_CRIT, "EXTENDED RAM parity error, likely hardware failure.");
233 log(LOG_CRIT, "\nNMI Resume ??\n");
236 int isa_port = inb(0x61);
237 int eisa_port = inb(0x461);
239 log(LOG_CRIT, "NMI ISA %x, EISA %x\n", isa_port, eisa_port);
241 if (MCA_system && mca_bus_nmi())
245 if (isa_port & NMI_PARITY) {
246 log(LOG_CRIT, "RAM parity error, likely hardware failure.");
250 if (isa_port & NMI_IOCHAN) {
251 log(LOG_CRIT, "I/O channel check, likely hardware failure.");
256 * On a real EISA machine, this will never happen. However it can
257 * happen on ISA machines which implement XT style floating point
258 * error handling (very rare). Save them from a meaningless panic.
260 if (eisa_port == 0xff)
263 if (eisa_port & ENMI_WATCHDOG) {
264 log(LOG_CRIT, "EISA watchdog timer expired, likely hardware failure.");
268 if (eisa_port & ENMI_BUSTIMER) {
269 log(LOG_CRIT, "EISA bus timeout, likely hardware failure.");
273 if (eisa_port & ENMI_IOSTATUS) {
274 log(LOG_CRIT, "EISA I/O port status error.");
282 * Create a default interrupt table to avoid problems caused by
283 * spurious interrupts during configuration of kernel, then setup
284 * interrupt control unit.
292 for (i = 0; i < ICU_LEN; i++)
293 icu_unset(i, (driver_intr_t *)NULL);
295 /* initialize 8259's */
298 outb(IO_ICU1, 0x19); /* reset; program device, four bytes */
301 outb(IO_ICU1, 0x11); /* reset; program device, four bytes */
303 outb(IO_ICU1+ICU_IMR_OFFSET, NRSVIDT); /* starting at this vector index */
304 outb(IO_ICU1+ICU_IMR_OFFSET, IRQ_SLAVE); /* slave on line 7 */
307 outb(IO_ICU1+ICU_IMR_OFFSET, 0x1f); /* (master) auto EOI, 8086 mode */
309 outb(IO_ICU1+ICU_IMR_OFFSET, 0x1d); /* (master) 8086 mode */
313 outb(IO_ICU1+ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */
315 outb(IO_ICU1+ICU_IMR_OFFSET, 1); /* 8086 mode */
318 outb(IO_ICU1+ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */
319 outb(IO_ICU1, 0x0a); /* default to IRR on read */
321 outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */
326 outb(IO_ICU2, 0x19); /* reset; program device, four bytes */
329 outb(IO_ICU2, 0x11); /* reset; program device, four bytes */
331 outb(IO_ICU2+ICU_IMR_OFFSET, NRSVIDT+8); /* staring at this vector index */
332 outb(IO_ICU2+ICU_IMR_OFFSET, ICU_SLAVEID); /* my slave id is 7 */
334 outb(IO_ICU2+ICU_IMR_OFFSET,9); /* 8086 mode */
337 outb(IO_ICU2+ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */
339 outb(IO_ICU2+ICU_IMR_OFFSET,1); /* 8086 mode */
342 outb(IO_ICU2+ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */
343 outb(IO_ICU2, 0x0a); /* default to IRR on read */
347 * Caught a stray interrupt, notify
350 isa_strayintr(vcookiep)
353 int intr = (void **)vcookiep - &intr_unit[0];
356 * XXX TODO print a different message for #7 if it is for a
357 * glitch. Glitches can be distinguished from real #7's by
358 * testing that the in-service bit is _not_ set. The test
359 * must be done before sending an EOI so it can't be done if
360 * we are using AUTO_EOI_1.
362 if (intrcnt[1 + intr] <= 5)
363 log(LOG_ERR, "stray irq %d\n", intr);
364 if (intrcnt[1 + intr] == 5)
366 "too many stray irq %d's; not logging any more\n", intr);
371 * Return a bitmap of the current interrupt requests. This is 8259-specific
372 * and is only suitable for use at probe time.
382 return ((irr2 << 8) | irr1);
387 * Update intrnames array with the specified name. This is used by
388 * vmstat(8) and the like.
391 update_intrname(int intr, char *name)
395 int name_index, off, strayintr;
398 * Initialise strings for bitbucket and stray interrupt counters.
399 * These have statically allocated indices 0 and 1 through ICU_LEN.
401 if (intrnames[0] == '\0') {
402 off = sprintf(intrnames, "???") + 1;
403 for (strayintr = 0; strayintr < ICU_LEN; strayintr++)
404 off += sprintf(intrnames + off, "stray irq%d",
410 if (snprintf(buf, sizeof(buf), "%s irq%d", name, intr) >= sizeof(buf))
414 * Search for `buf' in `intrnames'. In the usual case when it is
415 * not found, append it to the end if there is enough space (the \0
416 * terminator for the previous string, if any, becomes a separator).
418 for (cp = intrnames, name_index = 0;
419 cp != eintrnames && name_index < NR_INTRNAMES;
420 cp += strlen(cp) + 1, name_index++) {
422 if (strlen(buf) >= eintrnames - cp)
427 if (strcmp(cp, buf) == 0)
432 printf("update_intrname: counting %s irq%d as %s\n", name, intr,
436 intr_countp[intr] = &intrcnt[name_index];
440 icu_setup(int intr, driver_intr_t *handler, void *arg, int flags)
443 int select; /* the select register is 8 bits */
445 u_int32_t value; /* the window register is 32 bits */
450 if ((u_int)intr >= ICU_LEN) /* no 8259 SLAVE to ignore */
452 if ((u_int)intr >= ICU_LEN || intr == ICU_SLAVEID)
454 if (intr_handler[intr] != isa_strayintr)
459 intr_handler[intr] = handler;
460 intr_unit[intr] = arg;
462 if (flags & INTR_FAST) {
463 vector = TPR_FAST_INTS + intr;
464 setidt(vector, fastintr[intr],
465 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
468 vector = TPR_SLOW_INTS + intr;
469 #ifdef APIC_INTR_REORDER
470 #ifdef APIC_INTR_HIGHPRI_CLOCK
471 /* XXX: Hack (kludge?) for more accurate clock. */
472 if (intr == apic_8254_intr || intr == 8) {
473 vector = TPR_FAST_INTS + intr;
477 setidt(vector, slowintr[intr],
478 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
480 #ifdef APIC_INTR_REORDER
481 set_lapic_isrloc(intr, vector);
484 * Reprogram the vector in the IO APIC.
486 if (int_to_apicintpin[intr].ioapic >= 0) {
487 select = int_to_apicintpin[intr].redirindex;
488 value = io_apic_read(int_to_apicintpin[intr].ioapic,
489 select) & ~IOART_INTVEC;
490 io_apic_write(int_to_apicintpin[intr].ioapic,
491 select, value | vector);
494 setidt(ICU_OFFSET + intr,
495 flags & INTR_FAST ? fastintr[intr] : slowintr[intr],
496 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
504 * Dissociate an interrupt handler from an IRQ and set the handler to
505 * the stray interrupt handler. The 'handler' parameter is used only
506 * for consistency checking.
509 icu_unset(intr, handler)
511 driver_intr_t *handler;
515 if ((u_int)intr >= ICU_LEN || handler != intr_handler[intr])
521 intr_countp[intr] = &intrcnt[1 + intr];
522 intr_handler[intr] = isa_strayintr;
523 intr_unit[intr] = &intr_unit[intr];
525 /* XXX how do I re-create dvp here? */
526 setidt(flags & INTR_FAST ? TPR_FAST_INTS + intr : TPR_SLOW_INTS + intr,
527 slowintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
529 #ifdef APIC_INTR_REORDER
530 set_lapic_isrloc(intr, ICU_OFFSET + intr);
532 setidt(ICU_OFFSET + intr, slowintr[intr], SDT_SYS386IGT, SEL_KPL,
533 GSEL(GCODE_SEL, SEL_KPL));
540 inthand_add(const char *name, int irq, driver_intr_t handler, void *arg,
543 struct ithd *ithd = ithds[irq]; /* descriptor for the IRQ */
544 struct intrhand *head; /* chain of handlers for IRQ */
545 struct intrhand *idesc; /* descriptor for this handler */
546 struct proc *p; /* interrupt thread */
549 if (name == NULL) /* no name? */
550 panic ("anonymous interrupt");
551 if (ithd == NULL || ithd->it_ih == NULL) {
552 /* first handler for this irq. */
554 ithd = malloc(sizeof (struct ithd), M_DEVBUF,
562 * If we have a fast interrupt, we need to set the
563 * handler address directly. Do that below. For a
564 * slow interrupt, we don't need to know more details,
565 * so do it here because it's tidier.
567 if ((flags & INTR_FAST) == 0) {
569 * Only create a kernel thread if we don't already
572 if (ithd->it_proc == NULL) {
573 errcode = kthread_create(ithd_loop, NULL, &p,
574 RFSTOPPED | RFHIGHPID, "irq%d: %s", irq,
577 panic("inthand_add: Can't create "
579 p->p_intr_nesting_level = 1;
580 p->p_rtprio.type = RTP_PRIO_ITHREAD;
581 p->p_stat = SWAIT; /* we're idle */
583 /* Put in linkages. */
587 snprintf(ithd->it_proc->p_comm, MAXCOMLEN,
588 "irq%d: %s", irq, name);
589 p->p_rtprio.prio = pri;
592 * The interrupt process must be in place, but
593 * not necessarily schedulable, before we
594 * initialize the ICU, since it may cause an
595 * immediate interrupt.
597 if (icu_setup(irq, &sched_ithd, arg, flags) != 0)
598 panic("inthand_add: Can't initialize ICU");
600 } else if ((flags & INTR_EXCL) != 0
601 || (ithd->it_ih->ih_flags & INTR_EXCL) != 0) {
603 * We can't append the new handler if either
604 * list ithd or new handler do not allow
605 * interrupts to be shared.
608 printf("\tdevice combination %s and %s "
609 "doesn't support shared irq%d\n",
610 ithd->it_ih->ih_name, name, irq);
612 } else if (flags & INTR_FAST) {
613 /* We can only have one fast interrupt by itself. */
615 printf("\tCan't add fast interrupt %s"
616 " to normal interrupt %s on irq%d",
617 name, ithd->it_ih->ih_name, irq);
619 } else { /* update p_comm */
621 if (strlen(p->p_comm) + strlen(name) < MAXCOMLEN) {
622 strcat(p->p_comm, " ");
623 strcat(p->p_comm, name);
624 } else if (strlen(p->p_comm) == MAXCOMLEN)
625 p->p_comm[MAXCOMLEN - 1] = '+';
627 strcat(p->p_comm, "+");
629 idesc = malloc(sizeof (struct intrhand), M_DEVBUF, M_WAITOK | M_ZERO);
633 idesc->ih_handler = handler;
634 idesc->ih_argument = arg;
635 idesc->ih_flags = flags;
636 idesc->ih_ithd = ithd;
638 idesc->ih_name = malloc(strlen(name) + 1, M_DEVBUF, M_WAITOK);
639 if (idesc->ih_name == NULL) {
640 free(idesc, M_DEVBUF);
643 strcpy(idesc->ih_name, name);
645 /* Slow interrupts got set up above. */
646 if ((flags & INTR_FAST)
647 && (icu_setup(irq, idesc->ih_handler, idesc->ih_argument,
648 idesc->ih_flags) != 0) ) {
650 printf("\tinthand_add(irq%d) failed, result=%d\n",
652 free(idesc->ih_name, M_DEVBUF);
653 free(idesc, M_DEVBUF);
656 head = ithd->it_ih; /* look at chain of handlers */
658 while (head->ih_next != NULL)
659 head = head->ih_next; /* find the end */
660 head->ih_next = idesc; /* hook it in there */
662 ithd->it_ih = idesc; /* put it up front */
663 update_intrname(irq, idesc->ih_name);
668 * Deactivate and remove linked list the interrupt handler descriptor
669 * data connected created by an earlier call of inthand_add(), then
670 * adjust the interrupt masks if necessary.
672 * Return the memory held by the interrupt handler descriptor data
673 * structure to the system. First ensure the handler is not actively
678 inthand_remove(struct intrhand *idesc)
680 struct ithd *ithd; /* descriptor for the IRQ */
681 struct intrhand *ih; /* chain of handlers */
685 ithd = idesc->ih_ithd;
688 if (ih == idesc) /* first in the chain */
689 ithd->it_ih = idesc->ih_next; /* unhook it */
692 && (ih->ih_next != idesc) )
694 if (ih->ih_next != idesc)
696 ih->ih_next = ih->ih_next->ih_next;
699 if (ithd->it_ih == NULL) { /* no handlers left, */
700 icu_unset(ithd->irq, idesc->ih_handler);
701 ithds[ithd->irq] = NULL;
703 if ((idesc->ih_flags & INTR_FAST) == 0) {
704 mtx_enter(&sched_lock, MTX_SPIN);
705 if (ithd->it_proc->p_stat == SWAIT) {
706 ithd->it_proc->p_intr_nesting_level = 0;
707 ithd->it_proc->p_stat = SRUN;
708 setrunqueue(ithd->it_proc);
710 * We don't do an ast here because we really
711 * don't care when it runs next.
713 * XXX: should we lower the threads priority?
716 mtx_exit(&sched_lock, MTX_SPIN);
719 free(idesc->ih_name, M_DEVBUF);
720 free(idesc, M_DEVBUF);