2 * Copyright (c) 1991 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91
40 #include "opt_auto_eoi.h"
44 #include <sys/param.h>
47 #include <machine/lock.h>
50 #include <sys/systm.h>
51 #include <sys/syslog.h>
53 #include <sys/kernel.h>
54 #include <sys/kthread.h>
55 #include <sys/malloc.h>
56 #include <sys/module.h>
57 #include <sys/mutex.h>
58 #include <sys/unistd.h>
59 #include <sys/errno.h>
60 #include <sys/interrupt.h>
61 #include <machine/md_var.h>
62 #include <machine/segments.h>
66 #include <machine/smp.h>
67 #include <machine/smptests.h> /** FAST_HI */
68 #include <machine/resource.h>
71 #include <pc98/pc98/pc98.h>
72 #include <pc98/pc98/pc98_machdep.h>
73 #include <pc98/pc98/epsonio.h>
75 #include <i386/isa/isa.h>
77 #include <i386/isa/icu.h>
80 #include <isa/isavar.h>
82 #include <i386/isa/intr_machdep.h>
83 #include <sys/interrupt.h>
85 #include <machine/clock.h>
90 #include <i386/isa/mca_machdep.h>
96 u_long *intr_countp[ICU_LEN]; /* pointers to interrupt counters */
97 driver_intr_t *intr_handler[ICU_LEN]; /* first level interrupt handler */
98 struct ithd *ithds[ICU_LEN]; /* real interrupt handler */
99 void *intr_unit[ICU_LEN];
101 static inthand_t *fastintr[ICU_LEN] = {
102 &IDTVEC(fastintr0), &IDTVEC(fastintr1),
103 &IDTVEC(fastintr2), &IDTVEC(fastintr3),
104 &IDTVEC(fastintr4), &IDTVEC(fastintr5),
105 &IDTVEC(fastintr6), &IDTVEC(fastintr7),
106 &IDTVEC(fastintr8), &IDTVEC(fastintr9),
107 &IDTVEC(fastintr10), &IDTVEC(fastintr11),
108 &IDTVEC(fastintr12), &IDTVEC(fastintr13),
109 &IDTVEC(fastintr14), &IDTVEC(fastintr15),
111 &IDTVEC(fastintr16), &IDTVEC(fastintr17),
112 &IDTVEC(fastintr18), &IDTVEC(fastintr19),
113 &IDTVEC(fastintr20), &IDTVEC(fastintr21),
114 &IDTVEC(fastintr22), &IDTVEC(fastintr23),
118 static inthand_t *slowintr[ICU_LEN] = {
119 &IDTVEC(intr0), &IDTVEC(intr1), &IDTVEC(intr2), &IDTVEC(intr3),
120 &IDTVEC(intr4), &IDTVEC(intr5), &IDTVEC(intr6), &IDTVEC(intr7),
121 &IDTVEC(intr8), &IDTVEC(intr9), &IDTVEC(intr10), &IDTVEC(intr11),
122 &IDTVEC(intr12), &IDTVEC(intr13), &IDTVEC(intr14), &IDTVEC(intr15),
124 &IDTVEC(intr16), &IDTVEC(intr17), &IDTVEC(intr18), &IDTVEC(intr19),
125 &IDTVEC(intr20), &IDTVEC(intr21), &IDTVEC(intr22), &IDTVEC(intr23),
129 static driver_intr_t isa_strayintr;
132 #define NMI_PARITY 0x04
133 #define NMI_EPARITY 0x02
135 #define NMI_PARITY (1 << 7)
136 #define NMI_IOCHAN (1 << 6)
137 #define ENMI_WATCHDOG (1 << 7)
138 #define ENMI_BUSTIMER (1 << 6)
139 #define ENMI_IOSTATUS (1 << 5)
143 * Bus attachment for the ISA PIC.
145 static struct isa_pnp_id atpic_ids[] = {
146 { 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
151 atpic_probe(device_t dev)
155 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids)) <= 0)
161 * In the APIC_IO case we might be granted IRQ 2, as this is typically
162 * consumed by chaining between the two PIC components. If we're using
163 * the APIC, however, this may not be the case, and as such we should
164 * free the resource. (XXX untested)
166 * The generic ISA attachment code will handle allocating any other resources
167 * that we don't explicitly claim here.
170 atpic_attach(device_t dev)
174 struct resource *res;
176 /* try to allocate our IRQ and then free it */
178 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 0);
180 bus_release_resource(dev, SYS_RES_IRQ, rid, res);
185 static device_method_t atpic_methods[] = {
186 /* Device interface */
187 DEVMETHOD(device_probe, atpic_probe),
188 DEVMETHOD(device_attach, atpic_attach),
189 DEVMETHOD(device_detach, bus_generic_detach),
190 DEVMETHOD(device_shutdown, bus_generic_shutdown),
191 DEVMETHOD(device_suspend, bus_generic_suspend),
192 DEVMETHOD(device_resume, bus_generic_resume),
196 static driver_t atpic_driver = {
202 static devclass_t atpic_devclass;
204 DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0);
207 * Handle a NMI, possibly a machine check.
208 * return true to panic system, false to ignore.
216 int port = inb(0x33);
218 log(LOG_CRIT, "NMI PC98 port = %x\n", port);
219 if (epson_machine_id == 0x20)
220 epson_outb(0xc16, epson_inb(0xc16) | 0x1);
221 if (port & NMI_PARITY) {
222 log(LOG_CRIT, "BASE RAM parity error, likely hardware failure.");
224 } else if (port & NMI_EPARITY) {
225 log(LOG_CRIT, "EXTENDED RAM parity error, likely hardware failure.");
228 log(LOG_CRIT, "\nNMI Resume ??\n");
231 int isa_port = inb(0x61);
232 int eisa_port = inb(0x461);
234 log(LOG_CRIT, "NMI ISA %x, EISA %x\n", isa_port, eisa_port);
236 if (MCA_system && mca_bus_nmi())
240 if (isa_port & NMI_PARITY) {
241 log(LOG_CRIT, "RAM parity error, likely hardware failure.");
245 if (isa_port & NMI_IOCHAN) {
246 log(LOG_CRIT, "I/O channel check, likely hardware failure.");
251 * On a real EISA machine, this will never happen. However it can
252 * happen on ISA machines which implement XT style floating point
253 * error handling (very rare). Save them from a meaningless panic.
255 if (eisa_port == 0xff)
258 if (eisa_port & ENMI_WATCHDOG) {
259 log(LOG_CRIT, "EISA watchdog timer expired, likely hardware failure.");
263 if (eisa_port & ENMI_BUSTIMER) {
264 log(LOG_CRIT, "EISA bus timeout, likely hardware failure.");
268 if (eisa_port & ENMI_IOSTATUS) {
269 log(LOG_CRIT, "EISA I/O port status error.");
277 * Create a default interrupt table to avoid problems caused by
278 * spurious interrupts during configuration of kernel, then setup
279 * interrupt control unit.
287 for (i = 0; i < ICU_LEN; i++)
288 icu_unset(i, (driver_intr_t *)NULL);
290 /* initialize 8259's */
293 outb(IO_ICU1, 0x19); /* reset; program device, four bytes */
296 outb(IO_ICU1, 0x11); /* reset; program device, four bytes */
298 outb(IO_ICU1+ICU_IMR_OFFSET, NRSVIDT); /* starting at this vector index */
299 outb(IO_ICU1+ICU_IMR_OFFSET, IRQ_SLAVE); /* slave on line 7 */
302 outb(IO_ICU1+ICU_IMR_OFFSET, 0x1f); /* (master) auto EOI, 8086 mode */
304 outb(IO_ICU1+ICU_IMR_OFFSET, 0x1d); /* (master) 8086 mode */
308 outb(IO_ICU1+ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */
310 outb(IO_ICU1+ICU_IMR_OFFSET, 1); /* 8086 mode */
313 outb(IO_ICU1+ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */
314 outb(IO_ICU1, 0x0a); /* default to IRR on read */
316 outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */
321 outb(IO_ICU2, 0x19); /* reset; program device, four bytes */
324 outb(IO_ICU2, 0x11); /* reset; program device, four bytes */
326 outb(IO_ICU2+ICU_IMR_OFFSET, NRSVIDT+8); /* staring at this vector index */
327 outb(IO_ICU2+ICU_IMR_OFFSET, ICU_SLAVEID); /* my slave id is 7 */
329 outb(IO_ICU2+ICU_IMR_OFFSET,9); /* 8086 mode */
332 outb(IO_ICU2+ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */
334 outb(IO_ICU2+ICU_IMR_OFFSET,1); /* 8086 mode */
337 outb(IO_ICU2+ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */
338 outb(IO_ICU2, 0x0a); /* default to IRR on read */
342 * Caught a stray interrupt, notify
345 isa_strayintr(vcookiep)
348 int intr = (void **)vcookiep - &intr_unit[0];
351 * XXX TODO print a different message for #7 if it is for a
352 * glitch. Glitches can be distinguished from real #7's by
353 * testing that the in-service bit is _not_ set. The test
354 * must be done before sending an EOI so it can't be done if
355 * we are using AUTO_EOI_1.
357 if (intrcnt[1 + intr] <= 5)
358 log(LOG_ERR, "stray irq %d\n", intr);
359 if (intrcnt[1 + intr] == 5)
361 "too many stray irq %d's; not logging any more\n", intr);
366 * Return a bitmap of the current interrupt requests. This is 8259-specific
367 * and is only suitable for use at probe time.
377 return ((irr2 << 8) | irr1);
382 * Update intrnames array with the specified name. This is used by
383 * vmstat(8) and the like.
386 update_intrname(int intr, char *name)
390 int name_index, off, strayintr;
393 * Initialise strings for bitbucket and stray interrupt counters.
394 * These have statically allocated indices 0 and 1 through ICU_LEN.
396 if (intrnames[0] == '\0') {
397 off = sprintf(intrnames, "???") + 1;
398 for (strayintr = 0; strayintr < ICU_LEN; strayintr++)
399 off += sprintf(intrnames + off, "stray irq%d",
405 if (snprintf(buf, sizeof(buf), "%s irq%d", name, intr) >= sizeof(buf))
409 * Search for `buf' in `intrnames'. In the usual case when it is
410 * not found, append it to the end if there is enough space (the \0
411 * terminator for the previous string, if any, becomes a separator).
413 for (cp = intrnames, name_index = 0;
414 cp != eintrnames && name_index < NR_INTRNAMES;
415 cp += strlen(cp) + 1, name_index++) {
417 if (strlen(buf) >= eintrnames - cp)
422 if (strcmp(cp, buf) == 0)
427 printf("update_intrname: counting %s irq%d as %s\n", name, intr,
431 intr_countp[intr] = &intrcnt[name_index];
435 icu_setup(int intr, driver_intr_t *handler, void *arg, int flags)
438 int select; /* the select register is 8 bits */
440 u_int32_t value; /* the window register is 32 bits */
445 if ((u_int)intr >= ICU_LEN) /* no 8259 SLAVE to ignore */
447 if ((u_int)intr >= ICU_LEN || intr == ICU_SLAVEID)
449 if (intr_handler[intr] != isa_strayintr)
454 intr_handler[intr] = handler;
455 intr_unit[intr] = arg;
457 if (flags & INTR_FAST) {
458 vector = TPR_FAST_INTS + intr;
459 setidt(vector, fastintr[intr],
460 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
463 vector = TPR_SLOW_INTS + intr;
464 #ifdef APIC_INTR_REORDER
465 #ifdef APIC_INTR_HIGHPRI_CLOCK
466 /* XXX: Hack (kludge?) for more accurate clock. */
467 if (intr == apic_8254_intr || intr == 8) {
468 vector = TPR_FAST_INTS + intr;
472 setidt(vector, slowintr[intr],
473 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
475 #ifdef APIC_INTR_REORDER
476 set_lapic_isrloc(intr, vector);
479 * Reprogram the vector in the IO APIC.
481 if (int_to_apicintpin[intr].ioapic >= 0) {
482 select = int_to_apicintpin[intr].redirindex;
483 value = io_apic_read(int_to_apicintpin[intr].ioapic,
484 select) & ~IOART_INTVEC;
485 io_apic_write(int_to_apicintpin[intr].ioapic,
486 select, value | vector);
489 setidt(ICU_OFFSET + intr,
490 flags & INTR_FAST ? fastintr[intr] : slowintr[intr],
491 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
499 * Dissociate an interrupt handler from an IRQ and set the handler to
500 * the stray interrupt handler. The 'handler' parameter is used only
501 * for consistency checking.
504 icu_unset(intr, handler)
506 driver_intr_t *handler;
510 if ((u_int)intr >= ICU_LEN || handler != intr_handler[intr])
516 intr_countp[intr] = &intrcnt[1 + intr];
517 intr_handler[intr] = isa_strayintr;
518 intr_unit[intr] = &intr_unit[intr];
520 /* XXX how do I re-create dvp here? */
521 setidt(flags & INTR_FAST ? TPR_FAST_INTS + intr : TPR_SLOW_INTS + intr,
522 slowintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
524 #ifdef APIC_INTR_REORDER
525 set_lapic_isrloc(intr, ICU_OFFSET + intr);
527 setidt(ICU_OFFSET + intr, slowintr[intr], SDT_SYS386IGT, SEL_KPL,
528 GSEL(GCODE_SEL, SEL_KPL));
535 inthand_add(const char *name, int irq, driver_intr_t handler, void *arg,
538 struct ithd *ithd = ithds[irq]; /* descriptor for the IRQ */
539 struct intrhand *head; /* chain of handlers for IRQ */
540 struct intrhand *idesc; /* descriptor for this handler */
541 struct proc *p; /* interrupt thread */
544 if (name == NULL) /* no name? */
545 panic ("anonymous interrupt");
546 if (ithd == NULL || ithd->it_ih == NULL) {
547 /* first handler for this irq. */
549 ithd = malloc(sizeof (struct ithd), M_DEVBUF, M_WAITOK);
552 bzero(ithd, sizeof(struct ithd));
557 * If we have a fast interrupt, we need to set the
558 * handler address directly. Do that below. For a
559 * slow interrupt, we don't need to know more details,
560 * so do it here because it's tidier.
562 if ((flags & INTR_FAST) == 0) {
564 * Only create a kernel thread if we don't already
567 if (ithd->it_proc == NULL) {
568 errcode = kthread_create(ithd_loop, NULL, &p,
569 RFSTOPPED | RFHIGHPID, "irq%d: %s", irq,
572 panic("inthand_add: Can't create "
574 p->p_rtprio.type = RTP_PRIO_ITHREAD;
575 p->p_stat = SWAIT; /* we're idle */
577 /* Put in linkages. */
581 snprintf(ithd->it_proc->p_comm, MAXCOMLEN,
582 "irq%d: %s", irq, name);
583 p->p_rtprio.prio = pri;
586 * The interrupt process must be in place, but
587 * not necessarily schedulable, before we
588 * initialize the ICU, since it may cause an
589 * immediate interrupt.
591 if (icu_setup(irq, &sched_ithd, arg, flags) != 0)
592 panic("inthand_add: Can't initialize ICU");
594 } else if ((flags & INTR_EXCL) != 0
595 || (ithd->it_ih->ih_flags & INTR_EXCL) != 0) {
597 * We can't append the new handler if either
598 * list ithd or new handler do not allow
599 * interrupts to be shared.
602 printf("\tdevice combination %s and %s "
603 "doesn't support shared irq%d\n",
604 ithd->it_ih->ih_name, name, irq);
606 } else if (flags & INTR_FAST) {
607 /* We can only have one fast interrupt by itself. */
609 printf("\tCan't add fast interrupt %s"
610 " to normal interrupt %s on irq%d",
611 name, ithd->it_ih->ih_name, irq);
613 } else { /* update p_comm */
615 if (strlen(p->p_comm) + strlen(name) < MAXCOMLEN) {
616 strcat(p->p_comm, " ");
617 strcat(p->p_comm, name);
618 } else if (strlen(p->p_comm) == MAXCOMLEN)
619 p->p_comm[MAXCOMLEN - 1] = '+';
621 strcat(p->p_comm, "+");
623 idesc = malloc(sizeof (struct intrhand), M_DEVBUF, M_WAITOK);
626 bzero(idesc, sizeof (struct intrhand));
628 idesc->ih_handler = handler;
629 idesc->ih_argument = arg;
630 idesc->ih_flags = flags;
631 idesc->ih_ithd = ithd;
633 idesc->ih_name = malloc(strlen(name) + 1, M_DEVBUF, M_WAITOK);
634 if (idesc->ih_name == NULL) {
635 free(idesc, M_DEVBUF);
638 strcpy(idesc->ih_name, name);
640 /* Slow interrupts got set up above. */
641 if ((flags & INTR_FAST)
642 && (icu_setup(irq, idesc->ih_handler, idesc->ih_argument,
643 idesc->ih_flags) != 0) ) {
645 printf("\tinthand_add(irq%d) failed, result=%d\n",
647 free(idesc->ih_name, M_DEVBUF);
648 free(idesc, M_DEVBUF);
651 head = ithd->it_ih; /* look at chain of handlers */
653 while (head->ih_next != NULL)
654 head = head->ih_next; /* find the end */
655 head->ih_next = idesc; /* hook it in there */
657 ithd->it_ih = idesc; /* put it up front */
658 update_intrname(irq, idesc->ih_name);
663 * Deactivate and remove linked list the interrupt handler descriptor
664 * data connected created by an earlier call of inthand_add(), then
665 * adjust the interrupt masks if necessary.
667 * Return the memory held by the interrupt handler descriptor data
668 * structure to the system. First ensure the handler is not actively
673 inthand_remove(struct intrhand *idesc)
675 struct ithd *ithd; /* descriptor for the IRQ */
676 struct intrhand *ih; /* chain of handlers */
680 ithd = idesc->ih_ithd;
683 if (ih == idesc) /* first in the chain */
684 ithd->it_ih = idesc->ih_next; /* unhook it */
687 && (ih->ih_next != idesc) )
689 if (ih->ih_next != idesc)
691 ih->ih_next = ih->ih_next->ih_next;
694 if (ithd->it_ih == NULL) { /* no handlers left, */
695 icu_unset(ithd->irq, idesc->ih_handler);
696 ithds[ithd->irq] = NULL;
698 if ((idesc->ih_flags & INTR_FAST) == 0) {
699 mtx_enter(&sched_lock, MTX_SPIN);
700 if (ithd->it_proc->p_stat == SWAIT) {
701 ithd->it_proc->p_stat = SRUN;
702 setrunqueue(ithd->it_proc);
704 * We don't do an ast here because we really
705 * don't care when it runs next.
707 * XXX: should we lower the threads priority?
710 mtx_exit(&sched_lock, MTX_SPIN);
713 free(idesc, M_DEVBUF);