2 * Copyright (c) 1991 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91
40 #include "opt_auto_eoi.h"
44 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/syslog.h>
50 #include <sys/kernel.h>
51 #include <sys/kthread.h>
52 #include <sys/malloc.h>
53 #include <sys/module.h>
54 #include <sys/mutex.h>
55 #include <sys/unistd.h>
56 #include <sys/errno.h>
57 #include <sys/interrupt.h>
58 #include <machine/md_var.h>
59 #include <machine/segments.h>
60 #include <machine/intrcnt.h>
64 #include <machine/smptests.h> /** FAST_HI */
65 #include <machine/smp.h>
66 #include <machine/resource.h>
69 #include <pc98/pc98/pc98.h>
70 #include <pc98/pc98/pc98_machdep.h>
71 #include <pc98/pc98/epsonio.h>
73 #include <i386/isa/isa.h>
75 #include <i386/isa/icu.h>
78 #include <isa/isavar.h>
80 #include <i386/isa/intr_machdep.h>
81 #include <sys/interrupt.h>
83 #include <machine/clock.h>
87 #include <i386/isa/mca_machdep.h>
93 u_long *intr_countp[ICU_LEN]; /* pointers to interrupt counters */
94 driver_intr_t *intr_handler[ICU_LEN]; /* first level interrupt handler */
95 struct ithd *ithds[ICU_LEN]; /* real interrupt handler */
96 void *intr_unit[ICU_LEN];
98 static struct mtx ithds_table_lock; /* protect the ithds table */
100 static inthand_t *fastintr[ICU_LEN] = {
101 &IDTVEC(fastintr0), &IDTVEC(fastintr1),
102 &IDTVEC(fastintr2), &IDTVEC(fastintr3),
103 &IDTVEC(fastintr4), &IDTVEC(fastintr5),
104 &IDTVEC(fastintr6), &IDTVEC(fastintr7),
105 &IDTVEC(fastintr8), &IDTVEC(fastintr9),
106 &IDTVEC(fastintr10), &IDTVEC(fastintr11),
107 &IDTVEC(fastintr12), &IDTVEC(fastintr13),
108 &IDTVEC(fastintr14), &IDTVEC(fastintr15),
110 &IDTVEC(fastintr16), &IDTVEC(fastintr17),
111 &IDTVEC(fastintr18), &IDTVEC(fastintr19),
112 &IDTVEC(fastintr20), &IDTVEC(fastintr21),
113 &IDTVEC(fastintr22), &IDTVEC(fastintr23),
114 &IDTVEC(fastintr24), &IDTVEC(fastintr25),
115 &IDTVEC(fastintr26), &IDTVEC(fastintr27),
116 &IDTVEC(fastintr28), &IDTVEC(fastintr29),
117 &IDTVEC(fastintr30), &IDTVEC(fastintr31),
121 static inthand_t *slowintr[ICU_LEN] = {
122 &IDTVEC(intr0), &IDTVEC(intr1), &IDTVEC(intr2), &IDTVEC(intr3),
123 &IDTVEC(intr4), &IDTVEC(intr5), &IDTVEC(intr6), &IDTVEC(intr7),
124 &IDTVEC(intr8), &IDTVEC(intr9), &IDTVEC(intr10), &IDTVEC(intr11),
125 &IDTVEC(intr12), &IDTVEC(intr13), &IDTVEC(intr14), &IDTVEC(intr15),
127 &IDTVEC(intr16), &IDTVEC(intr17), &IDTVEC(intr18), &IDTVEC(intr19),
128 &IDTVEC(intr20), &IDTVEC(intr21), &IDTVEC(intr22), &IDTVEC(intr23),
129 &IDTVEC(intr24), &IDTVEC(intr25), &IDTVEC(intr26), &IDTVEC(intr27),
130 &IDTVEC(intr28), &IDTVEC(intr29), &IDTVEC(intr30), &IDTVEC(intr31),
134 static driver_intr_t isa_strayintr;
136 static void ithds_init(void *dummy);
137 static void ithread_enable(int vector);
138 static void ithread_disable(int vector);
141 #define NMI_PARITY 0x04
142 #define NMI_EPARITY 0x02
144 #define NMI_PARITY (1 << 7)
145 #define NMI_IOCHAN (1 << 6)
146 #define ENMI_WATCHDOG (1 << 7)
147 #define ENMI_BUSTIMER (1 << 6)
148 #define ENMI_IOSTATUS (1 << 5)
152 * Bus attachment for the ISA PIC.
154 static struct isa_pnp_id atpic_ids[] = {
155 { 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
160 atpic_probe(device_t dev)
164 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids)) <= 0)
170 * In the APIC_IO case we might be granted IRQ 2, as this is typically
171 * consumed by chaining between the two PIC components. If we're using
172 * the APIC, however, this may not be the case, and as such we should
173 * free the resource. (XXX untested)
175 * The generic ISA attachment code will handle allocating any other resources
176 * that we don't explicitly claim here.
179 atpic_attach(device_t dev)
183 struct resource *res;
185 /* try to allocate our IRQ and then free it */
187 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 0);
189 bus_release_resource(dev, SYS_RES_IRQ, rid, res);
194 static device_method_t atpic_methods[] = {
195 /* Device interface */
196 DEVMETHOD(device_probe, atpic_probe),
197 DEVMETHOD(device_attach, atpic_attach),
198 DEVMETHOD(device_detach, bus_generic_detach),
199 DEVMETHOD(device_shutdown, bus_generic_shutdown),
200 DEVMETHOD(device_suspend, bus_generic_suspend),
201 DEVMETHOD(device_resume, bus_generic_resume),
205 static driver_t atpic_driver = {
211 static devclass_t atpic_devclass;
213 DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0);
216 * Handle a NMI, possibly a machine check.
217 * return true to panic system, false to ignore.
225 int port = inb(0x33);
227 log(LOG_CRIT, "NMI PC98 port = %x\n", port);
228 if (epson_machine_id == 0x20)
229 epson_outb(0xc16, epson_inb(0xc16) | 0x1);
230 if (port & NMI_PARITY) {
231 log(LOG_CRIT, "BASE RAM parity error, likely hardware failure.");
233 } else if (port & NMI_EPARITY) {
234 log(LOG_CRIT, "EXTENDED RAM parity error, likely hardware failure.");
237 log(LOG_CRIT, "\nNMI Resume ??\n");
240 int isa_port = inb(0x61);
241 int eisa_port = inb(0x461);
243 log(LOG_CRIT, "NMI ISA %x, EISA %x\n", isa_port, eisa_port);
245 if (MCA_system && mca_bus_nmi())
249 if (isa_port & NMI_PARITY) {
250 log(LOG_CRIT, "RAM parity error, likely hardware failure.");
254 if (isa_port & NMI_IOCHAN) {
255 log(LOG_CRIT, "I/O channel check, likely hardware failure.");
260 * On a real EISA machine, this will never happen. However it can
261 * happen on ISA machines which implement XT style floating point
262 * error handling (very rare). Save them from a meaningless panic.
264 if (eisa_port == 0xff)
267 if (eisa_port & ENMI_WATCHDOG) {
268 log(LOG_CRIT, "EISA watchdog timer expired, likely hardware failure.");
272 if (eisa_port & ENMI_BUSTIMER) {
273 log(LOG_CRIT, "EISA bus timeout, likely hardware failure.");
277 if (eisa_port & ENMI_IOSTATUS) {
278 log(LOG_CRIT, "EISA I/O port status error.");
286 * Create a default interrupt table to avoid problems caused by
287 * spurious interrupts during configuration of kernel, then setup
288 * interrupt control unit.
296 for (i = 0; i < ICU_LEN; i++)
297 icu_unset(i, (driver_intr_t *)NULL);
299 /* initialize 8259's */
302 outb(IO_ICU1, 0x19); /* reset; program device, four bytes */
305 outb(IO_ICU1, 0x11); /* reset; program device, four bytes */
307 outb(IO_ICU1+ICU_IMR_OFFSET, NRSVIDT); /* starting at this vector index */
308 outb(IO_ICU1+ICU_IMR_OFFSET, IRQ_SLAVE); /* slave on line 7 */
311 outb(IO_ICU1+ICU_IMR_OFFSET, 0x1f); /* (master) auto EOI, 8086 mode */
313 outb(IO_ICU1+ICU_IMR_OFFSET, 0x1d); /* (master) 8086 mode */
317 outb(IO_ICU1+ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */
319 outb(IO_ICU1+ICU_IMR_OFFSET, 1); /* 8086 mode */
322 outb(IO_ICU1+ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */
323 outb(IO_ICU1, 0x0a); /* default to IRR on read */
325 outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */
330 outb(IO_ICU2, 0x19); /* reset; program device, four bytes */
333 outb(IO_ICU2, 0x11); /* reset; program device, four bytes */
335 outb(IO_ICU2+ICU_IMR_OFFSET, NRSVIDT+8); /* staring at this vector index */
336 outb(IO_ICU2+ICU_IMR_OFFSET, ICU_SLAVEID); /* my slave id is 7 */
338 outb(IO_ICU2+ICU_IMR_OFFSET,9); /* 8086 mode */
341 outb(IO_ICU2+ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */
343 outb(IO_ICU2+ICU_IMR_OFFSET,1); /* 8086 mode */
346 outb(IO_ICU2+ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */
347 outb(IO_ICU2, 0x0a); /* default to IRR on read */
351 * Caught a stray interrupt, notify
354 isa_strayintr(vcookiep)
357 int intr = (void **)vcookiep - &intr_unit[0];
360 * XXX TODO print a different message for #7 if it is for a
361 * glitch. Glitches can be distinguished from real #7's by
362 * testing that the in-service bit is _not_ set. The test
363 * must be done before sending an EOI so it can't be done if
364 * we are using AUTO_EOI_1.
366 if (intrcnt[1 + intr] <= 5)
367 log(LOG_ERR, "stray irq %d\n", intr);
368 if (intrcnt[1 + intr] == 5)
370 "too many stray irq %d's; not logging any more\n", intr);
375 * Return a bitmap of the current interrupt requests. This is 8259-specific
376 * and is only suitable for use at probe time.
386 return ((irr2 << 8) | irr1);
391 * Update intrnames array with the specified name. This is used by
392 * vmstat(8) and the like.
395 update_intrname(int intr, const char *name)
399 int name_index, off, strayintr;
402 * Initialise strings for bitbucket and stray interrupt counters.
403 * These have statically allocated indices 0 and 1 through ICU_LEN.
405 if (intrnames[0] == '\0') {
406 off = sprintf(intrnames, "???") + 1;
407 for (strayintr = 0; strayintr < ICU_LEN; strayintr++)
408 off += sprintf(intrnames + off, "stray irq%d",
414 if (snprintf(buf, sizeof(buf), "%s irq%d", name, intr) >= sizeof(buf))
418 * Search for `buf' in `intrnames'. In the usual case when it is
419 * not found, append it to the end if there is enough space (the \0
420 * terminator for the previous string, if any, becomes a separator).
422 for (cp = intrnames, name_index = 0;
423 cp != eintrnames && name_index < NR_INTRNAMES;
424 cp += strlen(cp) + 1, name_index++) {
426 if (strlen(buf) >= eintrnames - cp)
431 if (strcmp(cp, buf) == 0)
436 printf("update_intrname: counting %s irq%d as %s\n", name, intr,
440 intr_countp[intr] = &intrcnt[name_index];
444 icu_setup(int intr, driver_intr_t *handler, void *arg, int flags)
447 int select; /* the select register is 8 bits */
449 u_int32_t value; /* the window register is 32 bits */
454 if ((u_int)intr >= ICU_LEN) /* no 8259 SLAVE to ignore */
456 if ((u_int)intr >= ICU_LEN || intr == ICU_SLAVEID)
458 if (intr_handler[intr] != isa_strayintr)
463 intr_handler[intr] = handler;
464 intr_unit[intr] = arg;
466 if (flags & INTR_FAST) {
467 vector = TPR_FAST_INTS + intr;
468 setidt(vector, fastintr[intr],
469 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
472 vector = TPR_SLOW_INTS + intr;
473 #ifdef APIC_INTR_REORDER
474 #ifdef APIC_INTR_HIGHPRI_CLOCK
475 /* XXX: Hack (kludge?) for more accurate clock. */
476 if (intr == apic_8254_intr || intr == 8) {
477 vector = TPR_FAST_INTS + intr;
481 setidt(vector, slowintr[intr],
482 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
484 #ifdef APIC_INTR_REORDER
485 set_lapic_isrloc(intr, vector);
488 * Reprogram the vector in the IO APIC.
490 if (int_to_apicintpin[intr].ioapic >= 0) {
491 select = int_to_apicintpin[intr].redirindex;
492 value = io_apic_read(int_to_apicintpin[intr].ioapic,
493 select) & ~IOART_INTVEC;
494 io_apic_write(int_to_apicintpin[intr].ioapic,
495 select, value | vector);
498 setidt(ICU_OFFSET + intr,
499 flags & INTR_FAST ? fastintr[intr] : slowintr[intr],
500 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
508 * Dissociate an interrupt handler from an IRQ and set the handler to
509 * the stray interrupt handler. The 'handler' parameter is used only
510 * for consistency checking.
513 icu_unset(intr, handler)
515 driver_intr_t *handler;
519 if ((u_int)intr >= ICU_LEN || handler != intr_handler[intr])
525 intr_countp[intr] = &intrcnt[1 + intr];
526 intr_handler[intr] = isa_strayintr;
527 intr_unit[intr] = &intr_unit[intr];
529 /* XXX how do I re-create dvp here? */
530 setidt(flags & INTR_FAST ? TPR_FAST_INTS + intr : TPR_SLOW_INTS + intr,
531 slowintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
533 #ifdef APIC_INTR_REORDER
534 set_lapic_isrloc(intr, ICU_OFFSET + intr);
536 setidt(ICU_OFFSET + intr, slowintr[intr], SDT_SYS386IGT, SEL_KPL,
537 GSEL(GCODE_SEL, SEL_KPL));
544 ithds_init(void *dummy)
547 mtx_init(&ithds_table_lock, "ithread table lock", MTX_SPIN);
549 SYSINIT(ithds_init, SI_SUB_INTR, SI_ORDER_SECOND, ithds_init, NULL);
552 ithread_enable(int vector)
559 ithread_disable(int vector)
562 INTRDIS(1 << vector);
566 inthand_add(const char *name, int irq, driver_intr_t handler, void *arg,
567 enum intr_type flags, void **cookiep)
569 struct ithd *ithd; /* descriptor for the IRQ */
571 int created_ithd = 0;
574 * Work around a race where more than one CPU may be registering
575 * handlers on the same IRQ at the same time.
577 mtx_lock_spin(&ithds_table_lock);
579 mtx_unlock_spin(&ithds_table_lock);
581 errcode = ithread_create(&ithd, irq, 0, ithread_disable,
582 ithread_enable, "irq%d:", irq);
585 mtx_lock_spin(&ithds_table_lock);
586 if (ithds[irq] == NULL) {
589 mtx_unlock_spin(&ithds_table_lock);
595 mtx_unlock_spin(&ithds_table_lock);
596 ithread_destroy(orphan);
600 errcode = ithread_add_handler(ithd, name, handler, arg,
601 ithread_priority(flags), flags, cookiep);
603 if ((flags & INTR_FAST) == 0 || errcode)
605 * The interrupt process must be in place, but
606 * not necessarily schedulable, before we
607 * initialize the ICU, since it may cause an
608 * immediate interrupt.
610 if (icu_setup(irq, &sched_ithd, arg, flags) != 0)
611 panic("inthand_add: Can't initialize ICU");
616 if (flags & INTR_FAST) {
617 errcode = icu_setup(irq, handler, arg, flags);
618 if (errcode && bootverbose)
619 printf("\tinthand_add(irq%d) failed, result=%d\n",
625 update_intrname(irq, name);
630 * Deactivate and remove linked list the interrupt handler descriptor
631 * data connected created by an earlier call of inthand_add(), then
632 * adjust the interrupt masks if necessary.
634 * Return the memory held by the interrupt handler descriptor data
635 * structure to the system. First ensure the handler is not actively
639 inthand_remove(void *cookie)
642 return (ithread_remove_handler(cookie));