2 * Copyright (c) 1991 The Regents of the University of California.
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36 #ifndef _I386_ISA_INTR_MACHDEP_H_
37 #define _I386_ISA_INTR_MACHDEP_H_
40 * Low level interrupt code.
45 #if defined(SMP) || defined(APIC_IO)
47 * XXX FIXME: rethink location for all IPI vectors.
51 APIC TPR priority vector levels:
53 0xff (255) +-------------+
54 | | 15 (IPIs: Xspuriousint)
55 0xf0 (240) +-------------+
57 0xe0 (224) +-------------+
59 0xd0 (208) +-------------+
61 0xc0 (192) +-------------+
63 0xb0 (176) +-------------+
64 | | 10 (IPIs: Xcpustop)
65 0xa0 (160) +-------------+
66 | | 9 (IPIs: Xinvltlb)
67 0x90 (144) +-------------+
68 | | 8 (linux/BSD syscall, IGNORE FAST HW INTS)
69 0x80 (128) +-------------+
70 | | 7 (FAST_INTR 16-23)
71 0x70 (112) +-------------+
72 | | 6 (FAST_INTR 0-15)
73 0x60 (96) +-------------+
74 | | 5 (IGNORE HW INTS)
75 0x50 (80) +-------------+
77 0x40 (64) +------+------+
78 | | | 3 (upper APIC hardware INTs: PCI)
79 0x30 (48) +------+------+
80 | | 2 (start of hardware INTs: ISA)
81 0x20 (32) +-------------+
82 | | 1 (exceptions, traps, etc.)
83 0x10 (16) +-------------+
84 | | 0 (exceptions, traps, etc.)
85 0x00 (0) +-------------+
88 /* IDT vector base for regular (aka. slow) and fast interrupts */
89 #define TPR_SLOW_INTS 0x20
90 #define TPR_FAST_INTS 0x60
92 /* blocking values for local APIC Task Priority Register */
93 #define TPR_BLOCK_HWI 0x4f /* hardware INTs */
94 #define TPR_IGNORE_HWI 0x5f /* ignore INTs */
95 #define TPR_BLOCK_FHWI 0x7f /* hardware FAST INTs */
96 #define TPR_IGNORE_FHWI 0x8f /* ignore FAST INTs */
97 #define TPR_BLOCK_XINVLTLB 0x9f /* */
98 #define TPR_BLOCK_XCPUSTOP 0xaf /* */
99 #define TPR_BLOCK_ALL 0xff /* all INTs */
102 /* put a 'fake' HWI in top of APIC prio 0x3x, 32 + 31 = 63 = 0x3f */
103 #define XTEST1_OFFSET (ICU_OFFSET + 31)
104 #endif /** TEST_TEST1 */
107 #define XINVLTLB_OFFSET (ICU_OFFSET + 112)
110 /* inter-cpu clock handling */
111 #define XCPUCHECKSTATE_OFFSET (ICU_OFFSET + 113)
114 /* inter-CPU rendezvous */
115 #define XRENDEZVOUS_OFFSET (ICU_OFFSET + 114)
117 /* IPI to generate an additional software trap at the target CPU */
118 #define XCPUAST_OFFSET (ICU_OFFSET + 48)
120 /* IPI to signal CPUs to stop and wait for another CPU to restart them */
121 #define XCPUSTOP_OFFSET (ICU_OFFSET + 128)
124 * Note: this vector MUST be xxxx1111, 32 + 223 = 255 = 0xff:
126 #define XSPURIOUSINT_OFFSET (ICU_OFFSET + 223)
128 #endif /* SMP || APIC_IO */
133 * Type of the first (asm) part of an interrupt handler.
135 typedef void inthand_t __P((u_int cs, u_int ef, u_int esp, u_int ss));
137 #define IDTVEC(name) __CONCAT(X,name)
139 extern char eintrnames[]; /* end of intrnames[] */
140 extern u_long intrcnt[]; /* counts for for each device and stray */
141 extern char intrnames[]; /* string table containing device names */
142 extern u_long *intr_countp[]; /* pointers into intrcnt[] */
143 extern driver_intr_t *intr_handler[]; /* C entry points of intr handlers */
144 extern struct ithd *ithds[];
145 extern void *intr_unit[]; /* cookies to pass to intr handlers */
146 extern struct ithd softinterrupt; /* soft interrupt thread */
149 IDTVEC(fastintr0), IDTVEC(fastintr1),
150 IDTVEC(fastintr2), IDTVEC(fastintr3),
151 IDTVEC(fastintr4), IDTVEC(fastintr5),
152 IDTVEC(fastintr6), IDTVEC(fastintr7),
153 IDTVEC(fastintr8), IDTVEC(fastintr9),
154 IDTVEC(fastintr10), IDTVEC(fastintr11),
155 IDTVEC(fastintr12), IDTVEC(fastintr13),
156 IDTVEC(fastintr14), IDTVEC(fastintr15);
158 IDTVEC(intr0), IDTVEC(intr1), IDTVEC(intr2), IDTVEC(intr3),
159 IDTVEC(intr4), IDTVEC(intr5), IDTVEC(intr6), IDTVEC(intr7),
160 IDTVEC(intr8), IDTVEC(intr9), IDTVEC(intr10), IDTVEC(intr11),
161 IDTVEC(intr12), IDTVEC(intr13), IDTVEC(intr14), IDTVEC(intr15);
163 #if defined(SMP) || defined(APIC_IO)
165 IDTVEC(fastintr16), IDTVEC(fastintr17),
166 IDTVEC(fastintr18), IDTVEC(fastintr19),
167 IDTVEC(fastintr20), IDTVEC(fastintr21),
168 IDTVEC(fastintr22), IDTVEC(fastintr23),
169 IDTVEC(fastintr24), IDTVEC(fastintr25),
170 IDTVEC(fastintr26), IDTVEC(fastintr27),
171 IDTVEC(fastintr28), IDTVEC(fastintr29),
172 IDTVEC(fastintr30), IDTVEC(fastintr31);
174 IDTVEC(intr16), IDTVEC(intr17), IDTVEC(intr18), IDTVEC(intr19),
175 IDTVEC(intr20), IDTVEC(intr21), IDTVEC(intr22), IDTVEC(intr23),
176 IDTVEC(intr24), IDTVEC(intr25), IDTVEC(intr26), IDTVEC(intr27),
177 IDTVEC(intr28), IDTVEC(intr29), IDTVEC(intr30), IDTVEC(intr31);
180 Xinvltlb, /* TLB shootdowns */
182 Xcpucheckstate, /* Check cpu state */
184 Xcpuast, /* Additional software trap on other cpu */
185 Xcpustop, /* CPU stops & waits for another CPU to restart it */
186 Xspuriousint, /* handle APIC "spurious INTs" */
187 Xrendezvous; /* handle CPU rendezvous */
191 Xtest1; /* 'fake' HWI at top of APIC prio 0x3x, 32+31 = 0x3f */
192 #endif /** TEST_TEST1 */
193 #endif /* SMP || APIC_IO */
196 #define ICU_IMR_OFFSET 2 /* IO_ICU{1,2} + 2 */
197 #define ICU_SLAVEID 7
199 #define ICU_IMR_OFFSET 1 /* IO_ICU{1,2} + 1 */
200 #define ICU_SLAVEID 2
205 * This is to accommodate "mixed-mode" programming for
206 * motherboards that don't connect the 8254 to the IO APIC.
211 #define NR_INTRNAMES (1 + ICU_LEN + 2 * ICU_LEN)
213 void isa_defaultirq __P((void));
214 int isa_nmi __P((int cd));
215 int icu_setup __P((int intr, driver_intr_t *func, void *arg,
217 int icu_unset __P((int intr, driver_intr_t *handler));
220 * WARNING: These are internal functions and not to be used by device drivers!
221 * They are subject to change without notice.
223 int inthand_add(const char *name, int irq, driver_intr_t handler, void *arg,
224 enum intr_type flags, void **cookiep);
225 int inthand_remove(void *cookie);
226 void sched_ithd(void *dummy);
232 #endif /* !_I386_ISA_INTR_MACHDEP_H_ */