2 * Copyright (c) 1991 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 #ifndef _I386_ISA_INTR_MACHDEP_H_
37 #define _I386_ISA_INTR_MACHDEP_H_
40 * Low level interrupt code.
45 #if defined(SMP) || defined(APIC_IO)
47 * XXX FIXME: rethink location for all IPI vectors.
51 APIC TPR priority vector levels:
53 0xff (255) +-------------+
54 | | 15 (IPIs: Xspuriousint)
55 0xf0 (240) +-------------+
57 0xe0 (224) +-------------+
59 0xd0 (208) +-------------+
61 0xc0 (192) +-------------+
63 0xb0 (176) +-------------+
64 | | 10 (IPIs: Xcpustop)
65 0xa0 (160) +-------------+
66 | | 9 (IPIs: Xinvltlb)
67 0x90 (144) +-------------+
68 | | 8 (linux/BSD syscall, IGNORE FAST HW INTS)
69 0x80 (128) +-------------+
70 | | 7 (FAST_INTR 16-23)
71 0x70 (112) +-------------+
72 | | 6 (FAST_INTR 0-15)
73 0x60 (96) +-------------+
74 | | 5 (IGNORE HW INTS)
75 0x50 (80) +-------------+
77 0x40 (64) +------+------+
78 | | | 3 (upper APIC hardware INTs: PCI)
79 0x30 (48) +------+------+
80 | | 2 (start of hardware INTs: ISA)
81 0x20 (32) +-------------+
82 | | 1 (exceptions, traps, etc.)
83 0x10 (16) +-------------+
84 | | 0 (exceptions, traps, etc.)
85 0x00 (0) +-------------+
88 /* IDT vector base for regular (aka. slow) and fast interrupts */
89 #define TPR_SLOW_INTS 0x20
90 #define TPR_FAST_INTS 0x60
92 /* blocking values for local APIC Task Priority Register */
93 #define TPR_BLOCK_HWI 0x4f /* hardware INTs */
94 #define TPR_IGNORE_HWI 0x5f /* ignore INTs */
95 #define TPR_BLOCK_FHWI 0x7f /* hardware FAST INTs */
96 #define TPR_IGNORE_FHWI 0x8f /* ignore FAST INTs */
97 #define TPR_BLOCK_XINVLTLB 0x9f /* */
98 #define TPR_BLOCK_XCPUSTOP 0xaf /* */
99 #define TPR_BLOCK_ALL 0xff /* all INTs */
103 /* put a 'fake' HWI in top of APIC prio 0x3x, 32 + 31 = 63 = 0x3f */
104 #define XTEST1_OFFSET (ICU_OFFSET + 31)
105 #endif /** TEST_TEST1 */
108 #define XINVLTLB_OFFSET (ICU_OFFSET + 112)
111 /* inter-cpu clock handling */
112 #define XCPUCHECKSTATE_OFFSET (ICU_OFFSET + 113)
115 /* inter-CPU rendezvous */
116 #define XRENDEZVOUS_OFFSET (ICU_OFFSET + 114)
118 /* IPI to generate an additional software trap at the target CPU */
119 #define XCPUAST_OFFSET (ICU_OFFSET + 48)
121 /* IPI to signal the CPU holding the ISR lock that another IRQ has appeared */
122 #define XFORWARD_IRQ_OFFSET (ICU_OFFSET + 49)
124 /* IPI to signal CPUs to stop and wait for another CPU to restart them */
125 #define XCPUSTOP_OFFSET (ICU_OFFSET + 128)
128 * Note: this vector MUST be xxxx1111, 32 + 223 = 255 = 0xff:
130 #define XSPURIOUSINT_OFFSET (ICU_OFFSET + 223)
132 #endif /* SMP || APIC_IO */
137 * Type of the first (asm) part of an interrupt handler.
139 typedef void inthand_t __P((u_int cs, u_int ef, u_int esp, u_int ss));
141 #define IDTVEC(name) __CONCAT(X,name)
143 extern char eintrnames[]; /* end of intrnames[] */
144 extern u_long intrcnt[]; /* counts for for each device and stray */
145 extern char intrnames[]; /* string table containing device names */
146 extern u_long *intr_countp[]; /* pointers into intrcnt[] */
147 extern inthand2_t *intr_handler[]; /* C entry points of intr handlers */
148 extern u_int intr_mask[]; /* sets of intrs masked during handling of 1 */
149 extern void *intr_unit[]; /* cookies to pass to intr handlers */
152 IDTVEC(fastintr0), IDTVEC(fastintr1),
153 IDTVEC(fastintr2), IDTVEC(fastintr3),
154 IDTVEC(fastintr4), IDTVEC(fastintr5),
155 IDTVEC(fastintr6), IDTVEC(fastintr7),
156 IDTVEC(fastintr8), IDTVEC(fastintr9),
157 IDTVEC(fastintr10), IDTVEC(fastintr11),
158 IDTVEC(fastintr12), IDTVEC(fastintr13),
159 IDTVEC(fastintr14), IDTVEC(fastintr15);
161 IDTVEC(intr0), IDTVEC(intr1), IDTVEC(intr2), IDTVEC(intr3),
162 IDTVEC(intr4), IDTVEC(intr5), IDTVEC(intr6), IDTVEC(intr7),
163 IDTVEC(intr8), IDTVEC(intr9), IDTVEC(intr10), IDTVEC(intr11),
164 IDTVEC(intr12), IDTVEC(intr13), IDTVEC(intr14), IDTVEC(intr15);
166 #if defined(SMP) || defined(APIC_IO)
168 IDTVEC(fastintr16), IDTVEC(fastintr17),
169 IDTVEC(fastintr18), IDTVEC(fastintr19),
170 IDTVEC(fastintr20), IDTVEC(fastintr21),
171 IDTVEC(fastintr22), IDTVEC(fastintr23);
173 IDTVEC(intr16), IDTVEC(intr17), IDTVEC(intr18), IDTVEC(intr19),
174 IDTVEC(intr20), IDTVEC(intr21), IDTVEC(intr22), IDTVEC(intr23);
177 Xinvltlb, /* TLB shootdowns */
179 Xcpucheckstate, /* Check cpu state */
181 Xcpuast, /* Additional software trap on other cpu */
182 Xforward_irq, /* Forward irq to cpu holding ISR lock */
183 Xcpustop, /* CPU stops & waits for another CPU to restart it */
184 Xspuriousint, /* handle APIC "spurious INTs" */
185 Xrendezvous; /* handle CPU rendezvous */
189 Xtest1; /* 'fake' HWI at top of APIC prio 0x3x, 32+31 = 0x3f */
190 #endif /** TEST_TEST1 */
191 #endif /* SMP || APIC_IO */
193 void isa_defaultirq __P((void));
194 int isa_nmi __P((int cd));
195 int icu_setup __P((int intr, inthand2_t *func, void *arg,
196 u_int *maskptr, int flags));
197 int icu_unset __P((int intr, inthand2_t *handler));
198 int update_intr_masks __P((void));
200 intrmask_t splq __P((intrmask_t mask));
202 #define INTR_FAST 0x00000001 /* fast interrupt handler */
203 #define INTR_EXCL 0x00010000 /* excl. intr, default is shared */
204 struct intrec *inthand_add(const char *name, int irq, inthand2_t handler,
205 void *arg, intrmask_t *maskptr, int flags);
207 int inthand_remove(struct intrec *idesc);
213 #endif /* !_I386_ISA_INTR_MACHDEP_H_ */