2 * Copyright (c) 1990 William Jolitz.
3 * Copyright (c) 1991 The Regents of the University of California.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 4. Neither the name of the University nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
40 #include <sys/param.h>
41 #include <sys/systm.h>
43 #include <sys/kernel.h>
45 #include <sys/malloc.h>
46 #include <sys/module.h>
47 #include <sys/mutex.h>
48 #include <sys/mutex.h>
51 #include <sys/sysctl.h>
52 #include <machine/bus.h>
55 #include <sys/syslog.h>
57 #include <sys/signalvar.h>
60 #include <machine/asmacros.h>
61 #include <machine/cputypes.h>
62 #include <machine/frame.h>
63 #include <machine/md_var.h>
64 #include <machine/pcb.h>
65 #include <machine/psl.h>
66 #include <machine/resource.h>
67 #include <machine/specialreg.h>
68 #include <machine/segments.h>
69 #include <machine/ucontext.h>
71 #include <machine/intr_machdep.h>
74 #include <isa/isavar.h>
77 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
78 #define CPU_ENABLE_SSE
82 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
85 #if defined(__GNUCLIKE_ASM) && !defined(lint)
87 #define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw))
88 #define fnclex() __asm __volatile("fnclex")
89 #define fninit() __asm __volatile("fninit")
90 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr)))
91 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
92 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr)))
93 #define fp_divide_by_0() __asm __volatile( \
94 "fldz; fld1; fdiv %st,%st(1); fnop")
95 #define frstor(addr) __asm __volatile("frstor %0" : : "m" (*(addr)))
97 #define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr)))
98 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
99 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr))
100 #define stmxcsr(addr) __asm __volatile("stmxcsr %0" : : "m" (*(addr)))
103 xrstor(char *addr, uint64_t mask)
109 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi));
113 xsave(char *addr, uint64_t mask)
119 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) :
124 xsaveopt(char *addr, uint64_t mask)
130 __asm __volatile("xsaveopt %0" : "=m" (*addr) : "a" (low), "d" (hi) :
134 #else /* !(__GNUCLIKE_ASM && !lint) */
136 void fldcw(u_short cw);
139 void fnsave(caddr_t addr);
140 void fnstcw(caddr_t addr);
141 void fnstsw(caddr_t addr);
142 void fp_divide_by_0(void);
143 void frstor(caddr_t addr);
144 #ifdef CPU_ENABLE_SSE
145 void fxsave(caddr_t addr);
146 void fxrstor(caddr_t addr);
147 void ldmxcsr(u_int csr);
148 void stmxcsr(u_int *csr);
149 void xrstor(char *addr, uint64_t mask);
150 void xsave(char *addr, uint64_t mask);
151 void xsaveopt(char *addr, uint64_t mask);
154 #endif /* __GNUCLIKE_ASM && !lint */
156 #define start_emulating() load_cr0(rcr0() | CR0_TS)
157 #define stop_emulating() clts()
159 #ifdef CPU_ENABLE_SSE
160 #define GET_FPU_CW(thread) \
162 (thread)->td_pcb->pcb_save->sv_xmm.sv_env.en_cw : \
163 (thread)->td_pcb->pcb_save->sv_87.sv_env.en_cw)
164 #define GET_FPU_SW(thread) \
166 (thread)->td_pcb->pcb_save->sv_xmm.sv_env.en_sw : \
167 (thread)->td_pcb->pcb_save->sv_87.sv_env.en_sw)
168 #define SET_FPU_CW(savefpu, value) do { \
170 (savefpu)->sv_xmm.sv_env.en_cw = (value); \
172 (savefpu)->sv_87.sv_env.en_cw = (value); \
174 #else /* CPU_ENABLE_SSE */
175 #define GET_FPU_CW(thread) \
176 (thread->td_pcb->pcb_save->sv_87.sv_env.en_cw)
177 #define GET_FPU_SW(thread) \
178 (thread->td_pcb->pcb_save->sv_87.sv_env.en_sw)
179 #define SET_FPU_CW(savefpu, value) \
180 (savefpu)->sv_87.sv_env.en_cw = (value)
181 #endif /* CPU_ENABLE_SSE */
183 #ifdef CPU_ENABLE_SSE
184 CTASSERT(sizeof(union savefpu) == 512);
185 CTASSERT(sizeof(struct xstate_hdr) == 64);
186 CTASSERT(sizeof(struct savefpu_ymm) == 832);
189 * This requirement is to make it easier for asm code to calculate
190 * offset of the fpu save area from the pcb address. FPU save area
191 * must be 64-byte aligned.
193 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0);
196 * Ensure the copy of XCR0 saved in a core is contained in the padding
199 CTASSERT(X86_XSTATE_XCR0_OFFSET >= offsetof(struct savexmm, sv_pad) &&
200 X86_XSTATE_XCR0_OFFSET + sizeof(uint64_t) <= sizeof(struct savexmm));
202 static void fpu_clean_state(void);
205 static void fpusave(union savefpu *);
206 static void fpurstor(union savefpu *);
210 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD,
211 &hw_float, 0, "Floating point instructions executed in hardware");
213 #ifdef CPU_ENABLE_SSE
217 static uma_zone_t fpu_save_area_zone;
218 static union savefpu *npx_initialstate;
220 #ifdef CPU_ENABLE_SSE
221 struct xsave_area_elm_descr {
226 static int use_xsaveopt;
229 static volatile u_int npx_traps_while_probing;
231 alias_for_inthand_t probetrap;
235 .type " __XSTRING(CNAME(probetrap)) ",@function \n\
236 " __XSTRING(CNAME(probetrap)) ": \n\
238 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\
244 * Determine if an FPU is present and how to use it.
249 struct gate_descriptor save_idt_npxtrap;
250 u_short control, status;
253 * Modern CPUs all have an FPU that uses the INT16 interface
254 * and provide a simple way to verify that, so handle the
255 * common case right away.
257 if (cpu_feature & CPUID_FPU) {
262 save_idt_npxtrap = idt[IDT_MF];
263 setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL,
264 GSEL(GCODE_SEL, SEL_KPL));
267 * Don't trap while we're probing.
272 * Finish resetting the coprocessor, if any. If there is an error
273 * pending, then we may get a bogus IRQ13, but npx_intr() will handle
274 * it OK. Bogus halts have never been observed, but we enabled
275 * IRQ13 and cleared the BUSY# latch early to handle them anyway.
280 * Don't use fwait here because it might hang.
281 * Don't use fnop here because it usually hangs if there is no FPU.
283 DELAY(1000); /* wait for any IRQ13 */
285 if (npx_traps_while_probing != 0)
286 printf("fninit caused %u bogus npx trap(s)\n",
287 npx_traps_while_probing);
290 * Check for a status of mostly zero.
294 if ((status & 0xb8ff) == 0) {
296 * Good, now check for a proper control word.
300 if ((control & 0x1f3f) == 0x033f) {
302 * We have an npx, now divide by 0 to see if exception
305 control &= ~(1 << 2); /* enable divide by 0 trap */
307 #ifdef FPU_ERROR_BROKEN
309 * FPU error signal doesn't work on some CPU
315 npx_traps_while_probing = 0;
317 if (npx_traps_while_probing != 0) {
319 * Good, exception 16 works.
325 "FPU does not use exception 16 for error reporting\n");
331 * Probe failed. Floating point simply won't work.
332 * Notify user and disable FPU/MMX/SSE instruction execution.
334 printf("WARNING: no FPU!\n");
335 __asm __volatile("smsw %%ax; orb %0,%%al; lmsw %%ax" : :
336 "n" (CR0_EM | CR0_MP) : "ax");
339 idt[IDT_MF] = save_idt_npxtrap;
343 #ifdef CPU_ENABLE_SSE
345 * Enable XSAVE if supported and allowed by user.
346 * Calculate the xsave_mask.
352 uint64_t xsave_mask_user;
354 if (cpu_fxsr && (cpu_feature2 & CPUID2_XSAVE) != 0) {
356 TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave);
361 cpuid_count(0xd, 0x0, cp);
362 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
363 if ((cp[0] & xsave_mask) != xsave_mask)
364 panic("CPU0 does not support X87 or SSE: %x", cp[0]);
365 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0];
366 xsave_mask_user = xsave_mask;
367 TUNABLE_QUAD_FETCH("hw.xsave_mask", &xsave_mask_user);
368 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
369 xsave_mask &= xsave_mask_user;
370 if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512)
371 xsave_mask &= ~XFEATURE_AVX512;
372 if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX)
373 xsave_mask &= ~XFEATURE_MPX;
375 cpuid_count(0xd, 0x1, cp);
376 if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0)
382 * Calculate the fpu save area size.
387 #ifdef CPU_ENABLE_SSE
391 cpuid_count(0xd, 0x0, cp);
392 cpu_max_ext_state_size = cp[1];
395 * Reload the cpu_feature2, since we enabled OSXSAVE.
398 cpu_feature2 = cp[2];
401 cpu_max_ext_state_size = sizeof(union savefpu);
405 * Initialize floating point unit.
410 static union savefpu dummy;
412 #ifdef CPU_ENABLE_SSE
420 #ifdef CPU_ENABLE_SSE
425 #ifdef CPU_ENABLE_SSE
427 load_cr4(rcr4() | CR4_XSAVE);
428 load_xcr(XCR0, xsave_mask);
433 * XCR0 shall be set up before CPU can report the save area size.
439 * fninit has the same h/w bugs as fnsave. Use the detoxified
440 * fnsave to throw away any junk in the fpu. fpusave() initializes
443 * It is too early for critical_enter() to work on AP.
445 saveintr = intr_disable();
447 #ifdef CPU_ENABLE_SSE
453 control = __INITIAL_NPXCW__;
455 #ifdef CPU_ENABLE_SSE
457 mxcsr = __INITIAL_MXCSR__;
462 intr_restore(saveintr);
466 * On the boot CPU we generate a clean state that is used to
467 * initialize the floating point unit when it is first used by a
471 npxinitstate(void *arg __unused)
474 #ifdef CPU_ENABLE_SSE
475 int cp[4], i, max_ext_n;
481 npx_initialstate = malloc(cpu_max_ext_state_size, M_DEVBUF,
483 saveintr = intr_disable();
486 fpusave(npx_initialstate);
487 #ifdef CPU_ENABLE_SSE
489 if (npx_initialstate->sv_xmm.sv_env.en_mxcsr_mask)
491 npx_initialstate->sv_xmm.sv_env.en_mxcsr_mask;
493 cpu_mxcsr_mask = 0xFFBF;
496 * The fninit instruction does not modify XMM
497 * registers. The fpusave call dumped the garbage
498 * contained in the registers after reset to the
499 * initial state saved. Clear XMM registers file
500 * image to make the startup program state and signal
501 * handler XMM register content predictable.
503 bzero(npx_initialstate->sv_xmm.sv_fp,
504 sizeof(npx_initialstate->sv_xmm.sv_fp));
505 bzero(npx_initialstate->sv_xmm.sv_xmm,
506 sizeof(npx_initialstate->sv_xmm.sv_xmm));
509 bzero(npx_initialstate->sv_87.sv_ac,
510 sizeof(npx_initialstate->sv_87.sv_ac));
512 #ifdef CPU_ENABLE_SSE
514 * Create a table describing the layout of the CPU Extended
518 if (xsave_mask >> 32 != 0)
519 max_ext_n = fls(xsave_mask >> 32) + 32;
521 max_ext_n = fls(xsave_mask);
522 xsave_area_desc = malloc(max_ext_n * sizeof(struct
523 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO);
525 xsave_area_desc[0].offset = 0;
526 xsave_area_desc[0].size = 160;
528 xsave_area_desc[1].offset = 160;
529 xsave_area_desc[1].size = 288 - 160;
531 for (i = 2; i < max_ext_n; i++) {
532 cpuid_count(0xd, i, cp);
533 xsave_area_desc[i].offset = cp[1];
534 xsave_area_desc[i].size = cp[0];
539 fpu_save_area_zone = uma_zcreate("FPU_save_area",
540 cpu_max_ext_state_size, NULL, NULL, NULL, NULL,
541 XSAVE_AREA_ALIGN - 1, 0);
544 intr_restore(saveintr);
546 SYSINIT(npxinitstate, SI_SUB_DRIVERS, SI_ORDER_ANY, npxinitstate, NULL);
549 * Free coprocessor (if we have it).
557 if (curthread == PCPU_GET(fpcurthread)) {
559 fpusave(curpcb->pcb_save);
561 PCPU_SET(fpcurthread, NULL);
566 u_int masked_exceptions;
568 masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f;
570 * Log exceptions that would have trapped with the old
571 * control word (overflow, divide by 0, and invalid operand).
573 if (masked_exceptions & 0x0d)
575 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n",
576 td->td_proc->p_pid, td->td_proc->p_comm,
587 return (_MC_FPFMT_NODEV);
588 #ifdef CPU_ENABLE_SSE
590 return (_MC_FPFMT_XMM);
592 return (_MC_FPFMT_387);
596 * The following mechanism is used to ensure that the FPE_... value
597 * that is passed as a trapcode to the signal handler of the user
598 * process does not have more than one bit set.
600 * Multiple bits may be set if the user process modifies the control
601 * word while a status word bit is already set. While this is a sign
602 * of bad coding, we have no choise than to narrow them down to one
603 * bit, since we must not send a trapcode that is not exactly one of
606 * The mechanism has a static table with 127 entries. Each combination
607 * of the 7 FPU status word exception bits directly translates to a
608 * position in this table, where a single FPE_... value is stored.
609 * This FPE_... value stored there is considered the "most important"
610 * of the exception bits and will be sent as the signal code. The
611 * precedence of the bits is based upon Intel Document "Numerical
612 * Applications", Chapter "Special Computational Situations".
614 * The macro to choose one of these values does these steps: 1) Throw
615 * away status word bits that cannot be masked. 2) Throw away the bits
616 * currently masked in the control word, assuming the user isn't
617 * interested in them anymore. 3) Reinsert status word bit 7 (stack
618 * fault) if it is set, which cannot be masked but must be presered.
619 * 4) Use the remaining bits to point into the trapcode table.
621 * The 6 maskable bits in order of their preference, as stated in the
622 * above referenced Intel manual:
623 * 1 Invalid operation (FP_X_INV)
626 * 1c Operand of unsupported format
628 * 2 QNaN operand (not an exception, irrelavant here)
629 * 3 Any other invalid-operation not mentioned above or zero divide
630 * (FP_X_INV, FP_X_DZ)
631 * 4 Denormal operand (FP_X_DNML)
632 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
633 * 6 Inexact result (FP_X_IMP)
635 static char fpetable[128] = {
637 FPE_FLTINV, /* 1 - INV */
638 FPE_FLTUND, /* 2 - DNML */
639 FPE_FLTINV, /* 3 - INV | DNML */
640 FPE_FLTDIV, /* 4 - DZ */
641 FPE_FLTINV, /* 5 - INV | DZ */
642 FPE_FLTDIV, /* 6 - DNML | DZ */
643 FPE_FLTINV, /* 7 - INV | DNML | DZ */
644 FPE_FLTOVF, /* 8 - OFL */
645 FPE_FLTINV, /* 9 - INV | OFL */
646 FPE_FLTUND, /* A - DNML | OFL */
647 FPE_FLTINV, /* B - INV | DNML | OFL */
648 FPE_FLTDIV, /* C - DZ | OFL */
649 FPE_FLTINV, /* D - INV | DZ | OFL */
650 FPE_FLTDIV, /* E - DNML | DZ | OFL */
651 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
652 FPE_FLTUND, /* 10 - UFL */
653 FPE_FLTINV, /* 11 - INV | UFL */
654 FPE_FLTUND, /* 12 - DNML | UFL */
655 FPE_FLTINV, /* 13 - INV | DNML | UFL */
656 FPE_FLTDIV, /* 14 - DZ | UFL */
657 FPE_FLTINV, /* 15 - INV | DZ | UFL */
658 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
659 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
660 FPE_FLTOVF, /* 18 - OFL | UFL */
661 FPE_FLTINV, /* 19 - INV | OFL | UFL */
662 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
663 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
664 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
665 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
666 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
667 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
668 FPE_FLTRES, /* 20 - IMP */
669 FPE_FLTINV, /* 21 - INV | IMP */
670 FPE_FLTUND, /* 22 - DNML | IMP */
671 FPE_FLTINV, /* 23 - INV | DNML | IMP */
672 FPE_FLTDIV, /* 24 - DZ | IMP */
673 FPE_FLTINV, /* 25 - INV | DZ | IMP */
674 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
675 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
676 FPE_FLTOVF, /* 28 - OFL | IMP */
677 FPE_FLTINV, /* 29 - INV | OFL | IMP */
678 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
679 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
680 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
681 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
682 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
683 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
684 FPE_FLTUND, /* 30 - UFL | IMP */
685 FPE_FLTINV, /* 31 - INV | UFL | IMP */
686 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
687 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
688 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
689 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
690 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
691 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
692 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
693 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
694 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
695 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
696 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
697 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
698 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
699 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
700 FPE_FLTSUB, /* 40 - STK */
701 FPE_FLTSUB, /* 41 - INV | STK */
702 FPE_FLTUND, /* 42 - DNML | STK */
703 FPE_FLTSUB, /* 43 - INV | DNML | STK */
704 FPE_FLTDIV, /* 44 - DZ | STK */
705 FPE_FLTSUB, /* 45 - INV | DZ | STK */
706 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
707 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
708 FPE_FLTOVF, /* 48 - OFL | STK */
709 FPE_FLTSUB, /* 49 - INV | OFL | STK */
710 FPE_FLTUND, /* 4A - DNML | OFL | STK */
711 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
712 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
713 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
714 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
715 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
716 FPE_FLTUND, /* 50 - UFL | STK */
717 FPE_FLTSUB, /* 51 - INV | UFL | STK */
718 FPE_FLTUND, /* 52 - DNML | UFL | STK */
719 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
720 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
721 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
722 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
723 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
724 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
725 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
726 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
727 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
728 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
729 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
730 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
731 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
732 FPE_FLTRES, /* 60 - IMP | STK */
733 FPE_FLTSUB, /* 61 - INV | IMP | STK */
734 FPE_FLTUND, /* 62 - DNML | IMP | STK */
735 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
736 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
737 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
738 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
739 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
740 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
741 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
742 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
743 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
744 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
745 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
746 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
747 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
748 FPE_FLTUND, /* 70 - UFL | IMP | STK */
749 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
750 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
751 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
752 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
753 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
754 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
755 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
756 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
757 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
758 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
759 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
760 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
761 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
762 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
763 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
767 * Read the FP status and control words, then generate si_code value
768 * for SIGFPE. The error code chosen will be one of the
769 * FPE_... macros. It will be sent as the second argument to old
770 * BSD-style signal handlers and as "siginfo_t->si_code" (second
771 * argument) to SA_SIGINFO signal handlers.
773 * Some time ago, we cleared the x87 exceptions with FNCLEX there.
774 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The
775 * usermode code which understands the FPU hardware enough to enable
776 * the exceptions, can also handle clearing the exception state in the
777 * handler. The only consequence of not clearing the exception is the
778 * rethrow of the SIGFPE on return from the signal handler and
779 * reexecution of the corresponding instruction.
781 * For XMM traps, the exceptions were never cleared.
786 u_short control, status;
790 "npxtrap_x87: fpcurthread = %p, curthread = %p, hw_float = %d\n",
791 PCPU_GET(fpcurthread), curthread, hw_float);
792 panic("npxtrap from nowhere");
797 * Interrupt handling (for another interrupt) may have pushed the
798 * state to memory. Fetch the relevant parts of the state from
801 if (PCPU_GET(fpcurthread) != curthread) {
802 control = GET_FPU_CW(curthread);
803 status = GET_FPU_SW(curthread);
809 return (fpetable[status & ((~control & 0x3f) | 0x40)]);
812 #ifdef CPU_ENABLE_SSE
820 "npxtrap_sse: fpcurthread = %p, curthread = %p, hw_float = %d\n",
821 PCPU_GET(fpcurthread), curthread, hw_float);
822 panic("npxtrap from nowhere");
825 if (PCPU_GET(fpcurthread) != curthread)
826 mxcsr = curthread->td_pcb->pcb_save->sv_xmm.sv_env.en_mxcsr;
830 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]);
835 * Implement device not available (DNA) exception
837 * It would be better to switch FP context here (if curthread != fpcurthread)
838 * and not necessarily for every context switch, but it is too hard to
839 * access foreign pcb's.
842 static int err_count = 0;
851 if (PCPU_GET(fpcurthread) == curthread) {
852 printf("npxdna: fpcurthread == curthread %d times\n",
858 if (PCPU_GET(fpcurthread) != NULL) {
859 printf("npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n",
860 PCPU_GET(fpcurthread),
861 PCPU_GET(fpcurthread)->td_proc->p_pid,
862 curthread, curthread->td_proc->p_pid);
867 * Record new context early in case frstor causes a trap.
869 PCPU_SET(fpcurthread, curthread);
871 #ifdef CPU_ENABLE_SSE
876 if ((curpcb->pcb_flags & PCB_NPXINITDONE) == 0) {
878 * This is the first time this thread has used the FPU or
879 * the PCB doesn't contain a clean FPU state. Explicitly
880 * load an initial state.
882 * We prefer to restore the state from the actual save
883 * area in PCB instead of directly loading from
884 * npx_initialstate, to ignite the XSAVEOPT
887 bcopy(npx_initialstate, curpcb->pcb_save, cpu_max_ext_state_size);
888 fpurstor(curpcb->pcb_save);
889 if (curpcb->pcb_initial_npxcw != __INITIAL_NPXCW__)
890 fldcw(curpcb->pcb_initial_npxcw);
891 curpcb->pcb_flags |= PCB_NPXINITDONE;
892 if (PCB_USER_FPU(curpcb))
893 curpcb->pcb_flags |= PCB_NPXUSERINITDONE;
895 fpurstor(curpcb->pcb_save);
903 * Wrapper for fpusave() called from context switch routines.
905 * npxsave() must be called with interrupts disabled, so that it clears
906 * fpcurthread atomically with saving the state. We require callers to do the
907 * disabling, since most callers need to disable interrupts anyway to call
908 * npxsave() atomically with checking fpcurthread.
916 #ifdef CPU_ENABLE_SSE
918 xsaveopt((char *)addr, xsave_mask);
923 PCPU_SET(fpcurthread, NULL);
927 * Unconditionally save the current co-processor state across suspend and
931 npxsuspend(union savefpu *addr)
937 if (PCPU_GET(fpcurthread) == NULL) {
938 bcopy(npx_initialstate, addr, cpu_max_ext_state_size);
948 npxresume(union savefpu *addr)
968 * Discard pending exceptions in the !cpu_fxsr case so that unmasked
969 * ones don't cause a panic on the next frstor.
971 #ifdef CPU_ENABLE_SSE
976 td = PCPU_GET(fpcurthread);
977 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread"));
979 PCPU_SET(fpcurthread, NULL);
980 td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE;
985 * Get the user state of the FPU into pcb->pcb_user_save without
986 * dropping ownership (if possible). It returns the FPU ownership
990 npxgetregs(struct thread *td)
993 #ifdef CPU_ENABLE_SSE
994 uint64_t *xstate_bv, bit;
1001 return (_MC_FPOWNED_NONE);
1004 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) {
1005 bcopy(npx_initialstate, get_pcb_user_save_pcb(pcb),
1006 cpu_max_ext_state_size);
1007 SET_FPU_CW(get_pcb_user_save_pcb(pcb), pcb->pcb_initial_npxcw);
1009 return (_MC_FPOWNED_PCB);
1012 if (td == PCPU_GET(fpcurthread)) {
1013 fpusave(get_pcb_user_save_pcb(pcb));
1014 #ifdef CPU_ENABLE_SSE
1018 * fnsave initializes the FPU and destroys whatever
1019 * context it contains. Make sure the FPU owner
1020 * starts with a clean state next time.
1023 owned = _MC_FPOWNED_FPU;
1025 owned = _MC_FPOWNED_PCB;
1028 #ifdef CPU_ENABLE_SSE
1031 * Handle partially saved state.
1033 sa = (char *)get_pcb_user_save_pcb(pcb);
1034 xstate_bv = (uint64_t *)(sa + sizeof(union savefpu) +
1035 offsetof(struct xstate_hdr, xstate_bv));
1036 if (xsave_mask >> 32 != 0)
1037 max_ext_n = fls(xsave_mask >> 32) + 32;
1039 max_ext_n = fls(xsave_mask);
1040 for (i = 0; i < max_ext_n; i++) {
1042 if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0)
1044 bcopy((char *)npx_initialstate +
1045 xsave_area_desc[i].offset,
1046 sa + xsave_area_desc[i].offset,
1047 xsave_area_desc[i].size);
1056 npxuserinited(struct thread *td)
1061 if (PCB_USER_FPU(pcb))
1062 pcb->pcb_flags |= PCB_NPXINITDONE;
1063 pcb->pcb_flags |= PCB_NPXUSERINITDONE;
1066 #ifdef CPU_ENABLE_SSE
1068 npxsetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size)
1070 struct xstate_hdr *hdr, *ehdr;
1071 size_t len, max_len;
1074 /* XXXKIB should we clear all extended state in xstate_bv instead ? */
1075 if (xfpustate == NULL)
1078 return (EOPNOTSUPP);
1080 len = xfpustate_size;
1081 if (len < sizeof(struct xstate_hdr))
1083 max_len = cpu_max_ext_state_size - sizeof(union savefpu);
1087 ehdr = (struct xstate_hdr *)xfpustate;
1088 bv = ehdr->xstate_bv;
1093 if (bv & ~xsave_mask)
1096 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1);
1098 hdr->xstate_bv = bv;
1099 bcopy(xfpustate + sizeof(struct xstate_hdr),
1100 (char *)(hdr + 1), len - sizeof(struct xstate_hdr));
1107 npxsetregs(struct thread *td, union savefpu *addr, char *xfpustate,
1108 size_t xfpustate_size)
1111 #ifdef CPU_ENABLE_SSE
1120 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
1121 #ifdef CPU_ENABLE_SSE
1122 error = npxsetxstate(td, xfpustate, xfpustate_size);
1129 fnclex(); /* As in npxdrop(). */
1130 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
1131 fpurstor(get_pcb_user_save_td(td));
1133 pcb->pcb_flags |= PCB_NPXUSERINITDONE | PCB_NPXINITDONE;
1136 #ifdef CPU_ENABLE_SSE
1137 error = npxsetxstate(td, xfpustate, xfpustate_size);
1141 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
1149 union savefpu *addr;
1152 #ifdef CPU_ENABLE_SSE
1154 xsave((char *)addr, xsave_mask);
1162 #ifdef CPU_ENABLE_SSE
1164 npx_fill_fpregs_xmm1(struct savexmm *sv_xmm, struct save87 *sv_87)
1166 struct env87 *penv_87;
1167 struct envxmm *penv_xmm;
1170 penv_87 = &sv_87->sv_env;
1171 penv_xmm = &sv_xmm->sv_env;
1173 /* FPU control/status */
1174 penv_87->en_cw = penv_xmm->en_cw;
1175 penv_87->en_sw = penv_xmm->en_sw;
1176 penv_87->en_fip = penv_xmm->en_fip;
1177 penv_87->en_fcs = penv_xmm->en_fcs;
1178 penv_87->en_opcode = penv_xmm->en_opcode;
1179 penv_87->en_foo = penv_xmm->en_foo;
1180 penv_87->en_fos = penv_xmm->en_fos;
1182 /* FPU registers and tags */
1183 penv_87->en_tw = 0xffff;
1184 for (i = 0; i < 8; ++i) {
1185 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
1186 if ((penv_xmm->en_tw & (1 << i)) != 0)
1187 /* zero and special are set as valid */
1188 penv_87->en_tw &= ~(3 << i);
1193 npx_fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
1196 bzero(sv_87, sizeof(*sv_87));
1197 npx_fill_fpregs_xmm1(sv_xmm, sv_87);
1201 npx_set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
1203 struct env87 *penv_87;
1204 struct envxmm *penv_xmm;
1207 penv_87 = &sv_87->sv_env;
1208 penv_xmm = &sv_xmm->sv_env;
1210 /* FPU control/status */
1211 penv_xmm->en_cw = penv_87->en_cw;
1212 penv_xmm->en_sw = penv_87->en_sw;
1213 penv_xmm->en_fip = penv_87->en_fip;
1214 penv_xmm->en_fcs = penv_87->en_fcs;
1215 penv_xmm->en_opcode = penv_87->en_opcode;
1216 penv_xmm->en_foo = penv_87->en_foo;
1217 penv_xmm->en_fos = penv_87->en_fos;
1219 /* FPU registers and tags */
1220 penv_xmm->en_tw = 0;
1221 for (i = 0; i < 8; ++i) {
1222 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
1223 if ((penv_87->en_tw && (3 << i)) != (3 << i))
1224 penv_xmm->en_tw |= 1 << i;
1227 #endif /* CPU_ENABLE_SSE */
1230 npx_get_fsave(void *addr)
1237 sv = get_pcb_user_save_td(td);
1238 #ifdef CPU_ENABLE_SSE
1240 npx_fill_fpregs_xmm1(&sv->sv_xmm, addr);
1243 bcopy(sv, addr, sizeof(struct env87) +
1244 sizeof(struct fpacc87[8]));
1248 npx_set_fsave(void *addr)
1253 bzero(&sv, sizeof(sv));
1254 #ifdef CPU_ENABLE_SSE
1256 npx_set_fpregs_xmm(addr, &sv.sv_xmm);
1259 bcopy(addr, &sv, sizeof(struct env87) +
1260 sizeof(struct fpacc87[8]));
1261 error = npxsetregs(curthread, &sv, NULL, 0);
1265 #ifdef CPU_ENABLE_SSE
1267 * On AuthenticAMD processors, the fxrstor instruction does not restore
1268 * the x87's stored last instruction pointer, last data pointer, and last
1269 * opcode values, except in the rare case in which the exception summary
1270 * (ES) bit in the x87 status word is set to 1.
1272 * In order to avoid leaking this information across processes, we clean
1273 * these values by performing a dummy load before executing fxrstor().
1276 fpu_clean_state(void)
1278 static float dummy_variable = 0.0;
1282 * Clear the ES bit in the x87 status word if it is currently
1283 * set, in order to avoid causing a fault in the upcoming load.
1290 * Load the dummy variable into the x87 stack. This mangles
1291 * the x87 stack, but we don't care since we're about to call
1294 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable));
1296 #endif /* CPU_ENABLE_SSE */
1300 union savefpu *addr;
1303 #ifdef CPU_ENABLE_SSE
1305 xrstor((char *)addr, xsave_mask);
1315 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
1317 static struct isa_pnp_id npxisa_ids[] = {
1318 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
1323 npxisa_probe(device_t dev)
1326 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) {
1333 npxisa_attach(device_t dev)
1338 static device_method_t npxisa_methods[] = {
1339 /* Device interface */
1340 DEVMETHOD(device_probe, npxisa_probe),
1341 DEVMETHOD(device_attach, npxisa_attach),
1342 DEVMETHOD(device_detach, bus_generic_detach),
1343 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1344 DEVMETHOD(device_suspend, bus_generic_suspend),
1345 DEVMETHOD(device_resume, bus_generic_resume),
1350 static driver_t npxisa_driver = {
1356 static devclass_t npxisa_devclass;
1358 DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0);
1360 DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0);
1362 #endif /* DEV_ISA */
1364 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx",
1365 "Kernel contexts for FPU state");
1367 #define FPU_KERN_CTX_NPXINITDONE 0x01
1368 #define FPU_KERN_CTX_DUMMY 0x02
1369 #define FPU_KERN_CTX_INUSE 0x04
1371 struct fpu_kern_ctx {
1372 union savefpu *prev;
1377 struct fpu_kern_ctx *
1378 fpu_kern_alloc_ctx(u_int flags)
1380 struct fpu_kern_ctx *res;
1383 sz = sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN +
1384 cpu_max_ext_state_size;
1385 res = malloc(sz, M_FPUKERN_CTX, ((flags & FPU_KERN_NOWAIT) ?
1386 M_NOWAIT : M_WAITOK) | M_ZERO);
1391 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx)
1394 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("free'ing inuse ctx"));
1395 /* XXXKIB clear the memory ? */
1396 free(ctx, M_FPUKERN_CTX);
1399 static union savefpu *
1400 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx)
1404 p = (vm_offset_t)&ctx->hwstate1;
1405 p = roundup2(p, XSAVE_AREA_ALIGN);
1406 return ((union savefpu *)p);
1410 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags)
1414 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("using inuse ctx"));
1416 if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) {
1417 ctx->flags = FPU_KERN_CTX_DUMMY | FPU_KERN_CTX_INUSE;
1421 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save ==
1422 get_pcb_user_save_pcb(pcb), ("mangled pcb_save"));
1423 ctx->flags = FPU_KERN_CTX_INUSE;
1424 if ((pcb->pcb_flags & PCB_NPXINITDONE) != 0)
1425 ctx->flags |= FPU_KERN_CTX_NPXINITDONE;
1427 ctx->prev = pcb->pcb_save;
1428 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx);
1429 pcb->pcb_flags |= PCB_KERNNPX;
1430 pcb->pcb_flags &= ~PCB_NPXINITDONE;
1435 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx)
1439 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) != 0,
1440 ("leaving not inuse ctx"));
1441 ctx->flags &= ~FPU_KERN_CTX_INUSE;
1443 if (is_fpu_kern_thread(0) && (ctx->flags & FPU_KERN_CTX_DUMMY) != 0)
1447 if (curthread == PCPU_GET(fpcurthread))
1450 pcb->pcb_save = ctx->prev;
1451 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) {
1452 if ((pcb->pcb_flags & PCB_NPXUSERINITDONE) != 0)
1453 pcb->pcb_flags |= PCB_NPXINITDONE;
1455 pcb->pcb_flags &= ~PCB_NPXINITDONE;
1456 pcb->pcb_flags &= ~PCB_KERNNPX;
1458 if ((ctx->flags & FPU_KERN_CTX_NPXINITDONE) != 0)
1459 pcb->pcb_flags |= PCB_NPXINITDONE;
1461 pcb->pcb_flags &= ~PCB_NPXINITDONE;
1462 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave"));
1468 fpu_kern_thread(u_int flags)
1471 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0,
1472 ("Only kthread may use fpu_kern_thread"));
1473 KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb),
1474 ("mangled pcb_save"));
1475 KASSERT(PCB_USER_FPU(curpcb), ("recursive call"));
1477 curpcb->pcb_flags |= PCB_KERNNPX;
1482 is_fpu_kern_thread(u_int flags)
1485 if ((curthread->td_pflags & TDP_KTHREAD) == 0)
1487 return ((curpcb->pcb_flags & PCB_KERNNPX) != 0);
1491 * FPU save area alloc/free/init utility routines
1494 fpu_save_area_alloc(void)
1497 return (uma_zalloc(fpu_save_area_zone, 0));
1501 fpu_save_area_free(union savefpu *fsa)
1504 uma_zfree(fpu_save_area_zone, fsa);
1508 fpu_save_area_reset(union savefpu *fsa)
1511 bcopy(npx_initialstate, fsa, cpu_max_ext_state_size);