sys/i386/isa/rc.c

   1 /*
   2  * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia.
   3  * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD$
  28  *
  29  */
  30
  31 /*
  32  * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver
  33  *
  34  */
  35
  36 #include "rc.h"
  37
  38 /*#define RCDEBUG*/
  39
  40 #include <sys/param.h>
  41 #include <sys/systm.h>
  42 #include <sys/kernel.h>
  43 #include <sys/tty.h>
  44 #include <sys/conf.h>
  45 #include <sys/dkstat.h>
  46 #include <sys/fcntl.h>
  47 #include <sys/bus.h>
  48 #include <sys/interrupt.h>
  49
  50
  51 #include <i386/isa/isa_device.h>
  52
  53 #include <i386/isa/ic/cd180.h>
  54 #include <i386/isa/rcreg.h>
  55
  56 /* Prototypes */
  57 static int     rcprobe         __P((struct isa_device *));
  58 static int     rcattach        __P((struct isa_device *));
  59
  60 #define rcin(port)      RC_IN  (nec, port)
  61 #define rcout(port,v)   RC_OUT (nec, port, v)
  62
  63 #define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__)
  64 #define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd))
  65
  66 #define RC_IBUFSIZE     256
  67 #define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE)
  68 #define RC_OBUFSIZE     512
  69 #define RC_IHIGHWATER   (3 * RC_IBUFSIZE / 4)
  70 #define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE)
  71 #define LOTS_OF_EVENTS  64
  72
  73 #define RC_FAKEID       0x10
  74
  75 #define RC_PROBED 1
  76 #define RC_ATTACHED 2
  77
  78 #define GET_UNIT(dev)   (minor(dev) & 0x3F)
  79 #define CALLOUT(dev)    (minor(dev) & 0x80)
  80
  81 /* For isa routines */
  82 struct isa_driver rcdriver = {
  83         INTR_TYPE_TTY,
  84         rcprobe,
  85         rcattach,
  86         "rc"
  87 };
  88 COMPAT_ISA_DRIVER(rc, rcdriver);
  89
  90 static  d_open_t        rcopen;
  91 static  d_close_t       rcclose;
  92 static  d_ioctl_t       rcioctl;
  93
  94 #define CDEV_MAJOR      63
  95 static struct cdevsw rc_cdevsw = {
  96         /* open */      rcopen,
  97         /* close */     rcclose,
  98         /* read */      ttyread,
  99         /* write */     ttywrite,
 100         /* ioctl */     rcioctl,
 101         /* poll */      ttypoll,
 102         /* mmap */      nommap,
 103         /* strategy */  nostrategy,
 104         /* name */      "rc",
 105         /* maj */       CDEV_MAJOR,
 106         /* dump */      nodump,
 107         /* psize */     nopsize,
 108         /* flags */     D_TTY | D_KQFILTER,
 109         /* kqfilter */  ttykqfilter,
 110 };
 111
 112 /* Per-board structure */
 113 static struct rc_softc {
 114         u_int           rcb_probed;     /* 1 - probed, 2 - attached */
 115         u_int           rcb_addr;       /* Base I/O addr        */
 116         u_int           rcb_unit;       /* unit #               */
 117         u_char          rcb_dtr;        /* DTR status           */
 118         struct rc_chans *rcb_baserc;    /* base rc ptr          */
 119 } rc_softc[NRC];
 120
 121 /* Per-channel structure */
 122 static struct rc_chans  {
 123         struct rc_softc *rc_rcb;                /* back ptr             */
 124         u_short          rc_flags;              /* Misc. flags          */
 125         int              rc_chan;               /* Channel #            */
 126         u_char           rc_ier;                /* intr. enable reg     */
 127         u_char           rc_msvr;               /* modem sig. status    */
 128         u_char           rc_cor2;               /* options reg          */
 129         u_char           rc_pendcmd;            /* special cmd pending  */
 130         u_int            rc_dtrwait;            /* dtr timeout          */
 131         u_int            rc_dcdwaits;           /* how many waits DCD in open */
 132         u_char           rc_hotchar;            /* end packed optimize */
 133         struct tty      *rc_tp;                 /* tty struct           */
 134         u_char          *rc_iptr;               /* Chars input buffer         */
 135         u_char          *rc_hiwat;              /* hi-water mark        */
 136         u_char          *rc_bufend;             /* end of buffer        */
 137         u_char          *rc_optr;               /* ptr in output buf    */
 138         u_char          *rc_obufend;            /* end of output buf    */
 139         u_char           rc_ibuf[4 * RC_IBUFSIZE];  /* input buffer         */
 140         u_char           rc_obuf[RC_OBUFSIZE];  /* output buffer        */
 141 } rc_chans[NRC * CD180_NCHAN];
 142
 143 static int rc_scheduled_event = 0;
 144
 145 /* for pstat -t */
 146 static struct tty rc_tty[NRC * CD180_NCHAN];
 147 static const int  nrc_tty = NRC * CD180_NCHAN;
 148
 149 /* Flags */
 150 #define RC_DTR_OFF      0x0001          /* DTR wait, for close/open     */
 151 #define RC_ACTOUT       0x0002          /* Dial-out port active         */
 152 #define RC_RTSFLOW      0x0004          /* RTS flow ctl enabled         */
 153 #define RC_CTSFLOW      0x0008          /* CTS flow ctl enabled         */
 154 #define RC_DORXFER      0x0010          /* RXFER event planned          */
 155 #define RC_DOXXFER      0x0020          /* XXFER event planned          */
 156 #define RC_MODCHG       0x0040          /* Modem status changed         */
 157 #define RC_OSUSP        0x0080          /* Output suspended             */
 158 #define RC_OSBUSY       0x0100          /* start() routine in progress  */
 159 #define RC_WAS_BUFOVFL  0x0200          /* low-level buffer ovferflow   */
 160 #define RC_WAS_SILOVFL  0x0400          /* silo buffer overflow         */
 161 #define RC_SEND_RDY     0x0800          /* ready to send */
 162
 163 /* Table for translation of RCSR status bits to internal form */
 164 static int rc_rcsrt[16] = {
 165         0,             TTY_OE,               TTY_FE,
 166         TTY_FE|TTY_OE, TTY_PE,               TTY_PE|TTY_OE,
 167         TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI,
 168         TTY_BI|TTY_OE, TTY_BI|TTY_FE,        TTY_BI|TTY_FE|TTY_OE,
 169         TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE,
 170         TTY_BI|TTY_PE|TTY_FE|TTY_OE
 171 };
 172
 173 static void     *rc_ih;
 174
 175 /* Static prototypes */
 176 static ointhand2_t rcintr;
 177 static void rc_hwreset          __P((int, int, unsigned int));
 178 static int  rc_test             __P((int, int));
 179 static void rc_discard_output   __P((struct rc_chans *));
 180 static void rc_hardclose        __P((struct rc_chans *));
 181 static int  rc_modctl           __P((struct rc_chans *, int, int));
 182 static void rc_start            __P((struct tty *));
 183 static void rc_stop              __P((struct tty *, int rw));
 184 static int  rc_param            __P((struct tty *, struct termios *));
 185 static void rcpoll              __P((void *));
 186 static void rc_reinit           __P((struct rc_softc *));
 187 #ifdef RCDEBUG
 188 static void printrcflags();
 189 #endif
 190 static timeout_t rc_dtrwakeup;
 191 static timeout_t rc_wakeup;
 192 static void disc_optim          __P((struct tty *tp, struct termios *t, struct rc_chans *));
 193 static void rc_wait0            __P((int nec, int unit, int chan, int line));
 194
 195 /**********************************************/
 196
 197 /* Quick device probing */
 198 static int
 199 rcprobe(dvp)
 200         struct  isa_device      *dvp;
 201 {
 202         int             irq = ffs(dvp->id_irq) - 1;
 203         register int    nec = dvp->id_iobase;
 204
 205         if (dvp->id_unit > NRC)
 206                 return 0;
 207         if (!RC_VALIDADDR(nec)) {
 208                 printf("rc%d: illegal base address %x\n", dvp->id_unit, nec);
 209                 return 0;
 210         }
 211         if (!RC_VALIDIRQ(irq)) {
 212                 printf("rc%d: illegal IRQ value %d\n", dvp->id_unit, irq);
 213                 return 0;
 214         }
 215         rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */
 216         rcout(CD180_PPRH, 0x11);
 217         if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11)
 218                 return 0;
 219         /* Now, test the board more thoroughly, with diagnostic */
 220         if (rc_test(nec, dvp->id_unit))
 221                 return 0;
 222         rc_softc[dvp->id_unit].rcb_probed = RC_PROBED;
 223
 224         return 0xF;
 225 }
 226
 227 static int
 228 rcattach(dvp)
 229         struct  isa_device      *dvp;
 230 {
 231         register int            chan, nec = dvp->id_iobase;
 232         struct rc_softc         *rcb = &rc_softc[dvp->id_unit];
 233         struct rc_chans         *rc  = &rc_chans[dvp->id_unit * CD180_NCHAN];
 234         static int              rc_started = 0;
 235         struct tty              *tp;
 236
 237         dvp->id_ointr = rcintr;
 238
 239         /* Thorooughly test the device */
 240         if (rcb->rcb_probed != RC_PROBED)
 241                 return 0;
 242         rcb->rcb_addr   = nec;
 243         rcb->rcb_dtr    = 0;
 244         rcb->rcb_baserc = rc;
 245         rcb->rcb_unit   = dvp->id_unit;
 246         /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/
 247         printf("rc%d: %d chans, firmware rev. %c\n", rcb->rcb_unit,
 248                 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A');
 249
 250         for (chan = 0; chan < CD180_NCHAN; chan++, rc++) {
 251                 rc->rc_rcb     = rcb;
 252                 rc->rc_chan    = chan;
 253                 rc->rc_iptr    = rc->rc_ibuf;
 254                 rc->rc_bufend  = &rc->rc_ibuf[RC_IBUFSIZE];
 255                 rc->rc_hiwat   = &rc->rc_ibuf[RC_IHIGHWATER];
 256                 rc->rc_flags   = rc->rc_ier = rc->rc_msvr = 0;
 257                 rc->rc_cor2    = rc->rc_pendcmd = 0;
 258                 rc->rc_optr    = rc->rc_obufend  = rc->rc_obuf;
 259                 rc->rc_dtrwait = 3 * hz;
 260                 rc->rc_dcdwaits= 0;
 261                 rc->rc_hotchar = 0;
 262                 tp = rc->rc_tp = &rc_tty[chan + (dvp->id_unit * CD180_NCHAN)];
 263                 ttychars(tp);
 264                 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0;
 265                 tp->t_cflag = TTYDEF_CFLAG;
 266                 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
 267         }
 268         rcb->rcb_probed = RC_ATTACHED;
 269         if (!rc_started) {
 270                 cdevsw_add(&rc_cdevsw);
 271                 swi_add(&tty_ithd, "tty:rc", rcpoll, NULL, SWI_TTY, 0, &rc_ih);
 272                 rc_wakeup((void *)NULL);
 273                 rc_started = 1;
 274         }
 275         return 1;
 276 }
 277
 278 /* RC interrupt handling */
 279 static void
 280 rcintr(unit)
 281         int             unit;
 282 {
 283         register struct rc_softc        *rcb = &rc_softc[unit];
 284         register struct rc_chans        *rc;
 285         register int                    nec, resid;
 286         register u_char                 val, iack, bsr, ucnt, *optr;
 287         int                             good_data, t_state;
 288
 289         if (rcb->rcb_probed != RC_ATTACHED) {
 290                 printf("rc%d: bogus interrupt\n", unit);
 291                 return;
 292         }
 293         nec = rcb->rcb_addr;
 294
 295         bsr = ~(rcin(RC_BSR));
 296
 297         if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) {
 298                 printf("rc%d: extra interrupt\n", unit);
 299                 rcout(CD180_EOIR, 0);
 300                 return;
 301         }
 302
 303         while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) {
 304 #ifdef RCDEBUG_DETAILED
 305                 printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr,
 306                         (bsr & RC_BSR_TOUT)?"TOUT ":"",
 307                         (bsr & RC_BSR_RXINT)?"RXINT ":"",
 308                         (bsr & RC_BSR_TXINT)?"TXINT ":"",
 309                         (bsr & RC_BSR_MOINT)?"MOINT":"");
 310 #endif
 311                 if (bsr & RC_BSR_TOUT) {
 312                         printf("rc%d: hardware failure, reset board\n", unit);
 313                         rcout(RC_CTOUT, 0);
 314                         rc_reinit(rcb);
 315                         return;
 316                 }
 317                 if (bsr & RC_BSR_RXINT) {
 318                         iack = rcin(RC_PILR_RX);
 319                         good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID));
 320                         if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) {
 321                                 printf("rc%d: fake rxint: %02x\n", unit, iack);
 322                                 goto more_intrs;
 323                         }
 324                         rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
 325                         t_state = rc->rc_tp->t_state;
 326                         /* Do RTS flow control stuff */
 327                         if (  (rc->rc_flags & RC_RTSFLOW)
 328                             || !(t_state & TS_ISOPEN)
 329                            ) {
 330                                 if (  (   !(t_state & TS_ISOPEN)
 331                                        || (t_state & TS_TBLOCK)
 332                                       )
 333                                     && (rc->rc_msvr & MSVR_RTS)
 334                                    )
 335                                         rcout(CD180_MSVR,
 336                                                 rc->rc_msvr &= ~MSVR_RTS);
 337                                 else if (!(rc->rc_msvr & MSVR_RTS))
 338                                         rcout(CD180_MSVR,
 339                                                 rc->rc_msvr |= MSVR_RTS);
 340                         }
 341                         ucnt  = rcin(CD180_RDCR) & 0xF;
 342                         resid = 0;
 343
 344                         if (t_state & TS_ISOPEN) {
 345                                 /* check for input buffer overflow */
 346                                 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) {
 347                                         resid  = ucnt;
 348                                         ucnt   = rc->rc_bufend - rc->rc_iptr;
 349                                         resid -= ucnt;
 350                                         if (!(rc->rc_flags & RC_WAS_BUFOVFL)) {
 351                                                 rc->rc_flags |= RC_WAS_BUFOVFL;
 352                                                 rc_scheduled_event++;
 353                                         }
 354                                 }
 355                                 optr = rc->rc_iptr;
 356                                 /* check foor good data */
 357                                 if (good_data) {
 358                                         while (ucnt-- > 0) {
 359                                                 val = rcin(CD180_RDR);
 360                                                 optr[0] = val;
 361                                                 optr[INPUT_FLAGS_SHIFT] = 0;
 362                                                 optr++;
 363                                                 rc_scheduled_event++;
 364                                                 if (val != 0 && val == rc->rc_hotchar)
 365                                                         swi_sched(rc_ih, SWI_NOSWITCH);
 366                                         }
 367                                 } else {
 368                                         /* Store also status data */
 369                                         while (ucnt-- > 0) {
 370                                                 iack = rcin(CD180_RCSR);
 371                                                 if (iack & RCSR_Timeout)
 372                                                         break;
 373                                                 if (   (iack & RCSR_OE)
 374                                                     && !(rc->rc_flags & RC_WAS_SILOVFL)) {
 375                                                         rc->rc_flags |= RC_WAS_SILOVFL;
 376                                                         rc_scheduled_event++;
 377                                                 }
 378                                                 val = rcin(CD180_RDR);
 379                                                 /*
 380                                                   Don't store PE if IGNPAR and BREAK if IGNBRK,
 381                                                   this hack allows "raw" tty optimization
 382                                                   works even if IGN* is set.
 383                                                 */
 384                                                 if (   !(iack & (RCSR_PE|RCSR_FE|RCSR_Break))
 385                                                     || ((!(iack & (RCSR_PE|RCSR_FE))
 386                                                     ||  !(rc->rc_tp->t_iflag & IGNPAR))
 387                                                     && (!(iack & RCSR_Break)
 388                                                     ||  !(rc->rc_tp->t_iflag & IGNBRK)))) {
 389                                                         if (   (iack & (RCSR_PE|RCSR_FE))
 390                                                             && (t_state & TS_CAN_BYPASS_L_RINT)
 391                                                             && ((iack & RCSR_FE)
 392                                                             ||  ((iack & RCSR_PE)
 393                                                             &&  (rc->rc_tp->t_iflag & INPCK))))
 394                                                                 val = 0;
 395                                                         else if (val != 0 && val == rc->rc_hotchar)
 396                                                                 swi_sched(rc_ih, SWI_NOSWITCH);
 397                                                         optr[0] = val;
 398                                                         optr[INPUT_FLAGS_SHIFT] = iack;
 399                                                         optr++;
 400                                                         rc_scheduled_event++;
 401                                                 }
 402                                         }
 403                                 }
 404                                 rc->rc_iptr = optr;
 405                                 rc->rc_flags |= RC_DORXFER;
 406                         } else
 407                                 resid = ucnt;
 408                         /* Clear FIFO if necessary */
 409                         while (resid-- > 0) {
 410                                 if (!good_data)
 411                                         iack = rcin(CD180_RCSR);
 412                                 else
 413                                         iack = 0;
 414                                 if (iack & RCSR_Timeout)
 415                                         break;
 416                                 (void) rcin(CD180_RDR);
 417                         }
 418                         goto more_intrs;
 419                 }
 420                 if (bsr & RC_BSR_MOINT) {
 421                         iack = rcin(RC_PILR_MODEM);
 422                         if (iack != (GIVR_IT_MSCI | RC_FAKEID)) {
 423                                 printf("rc%d: fake moint: %02x\n", unit, iack);
 424                                 goto more_intrs;
 425                         }
 426                         rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
 427                         iack = rcin(CD180_MCR);
 428                         rc->rc_msvr = rcin(CD180_MSVR);
 429                         rcout(CD180_MCR, 0);
 430 #ifdef RCDEBUG
 431                         printrcflags(rc, "moint");
 432 #endif
 433                         if (rc->rc_flags & RC_CTSFLOW) {
 434                                 if (rc->rc_msvr & MSVR_CTS)
 435                                         rc->rc_flags |= RC_SEND_RDY;
 436                                 else
 437                                         rc->rc_flags &= ~RC_SEND_RDY;
 438                         } else
 439                                 rc->rc_flags |= RC_SEND_RDY;
 440                         if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) {
 441                                 rc_scheduled_event += LOTS_OF_EVENTS;
 442                                 rc->rc_flags |= RC_MODCHG;
 443                                 swi_sched(rc_ih, SWI_NOSWITCH);
 444                         }
 445                         goto more_intrs;
 446                 }
 447                 if (bsr & RC_BSR_TXINT) {
 448                         iack = rcin(RC_PILR_TX);
 449                         if (iack != (GIVR_IT_TDI | RC_FAKEID)) {
 450                                 printf("rc%d: fake txint: %02x\n", unit, iack);
 451                                 goto more_intrs;
 452                         }
 453                         rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
 454                         if (    (rc->rc_flags & RC_OSUSP)
 455                             || !(rc->rc_flags & RC_SEND_RDY)
 456                            )
 457                                 goto more_intrs;
 458                         /* Handle breaks and other stuff */
 459                         if (rc->rc_pendcmd) {
 460                                 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC);
 461                                 rcout(CD180_TDR,  CD180_C_ESC);
 462                                 rcout(CD180_TDR,  rc->rc_pendcmd);
 463                                 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC);
 464                                 rc->rc_pendcmd = 0;
 465                                 goto more_intrs;
 466                         }
 467                         optr = rc->rc_optr;
 468                         resid = rc->rc_obufend - optr;
 469                         if (resid > CD180_NFIFO)
 470                                 resid = CD180_NFIFO;
 471                         while (resid-- > 0)
 472                                 rcout(CD180_TDR, *optr++);
 473                         rc->rc_optr = optr;
 474
 475                         /* output completed? */
 476                         if (optr >= rc->rc_obufend) {
 477                                 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy);
 478 #ifdef RCDEBUG
 479                                 printf("rc%d/%d: output completed\n", unit, rc->rc_chan);
 480 #endif
 481                                 if (!(rc->rc_flags & RC_DOXXFER)) {
 482                                         rc_scheduled_event += LOTS_OF_EVENTS;
 483                                         rc->rc_flags |= RC_DOXXFER;
 484                                         swi_sched(rc_ih, SWI_NOSWITCH);
 485                                 }
 486                         }
 487                 }
 488         more_intrs:
 489                 rcout(CD180_EOIR, 0);   /* end of interrupt */
 490                 rcout(RC_CTOUT, 0);
 491                 bsr = ~(rcin(RC_BSR));
 492         }
 493 }
 494
 495 /* Feed characters to output buffer */
 496 static void rc_start(tp)
 497 register struct tty *tp;
 498 {
 499         register struct rc_chans       *rc = &rc_chans[GET_UNIT(tp->t_dev)];
 500         register int                    nec = rc->rc_rcb->rcb_addr, s;
 501
 502         if (rc->rc_flags & RC_OSBUSY)
 503                 return;
 504         s = spltty();
 505         rc->rc_flags |= RC_OSBUSY;
 506         disable_intr();
 507         if (tp->t_state & TS_TTSTOP)
 508                 rc->rc_flags |= RC_OSUSP;
 509         else
 510                 rc->rc_flags &= ~RC_OSUSP;
 511         /* Do RTS flow control stuff */
 512         if (   (rc->rc_flags & RC_RTSFLOW)
 513             && (tp->t_state & TS_TBLOCK)
 514             && (rc->rc_msvr & MSVR_RTS)
 515            ) {
 516                 rcout(CD180_CAR, rc->rc_chan);
 517                 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS);
 518         } else if (!(rc->rc_msvr & MSVR_RTS)) {
 519                 rcout(CD180_CAR, rc->rc_chan);
 520                 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS);
 521         }
 522         enable_intr();
 523         if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP))
 524                 goto out;
 525 #ifdef RCDEBUG
 526         printrcflags(rc, "rcstart");
 527 #endif
 528         ttwwakeup(tp);
 529 #ifdef RCDEBUG
 530         printf("rcstart: outq = %d obuf = %d\n",
 531                 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr);
 532 #endif
 533         if (tp->t_state & TS_BUSY)
 534                 goto    out;    /* output still in progress ... */
 535
 536         if (tp->t_outq.c_cc > 0) {
 537                 u_int   ocnt;
 538
 539                 tp->t_state |= TS_BUSY;
 540                 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf);
 541                 disable_intr();
 542                 rc->rc_optr = rc->rc_obuf;
 543                 rc->rc_obufend = rc->rc_optr + ocnt;
 544                 enable_intr();
 545                 if (!(rc->rc_ier & IER_TxRdy)) {
 546 #ifdef RCDEBUG
 547                         printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan);
 548 #endif
 549                         rcout(CD180_CAR, rc->rc_chan);
 550                         rcout(CD180_IER, rc->rc_ier |= IER_TxRdy);
 551                 }
 552         }
 553 out:
 554         rc->rc_flags &= ~RC_OSBUSY;
 555         (void) splx(s);
 556 }
 557
 558 /* Handle delayed events. */
 559 void rcpoll(void *arg)
 560 {
 561         register struct rc_chans *rc;
 562         register struct rc_softc *rcb;
 563         register u_char        *tptr, *eptr;
 564         register struct tty    *tp;
 565         register int            chan, icnt, nec, unit;
 566
 567         if (rc_scheduled_event == 0)
 568                 return;
 569 repeat:
 570         for (unit = 0; unit < NRC; unit++) {
 571                 rcb = &rc_softc[unit];
 572                 rc = rcb->rcb_baserc;
 573                 nec = rc->rc_rcb->rcb_addr;
 574                 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) {
 575                         tp = rc->rc_tp;
 576 #ifdef RCDEBUG
 577                         if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG|
 578                             RC_WAS_BUFOVFL|RC_WAS_SILOVFL))
 579                                 printrcflags(rc, "rcevent");
 580 #endif
 581                         if (rc->rc_flags & RC_WAS_BUFOVFL) {
 582                                 disable_intr();
 583                                 rc->rc_flags &= ~RC_WAS_BUFOVFL;
 584                                 rc_scheduled_event--;
 585                                 enable_intr();
 586                                 printf("rc%d/%d: interrupt-level buffer overflow\n",
 587                                         unit, chan);
 588                         }
 589                         if (rc->rc_flags & RC_WAS_SILOVFL) {
 590                                 disable_intr();
 591                                 rc->rc_flags &= ~RC_WAS_SILOVFL;
 592                                 rc_scheduled_event--;
 593                                 enable_intr();
 594                                 printf("rc%d/%d: silo overflow\n",
 595                                         unit, chan);
 596                         }
 597                         if (rc->rc_flags & RC_MODCHG) {
 598                                 disable_intr();
 599                                 rc->rc_flags &= ~RC_MODCHG;
 600                                 rc_scheduled_event -= LOTS_OF_EVENTS;
 601                                 enable_intr();
 602                                 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD));
 603                         }
 604                         if (rc->rc_flags & RC_DORXFER) {
 605                                 disable_intr();
 606                                 rc->rc_flags &= ~RC_DORXFER;
 607                                 eptr = rc->rc_iptr;
 608                                 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE])
 609                                         tptr = &rc->rc_ibuf[RC_IBUFSIZE];
 610                                 else
 611                                         tptr = rc->rc_ibuf;
 612                                 icnt = eptr - tptr;
 613                                 if (icnt > 0) {
 614                                         if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
 615                                                 rc->rc_iptr   = rc->rc_ibuf;
 616                                                 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
 617                                                 rc->rc_hiwat  = &rc->rc_ibuf[RC_IHIGHWATER];
 618                                         } else {
 619                                                 rc->rc_iptr   = &rc->rc_ibuf[RC_IBUFSIZE];
 620                                                 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE];
 621                                                 rc->rc_hiwat  =
 622                                                         &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER];
 623                                         }
 624                                         if (   (rc->rc_flags & RC_RTSFLOW)
 625                                             && (tp->t_state & TS_ISOPEN)
 626                                             && !(tp->t_state & TS_TBLOCK)
 627                                             && !(rc->rc_msvr & MSVR_RTS)
 628                                             ) {
 629                                                 rcout(CD180_CAR, chan);
 630                                                 rcout(CD180_MSVR,
 631                                                         rc->rc_msvr |= MSVR_RTS);
 632                                         }
 633                                         rc_scheduled_event -= icnt;
 634                                 }
 635                                 enable_intr();
 636
 637                                 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN))
 638                                         goto done1;
 639
 640                                 if (   (tp->t_state & TS_CAN_BYPASS_L_RINT)
 641                                     && !(tp->t_state & TS_LOCAL)) {
 642                                         if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER
 643                                             && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF))
 644                                             && !(tp->t_state & TS_TBLOCK))
 645                                                 ttyblock(tp);
 646                                         tk_nin += icnt;
 647                                         tk_rawcc += icnt;
 648                                         tp->t_rawcc += icnt;
 649                                         if (b_to_q(tptr, icnt, &tp->t_rawq))
 650                                                 printf("rc%d/%d: tty-level buffer overflow\n",
 651                                                         unit, chan);
 652                                         ttwakeup(tp);
 653                                         if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY)
 654                                             || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) {
 655                                                 tp->t_state &= ~TS_TTSTOP;
 656                                                 tp->t_lflag &= ~FLUSHO;
 657                                                 rc_start(tp);
 658                                         }
 659                                 } else {
 660                                         for (; tptr < eptr; tptr++)
 661                                                 (*linesw[tp->t_line].l_rint)
 662                                                     (tptr[0] |
 663                                                     rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp);
 664                                 }
 665 done1: ;
 666                         }
 667                         if (rc->rc_flags & RC_DOXXFER) {
 668                                 disable_intr();
 669                                 rc_scheduled_event -= LOTS_OF_EVENTS;
 670                                 rc->rc_flags &= ~RC_DOXXFER;
 671                                 rc->rc_tp->t_state &= ~TS_BUSY;
 672                                 enable_intr();
 673                                 (*linesw[tp->t_line].l_start)(tp);
 674                         }
 675                 }
 676                 if (rc_scheduled_event == 0)
 677                         break;
 678         }
 679         if (rc_scheduled_event >= LOTS_OF_EVENTS)
 680                 goto repeat;
 681 }
 682
 683 static  void
 684 rc_stop(tp, rw)
 685         register struct tty     *tp;
 686         int                     rw;
 687 {
 688         register struct rc_chans        *rc = &rc_chans[GET_UNIT(tp->t_dev)];
 689         u_char *tptr, *eptr;
 690
 691 #ifdef RCDEBUG
 692         printf("rc%d/%d: rc_stop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan,
 693                 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":"");
 694 #endif
 695         if (rw & FWRITE)
 696                 rc_discard_output(rc);
 697         disable_intr();
 698         if (rw & FREAD) {
 699                 rc->rc_flags &= ~RC_DORXFER;
 700                 eptr = rc->rc_iptr;
 701                 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
 702                         tptr = &rc->rc_ibuf[RC_IBUFSIZE];
 703                         rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
 704                 } else {
 705                         tptr = rc->rc_ibuf;
 706                         rc->rc_iptr = rc->rc_ibuf;
 707                 }
 708                 rc_scheduled_event -= eptr - tptr;
 709         }
 710         if (tp->t_state & TS_TTSTOP)
 711                 rc->rc_flags |= RC_OSUSP;
 712         else
 713                 rc->rc_flags &= ~RC_OSUSP;
 714         enable_intr();
 715 }
 716
 717 static  int
 718 rcopen(dev, flag, mode, p)
 719         dev_t           dev;
 720         int             flag, mode;
 721         struct proc    *p;
 722 {
 723         register struct rc_chans *rc;
 724         register struct tty      *tp;
 725         int             unit, nec, s, error = 0;
 726
 727         unit = GET_UNIT(dev);
 728         if (unit >= NRC * CD180_NCHAN)
 729                 return ENXIO;
 730         if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED)
 731                 return ENXIO;
 732         rc  = &rc_chans[unit];
 733         tp  = rc->rc_tp;
 734         dev->si_tty = tp;
 735         nec = rc->rc_rcb->rcb_addr;
 736 #ifdef RCDEBUG
 737         printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
 738 #endif
 739         s = spltty();
 740
 741 again:
 742         while (rc->rc_flags & RC_DTR_OFF) {
 743                 error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0);
 744                 if (error != 0)
 745                         goto out;
 746         }
 747         if (tp->t_state & TS_ISOPEN) {
 748                 if (CALLOUT(dev)) {
 749                         if (!(rc->rc_flags & RC_ACTOUT)) {
 750                                 error = EBUSY;
 751                                 goto out;
 752                         }
 753                 } else {
 754                         if (rc->rc_flags & RC_ACTOUT) {
 755                                 if (flag & O_NONBLOCK) {
 756                                         error = EBUSY;
 757                                         goto out;
 758                                 }
 759                                 error = tsleep(&rc->rc_rcb,
 760                                      TTIPRI|PCATCH, "rcbi", 0);
 761                                 if (error)
 762                                         goto out;
 763                                 goto again;
 764                         }
 765                 }
 766                 if (tp->t_state & TS_XCLUDE &&
 767                     suser(p)) {
 768                         error = EBUSY;
 769                         goto out;
 770                 }
 771         } else {
 772                 tp->t_oproc   = rc_start;
 773                 tp->t_param   = rc_param;
 774                 tp->t_stop    = rc_stop;
 775                 tp->t_dev     = dev;
 776
 777                 if (CALLOUT(dev))
 778                         tp->t_cflag |= CLOCAL;
 779                 else
 780                         tp->t_cflag &= ~CLOCAL;
 781
 782                 error = rc_param(tp, &tp->t_termios);
 783                 if (error)
 784                         goto out;
 785                 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET);
 786
 787                 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev))
 788                         (*linesw[tp->t_line].l_modem)(tp, 1);
 789         }
 790         if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev)
 791             && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
 792                 rc->rc_dcdwaits++;
 793                 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0);
 794                 rc->rc_dcdwaits--;
 795                 if (error != 0)
 796                         goto out;
 797                 goto again;
 798         }
 799         error = (*linesw[tp->t_line].l_open)(dev, tp);
 800         disc_optim(tp, &tp->t_termios, rc);
 801         if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev))
 802                 rc->rc_flags |= RC_ACTOUT;
 803 out:
 804         (void) splx(s);
 805
 806         if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN))
 807                 rc_hardclose(rc);
 808
 809         return error;
 810 }
 811
 812 static  int
 813 rcclose(dev, flag, mode, p)
 814         dev_t           dev;
 815         int             flag, mode;
 816         struct proc    *p;
 817 {
 818         register struct rc_chans *rc;
 819         register struct tty      *tp;
 820         int  s, unit = GET_UNIT(dev);
 821
 822         if (unit >= NRC * CD180_NCHAN)
 823                 return ENXIO;
 824         rc  = &rc_chans[unit];
 825         tp  = rc->rc_tp;
 826 #ifdef RCDEBUG
 827         printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
 828 #endif
 829         s = spltty();
 830         (*linesw[tp->t_line].l_close)(tp, flag);
 831         disc_optim(tp, &tp->t_termios, rc);
 832         rc_stop(tp, FREAD | FWRITE);
 833         rc_hardclose(rc);
 834         ttyclose(tp);
 835         splx(s);
 836         return 0;
 837 }
 838
 839 static void rc_hardclose(rc)
 840 register struct rc_chans *rc;
 841 {
 842         register int s, nec = rc->rc_rcb->rcb_addr;
 843         register struct tty *tp = rc->rc_tp;
 844
 845         s = spltty();
 846         rcout(CD180_CAR, rc->rc_chan);
 847
 848         /* Disable rx/tx intrs */
 849         rcout(CD180_IER, rc->rc_ier = 0);
 850         if (   (tp->t_cflag & HUPCL)
 851             || (!(rc->rc_flags & RC_ACTOUT)
 852                && !(rc->rc_msvr & MSVR_CD)
 853                && !(tp->t_cflag & CLOCAL))
 854             || !(tp->t_state & TS_ISOPEN)
 855            ) {
 856                 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
 857                 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
 858                 (void) rc_modctl(rc, TIOCM_RTS, DMSET);
 859                 if (rc->rc_dtrwait) {
 860                         timeout(rc_dtrwakeup, rc, rc->rc_dtrwait);
 861                         rc->rc_flags |= RC_DTR_OFF;
 862                 }
 863         }
 864         rc->rc_flags &= ~RC_ACTOUT;
 865         wakeup((caddr_t) &rc->rc_rcb);  /* wake bi */
 866         wakeup(TSA_CARR_ON(tp));
 867         (void) splx(s);
 868 }
 869
 870 /* Reset the bastard */
 871 static void rc_hwreset(unit, nec, chipid)
 872         register int    unit, nec;
 873         unsigned int    chipid;
 874 {
 875         CCRCMD(unit, -1, CCR_HWRESET);            /* Hardware reset */
 876         DELAY(20000);
 877         WAITFORCCR(unit, -1);
 878
 879         rcout(RC_CTOUT, 0);             /* Clear timeout  */
 880         rcout(CD180_GIVR,  chipid);
 881         rcout(CD180_GICR,  0);
 882
 883         /* Set Prescaler Registers (1 msec) */
 884         rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF);
 885         rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8);
 886
 887         /* Initialize Priority Interrupt Level Registers */
 888         rcout(CD180_PILR1, RC_PILR_MODEM);
 889         rcout(CD180_PILR2, RC_PILR_TX);
 890         rcout(CD180_PILR3, RC_PILR_RX);
 891
 892         /* Reset DTR */
 893         rcout(RC_DTREG, ~0);
 894 }
 895
 896 /* Set channel parameters */
 897 static int rc_param(tp, ts)
 898         register struct  tty    *tp;
 899         struct termios          *ts;
 900 {
 901         register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
 902         register int    nec = rc->rc_rcb->rcb_addr;
 903         int      idivs, odivs, s, val, cflag, iflag, lflag, inpflow;
 904
 905         if (   ts->c_ospeed < 0 || ts->c_ospeed > 76800
 906             || ts->c_ispeed < 0 || ts->c_ispeed > 76800
 907            )
 908                 return (EINVAL);
 909         if (ts->c_ispeed == 0)
 910                 ts->c_ispeed = ts->c_ospeed;
 911         odivs = RC_BRD(ts->c_ospeed);
 912         idivs = RC_BRD(ts->c_ispeed);
 913
 914         s = spltty();
 915
 916         /* Select channel */
 917         rcout(CD180_CAR, rc->rc_chan);
 918
 919         /* If speed == 0, hangup line */
 920         if (ts->c_ospeed == 0) {
 921                 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
 922                 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
 923                 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
 924         }
 925
 926         tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
 927         cflag = ts->c_cflag;
 928         iflag = ts->c_iflag;
 929         lflag = ts->c_lflag;
 930
 931         if (idivs > 0) {
 932                 rcout(CD180_RBPRL, idivs & 0xFF);
 933                 rcout(CD180_RBPRH, idivs >> 8);
 934         }
 935         if (odivs > 0) {
 936                 rcout(CD180_TBPRL, odivs & 0xFF);
 937                 rcout(CD180_TBPRH, odivs >> 8);
 938         }
 939
 940         /* set timeout value */
 941         if (ts->c_ispeed > 0) {
 942                 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1;
 943
 944                 if (   !(lflag & ICANON)
 945                     && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0
 946                     && ts->c_cc[VTIME] * 10 > itm)
 947                         itm = ts->c_cc[VTIME] * 10;
 948
 949                 rcout(CD180_RTPR, itm <= 255 ? itm : 255);
 950         }
 951
 952         switch (cflag & CSIZE) {
 953                 case CS5:       val = COR1_5BITS;      break;
 954                 case CS6:       val = COR1_6BITS;      break;
 955                 case CS7:       val = COR1_7BITS;      break;
 956                 default:
 957                 case CS8:       val = COR1_8BITS;      break;
 958         }
 959         if (cflag & PARENB) {
 960                 val |= COR1_NORMPAR;
 961                 if (cflag & PARODD)
 962                         val |= COR1_ODDP;
 963                 if (!(cflag & INPCK))
 964                         val |= COR1_Ignore;
 965         } else
 966                 val |= COR1_Ignore;
 967         if (cflag & CSTOPB)
 968                 val |= COR1_2SB;
 969         rcout(CD180_COR1, val);
 970
 971         /* Set FIFO threshold */
 972         val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2;
 973         inpflow = 0;
 974         if (   (iflag & IXOFF)
 975             && (   ts->c_cc[VSTOP] != _POSIX_VDISABLE
 976                 && (   ts->c_cc[VSTART] != _POSIX_VDISABLE
 977                     || (iflag & IXANY)
 978                    )
 979                )
 980            ) {
 981                 inpflow = 1;
 982                 val |= COR3_SCDE|COR3_FCT;
 983         }
 984         rcout(CD180_COR3, val);
 985
 986         /* Initialize on-chip automatic flow control */
 987         val = 0;
 988         rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY);
 989         if (cflag & CCTS_OFLOW) {
 990                 rc->rc_flags |= RC_CTSFLOW;
 991                 val |= COR2_CtsAE;
 992         } else
 993                 rc->rc_flags |= RC_SEND_RDY;
 994         if (tp->t_state & TS_TTSTOP)
 995                 rc->rc_flags |= RC_OSUSP;
 996         else
 997                 rc->rc_flags &= ~RC_OSUSP;
 998         if (cflag & CRTS_IFLOW)
 999                 rc->rc_flags |= RC_RTSFLOW;
1000         else
1001                 rc->rc_flags &= ~RC_RTSFLOW;
1002
1003         if (inpflow) {
1004                 if (ts->c_cc[VSTART] != _POSIX_VDISABLE)
1005                         rcout(CD180_SCHR1, ts->c_cc[VSTART]);
1006                 rcout(CD180_SCHR2, ts->c_cc[VSTOP]);
1007                 val |= COR2_TxIBE;
1008                 if (iflag & IXANY)
1009                         val |= COR2_IXM;
1010         }
1011
1012         rcout(CD180_COR2, rc->rc_cor2 = val);
1013
1014         CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1015                 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1016
1017         disc_optim(tp, ts, rc);
1018
1019         /* modem ctl */
1020         val = cflag & CLOCAL ? 0 : MCOR1_CDzd;
1021         if (cflag & CCTS_OFLOW)
1022                 val |= MCOR1_CTSzd;
1023         rcout(CD180_MCOR1, val);
1024
1025         val = cflag & CLOCAL ? 0 : MCOR2_CDod;
1026         if (cflag & CCTS_OFLOW)
1027                 val |= MCOR2_CTSod;
1028         rcout(CD180_MCOR2, val);
1029
1030         /* enable i/o and interrupts */
1031         CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1032                 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS));
1033         WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
1034
1035         rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD;
1036         if (cflag & CCTS_OFLOW)
1037                 rc->rc_ier |= IER_CTS;
1038         if (cflag & CREAD)
1039                 rc->rc_ier |= IER_RxData;
1040         if (tp->t_state & TS_BUSY)
1041                 rc->rc_ier |= IER_TxRdy;
1042         if (ts->c_ospeed != 0)
1043                 rc_modctl(rc, TIOCM_DTR, DMBIS);
1044         if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS))
1045                 rc->rc_flags |= RC_SEND_RDY;
1046         rcout(CD180_IER, rc->rc_ier);
1047         (void) splx(s);
1048         return 0;
1049 }
1050
1051 /* Re-initialize board after bogus interrupts */
1052 static void rc_reinit(rcb)
1053 struct rc_softc         *rcb;
1054 {
1055         register struct rc_chans       *rc, *rce;
1056         register int                    nec;
1057
1058         nec = rcb->rcb_addr;
1059         rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID);
1060         rc  = &rc_chans[rcb->rcb_unit * CD180_NCHAN];
1061         rce = rc + CD180_NCHAN;
1062         for (; rc < rce; rc++)
1063                 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios);
1064 }
1065
1066 static  int
1067 rcioctl(dev, cmd, data, flag, p)
1068 dev_t           dev;
1069 u_long          cmd;
1070 int             flag;
1071 caddr_t         data;
1072 struct proc     *p;
1073 {
1074         register struct rc_chans       *rc = &rc_chans[GET_UNIT(dev)];
1075         register int                    s, error;
1076         struct tty                     *tp = rc->rc_tp;
1077
1078         error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
1079         if (error != ENOIOCTL)
1080                 return (error);
1081         error = ttioctl(tp, cmd, data, flag);
1082         disc_optim(tp, &tp->t_termios, rc);
1083         if (error != ENOIOCTL)
1084                 return (error);
1085         s = spltty();
1086
1087         switch (cmd) {
1088             case TIOCSBRK:
1089                 rc->rc_pendcmd = CD180_C_SBRK;
1090                 break;
1091
1092             case TIOCCBRK:
1093                 rc->rc_pendcmd = CD180_C_EBRK;
1094                 break;
1095
1096             case TIOCSDTR:
1097                 (void) rc_modctl(rc, TIOCM_DTR, DMBIS);
1098                 break;
1099
1100             case TIOCCDTR:
1101                 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
1102                 break;
1103
1104             case TIOCMGET:
1105                 *(int *) data = rc_modctl(rc, 0, DMGET);
1106                 break;
1107
1108             case TIOCMSET:
1109                 (void) rc_modctl(rc, *(int *) data, DMSET);
1110                 break;
1111
1112             case TIOCMBIC:
1113                 (void) rc_modctl(rc, *(int *) data, DMBIC);
1114                 break;
1115
1116             case TIOCMBIS:
1117                 (void) rc_modctl(rc, *(int *) data, DMBIS);
1118                 break;
1119
1120             case TIOCMSDTRWAIT:
1121                 error = suser(p);
1122                 if (error != 0) {
1123                         splx(s);
1124                         return (error);
1125                 }
1126                 rc->rc_dtrwait = *(int *)data * hz / 100;
1127                 break;
1128
1129             case TIOCMGDTRWAIT:
1130                 *(int *)data = rc->rc_dtrwait * 100 / hz;
1131                 break;
1132
1133             default:
1134                 (void) splx(s);
1135                 return ENOTTY;
1136         }
1137         (void) splx(s);
1138         return 0;
1139 }
1140
1141
1142 /* Modem control routines */
1143
1144 static int rc_modctl(rc, bits, cmd)
1145 register struct rc_chans       *rc;
1146 int                             bits, cmd;
1147 {
1148         register int    nec = rc->rc_rcb->rcb_addr;
1149         u_char         *dtr = &rc->rc_rcb->rcb_dtr, msvr;
1150
1151         rcout(CD180_CAR, rc->rc_chan);
1152
1153         switch (cmd) {
1154             case DMSET:
1155                 rcout(RC_DTREG, (bits & TIOCM_DTR) ?
1156                                 ~(*dtr |= 1 << rc->rc_chan) :
1157                                 ~(*dtr &= ~(1 << rc->rc_chan)));
1158                 msvr = rcin(CD180_MSVR);
1159                 if (bits & TIOCM_RTS)
1160                         msvr |= MSVR_RTS;
1161                 else
1162                         msvr &= ~MSVR_RTS;
1163                 if (bits & TIOCM_DTR)
1164                         msvr |= MSVR_DTR;
1165                 else
1166                         msvr &= ~MSVR_DTR;
1167                 rcout(CD180_MSVR, msvr);
1168                 break;
1169
1170             case DMBIS:
1171                 if (bits & TIOCM_DTR)
1172                         rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan));
1173                 msvr = rcin(CD180_MSVR);
1174                 if (bits & TIOCM_RTS)
1175                         msvr |= MSVR_RTS;
1176                 if (bits & TIOCM_DTR)
1177                         msvr |= MSVR_DTR;
1178                 rcout(CD180_MSVR, msvr);
1179                 break;
1180
1181             case DMGET:
1182                 bits = TIOCM_LE;
1183                 msvr = rc->rc_msvr = rcin(CD180_MSVR);
1184
1185                 if (msvr & MSVR_RTS)
1186                         bits |= TIOCM_RTS;
1187                 if (msvr & MSVR_CTS)
1188                         bits |= TIOCM_CTS;
1189                 if (msvr & MSVR_DSR)
1190                         bits |= TIOCM_DSR;
1191                 if (msvr & MSVR_DTR)
1192                         bits |= TIOCM_DTR;
1193                 if (msvr & MSVR_CD)
1194                         bits |= TIOCM_CD;
1195                 if (~rcin(RC_RIREG) & (1 << rc->rc_chan))
1196                         bits |= TIOCM_RI;
1197                 return bits;
1198
1199             case DMBIC:
1200                 if (bits & TIOCM_DTR)
1201                         rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan)));
1202                 msvr = rcin(CD180_MSVR);
1203                 if (bits & TIOCM_RTS)
1204                         msvr &= ~MSVR_RTS;
1205                 if (bits & TIOCM_DTR)
1206                         msvr &= ~MSVR_DTR;
1207                 rcout(CD180_MSVR, msvr);
1208                 break;
1209         }
1210         rc->rc_msvr = rcin(CD180_MSVR);
1211         return 0;
1212 }
1213
1214 /* Test the board. */
1215 int rc_test(nec, unit)
1216         register int    nec;
1217         int             unit;
1218 {
1219         int     chan = 0;
1220         int     i = 0, rcnt, old_level;
1221         unsigned int    iack, chipid;
1222         unsigned short  divs;
1223         static  u_char  ctest[] = "\377\125\252\045\244\0\377";
1224 #define CTLEN   8
1225 #define ERR(s)  { \
1226                 printf("rc%d: ", unit); printf s ; printf("\n"); \
1227                 (void) splx(old_level); return 1; }
1228
1229         struct rtest {
1230                 u_char  txbuf[CD180_NFIFO];     /* TX buffer  */
1231                 u_char  rxbuf[CD180_NFIFO];     /* RX buffer  */
1232                 int     rxptr;                  /* RX pointer */
1233                 int     txptr;                  /* TX pointer */
1234         } tchans[CD180_NCHAN];
1235
1236         old_level = spltty();
1237
1238         chipid = RC_FAKEID;
1239
1240         /* First, reset board to inital state */
1241         rc_hwreset(unit, nec, chipid);
1242
1243         divs = RC_BRD(19200);
1244
1245         /* Initialize channels */
1246         for (chan = 0; chan < CD180_NCHAN; chan++) {
1247
1248                 /* Select and reset channel */
1249                 rcout(CD180_CAR, chan);
1250                 CCRCMD(unit, chan, CCR_ResetChan);
1251                 WAITFORCCR(unit, chan);
1252
1253                 /* Set speed */
1254                 rcout(CD180_RBPRL, divs & 0xFF);
1255                 rcout(CD180_RBPRH, divs >> 8);
1256                 rcout(CD180_TBPRL, divs & 0xFF);
1257                 rcout(CD180_TBPRH, divs >> 8);
1258
1259                 /* set timeout value */
1260                 rcout(CD180_RTPR,  0);
1261
1262                 /* Establish local loopback */
1263                 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB);
1264                 rcout(CD180_COR2, COR2_LLM);
1265                 rcout(CD180_COR3, CD180_NFIFO);
1266                 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1267                 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN);
1268                 WAITFORCCR(unit, chan);
1269                 rcout(CD180_MSVR, MSVR_RTS);
1270
1271                 /* Fill TXBUF with test data */
1272                 for (i = 0; i < CD180_NFIFO; i++) {
1273                         tchans[chan].txbuf[i] = ctest[i];
1274                         tchans[chan].rxbuf[i] = 0;
1275                 }
1276                 tchans[chan].txptr = tchans[chan].rxptr = 0;
1277
1278                 /* Now, start transmit */
1279                 rcout(CD180_IER, IER_TxMpty|IER_RxData);
1280         }
1281         /* Pseudo-interrupt poll stuff */
1282         for (rcnt = 10000; rcnt-- > 0; rcnt--) {
1283                 i = ~(rcin(RC_BSR));
1284                 if (i & RC_BSR_TOUT)
1285                         ERR(("BSR timeout bit set\n"))
1286                 else if (i & RC_BSR_TXINT) {
1287                         iack = rcin(RC_PILR_TX);
1288                         if (iack != (GIVR_IT_TDI | chipid))
1289                                 ERR(("Bad TX intr ack (%02x != %02x)\n",
1290                                         iack, GIVR_IT_TDI | chipid));
1291                         chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1292                         /* If no more data to transmit, disable TX intr */
1293                         if (tchans[chan].txptr >= CD180_NFIFO) {
1294                                 iack = rcin(CD180_IER);
1295                                 rcout(CD180_IER, iack & ~IER_TxMpty);
1296                         } else {
1297                                 for (iack = tchans[chan].txptr;
1298                                     iack < CD180_NFIFO; iack++)
1299                                         rcout(CD180_TDR,
1300                                             tchans[chan].txbuf[iack]);
1301                                 tchans[chan].txptr = iack;
1302                         }
1303                         rcout(CD180_EOIR, 0);
1304                 } else if (i & RC_BSR_RXINT) {
1305                         u_char ucnt;
1306
1307                         iack = rcin(RC_PILR_RX);
1308                         if (iack != (GIVR_IT_RGDI | chipid) &&
1309                             iack != (GIVR_IT_REI  | chipid))
1310                                 ERR(("Bad RX intr ack (%02x != %02x)\n",
1311                                         iack, GIVR_IT_RGDI | chipid))
1312                         chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1313                         ucnt = rcin(CD180_RDCR) & 0xF;
1314                         while (ucnt-- > 0) {
1315                                 iack = rcin(CD180_RCSR);
1316                                 if (iack & RCSR_Timeout)
1317                                         break;
1318                                 if (iack & 0xF)
1319                                         ERR(("Bad char chan %d (RCSR = %02X)\n",
1320                                             chan, iack))
1321                                 if (tchans[chan].rxptr > CD180_NFIFO)
1322                                         ERR(("Got extra chars chan %d\n",
1323                                             chan))
1324                                 tchans[chan].rxbuf[tchans[chan].rxptr++] =
1325                                         rcin(CD180_RDR);
1326                         }
1327                         rcout(CD180_EOIR, 0);
1328                 }
1329                 rcout(RC_CTOUT, 0);
1330                 for (iack = chan = 0; chan < CD180_NCHAN; chan++)
1331                         if (tchans[chan].rxptr >= CD180_NFIFO)
1332                                 iack++;
1333                 if (iack == CD180_NCHAN)
1334                         break;
1335         }
1336         for (chan = 0; chan < CD180_NCHAN; chan++) {
1337                 /* Select and reset channel */
1338                 rcout(CD180_CAR, chan);
1339                 CCRCMD(unit, chan, CCR_ResetChan);
1340         }
1341
1342         if (!rcnt)
1343                 ERR(("looses characters during local loopback\n"))
1344         /* Now, check data */
1345         for (chan = 0; chan < CD180_NCHAN; chan++)
1346                 for (i = 0; i < CD180_NFIFO; i++)
1347                         if (ctest[i] != tchans[chan].rxbuf[i])
1348                                 ERR(("data mismatch chan %d ptr %d (%d != %d)\n",
1349                                     chan, i, ctest[i], tchans[chan].rxbuf[i]))
1350         (void) splx(old_level);
1351         return 0;
1352 }
1353
1354 #ifdef RCDEBUG
1355 static void printrcflags(rc, comment)
1356 struct rc_chans  *rc;
1357 char             *comment;
1358 {
1359         u_short f = rc->rc_flags;
1360         register int    nec = rc->rc_rcb->rcb_addr;
1361
1362         printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n",
1363                 rc->rc_rcb->rcb_unit, rc->rc_chan, comment,
1364                 (f & RC_DTR_OFF)?"DTR_OFF " :"",
1365                 (f & RC_ACTOUT) ?"ACTOUT " :"",
1366                 (f & RC_RTSFLOW)?"RTSFLOW " :"",
1367                 (f & RC_CTSFLOW)?"CTSFLOW " :"",
1368                 (f & RC_DORXFER)?"DORXFER " :"",
1369                 (f & RC_DOXXFER)?"DOXXFER " :"",
1370                 (f & RC_MODCHG) ?"MODCHG "  :"",
1371                 (f & RC_OSUSP)  ?"OSUSP " :"",
1372                 (f & RC_OSBUSY) ?"OSBUSY " :"",
1373                 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"",
1374                 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"",
1375                 (f & RC_SEND_RDY) ?"SEND_RDY":"");
1376
1377         rcout(CD180_CAR, rc->rc_chan);
1378
1379         printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n",
1380                 rc->rc_rcb->rcb_unit, rc->rc_chan,
1381                 rcin(CD180_MSVR),
1382                 rcin(CD180_IER),
1383                 rcin(CD180_CCSR));
1384 }
1385 #endif /* RCDEBUG */
1386
1387 static void
1388 rc_dtrwakeup(chan)
1389         void    *chan;
1390 {
1391         struct rc_chans  *rc;
1392
1393         rc = (struct rc_chans *)chan;
1394         rc->rc_flags &= ~RC_DTR_OFF;
1395         wakeup(&rc->rc_dtrwait);
1396 }
1397
1398 static void
1399 rc_discard_output(rc)
1400         struct rc_chans  *rc;
1401 {
1402         disable_intr();
1403         if (rc->rc_flags & RC_DOXXFER) {
1404                 rc_scheduled_event -= LOTS_OF_EVENTS;
1405                 rc->rc_flags &= ~RC_DOXXFER;
1406         }
1407         rc->rc_optr = rc->rc_obufend;
1408         rc->rc_tp->t_state &= ~TS_BUSY;
1409         enable_intr();
1410         ttwwakeup(rc->rc_tp);
1411 }
1412
1413 static void
1414 rc_wakeup(chan)
1415         void    *chan;
1416 {
1417         timeout(rc_wakeup, (caddr_t)NULL, 1);
1418
1419         if (rc_scheduled_event != 0) {
1420                 int     s;
1421
1422                 s = splsofttty();
1423                 rcpoll(NULL);
1424                 splx(s);
1425         }
1426 }
1427
1428 static void
1429 disc_optim(tp, t, rc)
1430         struct tty      *tp;
1431         struct termios  *t;
1432         struct rc_chans *rc;
1433 {
1434
1435         if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
1436             && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
1437             && (!(t->c_iflag & PARMRK)
1438                 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
1439             && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
1440             && linesw[tp->t_line].l_rint == ttyinput)
1441                 tp->t_state |= TS_CAN_BYPASS_L_RINT;
1442         else
1443                 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
1444         rc->rc_hotchar = linesw[tp->t_line].l_hotchar;
1445 }
1446
1447 static void
1448 rc_wait0(nec, unit, chan, line)
1449         int     nec, unit, chan, line;
1450 {
1451         int rcnt;
1452
1453         for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--)
1454                 DELAY(30);
1455         if (rcnt == 0)
1456                 printf("rc%d/%d: channel command timeout, rc.c line: %d\n",
1457                       unit, chan, line);
1458 }