2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/sysctl.h>
40 #include <dev/pci/pcivar.h>
41 #include <dev/pci/pcireg.h>
42 #include <dev/pci/pcib_private.h>
43 #include <isa/isavar.h>
45 #include <machine/md_var.h>
47 #include <machine/legacyvar.h>
48 #include <machine/pci_cfgreg.h>
49 #include <machine/resource.h>
53 static int pcibios_pcib_route_interrupt(device_t pcib, device_t dev,
57 legacy_pcib_maxslots(device_t dev)
62 /* read configuration space register */
65 legacy_pcib_read_config(device_t dev, int bus, int slot, int func,
68 return(pci_cfgregread(bus, slot, func, reg, bytes));
71 /* write configuration space register */
74 legacy_pcib_write_config(device_t dev, int bus, int slot, int func,
75 int reg, u_int32_t data, int bytes)
77 pci_cfgregwrite(bus, slot, func, reg, data, bytes);
80 /* Pass MSI requests up to the nexus. */
83 legacy_pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount,
88 bus = device_get_parent(pcib);
89 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
94 legacy_pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
98 bus = device_get_parent(pcib);
99 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
103 legacy_pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
108 bus = device_get_parent(pcib);
109 return (PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data));
113 legacy_pcib_is_host_bridge(int bus, int slot, int func,
114 uint32_t id, uint8_t class, uint8_t subclass,
117 const char *s = NULL;
118 static uint8_t pxb[4]; /* hack for 450nx */
124 s = "Intel 824?? host to PCI bridge";
125 /* XXX This is a guess */
126 /* *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x41, 1); */
130 s = "Intel 82810 (i810 GMCH) Host To Hub bridge";
133 s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge";
136 s = "Intel 82810E (i810E GMCH) Host To Hub bridge";
139 s = "Intel 82815 (i815 GMCH) Host To Hub bridge";
142 s = "Intel 82443LX (440 LX) host to PCI bridge";
145 s = "Intel 82443BX (440 BX) host to PCI bridge";
148 s = "Intel 82443BX host to PCI bridge (AGP disabled)";
151 s = "Intel 82443MX host to PCI bridge";
154 s = "Intel 82443GX host to PCI bridge";
157 s = "Intel 82443GX host to AGP bridge";
160 s = "Intel 82443GX host to PCI bridge (AGP disabled)";
163 s = "Intel 82454KX/GX (Orion) host to PCI bridge";
164 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x4a, 1);
168 * For the 450nx chipset, there is a whole bundle of
169 * things pretending to be host bridges. The MIOC will
170 * be seen first and isn't really a pci bridge (the
171 * actual busses are attached to the PXB's). We need to
172 * read the registers of the MIOC to figure out the
173 * bus numbers for the PXB channels.
175 * Since the MIOC doesn't have a pci bus attached, we
176 * pretend it wasn't there.
178 pxb[0] = legacy_pcib_read_config(0, bus, slot, func,
179 0xd0, 1); /* BUSNO[0] */
180 pxb[1] = legacy_pcib_read_config(0, bus, slot, func,
181 0xd1, 1) + 1; /* SUBA[0]+1 */
182 pxb[2] = legacy_pcib_read_config(0, bus, slot, func,
183 0xd3, 1); /* BUSNO[1] */
184 pxb[3] = legacy_pcib_read_config(0, bus, slot, func,
185 0xd4, 1) + 1; /* SUBA[1]+1 */
190 s = "Intel 82454NX PXB#0, Bus#A";
194 s = "Intel 82454NX PXB#0, Bus#B";
198 s = "Intel 82454NX PXB#1, Bus#A";
202 s = "Intel 82454NX PXB#1, Bus#B";
208 /* AMD -- vendor 0x1022 */
210 s = "AMD Elan SC520 host to PCI bridge";
212 init_AMD_Elan_sc520();
215 "*** WARNING: missing CPU_ELAN -- timekeeping may be wrong\n");
219 s = "AMD-751 host to PCI bridge";
222 s = "AMD-761 host to PCI bridge";
225 /* SiS -- vendor 0x1039 */
236 s = "SiS 5591 host to PCI bridge";
239 s = "SiS 5591 host to AGP bridge";
242 /* VLSI -- vendor 0x1004 */
244 s = "VLSI 82C592 Host to PCI bridge";
247 /* XXX Here is MVP3, I got the datasheet but NO M/B to test it */
248 /* totally. Please let me know if anything wrong. -F */
249 /* XXX need info on the MVP3 -- any takers? */
251 s = "VIA 82C598MVP (Apollo MVP3) host bridge";
254 /* AcerLabs -- vendor 0x10b9 */
255 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
256 /* id is '10b9" but the register always shows "10b9". -Foxfair */
258 s = "AcerLabs M1541 (Aladdin-V) PCI host bridge";
261 /* OPTi -- vendor 0x1045 */
263 s = "OPTi 82C700 host to PCI bridge";
266 s = "OPTi 82C822 host to PCI Bridge";
269 /* ServerWorks -- vendor 0x1166 */
271 s = "ServerWorks NB6536 2.0HE host to PCI bridge";
272 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
281 case 0x010f1014: /* IBM re-badged ServerWorks chipset */
282 s = "ServerWorks host to PCI bridge";
283 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
287 s = "ServerWorks NB6635 3.0LE host to PCI bridge";
288 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
292 s = "ServerWorks CIOB30 host to PCI bridge";
293 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
298 case 0x03021014: /* IBM re-badged ServerWorks chipset */
299 s = "ServerWorks CMIC-HE host to PCI-X bridge";
300 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
303 /* XXX unknown chipset, but working */
307 s = "ServerWorks host to PCI bridge(unknown chipset)";
308 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
311 /* Compaq/HP -- vendor 0x0e11 */
313 s = "Compaq/HP Model 6010 HotPlug PCI Bridge";
314 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0xc8, 1);
317 /* Integrated Micro Solutions -- vendor 0x10e0 */
319 s = "Integrated Micro Solutions VL Bridge";
323 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
324 s = "Host to PCI bridge";
332 * Scan the first pci bus for host-pci bridges and add pcib instances
333 * to the nexus for each bridge.
336 legacy_pcib_identify(driver_t *driver, device_t parent)
345 devclass_t pci_devclass;
347 if (pci_cfgregopen() == 0)
350 * Check to see if we haven't already had a PCI bus added
351 * via some other means. If we have, bail since otherwise
352 * we're going to end up duplicating it.
354 if ((pci_devclass = devclass_find("pci")) &&
355 devclass_get_device(pci_devclass, 0))
361 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
363 hdrtype = legacy_pcib_read_config(0, bus, slot, func,
366 * When enumerating bus devices, the standard says that
367 * one should check the header type and ignore the slots whose
368 * header types that the software doesn't know about. We use
369 * this to filter out devices.
371 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
373 if ((hdrtype & PCIM_MFDEV) &&
374 (!found_orion || hdrtype != 0xff))
375 pcifunchigh = PCI_FUNCMAX;
378 for (func = 0; func <= pcifunchigh; func++) {
380 * Read the IDs and class from the device.
383 u_int8_t class, subclass, busnum;
388 id = legacy_pcib_read_config(0, bus, slot, func,
392 class = legacy_pcib_read_config(0, bus, slot, func,
394 subclass = legacy_pcib_read_config(0, bus, slot, func,
397 s = legacy_pcib_is_host_bridge(bus, slot, func,
404 * Check to see if the physical bus has already
405 * been seen. Eg: hybrid 32 and 64 bit host
406 * bridges to the same logical bus.
408 if (device_get_children(parent, &devs, &ndevs) == 0) {
409 for (i = 0; s != NULL && i < ndevs; i++) {
410 if (strcmp(device_get_name(devs[i]),
413 if (legacy_get_pcibus(devs[i]) == busnum)
422 * Add at priority 100 to make sure we
423 * go after any motherboard resources
425 child = BUS_ADD_CHILD(parent, 100,
427 device_set_desc(child, s);
428 legacy_set_pcibus(child, busnum);
431 if (id == 0x12258086)
433 if (id == 0x84c48086)
437 if (found824xx && bus == 0) {
443 * Make sure we add at least one bridge since some old
444 * hardware doesn't actually have a host-pci bridge device.
445 * Note that pci_cfgregopen() thinks we have PCI devices..
450 "legacy_pcib_identify: no bridge found, adding pcib0 anyway\n");
451 child = BUS_ADD_CHILD(parent, 100, "pcib", 0);
452 legacy_set_pcibus(child, 0);
457 legacy_pcib_probe(device_t dev)
460 if (pci_cfgregopen() == 0)
466 legacy_pcib_attach(device_t dev)
472 * Look for a PCI BIOS interrupt routing table as that will be
473 * our method of routing interrupts if we have one.
475 bus = pcib_get_bus(dev);
476 if (pci_pir_probe(bus, 0)) {
477 pir = BUS_ADD_CHILD(device_get_parent(dev), 0, "pir", 0);
479 device_probe_and_attach(pir);
481 device_add_child(dev, "pci", bus);
482 return bus_generic_attach(dev);
486 legacy_pcib_read_ivar(device_t dev, device_t child, int which,
491 case PCIB_IVAR_DOMAIN:
495 *result = legacy_get_pcibus(dev);
502 legacy_pcib_write_ivar(device_t dev, device_t child, int which,
507 case PCIB_IVAR_DOMAIN:
510 legacy_set_pcibus(dev, value);
516 SYSCTL_DECL(_hw_pci);
518 static unsigned long legacy_host_mem_start = 0x80000000;
519 TUNABLE_ULONG("hw.pci.host_mem_start", &legacy_host_mem_start);
520 SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN,
521 &legacy_host_mem_start, 0x80000000,
522 "Limit the host bridge memory to being above this address. Must be\n\
523 set at boot via a tunable.");
526 legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
527 u_long start, u_long end, u_long count, u_int flags)
530 * If no memory preference is given, use upper 32MB slot most
531 * bioses use for their memory window. Typically other bridges
532 * before us get in the way to assert their preferences on memory.
533 * Hardcoding like this sucks, so a more MD/MI way needs to be
534 * found to do it. This is typically only used on older laptops
535 * that don't have pci busses behind pci bridge, so assuming > 32MB
538 * However, this can cause problems for other chipsets, so we make
539 * this tunable by hw.pci.host_mem_start.
541 if (type == SYS_RES_MEMORY && start == 0UL && end == ~0UL)
542 start = legacy_host_mem_start;
543 if (type == SYS_RES_IOPORT && start == 0UL && end == ~0UL)
545 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
549 static device_method_t legacy_pcib_methods[] = {
550 /* Device interface */
551 DEVMETHOD(device_identify, legacy_pcib_identify),
552 DEVMETHOD(device_probe, legacy_pcib_probe),
553 DEVMETHOD(device_attach, legacy_pcib_attach),
554 DEVMETHOD(device_shutdown, bus_generic_shutdown),
555 DEVMETHOD(device_suspend, bus_generic_suspend),
556 DEVMETHOD(device_resume, bus_generic_resume),
559 DEVMETHOD(bus_print_child, bus_generic_print_child),
560 DEVMETHOD(bus_read_ivar, legacy_pcib_read_ivar),
561 DEVMETHOD(bus_write_ivar, legacy_pcib_write_ivar),
562 DEVMETHOD(bus_alloc_resource, legacy_pcib_alloc_resource),
563 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
564 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
565 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
566 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
567 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
570 DEVMETHOD(pcib_maxslots, legacy_pcib_maxslots),
571 DEVMETHOD(pcib_read_config, legacy_pcib_read_config),
572 DEVMETHOD(pcib_write_config, legacy_pcib_write_config),
573 DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
574 DEVMETHOD(pcib_alloc_msi, legacy_pcib_alloc_msi),
575 DEVMETHOD(pcib_release_msi, pcib_release_msi),
576 DEVMETHOD(pcib_alloc_msix, legacy_pcib_alloc_msix),
577 DEVMETHOD(pcib_release_msix, pcib_release_msix),
578 DEVMETHOD(pcib_map_msi, legacy_pcib_map_msi),
583 static devclass_t hostb_devclass;
585 DEFINE_CLASS_0(pcib, legacy_pcib_driver, legacy_pcib_methods, 1);
586 DRIVER_MODULE(pcib, legacy, legacy_pcib_driver, hostb_devclass, 0, 0);
590 * Install placeholder to claim the resources owned by the
591 * PCI bus interface. This could be used to extract the
592 * config space registers in the extreme case where the PnP
593 * ID is available and the PCI BIOS isn't, but for now we just
594 * eat the PnP ID and do nothing else.
596 * XXX we should silence this probe, as it will generally confuse
599 static struct isa_pnp_id pcibus_pnp_ids[] = {
600 { 0x030ad041 /* PNP0A03 */, "PCI Bus" },
605 pcibus_pnp_probe(device_t dev)
609 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0)
615 pcibus_pnp_attach(device_t dev)
620 static device_method_t pcibus_pnp_methods[] = {
621 /* Device interface */
622 DEVMETHOD(device_probe, pcibus_pnp_probe),
623 DEVMETHOD(device_attach, pcibus_pnp_attach),
624 DEVMETHOD(device_detach, bus_generic_detach),
625 DEVMETHOD(device_shutdown, bus_generic_shutdown),
626 DEVMETHOD(device_suspend, bus_generic_suspend),
627 DEVMETHOD(device_resume, bus_generic_resume),
631 static devclass_t pcibus_pnp_devclass;
633 DEFINE_CLASS_0(pcibus_pnp, pcibus_pnp_driver, pcibus_pnp_methods, 1);
634 DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0);
638 * Provide a PCI-PCI bridge driver for PCI busses behind PCI-PCI bridges
639 * that appear in the PCIBIOS Interrupt Routing Table to use the routing
640 * table for interrupt routing when possible.
642 static int pcibios_pcib_probe(device_t bus);
644 static device_method_t pcibios_pcib_pci_methods[] = {
645 /* Device interface */
646 DEVMETHOD(device_probe, pcibios_pcib_probe),
647 DEVMETHOD(device_attach, pcib_attach),
648 DEVMETHOD(device_shutdown, bus_generic_shutdown),
649 DEVMETHOD(device_suspend, bus_generic_suspend),
650 DEVMETHOD(device_resume, bus_generic_resume),
653 DEVMETHOD(bus_print_child, bus_generic_print_child),
654 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
655 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
656 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
657 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
658 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
659 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
660 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
661 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
664 DEVMETHOD(pcib_maxslots, pcib_maxslots),
665 DEVMETHOD(pcib_read_config, pcib_read_config),
666 DEVMETHOD(pcib_write_config, pcib_write_config),
667 DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
668 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi),
669 DEVMETHOD(pcib_release_msi, pcib_release_msi),
670 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix),
671 DEVMETHOD(pcib_release_msix, pcib_release_msix),
672 DEVMETHOD(pcib_map_msi, pcib_map_msi),
677 static devclass_t pcib_devclass;
679 DEFINE_CLASS_0(pcib, pcibios_pcib_driver, pcibios_pcib_pci_methods,
680 sizeof(struct pcib_softc));
681 DRIVER_MODULE(pcibios_pcib, pci, pcibios_pcib_driver, pcib_devclass, 0, 0);
684 pcibios_pcib_probe(device_t dev)
688 if ((pci_get_class(dev) != PCIC_BRIDGE) ||
689 (pci_get_subclass(dev) != PCIS_BRIDGE_PCI))
691 bus = pci_read_config(dev, PCIR_SECBUS_1, 1);
694 if (!pci_pir_probe(bus, 1))
696 device_set_desc(dev, "PCIBIOS PCI-PCI bridge");
701 pcibios_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
703 return (pci_pir_route_interrupt(pci_get_bus(dev), pci_get_slot(dev),
704 pci_get_function(dev), pin));