2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/sysctl.h>
40 #include <dev/pci/pcivar.h>
41 #include <dev/pci/pcireg.h>
42 #include <dev/pci/pcib_private.h>
43 #include <isa/isavar.h>
45 #include <machine/md_var.h>
47 #include <machine/legacyvar.h>
48 #include <machine/pci_cfgreg.h>
49 #include <machine/resource.h>
53 static int pcibios_pcib_route_interrupt(device_t pcib, device_t dev,
57 legacy_pcib_maxslots(device_t dev)
62 /* read configuration space register */
65 legacy_pcib_read_config(device_t dev, int bus, int slot, int func,
68 return(pci_cfgregread(bus, slot, func, reg, bytes));
71 /* write configuration space register */
74 legacy_pcib_write_config(device_t dev, int bus, int slot, int func,
75 int reg, u_int32_t data, int bytes)
77 pci_cfgregwrite(bus, slot, func, reg, data, bytes);
80 /* Pass MSI alloc requests up to the nexus. */
83 legacy_pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount,
88 bus = device_get_parent(pcib);
89 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
94 legacy_pcib_alloc_msix(device_t pcib, device_t dev, int index, int *irq)
98 bus = device_get_parent(pcib);
99 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, index, irq));
103 legacy_pcib_is_host_bridge(int bus, int slot, int func,
104 uint32_t id, uint8_t class, uint8_t subclass,
107 const char *s = NULL;
108 static uint8_t pxb[4]; /* hack for 450nx */
114 s = "Intel 824?? host to PCI bridge";
115 /* XXX This is a guess */
116 /* *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x41, 1); */
120 s = "Intel 82810 (i810 GMCH) Host To Hub bridge";
123 s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge";
126 s = "Intel 82810E (i810E GMCH) Host To Hub bridge";
129 s = "Intel 82815 (i815 GMCH) Host To Hub bridge";
132 s = "Intel 82443LX (440 LX) host to PCI bridge";
135 s = "Intel 82443BX (440 BX) host to PCI bridge";
138 s = "Intel 82443BX host to PCI bridge (AGP disabled)";
141 s = "Intel 82443MX host to PCI bridge";
144 s = "Intel 82443GX host to PCI bridge";
147 s = "Intel 82443GX host to AGP bridge";
150 s = "Intel 82443GX host to PCI bridge (AGP disabled)";
153 s = "Intel 82454KX/GX (Orion) host to PCI bridge";
154 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x4a, 1);
158 * For the 450nx chipset, there is a whole bundle of
159 * things pretending to be host bridges. The MIOC will
160 * be seen first and isn't really a pci bridge (the
161 * actual busses are attached to the PXB's). We need to
162 * read the registers of the MIOC to figure out the
163 * bus numbers for the PXB channels.
165 * Since the MIOC doesn't have a pci bus attached, we
166 * pretend it wasn't there.
168 pxb[0] = legacy_pcib_read_config(0, bus, slot, func,
169 0xd0, 1); /* BUSNO[0] */
170 pxb[1] = legacy_pcib_read_config(0, bus, slot, func,
171 0xd1, 1) + 1; /* SUBA[0]+1 */
172 pxb[2] = legacy_pcib_read_config(0, bus, slot, func,
173 0xd3, 1); /* BUSNO[1] */
174 pxb[3] = legacy_pcib_read_config(0, bus, slot, func,
175 0xd4, 1) + 1; /* SUBA[1]+1 */
180 s = "Intel 82454NX PXB#0, Bus#A";
184 s = "Intel 82454NX PXB#0, Bus#B";
188 s = "Intel 82454NX PXB#1, Bus#A";
192 s = "Intel 82454NX PXB#1, Bus#B";
198 /* AMD -- vendor 0x1022 */
200 s = "AMD Elan SC520 host to PCI bridge";
202 init_AMD_Elan_sc520();
205 "*** WARNING: missing CPU_ELAN -- timekeeping may be wrong\n");
209 s = "AMD-751 host to PCI bridge";
212 s = "AMD-761 host to PCI bridge";
215 /* SiS -- vendor 0x1039 */
226 s = "SiS 5591 host to PCI bridge";
229 s = "SiS 5591 host to AGP bridge";
232 /* VLSI -- vendor 0x1004 */
234 s = "VLSI 82C592 Host to PCI bridge";
237 /* XXX Here is MVP3, I got the datasheet but NO M/B to test it */
238 /* totally. Please let me know if anything wrong. -F */
239 /* XXX need info on the MVP3 -- any takers? */
241 s = "VIA 82C598MVP (Apollo MVP3) host bridge";
244 /* AcerLabs -- vendor 0x10b9 */
245 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
246 /* id is '10b9" but the register always shows "10b9". -Foxfair */
248 s = "AcerLabs M1541 (Aladdin-V) PCI host bridge";
251 /* OPTi -- vendor 0x1045 */
253 s = "OPTi 82C700 host to PCI bridge";
256 s = "OPTi 82C822 host to PCI Bridge";
259 /* ServerWorks -- vendor 0x1166 */
261 s = "ServerWorks NB6536 2.0HE host to PCI bridge";
262 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
271 case 0x010f1014: /* IBM re-badged ServerWorks chipset */
272 s = "ServerWorks host to PCI bridge";
273 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
277 s = "ServerWorks NB6635 3.0LE host to PCI bridge";
278 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
282 s = "ServerWorks CIOB30 host to PCI bridge";
283 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
288 case 0x03021014: /* IBM re-badged ServerWorks chipset */
289 s = "ServerWorks CMIC-HE host to PCI-X bridge";
290 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
293 /* XXX unknown chipset, but working */
297 s = "ServerWorks host to PCI bridge(unknown chipset)";
298 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
301 /* Compaq/HP -- vendor 0x0e11 */
303 s = "Compaq/HP Model 6010 HotPlug PCI Bridge";
304 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0xc8, 1);
307 /* Integrated Micro Solutions -- vendor 0x10e0 */
309 s = "Integrated Micro Solutions VL Bridge";
313 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
314 s = "Host to PCI bridge";
322 * Scan the first pci bus for host-pci bridges and add pcib instances
323 * to the nexus for each bridge.
326 legacy_pcib_identify(driver_t *driver, device_t parent)
335 devclass_t pci_devclass;
337 if (pci_cfgregopen() == 0)
340 * Check to see if we haven't already had a PCI bus added
341 * via some other means. If we have, bail since otherwise
342 * we're going to end up duplicating it.
344 if ((pci_devclass = devclass_find("pci")) &&
345 devclass_get_device(pci_devclass, 0))
351 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
353 hdrtype = legacy_pcib_read_config(0, bus, slot, func,
356 * When enumerating bus devices, the standard says that
357 * one should check the header type and ignore the slots whose
358 * header types that the software doesn't know about. We use
359 * this to filter out devices.
361 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
363 if ((hdrtype & PCIM_MFDEV) &&
364 (!found_orion || hdrtype != 0xff))
365 pcifunchigh = PCI_FUNCMAX;
368 for (func = 0; func <= pcifunchigh; func++) {
370 * Read the IDs and class from the device.
373 u_int8_t class, subclass, busnum;
378 id = legacy_pcib_read_config(0, bus, slot, func,
382 class = legacy_pcib_read_config(0, bus, slot, func,
384 subclass = legacy_pcib_read_config(0, bus, slot, func,
387 s = legacy_pcib_is_host_bridge(bus, slot, func,
394 * Check to see if the physical bus has already
395 * been seen. Eg: hybrid 32 and 64 bit host
396 * bridges to the same logical bus.
398 if (device_get_children(parent, &devs, &ndevs) == 0) {
399 for (i = 0; s != NULL && i < ndevs; i++) {
400 if (strcmp(device_get_name(devs[i]),
403 if (legacy_get_pcibus(devs[i]) == busnum)
412 * Add at priority 100 to make sure we
413 * go after any motherboard resources
415 child = BUS_ADD_CHILD(parent, 100,
417 device_set_desc(child, s);
418 legacy_set_pcibus(child, busnum);
421 if (id == 0x12258086)
423 if (id == 0x84c48086)
427 if (found824xx && bus == 0) {
433 * Make sure we add at least one bridge since some old
434 * hardware doesn't actually have a host-pci bridge device.
435 * Note that pci_cfgregopen() thinks we have PCI devices..
440 "legacy_pcib_identify: no bridge found, adding pcib0 anyway\n");
441 child = BUS_ADD_CHILD(parent, 100, "pcib", 0);
442 legacy_set_pcibus(child, 0);
447 legacy_pcib_probe(device_t dev)
450 if (pci_cfgregopen() == 0)
456 legacy_pcib_attach(device_t dev)
462 * Look for a PCI BIOS interrupt routing table as that will be
463 * our method of routing interrupts if we have one.
465 bus = pcib_get_bus(dev);
466 if (pci_pir_probe(bus, 0)) {
467 pir = BUS_ADD_CHILD(device_get_parent(dev), 0, "pir", 0);
469 device_probe_and_attach(pir);
471 device_add_child(dev, "pci", bus);
472 return bus_generic_attach(dev);
476 legacy_pcib_read_ivar(device_t dev, device_t child, int which,
482 *result = legacy_get_pcibus(dev);
489 legacy_pcib_write_ivar(device_t dev, device_t child, int which,
495 legacy_set_pcibus(dev, value);
501 SYSCTL_DECL(_hw_pci);
503 static unsigned long legacy_host_mem_start = 0x80000000;
504 TUNABLE_ULONG("hw.pci.host_mem_start", &legacy_host_mem_start);
505 SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN,
506 &legacy_host_mem_start, 0x80000000,
507 "Limit the host bridge memory to being above this address. Must be\n\
508 set at boot via a tunable.");
511 legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
512 u_long start, u_long end, u_long count, u_int flags)
515 * If no memory preference is given, use upper 32MB slot most
516 * bioses use for their memory window. Typically other bridges
517 * before us get in the way to assert their preferences on memory.
518 * Hardcoding like this sucks, so a more MD/MI way needs to be
519 * found to do it. This is typically only used on older laptops
520 * that don't have pci busses behind pci bridge, so assuming > 32MB
523 * However, this can cause problems for other chipsets, so we make
524 * this tunable by hw.pci.host_mem_start.
526 if (type == SYS_RES_MEMORY && start == 0UL && end == ~0UL)
527 start = legacy_host_mem_start;
528 if (type == SYS_RES_IOPORT && start == 0UL && end == ~0UL)
530 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
534 static device_method_t legacy_pcib_methods[] = {
535 /* Device interface */
536 DEVMETHOD(device_identify, legacy_pcib_identify),
537 DEVMETHOD(device_probe, legacy_pcib_probe),
538 DEVMETHOD(device_attach, legacy_pcib_attach),
539 DEVMETHOD(device_shutdown, bus_generic_shutdown),
540 DEVMETHOD(device_suspend, bus_generic_suspend),
541 DEVMETHOD(device_resume, bus_generic_resume),
544 DEVMETHOD(bus_print_child, bus_generic_print_child),
545 DEVMETHOD(bus_read_ivar, legacy_pcib_read_ivar),
546 DEVMETHOD(bus_write_ivar, legacy_pcib_write_ivar),
547 DEVMETHOD(bus_alloc_resource, legacy_pcib_alloc_resource),
548 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
549 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
550 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
551 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
552 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
555 DEVMETHOD(pcib_maxslots, legacy_pcib_maxslots),
556 DEVMETHOD(pcib_read_config, legacy_pcib_read_config),
557 DEVMETHOD(pcib_write_config, legacy_pcib_write_config),
558 DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
559 DEVMETHOD(pcib_alloc_msi, legacy_pcib_alloc_msi),
560 DEVMETHOD(pcib_release_msi, pcib_release_msi),
561 DEVMETHOD(pcib_alloc_msix, legacy_pcib_alloc_msix),
562 DEVMETHOD(pcib_release_msix, pcib_release_msix),
567 static devclass_t hostb_devclass;
569 DEFINE_CLASS_0(pcib, legacy_pcib_driver, legacy_pcib_methods, 1);
570 DRIVER_MODULE(pcib, legacy, legacy_pcib_driver, hostb_devclass, 0, 0);
574 * Install placeholder to claim the resources owned by the
575 * PCI bus interface. This could be used to extract the
576 * config space registers in the extreme case where the PnP
577 * ID is available and the PCI BIOS isn't, but for now we just
578 * eat the PnP ID and do nothing else.
580 * XXX we should silence this probe, as it will generally confuse
583 static struct isa_pnp_id pcibus_pnp_ids[] = {
584 { 0x030ad041 /* PNP0A03 */, "PCI Bus" },
589 pcibus_pnp_probe(device_t dev)
593 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0)
599 pcibus_pnp_attach(device_t dev)
604 static device_method_t pcibus_pnp_methods[] = {
605 /* Device interface */
606 DEVMETHOD(device_probe, pcibus_pnp_probe),
607 DEVMETHOD(device_attach, pcibus_pnp_attach),
608 DEVMETHOD(device_detach, bus_generic_detach),
609 DEVMETHOD(device_shutdown, bus_generic_shutdown),
610 DEVMETHOD(device_suspend, bus_generic_suspend),
611 DEVMETHOD(device_resume, bus_generic_resume),
615 static devclass_t pcibus_pnp_devclass;
617 DEFINE_CLASS_0(pcibus_pnp, pcibus_pnp_driver, pcibus_pnp_methods, 1);
618 DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0);
622 * Provide a PCI-PCI bridge driver for PCI busses behind PCI-PCI bridges
623 * that appear in the PCIBIOS Interrupt Routing Table to use the routing
624 * table for interrupt routing when possible.
626 static int pcibios_pcib_probe(device_t bus);
628 static device_method_t pcibios_pcib_pci_methods[] = {
629 /* Device interface */
630 DEVMETHOD(device_probe, pcibios_pcib_probe),
631 DEVMETHOD(device_attach, pcib_attach),
632 DEVMETHOD(device_shutdown, bus_generic_shutdown),
633 DEVMETHOD(device_suspend, bus_generic_suspend),
634 DEVMETHOD(device_resume, bus_generic_resume),
637 DEVMETHOD(bus_print_child, bus_generic_print_child),
638 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
639 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
640 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
641 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
642 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
643 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
644 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
645 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
648 DEVMETHOD(pcib_maxslots, pcib_maxslots),
649 DEVMETHOD(pcib_read_config, pcib_read_config),
650 DEVMETHOD(pcib_write_config, pcib_write_config),
651 DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
652 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi),
653 DEVMETHOD(pcib_release_msi, pcib_release_msi),
654 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix),
655 DEVMETHOD(pcib_release_msix, pcib_release_msix),
660 static devclass_t pcib_devclass;
662 DEFINE_CLASS_0(pcib, pcibios_pcib_driver, pcibios_pcib_pci_methods,
663 sizeof(struct pcib_softc));
664 DRIVER_MODULE(pcibios_pcib, pci, pcibios_pcib_driver, pcib_devclass, 0, 0);
667 pcibios_pcib_probe(device_t dev)
671 if ((pci_get_class(dev) != PCIC_BRIDGE) ||
672 (pci_get_subclass(dev) != PCIS_BRIDGE_PCI))
674 bus = pci_read_config(dev, PCIR_SECBUS_1, 1);
677 if (!pci_pir_probe(bus, 1))
679 device_set_desc(dev, "PCIBIOS PCI-PCI bridge");
684 pcibios_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
686 return (pci_pir_route_interrupt(pci_get_bus(dev), pci_get_slot(dev),
687 pci_get_function(dev), pin));