2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include <sys/param.h> /* XXX trim includes */
33 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/malloc.h>
40 #include <machine/md_var.h>
41 #include <pci/pcivar.h>
42 #include <pci/pcireg.h>
43 #include <isa/isavar.h>
44 #include <machine/nexusvar.h>
45 #include <machine/pci_cfgreg.h>
46 #include <machine/segments.h>
47 #include <machine/pc/bios.h>
55 static int pcibios_cfgread(int bus, int slot, int func, int reg, int bytes);
56 static void pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
57 static int pcibios_cfgopen(void);
58 static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
59 static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
60 static int pcireg_cfgopen(void);
62 static struct PIR_entry *pci_route_table;
63 static int pci_route_count;
66 * Initialise access to PCI configuration space
71 static int opened = 0;
73 static struct PIR_table *pt;
80 if (pcibios_cfgopen() != 0) {
82 } else if (pcireg_cfgopen() != 0) {
89 * Look for the interrupt routing table.
91 /* XXX use PCI BIOS if it's available */
93 if ((pt == NULL) && ((sigaddr = bios_sigsearch(0, "$PIR", 4, 16, 0)) != 0)) {
94 pt = (struct PIR_table *)(uintptr_t)BIOS_PADDRTOVADDR(sigaddr);
95 for (cv = (u_int8_t *)pt, ck = 0, i = 0; i < (pt->pt_header.ph_length); i++) {
99 pci_route_table = &pt->pt_entry[0];
100 pci_route_count = (pt->pt_header.ph_length - sizeof(struct PIR_header)) / sizeof(struct PIR_entry);
101 printf("Using $PIR table, %d entries at %p\n", pci_route_count, pci_route_table);
110 * Read configuration space register
113 pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
116 pcibios_cfgread(bus, slot, func, reg, bytes) :
117 pcireg_cfgread(bus, slot, func, reg, bytes));
121 * Write configuration space register
124 pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
127 pcibios_cfgwrite(bus, slot, func, reg, data, bytes) :
128 pcireg_cfgwrite(bus, slot, func, reg, data, bytes));
132 * Route a PCI interrupt
134 * XXX this needs to learn to actually route uninitialised interrupts as well
135 * as just returning interrupts for stuff that's already initialised.
137 * XXX we don't do anything "right" with the function number in the PIR table
138 * (because the consumer isn't currently passing it in).
141 pci_cfgintr(int bus, int device, int pin)
143 struct PIR_entry *pe;
145 struct bios_regs args;
147 if ((bus < 0) || (bus > 255) || (device < 0) || (device > 255) ||
148 (pin < 1) || (pin > 4))
152 * Scan the entry table for a contender
154 for (i = 0, pe = pci_route_table; i < pci_route_count; i++, pe++) {
155 if ((bus != pe->pe_bus) || (device != pe->pe_device))
157 if (!powerof2(pe->pe_intpin[pin - 1].irqs)) {
158 printf("pci_cfgintr: %d:%d:%c is not routed to a unique interrupt\n",
159 bus, device, 'A' + pin - 1);
162 irq = ffs(pe->pe_intpin[pin - 1].irqs) - 1;
163 printf("pci_cfgintr: %d:%d:%c routed to irq %d\n",
164 bus, device, 'A' + pin - 1, irq);
167 * Ask the BIOS to route the interrupt
169 args.eax = PCIBIOS_ROUTE_INTERRUPT;
170 args.ebx = (bus << 8) | (device << 3);
171 args.ecx = (irq << 8) | (0xa + pin - 1); /* pin value is 0xa - 0xd */
172 bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
174 /* XXX if it fails, we should smack the router hardware directly */
183 * Config space access using BIOS functions
186 pcibios_cfgread(int bus, int slot, int func, int reg, int bytes)
188 struct bios_regs args;
193 args.eax = PCIBIOS_READ_CONFIG_BYTE;
197 args.eax = PCIBIOS_READ_CONFIG_WORD;
201 args.eax = PCIBIOS_READ_CONFIG_DWORD;
207 args.ebx = (bus << 8) | (slot << 3) | func;
209 bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
210 /* check call results? */
211 return(args.ecx & mask);
215 pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
217 struct bios_regs args;
221 args.eax = PCIBIOS_WRITE_CONFIG_BYTE;
224 args.eax = PCIBIOS_WRITE_CONFIG_WORD;
227 args.eax = PCIBIOS_WRITE_CONFIG_DWORD;
232 args.ebx = (bus << 8) | (slot << 3) | func;
235 bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
239 * Determine whether there is a PCI BIOS present
242 pcibios_cfgopen(void)
244 /* check for a found entrypoint */
245 return(PCIbios.entry != 0);
249 * Configuration space access using direct register operations
252 /* enable configuration space accesses and return data port address */
254 pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
258 if (bus <= PCI_BUSMAX
260 && func <= PCI_FUNCMAX
263 && (unsigned) bytes <= 4
264 && (reg & (bytes -1)) == 0) {
267 outl(CONF1_ADDR_PORT, (1 << 31)
268 | (bus << 16) | (slot << 11)
269 | (func << 8) | (reg & ~0x03));
270 dataport = CONF1_DATA_PORT + (reg & 0x03);
273 outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));
274 outb(CONF2_FORWARD_PORT, bus);
275 dataport = 0xc000 | (slot << 8) | reg;
282 /* disable configuration space accesses */
288 outl(CONF1_ADDR_PORT, 0);
291 outb(CONF2_ENABLE_PORT, 0);
292 outb(CONF2_FORWARD_PORT, 0);
298 pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
303 port = pci_cfgenable(bus, slot, func, reg, bytes);
323 pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
327 port = pci_cfgenable(bus, slot, func, reg, bytes);
344 /* check whether the configuration mechanism has been correctly identified */
346 pci_cfgcheck(int maxdev)
351 printf("pci_cfgcheck:\tdevice ");
353 for (device = 0; device < maxdev; device++) {
354 unsigned id, class, header;
356 printf("%d ", device);
358 id = inl(pci_cfgenable(0, device, 0, 0, 4));
359 if (id == 0 || id == -1)
362 class = inl(pci_cfgenable(0, device, 0, 8, 4)) >> 8;
364 printf("[class=%06x] ", class);
365 if (class == 0 || (class & 0xf870ff) != 0)
368 header = inb(pci_cfgenable(0, device, 0, 14, 1));
370 printf("[hdr=%02x] ", header);
371 if ((header & 0x7e) != 0)
375 printf("is there (id=%08x)\n", id);
381 printf("-- nothing found\n");
390 unsigned long mode1res,oldval1;
391 unsigned char mode2res,oldval2;
393 oldval1 = inl(CONF1_ADDR_PORT);
396 printf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08lx\n",
400 if ((oldval1 & CONF1_ENABLE_MSK) == 0) {
405 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
406 outb(CONF1_ADDR_PORT +3, 0);
407 mode1res = inl(CONF1_ADDR_PORT);
408 outl(CONF1_ADDR_PORT, oldval1);
411 printf("pci_open(1a):\tmode1res=0x%08lx (0x%08lx)\n",
412 mode1res, CONF1_ENABLE_CHK);
415 if (pci_cfgcheck(32))
419 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1);
420 mode1res = inl(CONF1_ADDR_PORT);
421 outl(CONF1_ADDR_PORT, oldval1);
424 printf("pci_open(1b):\tmode1res=0x%08lx (0x%08lx)\n",
425 mode1res, CONF1_ENABLE_CHK1);
427 if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) {
428 if (pci_cfgcheck(32))
433 oldval2 = inb(CONF2_ENABLE_PORT);
436 printf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n",
440 if ((oldval2 & 0xf0) == 0) {
445 outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK);
446 mode2res = inb(CONF2_ENABLE_PORT);
447 outb(CONF2_ENABLE_PORT, oldval2);
450 printf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n",
451 mode2res, CONF2_ENABLE_CHK);
453 if (mode2res == CONF2_ENABLE_RES) {
455 printf("pci_open(2a):\tnow trying mechanism 2\n");
457 if (pci_cfgcheck(16))