2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
6 * Copyright (c) 2000, BSDi
7 * Copyright (c) 2004, Scott Long <scottl@freebsd.org>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice unmodified, this list of conditions, and the following
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/mutex.h>
41 #include <sys/malloc.h>
42 #include <sys/queue.h>
43 #include <sys/sysctl.h>
44 #include <dev/pci/pcivar.h>
45 #include <dev/pci/pcireg.h>
46 #include <machine/pci_cfgreg.h>
47 #include <machine/pc/bios.h>
50 #include <vm/vm_param.h>
51 #include <vm/vm_kern.h>
52 #include <vm/vm_extern.h>
55 #define PRVERB(a) do { \
61 struct pcie_cfg_elem {
62 TAILQ_ENTRY(pcie_cfg_elem) elem;
69 static TAILQ_HEAD(pcie_cfg_list, pcie_cfg_elem) pcie_list[MAXCPU];
70 static uint64_t pcie_base;
71 static int pcie_minbus, pcie_maxbus;
72 static uint32_t pcie_badslots;
75 static struct mtx pcicfg_mtx;
76 static int mcfg_enable = 1;
77 SYSCTL_INT(_hw_pci, OID_AUTO, mcfg, CTLFLAG_RDTUN, &mcfg_enable, 0,
78 "Enable support for PCI-e memory mapped config access");
80 static uint32_t pci_docfgregread(int bus, int slot, int func, int reg,
82 static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
83 static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
84 static int pcireg_cfgopen(void);
85 static int pciereg_cfgread(int bus, unsigned slot, unsigned func,
86 unsigned reg, unsigned bytes);
87 static void pciereg_cfgwrite(int bus, unsigned slot, unsigned func,
88 unsigned reg, int data, unsigned bytes);
91 * Some BIOS writers seem to want to ignore the spec and put
92 * 0 in the intline rather than 255 to indicate none. Some use
93 * numbers in the range 128-254 to indicate something strange and
94 * apparently undocumented anywhere. Assume these are completely bogus
95 * and map them to 255, which means "none".
98 pci_i386_map_intline(int line)
100 if (line == 0 || line >= 128)
101 return (PCI_INVALID_IRQ);
106 pcibios_get_version(void)
108 struct bios_regs args;
110 if (PCIbios.ventry == 0) {
111 PRVERB(("pcibios: No call entry point\n"));
114 args.eax = PCIBIOS_BIOS_PRESENT;
115 if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) {
116 PRVERB(("pcibios: BIOS_PRESENT call failed\n"));
119 if (args.edx != 0x20494350) {
120 PRVERB(("pcibios: BIOS_PRESENT didn't return 'PCI ' in edx\n"));
123 return (args.ebx & 0xffff);
127 * Initialise access to PCI configuration space
133 static int opened = 0;
138 if (cfgmech == CFGMECH_NONE && pcireg_cfgopen() == 0)
141 v = pcibios_get_version();
143 PRVERB(("pcibios: BIOS version %x.%02x\n", (v & 0xff00) >> 8,
145 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
148 /* $PIR requires PCI BIOS 2.10 or greater. */
156 pci_docfgregread(int bus, int slot, int func, int reg, int bytes)
159 if (cfgmech == CFGMECH_PCIE &&
160 (bus >= pcie_minbus && bus <= pcie_maxbus) &&
161 (bus != 0 || !(1 << slot & pcie_badslots)))
162 return (pciereg_cfgread(bus, slot, func, reg, bytes));
164 return (pcireg_cfgread(bus, slot, func, reg, bytes));
168 * Read configuration space register
171 pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
176 * Some BIOS writers seem to want to ignore the spec and put
177 * 0 in the intline rather than 255 to indicate none. The rest of
178 * the code uses 255 as an invalid IRQ.
180 if (reg == PCIR_INTLINE && bytes == 1) {
181 line = pci_docfgregread(bus, slot, func, PCIR_INTLINE, 1);
182 return (pci_i386_map_intline(line));
184 return (pci_docfgregread(bus, slot, func, reg, bytes));
188 * Write configuration space register
191 pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
194 if (cfgmech == CFGMECH_PCIE &&
195 (bus >= pcie_minbus && bus <= pcie_maxbus) &&
196 (bus != 0 || !(1 << slot & pcie_badslots)))
197 pciereg_cfgwrite(bus, slot, func, reg, data, bytes);
199 pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
203 * Configuration space access using direct register operations
206 /* enable configuration space accesses and return data port address */
208 pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
212 if (bus <= PCI_BUSMAX
214 && func <= PCI_FUNCMAX
215 && (unsigned)reg <= PCI_REGMAX
217 && (unsigned)bytes <= 4
218 && (reg & (bytes - 1)) == 0) {
222 outl(CONF1_ADDR_PORT, (1U << 31)
223 | (bus << 16) | (slot << 11)
224 | (func << 8) | (reg & ~0x03));
225 dataport = CONF1_DATA_PORT + (reg & 0x03);
228 outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));
229 outb(CONF2_FORWARD_PORT, bus);
230 dataport = 0xc000 | (slot << 8) | reg;
237 /* disable configuration space accesses */
245 * Do nothing for the config mechanism 1 case.
246 * Writing a 0 to the address port can apparently
247 * confuse some bridges and cause spurious
252 outb(CONF2_ENABLE_PORT, 0);
258 pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
263 mtx_lock_spin(&pcicfg_mtx);
264 port = pci_cfgenable(bus, slot, func, reg, bytes);
279 mtx_unlock_spin(&pcicfg_mtx);
284 pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
288 mtx_lock_spin(&pcicfg_mtx);
289 port = pci_cfgenable(bus, slot, func, reg, bytes);
304 mtx_unlock_spin(&pcicfg_mtx);
307 /* check whether the configuration mechanism has been correctly identified */
309 pci_cfgcheck(int maxdev)
317 printf("pci_cfgcheck:\tdevice ");
319 for (device = 0; device < maxdev; device++) {
321 printf("%d ", device);
323 port = pci_cfgenable(0, device, 0, 0, 4);
325 if (id == 0 || id == 0xffffffff)
328 port = pci_cfgenable(0, device, 0, 8, 4);
329 class = inl(port) >> 8;
331 printf("[class=%06x] ", class);
332 if (class == 0 || (class & 0xf870ff) != 0)
335 port = pci_cfgenable(0, device, 0, 14, 1);
338 printf("[hdr=%02x] ", header);
339 if ((header & 0x7e) != 0)
343 printf("is there (id=%08x)\n", id);
349 printf("-- nothing found\n");
358 uint32_t mode1res, oldval1;
359 uint8_t mode2res, oldval2;
361 /* Check for type #1 first. */
362 oldval1 = inl(CONF1_ADDR_PORT);
365 printf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08x\n",
372 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
374 mode1res = inl(CONF1_ADDR_PORT);
375 outl(CONF1_ADDR_PORT, oldval1);
378 printf("pci_open(1a):\tmode1res=0x%08x (0x%08lx)\n", mode1res,
382 if (pci_cfgcheck(32))
386 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1);
387 mode1res = inl(CONF1_ADDR_PORT);
388 outl(CONF1_ADDR_PORT, oldval1);
391 printf("pci_open(1b):\tmode1res=0x%08x (0x%08lx)\n", mode1res,
394 if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) {
395 if (pci_cfgcheck(32))
399 /* Type #1 didn't work, so try type #2. */
400 oldval2 = inb(CONF2_ENABLE_PORT);
403 printf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n",
407 if ((oldval2 & 0xf0) == 0) {
411 outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK);
412 mode2res = inb(CONF2_ENABLE_PORT);
413 outb(CONF2_ENABLE_PORT, oldval2);
416 printf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n",
417 mode2res, CONF2_ENABLE_CHK);
419 if (mode2res == CONF2_ENABLE_RES) {
421 printf("pci_open(2a):\tnow trying mechanism 2\n");
423 if (pci_cfgcheck(16))
428 /* Nothing worked, so punt. */
429 cfgmech = CFGMECH_NONE;
435 pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
437 struct pcie_cfg_list *pcielist;
438 struct pcie_cfg_elem *pcie_array, *elem;
452 if (!pae_mode && base >= 0x100000000) {
455 "PCI: Memory Mapped PCI configuration area base 0x%jx too high\n",
461 printf("PCIe: Memory Mapped configuration base @ 0x%jx\n",
465 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu)
468 pcie_array = malloc(sizeof(struct pcie_cfg_elem) * PCIE_CACHE,
470 if (pcie_array == NULL)
473 va = kva_alloc(PCIE_CACHE * PAGE_SIZE);
475 free(pcie_array, M_DEVBUF);
480 pcielist = &pcie_list[pc->pc_cpuid];
482 pcielist = &pcie_list[0];
484 TAILQ_INIT(pcielist);
485 for (i = 0; i < PCIE_CACHE; i++) {
486 elem = &pcie_array[i];
487 elem->vapage = va + (i * PAGE_SIZE);
489 TAILQ_INSERT_HEAD(pcielist, elem, elem);
494 pcie_minbus = minbus;
495 pcie_maxbus = maxbus;
496 cfgmech = CFGMECH_PCIE;
500 * On some AMD systems, some of the devices on bus 0 are
501 * inaccessible using memory-mapped PCI config access. Walk
502 * bus 0 looking for such devices. For these devices, we will
503 * fall back to using type 1 config access instead.
505 if (pci_cfgregopen() != 0) {
506 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
507 val1 = pcireg_cfgread(0, slot, 0, 0, 4);
508 if (val1 == 0xffffffff)
511 val2 = pciereg_cfgread(0, slot, 0, 0, 4);
513 pcie_badslots |= (1 << slot);
520 #define PCIE_PADDR(base, reg, bus, slot, func) \
522 ((((bus) & 0xff) << 20) | \
523 (((slot) & 0x1f) << 15) | \
524 (((func) & 0x7) << 12) | \
527 static __inline vm_offset_t
528 pciereg_findaddr(int bus, unsigned slot, unsigned func, unsigned reg)
530 struct pcie_cfg_list *pcielist;
531 struct pcie_cfg_elem *elem;
532 vm_paddr_t pa, papage;
534 pa = PCIE_PADDR(pcie_base, reg, bus, slot, func);
535 papage = pa & ~PAGE_MASK;
538 * Find an element in the cache that matches the physical page desired,
539 * or create a new mapping from the least recently used element.
540 * A very simple LRU algorithm is used here, does it need to be more
543 pcielist = &pcie_list[PCPU_GET(cpuid)];
544 TAILQ_FOREACH(elem, pcielist, elem) {
545 if (elem->papage == papage)
550 elem = TAILQ_LAST(pcielist, pcie_cfg_list);
551 if (elem->papage != 0) {
552 pmap_kremove(elem->vapage);
553 invlpg(elem->vapage);
555 pmap_kenter(elem->vapage, papage);
556 elem->papage = papage;
559 if (elem != TAILQ_FIRST(pcielist)) {
560 TAILQ_REMOVE(pcielist, elem, elem);
561 TAILQ_INSERT_HEAD(pcielist, elem, elem);
563 return (elem->vapage | (pa & PAGE_MASK));
567 * AMD BIOS And Kernel Developer's Guides for CPU families starting with 10h
568 * have a requirement that all accesses to the memory mapped PCI configuration
569 * space are done using AX class of registers.
570 * Since other vendors do not currently have any contradicting requirements
571 * the AMD access pattern is applied universally.
575 pciereg_cfgread(int bus, unsigned slot, unsigned func, unsigned reg,
581 if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX ||
582 func > PCI_FUNCMAX || reg > PCIE_REGMAX)
586 va = pciereg_findaddr(bus, slot, func, reg);
590 __asm("movl %1, %0" : "=a" (data)
591 : "m" (*(volatile uint32_t *)va));
594 __asm("movzwl %1, %0" : "=a" (data)
595 : "m" (*(volatile uint16_t *)va));
598 __asm("movzbl %1, %0" : "=a" (data)
599 : "m" (*(volatile uint8_t *)va));
608 pciereg_cfgwrite(int bus, unsigned slot, unsigned func, unsigned reg, int data,
613 if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX ||
614 func > PCI_FUNCMAX || reg > PCIE_REGMAX)
618 va = pciereg_findaddr(bus, slot, func, reg);
622 __asm("movl %1, %0" : "=m" (*(volatile uint32_t *)va)
626 __asm("movw %1, %0" : "=m" (*(volatile uint16_t *)va)
627 : "a" ((uint16_t)data));
630 __asm("movb %1, %0" : "=m" (*(volatile uint8_t *)va)
631 : "a" ((uint8_t)data));