2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
5 * Copyright (c) 2004, Scott Long <scottl@freebsd.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/mutex.h>
41 #include <sys/malloc.h>
42 #include <sys/queue.h>
43 #include <sys/sysctl.h>
44 #include <dev/pci/pcivar.h>
45 #include <dev/pci/pcireg.h>
46 #include <machine/pci_cfgreg.h>
47 #include <machine/pc/bios.h>
50 #include <vm/vm_param.h>
51 #include <vm/vm_kern.h>
52 #include <vm/vm_extern.h>
56 #include <machine/xbox.h>
59 #define PRVERB(a) do { \
65 struct pcie_cfg_elem {
66 TAILQ_ENTRY(pcie_cfg_elem) elem;
80 static TAILQ_HEAD(pcie_cfg_list, pcie_cfg_elem) pcie_list[MAXCPU];
81 static uint64_t pcie_base;
82 static int pcie_minbus, pcie_maxbus;
83 static uint32_t pcie_badslots;
86 static struct mtx pcicfg_mtx;
87 static int mcfg_enable = 1;
88 SYSCTL_INT(_hw_pci, OID_AUTO, mcfg, CTLFLAG_RDTUN, &mcfg_enable, 0,
89 "Enable support for PCI-e memory mapped config access");
91 static uint32_t pci_docfgregread(int bus, int slot, int func, int reg,
93 static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
94 static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
95 static int pcireg_cfgopen(void);
96 static int pciereg_cfgread(int bus, unsigned slot, unsigned func,
97 unsigned reg, unsigned bytes);
98 static void pciereg_cfgwrite(int bus, unsigned slot, unsigned func,
99 unsigned reg, int data, unsigned bytes);
102 * Some BIOS writers seem to want to ignore the spec and put
103 * 0 in the intline rather than 255 to indicate none. Some use
104 * numbers in the range 128-254 to indicate something strange and
105 * apparently undocumented anywhere. Assume these are completely bogus
106 * and map them to 255, which means "none".
109 pci_i386_map_intline(int line)
111 if (line == 0 || line >= 128)
112 return (PCI_INVALID_IRQ);
117 pcibios_get_version(void)
119 struct bios_regs args;
121 if (PCIbios.ventry == 0) {
122 PRVERB(("pcibios: No call entry point\n"));
125 args.eax = PCIBIOS_BIOS_PRESENT;
126 if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) {
127 PRVERB(("pcibios: BIOS_PRESENT call failed\n"));
130 if (args.edx != 0x20494350) {
131 PRVERB(("pcibios: BIOS_PRESENT didn't return 'PCI ' in edx\n"));
134 return (args.ebx & 0xffff);
138 * Initialise access to PCI configuration space
143 static int opened = 0;
151 if (cfgmech == CFGMECH_NONE && pcireg_cfgopen() == 0)
154 v = pcibios_get_version();
156 PRVERB(("pcibios: BIOS version %x.%02x\n", (v & 0xff00) >> 8,
158 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
161 /* $PIR requires PCI BIOS 2.10 or greater. */
165 if (cfgmech == CFGMECH_PCIE)
169 * Grope around in the PCI config space to see if this is a
170 * chipset that is capable of doing memory-mapped config cycles.
171 * This also implies that it can do PCIe extended config cycles.
174 /* Check for supported chipsets */
175 vid = pci_cfgregread(0, 0, 0, PCIR_VENDOR, 2);
176 did = pci_cfgregread(0, 0, 0, PCIR_DEVICE, 2);
182 /* Intel 7520 or 7320 */
183 pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16;
184 pcie_cfgregopen(pciebar, 0, 255);
189 /* Intel 915, 925, or 915GM */
190 pciebar = pci_cfgregread(0, 0, 0, 0x48, 4);
191 pcie_cfgregopen(pciebar, 0, 255);
200 pci_docfgregread(int bus, int slot, int func, int reg, int bytes)
203 if (cfgmech == CFGMECH_PCIE &&
204 (bus >= pcie_minbus && bus <= pcie_maxbus) &&
205 (bus != 0 || !(1 << slot & pcie_badslots)))
206 return (pciereg_cfgread(bus, slot, func, reg, bytes));
208 return (pcireg_cfgread(bus, slot, func, reg, bytes));
212 * Read configuration space register
215 pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
220 * Some BIOS writers seem to want to ignore the spec and put
221 * 0 in the intline rather than 255 to indicate none. The rest of
222 * the code uses 255 as an invalid IRQ.
224 if (reg == PCIR_INTLINE && bytes == 1) {
225 line = pci_docfgregread(bus, slot, func, PCIR_INTLINE, 1);
226 return (pci_i386_map_intline(line));
228 return (pci_docfgregread(bus, slot, func, reg, bytes));
232 * Write configuration space register
235 pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
238 if (cfgmech == CFGMECH_PCIE &&
239 (bus >= pcie_minbus && bus <= pcie_maxbus) &&
240 (bus != 0 || !(1 << slot & pcie_badslots)))
241 pciereg_cfgwrite(bus, slot, func, reg, data, bytes);
243 pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
247 * Configuration space access using direct register operations
250 /* enable configuration space accesses and return data port address */
252 pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
257 if (arch_i386_is_xbox) {
259 * The Xbox MCPX chipset is a derivative of the nForce 1
260 * chipset. It almost has the same bus layout; some devices
261 * cannot be used, because they have been removed.
265 * Devices 00:00.1 and 00:00.2 used to be memory controllers on
266 * the nForce chipset, but on the Xbox, using them will lockup
269 if (bus == 0 && slot == 0 && (func == 1 || func == 2))
273 * Bus 1 only contains a VGA controller at 01:00.0. When you try
274 * to probe beyond that device, you only get garbage, which
275 * could cause lockups.
277 if (bus == 1 && (slot != 0 || func != 0))
281 * Bus 2 used to contain the AGP controller, but the Xbox MCPX
282 * doesn't have one. Probing it can cause lockups.
289 if (bus <= PCI_BUSMAX
291 && func <= PCI_FUNCMAX
292 && (unsigned)reg <= PCI_REGMAX
294 && (unsigned)bytes <= 4
295 && (reg & (bytes - 1)) == 0) {
299 outl(CONF1_ADDR_PORT, (1U << 31)
300 | (bus << 16) | (slot << 11)
301 | (func << 8) | (reg & ~0x03));
302 dataport = CONF1_DATA_PORT + (reg & 0x03);
305 outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));
306 outb(CONF2_FORWARD_PORT, bus);
307 dataport = 0xc000 | (slot << 8) | reg;
314 /* disable configuration space accesses */
322 * Do nothing for the config mechanism 1 case.
323 * Writing a 0 to the address port can apparently
324 * confuse some bridges and cause spurious
329 outb(CONF2_ENABLE_PORT, 0);
335 pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
340 mtx_lock_spin(&pcicfg_mtx);
341 port = pci_cfgenable(bus, slot, func, reg, bytes);
356 mtx_unlock_spin(&pcicfg_mtx);
361 pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
365 mtx_lock_spin(&pcicfg_mtx);
366 port = pci_cfgenable(bus, slot, func, reg, bytes);
381 mtx_unlock_spin(&pcicfg_mtx);
384 /* check whether the configuration mechanism has been correctly identified */
386 pci_cfgcheck(int maxdev)
394 printf("pci_cfgcheck:\tdevice ");
396 for (device = 0; device < maxdev; device++) {
398 printf("%d ", device);
400 port = pci_cfgenable(0, device, 0, 0, 4);
402 if (id == 0 || id == 0xffffffff)
405 port = pci_cfgenable(0, device, 0, 8, 4);
406 class = inl(port) >> 8;
408 printf("[class=%06x] ", class);
409 if (class == 0 || (class & 0xf870ff) != 0)
412 port = pci_cfgenable(0, device, 0, 14, 1);
415 printf("[hdr=%02x] ", header);
416 if ((header & 0x7e) != 0)
420 printf("is there (id=%08x)\n", id);
426 printf("-- nothing found\n");
435 uint32_t mode1res, oldval1;
436 uint8_t mode2res, oldval2;
438 /* Check for type #1 first. */
439 oldval1 = inl(CONF1_ADDR_PORT);
442 printf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08x\n",
449 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
451 mode1res = inl(CONF1_ADDR_PORT);
452 outl(CONF1_ADDR_PORT, oldval1);
455 printf("pci_open(1a):\tmode1res=0x%08x (0x%08lx)\n", mode1res,
459 if (pci_cfgcheck(32))
463 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1);
464 mode1res = inl(CONF1_ADDR_PORT);
465 outl(CONF1_ADDR_PORT, oldval1);
468 printf("pci_open(1b):\tmode1res=0x%08x (0x%08lx)\n", mode1res,
471 if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) {
472 if (pci_cfgcheck(32))
476 /* Type #1 didn't work, so try type #2. */
477 oldval2 = inb(CONF2_ENABLE_PORT);
480 printf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n",
484 if ((oldval2 & 0xf0) == 0) {
489 outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK);
490 mode2res = inb(CONF2_ENABLE_PORT);
491 outb(CONF2_ENABLE_PORT, oldval2);
494 printf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n",
495 mode2res, CONF2_ENABLE_CHK);
497 if (mode2res == CONF2_ENABLE_RES) {
499 printf("pci_open(2a):\tnow trying mechanism 2\n");
501 if (pci_cfgcheck(16))
506 /* Nothing worked, so punt. */
507 cfgmech = CFGMECH_NONE;
513 pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
515 struct pcie_cfg_list *pcielist;
516 struct pcie_cfg_elem *pcie_array, *elem;
531 if (base >= 0x100000000) {
534 "PCI: Memory Mapped PCI configuration area base 0x%jx too high\n",
541 printf("PCIe: Memory Mapped configuration base @ 0x%jx\n",
545 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu)
549 pcie_array = malloc(sizeof(struct pcie_cfg_elem) * PCIE_CACHE,
551 if (pcie_array == NULL)
554 va = kva_alloc(PCIE_CACHE * PAGE_SIZE);
556 free(pcie_array, M_DEVBUF);
561 pcielist = &pcie_list[pc->pc_cpuid];
563 pcielist = &pcie_list[0];
565 TAILQ_INIT(pcielist);
566 for (i = 0; i < PCIE_CACHE; i++) {
567 elem = &pcie_array[i];
568 elem->vapage = va + (i * PAGE_SIZE);
570 TAILQ_INSERT_HEAD(pcielist, elem, elem);
575 pcie_minbus = minbus;
576 pcie_maxbus = maxbus;
577 cfgmech = CFGMECH_PCIE;
581 * On some AMD systems, some of the devices on bus 0 are
582 * inaccessible using memory-mapped PCI config access. Walk
583 * bus 0 looking for such devices. For these devices, we will
584 * fall back to using type 1 config access instead.
586 if (pci_cfgregopen() != 0) {
587 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
588 val1 = pcireg_cfgread(0, slot, 0, 0, 4);
589 if (val1 == 0xffffffff)
592 val2 = pciereg_cfgread(0, slot, 0, 0, 4);
594 pcie_badslots |= (1 << slot);
601 #define PCIE_PADDR(base, reg, bus, slot, func) \
603 ((((bus) & 0xff) << 20) | \
604 (((slot) & 0x1f) << 15) | \
605 (((func) & 0x7) << 12) | \
608 static __inline vm_offset_t
609 pciereg_findaddr(int bus, unsigned slot, unsigned func, unsigned reg)
611 struct pcie_cfg_list *pcielist;
612 struct pcie_cfg_elem *elem;
613 vm_paddr_t pa, papage;
615 pa = PCIE_PADDR(pcie_base, reg, bus, slot, func);
616 papage = pa & ~PAGE_MASK;
619 * Find an element in the cache that matches the physical page desired,
620 * or create a new mapping from the least recently used element.
621 * A very simple LRU algorithm is used here, does it need to be more
624 pcielist = &pcie_list[PCPU_GET(cpuid)];
625 TAILQ_FOREACH(elem, pcielist, elem) {
626 if (elem->papage == papage)
631 elem = TAILQ_LAST(pcielist, pcie_cfg_list);
632 if (elem->papage != 0) {
633 pmap_kremove(elem->vapage);
634 invlpg(elem->vapage);
636 pmap_kenter(elem->vapage, papage);
637 elem->papage = papage;
640 if (elem != TAILQ_FIRST(pcielist)) {
641 TAILQ_REMOVE(pcielist, elem, elem);
642 TAILQ_INSERT_HEAD(pcielist, elem, elem);
644 return (elem->vapage | (pa & PAGE_MASK));
648 * AMD BIOS And Kernel Developer's Guides for CPU families starting with 10h
649 * have a requirement that all accesses to the memory mapped PCI configuration
650 * space are done using AX class of registers.
651 * Since other vendors do not currently have any contradicting requirements
652 * the AMD access pattern is applied universally.
656 pciereg_cfgread(int bus, unsigned slot, unsigned func, unsigned reg,
662 if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX ||
663 func > PCI_FUNCMAX || reg > PCIE_REGMAX)
667 va = pciereg_findaddr(bus, slot, func, reg);
671 __asm("movl %1, %0" : "=a" (data)
672 : "m" (*(volatile uint32_t *)va));
675 __asm("movzwl %1, %0" : "=a" (data)
676 : "m" (*(volatile uint16_t *)va));
679 __asm("movzbl %1, %0" : "=a" (data)
680 : "m" (*(volatile uint8_t *)va));
689 pciereg_cfgwrite(int bus, unsigned slot, unsigned func, unsigned reg, int data,
694 if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX ||
695 func > PCI_FUNCMAX || reg > PCIE_REGMAX)
699 va = pciereg_findaddr(bus, slot, func, reg);
703 __asm("movl %1, %0" : "=m" (*(volatile uint32_t *)va)
707 __asm("movw %1, %0" : "=m" (*(volatile uint16_t *)va)
708 : "a" ((uint16_t)data));
711 __asm("movb %1, %0" : "=m" (*(volatile uint8_t *)va)
712 : "a" ((uint8_t)data));