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1 /*
2  *   Copyright (c) 1999 Gary Jennejohn. All rights reserved.
3  *
4  *   Redistribution and use in source and binary forms, with or without
5  *   modification, are permitted provided that the following conditions
6  *   are met:
7  *
8  *   1. Redistributions of source code must retain the above copyright
9  *      notice, this list of conditions and the following disclaimer.
10  *   2. Redistributions in binary form must reproduce the above copyright
11  *      notice, this list of conditions and the following disclaimer in the
12  *      documentation and/or other materials provided with the distribution.
13  *   3. Neither the name of the author nor the names of any co-contributors
14  *      may be used to endorse or promote products derived from this software
15  *      without specific prior written permission.
16  *   4. Altered versions must be plainly marked as such, and must not be
17  *      misrepresented as being the original software and/or documentation.
18  *   
19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29  *   SUCH DAMAGE.
30  *
31  *---------------------------------------------------------------------------
32  *   a lot of code was borrowed from i4b_bchan.c and i4b_hscx.c
33  *---------------------------------------------------------------------------
34  *
35  *      Fritz!Card PCI specific routines for isic driver
36  *      ------------------------------------------------
37  *
38  *      New-bus'ified by Gary Jennejohn - 15 Nov 99.
39  *
40  *      $Id: i4b_avm_fritz_pci.c,v 1.3 1999/12/13 21:25:26 hm Exp $
41  *
42  * $FreeBSD$
43  *
44  *      last edit-date: [Mon Dec 13 21:59:04 1999]
45  *
46  *---------------------------------------------------------------------------*/
47
48 #include "isic.h"
49 #include "opt_i4b.h"
50
51 #if NISIC > 0 && defined(AVM_A1_PCI)
52
53 #include <sys/param.h>
54 #include <sys/kernel.h>
55 #include <sys/systm.h>
56 #include <sys/mbuf.h>
57
58 #include <machine/clock.h>      /* for DELAY */
59 #include <machine/bus_pio.h> /* this device uses port accesses only */
60 #include <machine/bus.h>
61 #include <machine/resource.h>
62 #include <sys/bus.h>
63 #include <sys/rman.h>
64
65 #include <pci/pcireg.h>
66 #include <pci/pcivar.h>
67
68 #include <sys/socket.h>
69 #include <net/if.h>
70
71 #include <machine/i4b_debug.h>
72 #include <machine/i4b_ioctl.h>
73
74 #include <i4b/include/i4b_global.h>
75 #include <i4b/include/i4b_l1l2.h>
76 #include <i4b/include/i4b_mbuf.h>
77
78 #include <i4b/layer1/i4b_l1.h>
79 #include <i4b/layer1/i4b_isac.h>
80 #include <i4b/layer1/i4b_hscx.h>
81
82 #define PCI_AVMA1_VID 0x1244
83 #define PCI_AVMA1_DID 0x0a00
84
85 /* prototypes */
86 static void avma1pp_disable(device_t);
87
88 static void avma1pp_intr(void *);
89 static void hscx_write_reg(int, u_int, u_int, struct l1_softc *);
90 static u_char hscx_read_reg(int, u_int, struct l1_softc *);
91 static u_int hscx_read_reg_int(int, u_int, struct l1_softc *);
92 static void hscx_read_fifo(int, void *, size_t, struct l1_softc *);
93 static void hscx_write_fifo(int, void *, size_t, struct l1_softc *);
94 static void avma1pp_hscx_int_handler(struct l1_softc *);
95 static void avma1pp_hscx_intr(int, u_int, struct l1_softc *);
96 static void avma1pp_init_linktab(struct l1_softc *);
97 static void avma1pp_bchannel_setup(int, int, int, int);
98 static void avma1pp_bchannel_start(int, int);
99 static void avma1pp_hscx_init(struct l1_softc *, int, int);
100 static void avma1pp_bchannel_stat(int, int, bchan_statistics_t *);
101 static void avma1pp_set_linktab(int, int, drvr_link_t *);
102 static isdn_link_t * avma1pp_ret_linktab(int, int);
103 static int avma1pp_pci_probe(device_t);
104 int isic_attach_avma1pp(device_t);
105
106 static device_method_t avma1pp_pci_methods[] = {
107         /* Device interface */
108         DEVMETHOD(device_probe,         avma1pp_pci_probe),
109         DEVMETHOD(device_attach,        isic_attach_avma1pp),
110         DEVMETHOD(device_shutdown,      avma1pp_disable),
111
112         /* bus interface */
113         DEVMETHOD(bus_print_child,      bus_generic_print_child),
114         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
115
116         { 0, 0 }
117 };
118
119 /* a minimal softc for the Fritz!Card PCI */
120 struct avma1pp_softc 
121 {
122         bus_space_handle_t      avma1pp_bhandle;
123         bus_space_tag_t         avma1pp_btag;
124         void                    *avma1pp_intrhand;
125         struct resource         *avma1pp_irq;
126         struct resource         *avma1pp_res;
127         u_int8_t                avma1pp_unit;   /* interface number */
128         /* pointer to l1_sc */
129         struct l1_softc *avma1pp_isc;
130 };
131
132 static driver_t avma1pp_pci_driver = {
133         "isic",
134         avma1pp_pci_methods,
135         sizeof(struct avma1pp_softc)
136 };
137
138 static devclass_t avma1pp_pci_devclass;
139
140 DRIVER_MODULE(avma1pp, pci, avma1pp_pci_driver, avma1pp_pci_devclass, 0, 0);
141
142 /*---------------------------------------------------------------------------*
143  *      AVM PCI Fritz!Card special registers
144  *---------------------------------------------------------------------------*/
145
146 /*
147  *      register offsets from i/o base
148  */
149 #define STAT0_OFFSET            0x02
150 #define STAT1_OFFSET            0x03
151 #define ADDR_REG_OFFSET         0x04
152 /*#define MODREG_OFFSET         0x06
153 #define VERREG_OFFSET           0x07*/
154
155 /* these 2 are used to select an ISAC register set */
156 #define ISAC_LO_REG_OFFSET      0x04
157 #define ISAC_HI_REG_OFFSET      0x06
158
159 /* offset higher than this goes to the HI register set */
160 #define MAX_LO_REG_OFFSET       0x2f
161
162 /* mask for the offset */
163 #define ISAC_REGSET_MASK        0x0f
164
165 /* the offset from the base to the ISAC registers */
166 #define ISAC_REG_OFFSET         0x10
167
168 /* the offset from the base to the ISAC FIFO */
169 #define ISAC_FIFO               0x02
170
171 /* not really the HSCX, but sort of */
172 #define HSCX_FIFO               0x00
173 #define HSCX_STAT               0x04
174
175 /*
176  *      AVM PCI Status Latch 0 read only bits
177  */
178 #define ASL_IRQ_ISAC            0x01    /* ISAC  interrupt, active low */
179 #define ASL_IRQ_HSCX            0x02    /* HSX   interrupt, active low */
180 #define ASL_IRQ_TIMER           0x04    /* Timer interrupt, active low */
181 #define ASL_IRQ_BCHAN           ASL_IRQ_HSCX
182 /* actually active LOW */
183 #define ASL_IRQ_Pending         (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
184
185 /*
186  *      AVM Status Latch 0 write only bits
187  */
188 #define ASL_RESET_ALL           0x01  /* reset siemens IC's, active 1 */
189 #define ASL_TIMERDISABLE        0x02  /* active high */
190 #define ASL_TIMERRESET          0x04  /* active high */
191 #define ASL_ENABLE_INT          0x08  /* active high */
192 #define ASL_TESTBIT             0x10  /* active high */
193
194 /*
195  *      AVM Status Latch 1 write only bits
196  */
197 #define ASL1_INTSEL              0x0f  /* active high */
198 #define ASL1_ENABLE_IOM          0x80  /* active high */
199
200 /*
201  * "HSCX" mode bits
202  */
203 #define  HSCX_MODE_ITF_FLG      0x01
204 #define  HSCX_MODE_TRANS        0x02
205 #define  HSCX_MODE_CCR_7        0x04
206 #define  HSCX_MODE_CCR_16       0x08
207 #define  HSCX_MODE_TESTLOOP     0x80
208
209 /*
210  * "HSCX" status bits
211  */
212 #define  HSCX_STAT_RME          0x01
213 #define  HSCX_STAT_RDO          0x10
214 #define  HSCX_STAT_CRCVFRRAB    0x0E
215 #define  HSCX_STAT_CRCVFR       0x06
216 #define  HSCX_STAT_RML_MASK     0x3f00
217
218 /*
219  * "HSCX" interrupt bits
220  */
221 #define  HSCX_INT_XPR           0x80
222 #define  HSCX_INT_XDU           0x40
223 #define  HSCX_INT_RPR           0x20
224 #define  HSCX_INT_MASK          0xE0
225
226 /*
227  * "HSCX" command bits
228  */
229 #define  HSCX_CMD_XRS           0x80
230 #define  HSCX_CMD_XME           0x01
231 #define  HSCX_CMD_RRS           0x20
232 #define  HSCX_CMD_XML_MASK      0x3f00
233
234 /*
235  * Commands and parameters are sent to the "HSCX" as a long, but the
236  * fields are handled as bytes.
237  *
238  * The long contains:
239  *      (prot << 16)|(txl << 8)|cmd
240  *
241  * where:
242  *      prot = protocol to use
243  *      txl = transmit length
244  *      cmd = the command to be executed
245  *
246  * The fields are defined as u_char in struct l1_softc.
247  *
248  * Macro to coalesce the byte fields into a u_int
249  */
250 #define AVMA1PPSETCMDLONG(f) (f) = ((sc->avma1pp_cmd) | (sc->avma1pp_txl << 8) \
251                                         | (sc->avma1pp_prot << 16))
252
253 /*
254  * to prevent deactivating the "HSCX" when both channels are active we
255  * define an HSCX_ACTIVE flag which is or'd into the channel's state
256  * flag in avma1pp_bchannel_setup upon active and cleared upon deactivation.
257  * It is set high to allow room for new flags.
258  */
259 #define HSCX_AVMA1PP_ACTIVE     0x1000 
260
261 /*---------------------------------------------------------------------------*
262  *      AVM read fifo routines
263  *---------------------------------------------------------------------------*/
264
265 static void
266 avma1pp_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
267 {
268         struct avma1pp_softc *asc = (struct avma1pp_softc *)sc->sc_ipacbase;
269
270         switch (what) {
271                 case ISIC_WHAT_ISAC:
272                         bus_space_write_1(asc->avma1pp_btag, asc->avma1pp_bhandle,  ADDR_REG_OFFSET, ISAC_FIFO);
273                         bus_space_read_multi_1(asc->avma1pp_btag, asc->avma1pp_bhandle,  ISAC_REG_OFFSET, buf, size);
274                         break;
275                 case ISIC_WHAT_HSCXA:
276                         hscx_read_fifo(0, buf, size, sc);
277                         break;
278                 case ISIC_WHAT_HSCXB:
279                         hscx_read_fifo(1, buf, size, sc);
280                         break;
281         }
282 }
283
284 static void
285 hscx_read_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
286 {
287         u_int32_t *ip;
288         size_t cnt;
289         struct avma1pp_softc *asc = (struct avma1pp_softc *)sc->sc_ipacbase;
290
291
292         bus_space_write_4(asc->avma1pp_btag, asc->avma1pp_bhandle, ADDR_REG_OFFSET, chan);
293         ip = (u_int32_t *)buf;
294         cnt = 0;
295         /* what if len isn't a multiple of sizeof(int) and buf is */
296         /* too small ???? */
297         while (cnt < len)
298         {
299                 *ip++ = bus_space_read_4(asc->avma1pp_btag, asc->avma1pp_bhandle, ISAC_REG_OFFSET);
300                 cnt += 4;
301         }
302 }
303
304 /*---------------------------------------------------------------------------*
305  *      AVM write fifo routines
306  *---------------------------------------------------------------------------*/
307 static void
308 avma1pp_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
309 {
310         struct avma1pp_softc *asc = (struct avma1pp_softc *)sc->sc_ipacbase;
311
312         switch (what) {
313                 case ISIC_WHAT_ISAC:
314                         bus_space_write_1(asc->avma1pp_btag, asc->avma1pp_bhandle,  ADDR_REG_OFFSET, ISAC_FIFO);
315                         bus_space_write_multi_1(asc->avma1pp_btag, asc->avma1pp_bhandle,  ISAC_REG_OFFSET, (u_int8_t*)buf, size);
316                         break;
317                 case ISIC_WHAT_HSCXA:
318                         hscx_write_fifo(0, buf, size, sc);
319                         break;
320                 case ISIC_WHAT_HSCXB:
321                         hscx_write_fifo(1, buf, size, sc);
322                         break;
323         }
324 }
325
326 static void
327 hscx_write_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
328 {
329         u_int32_t *ip;
330         size_t cnt;
331         l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
332         struct avma1pp_softc *asc = (struct avma1pp_softc *)sc->sc_ipacbase;
333
334
335         sc->avma1pp_cmd &= ~HSCX_CMD_XME;
336         sc->avma1pp_txl = 0;
337         if (Bchan->out_mbuf_cur == NULL)
338         {
339           if (Bchan->bprot != BPROT_NONE)
340                  sc->avma1pp_cmd |= HSCX_CMD_XME;
341         }
342         if (len != sc->sc_bfifolen)
343                 sc->avma1pp_txl = len;
344         
345         cnt = 0; /* borrow cnt */
346         AVMA1PPSETCMDLONG(cnt);
347         hscx_write_reg(chan, HSCX_STAT, cnt, sc);
348
349         ip = (u_int32_t *)buf;
350         cnt = 0;
351         while (cnt < len)
352         {
353                 bus_space_write_4(asc->avma1pp_btag, asc->avma1pp_bhandle, ISAC_REG_OFFSET, *ip);
354                 ip++;
355                 cnt += 4;
356         }
357 }
358
359 /*---------------------------------------------------------------------------*
360  *      AVM write register routines
361  *---------------------------------------------------------------------------*/
362
363 static void
364 avma1pp_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
365 {
366         u_char reg_bank;
367         struct avma1pp_softc *asc = (struct avma1pp_softc *)sc->sc_ipacbase;
368
369         switch (what) {
370                 case ISIC_WHAT_ISAC:
371                         reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
372 #ifdef AVMA1PCI_DEBUG
373                         printf("write_reg bank %d  off %ld.. ", (int)reg_bank, (long)offs);
374 #endif
375                         /* set the register bank */
376                         bus_space_write_1(asc->avma1pp_btag, asc->avma1pp_bhandle, ADDR_REG_OFFSET, reg_bank);
377                         bus_space_write_1(asc->avma1pp_btag, asc->avma1pp_bhandle, ISAC_REG_OFFSET + (offs & ISAC_REGSET_MASK), data);
378                         break;
379                 case ISIC_WHAT_HSCXA:
380                         hscx_write_reg(0, offs, data, sc);
381                         break;
382                 case ISIC_WHAT_HSCXB:
383                         hscx_write_reg(1, offs, data, sc);
384                         break;
385         }
386 }
387
388 static void
389 hscx_write_reg(int chan, u_int off, u_int val, struct l1_softc *sc)
390 {
391         struct avma1pp_softc *asc = (struct avma1pp_softc *)sc->sc_ipacbase;
392
393         /* HACK */
394         if (off == H_MASK)
395                 return;
396         /* point at the correct channel */
397         bus_space_write_4(asc->avma1pp_btag, asc->avma1pp_bhandle, ADDR_REG_OFFSET, chan);
398         bus_space_write_4(asc->avma1pp_btag, asc->avma1pp_bhandle, ISAC_REG_OFFSET + off, val);
399 }
400
401 /*---------------------------------------------------------------------------*
402  *      AVM read register routines
403  *---------------------------------------------------------------------------*/
404 static u_int8_t
405 avma1pp_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
406 {
407         u_char reg_bank;
408         struct avma1pp_softc *asc = (struct avma1pp_softc *)sc->sc_ipacbase;
409
410         switch (what) {
411                 case ISIC_WHAT_ISAC:
412                         reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
413 #ifdef AVMA1PCI_DEBUG
414                         printf("read_reg bank %d  off %ld.. ", (int)reg_bank, (long)offs);
415 #endif
416                         /* set the register bank */
417                         bus_space_write_1(asc->avma1pp_btag, asc->avma1pp_bhandle, ADDR_REG_OFFSET, reg_bank);
418                         return(bus_space_read_1(asc->avma1pp_btag, asc->avma1pp_bhandle, ISAC_REG_OFFSET +
419                                 (offs & ISAC_REGSET_MASK)));
420                 case ISIC_WHAT_HSCXA:
421                         return hscx_read_reg(0, offs, sc);
422                 case ISIC_WHAT_HSCXB:
423                         return hscx_read_reg(1, offs, sc);
424         }
425         return 0;
426 }
427
428 static u_char
429 hscx_read_reg(int chan, u_int off, struct l1_softc *sc)
430 {
431         return(hscx_read_reg_int(chan, off, sc) & 0xff);
432 }
433
434 /*
435  * need to be able to return an int because the RBCH is in the 2nd
436  * byte.
437  */
438 static u_int
439 hscx_read_reg_int(int chan, u_int off, struct l1_softc *sc)
440 {
441         struct avma1pp_softc *asc = (struct avma1pp_softc *)sc->sc_ipacbase;
442
443         /* HACK */
444         if (off == H_ISTA)
445                 return(0);
446         /* point at the correct channel */
447         bus_space_write_4(asc->avma1pp_btag, asc->avma1pp_bhandle, ADDR_REG_OFFSET, chan);
448         return(bus_space_read_4(asc->avma1pp_btag, asc->avma1pp_bhandle, ISAC_REG_OFFSET + off));
449 }
450
451 /*---------------------------------------------------------------------------*
452  *      avma1pp_probe - probe for a card
453  *---------------------------------------------------------------------------*/
454 static int
455 avma1pp_pci_probe(dev)
456         device_t                dev;
457 {
458         u_int16_t               did, vid;
459
460         vid = pci_get_vendor(dev);
461         did = pci_get_device(dev);
462
463         if ((vid == PCI_AVMA1_VID) && (did == PCI_AVMA1_DID)) {
464                 device_set_desc(dev, "AVM Fritz!Card PCI");
465                 return(0);
466         }
467
468         return(ENXIO);
469 }
470
471 /*---------------------------------------------------------------------------*
472  *      isic_attach_avma1pp - attach Fritz!Card PCI
473  *---------------------------------------------------------------------------*/
474 int
475 isic_attach_avma1pp(device_t dev)
476 {
477         struct l1_softc *sc;
478         u_int v;
479         /* start of new-bus stuff */
480         struct avma1pp_softc *asc;
481         int unit, error = 0, rid;
482         int s;
483         u_int16_t did, vid;
484
485         s = splimp();
486
487         vid = pci_get_vendor(dev);
488         did = pci_get_device(dev);
489         asc = device_get_softc(dev);
490         unit = device_get_unit(dev);
491         bzero(asc, sizeof(struct avma1pp_softc));
492
493         if(unit > ISIC_MAXUNIT) {
494                 printf("avma1pp%d: Error, unit > ISIC_MAXUNIT!\n", unit);
495                 splx(s);
496                 return(ENXIO);
497         }
498
499         if ((vid != PCI_AVMA1_VID) && (did != PCI_AVMA1_DID)) {
500                 printf("avma1pp%d: unknown device!?\n", unit);
501                 goto fail;
502         }
503
504         asc->avma1pp_unit = unit;
505
506         rid = PCIR_MAPS+4;
507         asc->avma1pp_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
508                 0, ~0, 1, RF_ACTIVE);
509
510         if (asc->avma1pp_res == NULL) {
511                 printf("avma1pp%d: couldn't map IO port\n", unit);
512                 error = ENXIO;
513                 goto fail;
514         }
515
516         asc->avma1pp_btag = rman_get_bustag(asc->avma1pp_res);
517         asc->avma1pp_bhandle = rman_get_bushandle(asc->avma1pp_res);
518
519         /* Allocate interrupt */
520         rid = 0;
521         asc->avma1pp_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
522             RF_SHAREABLE | RF_ACTIVE);
523
524         if (asc->avma1pp_irq == NULL) {
525                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, asc->avma1pp_res);
526                 printf("avma1pp%d: couldn't map interrupt\n", unit);
527                 error = ENXIO;
528                 goto fail;
529         }
530
531         error = bus_setup_intr(dev, asc->avma1pp_irq, INTR_TYPE_NET, avma1pp_intr, asc, &asc->avma1pp_intrhand);
532
533         if (error) {
534                 bus_release_resource(dev, SYS_RES_IRQ, 0, asc->avma1pp_res);
535                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, asc->avma1pp_res);
536                 printf("avma1pp%d: couldn't set up irq\n", unit);
537                 goto fail;
538         }
539
540         sc = asc->avma1pp_isc = &l1_sc[unit];
541         sc->sc_unit = unit;
542
543         /* mis-use sc_ipacbase to point at avma1pp_softc */
544         IPAC_BASE = (caddr_t)asc;
545         /* end of new-bus stuff */
546
547         /* the ISAC lives at offset 0x10, but we can't use that. */
548         /* instead, put the unit number into the lower byte - HACK */
549         ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
550
551         /* this thing doesn't have an HSCX, so fake the base addresses */
552         HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
553         HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
554
555         /* setup access routines */
556
557         sc->clearirq = NULL;
558         sc->readreg = avma1pp_read_reg;
559         sc->writereg = avma1pp_write_reg;
560
561         sc->readfifo = avma1pp_read_fifo;
562         sc->writefifo = avma1pp_write_fifo;
563
564         /* setup card type */
565         
566         sc->sc_cardtyp = CARD_TYPEP_AVMA1PCI;
567
568         /* setup IOM bus type */
569         
570         sc->sc_bustyp = BUS_TYPE_IOM2;
571
572         /* set up some other miscellaneous things */
573         sc->sc_ipac = 0;
574         sc->sc_bfifolen = HSCX_FIFO_LEN;
575
576         /* reset the card */
577         /* the Linux driver does this to clear any pending ISAC interrupts */
578         v = 0;
579         v = ISAC_READ(I_STAR);
580 #ifdef AVMA1PCI_DEBUG
581         printf("avma1pp_attach: I_STAR %x...", v);
582 #endif
583         v = ISAC_READ(I_MODE);
584 #ifdef AVMA1PCI_DEBUG
585         printf("avma1pp_attach: I_MODE %x...", v);
586 #endif
587         v = ISAC_READ(I_ADF2);
588 #ifdef AVMA1PCI_DEBUG
589         printf("avma1pp_attach: I_ADF2 %x...", v);
590 #endif
591         v = ISAC_READ(I_ISTA);
592 #ifdef AVMA1PCI_DEBUG
593         printf("avma1pp_attach: I_ISTA %x...", v);
594 #endif
595         if (v & ISAC_ISTA_EXI)
596         {
597                  v = ISAC_READ(I_EXIR);
598 #ifdef AVMA1PCI_DEBUG
599                  printf("avma1pp_attach: I_EXIR %x...", v);
600 #endif
601         }
602         v = ISAC_READ(I_CIRR);
603 #ifdef AVMA1PCI_DEBUG
604         printf("avma1pp_attach: I_CIRR %x...", v);
605 #endif
606         ISAC_WRITE(I_MASK, 0xff);
607         /* the Linux driver does this to clear any pending HSCX interrupts */
608         v = hscx_read_reg_int(0, HSCX_STAT, sc);
609 #ifdef AVMA1PCI_DEBUG
610         printf("avma1pp_attach: 0 HSCX_STAT %x...", v);
611 #endif
612         v = hscx_read_reg_int(1, HSCX_STAT, sc);
613 #ifdef AVMA1PCI_DEBUG
614         printf("avma1pp_attach: 1 HSCX_STAT %x\n", v);
615 #endif
616
617         bus_space_write_1(asc->avma1pp_btag, asc->avma1pp_bhandle, STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
618         DELAY(SEC_DELAY/100); /* 10 ms */
619         bus_space_write_1(asc->avma1pp_btag, asc->avma1pp_bhandle, STAT0_OFFSET, ASL_TIMERRESET|ASL_ENABLE_INT|ASL_TIMERDISABLE);
620         DELAY(SEC_DELAY/100); /* 10 ms */
621 #ifdef AVMA1PCI_DEBUG
622         bus_space_write_1(asc->avma1pp_btag, asc->avma1pp_bhandle, STAT1_OFFSET, ASL1_ENABLE_IOM|sc->sc_irq);
623         DELAY(SEC_DELAY/100); /* 10 ms */
624         v = bus_space_read_1(asc->avma1pp_btag, asc->avma1pp_bhandle, STAT1_OFFSET);
625         printf("after reset: S1 %#x\n", v);
626
627         v = bus_space_read_4(asc->avma1pp_btag, asc->avma1pp_bhandle, 0);
628         printf("isic_attach_avma1pp: v %#x\n", v);
629 #endif
630
631    /* from here to the end would normally be done in isic_pciattach */
632
633          printf("isic%d: ISAC %s (IOM-%c)\n", unit,
634                 "2085 Version A1/A2 or 2086/2186 Version 1.1",
635                  sc->sc_bustyp == BUS_TYPE_IOM1 ? '1' : '2');
636
637         /* init the ISAC */
638         isic_isac_init(sc);
639
640         /* init the "HSCX" */
641         avma1pp_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
642         
643         avma1pp_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
644
645         /* can't use the normal B-Channel stuff */
646         avma1pp_init_linktab(sc);
647
648         /* set trace level */
649
650         sc->sc_trace = TRACE_OFF;
651
652         sc->sc_state = ISAC_IDLE;
653
654         sc->sc_ibuf = NULL;
655         sc->sc_ib = NULL;
656         sc->sc_ilen = 0;
657
658         sc->sc_obuf = NULL;
659         sc->sc_op = NULL;
660         sc->sc_ol = 0;
661         sc->sc_freeflag = 0;
662
663         sc->sc_obuf2 = NULL;
664         sc->sc_freeflag2 = 0;
665
666 #ifdef USENEWFIELDS
667         /* new fields */
668         sc->recover = isic_recover;
669         sc->next_state = isic_next_state;
670         sc->ph_data_req = isic_isac_ph_data_req;
671         sc->l1_cmd = isic_isac_l1_cmd;
672 #endif
673
674 #if defined(__FreeBSD__) && __FreeBSD__ >=3
675         callout_handle_init(&sc->sc_T3_callout);
676         callout_handle_init(&sc->sc_T4_callout);        
677 #endif
678         
679         /* init higher protocol layers */
680         
681         MPH_Status_Ind(sc->sc_unit, STI_ATTACH, sc->sc_cardtyp);
682
683   fail:
684         splx(s);
685         return(error);
686 }
687
688 /*
689  * this is the real interrupt routine
690  */
691 static void
692 avma1pp_hscx_intr(int h_chan, u_int stat, struct l1_softc *sc)
693 {
694         register l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
695         int activity = -1;
696         u_int param = 0;
697         
698         DBGL1(L1_H_IRQ, "avma1pp_hscx_intr", ("%#x\n", stat));
699
700         if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
701         {
702                 chan->stat_XDU++;                       
703                 DBGL1(L1_H_XFRERR, "avma1pp_hscx_intr", ("xmit data underrun\n"));
704                 /* abort the transmission */
705                 sc->avma1pp_txl = 0;
706                 sc->avma1pp_cmd |= HSCX_CMD_XRS;
707                 AVMA1PPSETCMDLONG(param);
708                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
709                 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
710                 AVMA1PPSETCMDLONG(param);
711                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
712
713                 if (chan->out_mbuf_head != NULL)  /* don't continue to transmit this buffer */
714                 {
715                         i4b_Bfreembuf(chan->out_mbuf_head);
716                         chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
717                 }
718         }
719
720         /*
721          * The following is based on examination of the Linux driver.
722          *
723          * The logic here is different than with a "real" HSCX; all kinds
724          * of information (interrupt/status bits) are in stat.
725          *              HSCX_INT_RPR indicates a receive interrupt
726          *                      HSCX_STAT_RDO indicates an overrun condition, abort -
727          *                      otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
728          *                      HSCX_STAT_RME indicates end-of-frame and apparently any
729          *                      CRC/framing errors are only reported in this state.
730          *                              if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
731          *                                      CRC/framing error
732          */
733         
734         if(stat & HSCX_INT_RPR)
735         {
736                 register int fifo_data_len;
737                 int error = 0;
738                 /* always have to read the FIFO, so use a scratch buffer */
739                 u_char scrbuf[HSCX_FIFO_LEN];
740
741                 if(stat & HSCX_STAT_RDO)
742                 {
743                         chan->stat_RDO++;
744                         DBGL1(L1_H_XFRERR, "avma1pp_hscx_intr", ("receive data overflow\n"));
745                         error++;                                
746                 }
747
748                 /*
749                  * check whether we're receiving data for an inactive B-channel
750                  * and discard it. This appears to happen for telephony when
751                  * both B-channels are active and one is deactivated. Since
752                  * it is not really possible to deactivate the channel in that
753                  * case (the ASIC seems to deactivate _both_ channels), the
754                  * "deactivated" channel keeps receiving data which can lead
755                  * to exhaustion of mbufs and a kernel panic.
756                  *
757                  * This is a hack, but it's the only solution I can think of
758                  * without having the documentation for the ASIC.
759                  * GJ - 28 Nov 1999
760                  */
761                  if (chan->state == HSCX_IDLE)
762                  {
763                         DBGL1(L1_H_XFRERR, "avma1pp_hscx_intr", ("toss data from %d\n", h_chan));
764                         error++;
765                  }
766
767                 fifo_data_len = ((stat & HSCX_STAT_RML_MASK) >> 8);
768                 
769                 if(fifo_data_len == 0)
770                         fifo_data_len = sc->sc_bfifolen;
771
772                 /* ALWAYS read data from HSCX fifo */
773         
774                 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
775                 chan->rxcount += fifo_data_len;
776
777                 /* all error conditions checked, now decide and take action */
778                 
779                 if(error == 0)
780                 {
781                         if(chan->in_mbuf == NULL)
782                         {
783                                 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
784                                         panic("L1 avma1pp_hscx_intr: RME, cannot allocate mbuf!\n");
785                                 chan->in_cbptr = chan->in_mbuf->m_data;
786                                 chan->in_len = 0;
787                         }
788
789                         if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
790                         {
791                                 /* OK to copy the data */
792                                 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
793                                 chan->in_cbptr += fifo_data_len;
794                                 chan->in_len += fifo_data_len;
795
796                                 /* setup mbuf data length */
797                                         
798                                 chan->in_mbuf->m_len = chan->in_len;
799                                 chan->in_mbuf->m_pkthdr.len = chan->in_len;
800
801                                 if(sc->sc_trace & TRACE_B_RX)
802                                 {
803                                         i4b_trace_hdr_t hdr;
804                                         hdr.unit = sc->sc_unit;
805                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
806                                         hdr.dir = FROM_NT;
807                                         hdr.count = ++sc->sc_trace_bcount;
808                                         MICROTIME(hdr.time);
809                                         MPH_Trace_Ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
810                                 }
811
812                                 if (stat & HSCX_STAT_RME)
813                                 {
814                                   if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
815                                   {
816                                          (*chan->drvr_linktab->bch_rx_data_ready)(chan->drvr_linktab->unit);
817                                          activity = ACT_RX;
818                                 
819                                          /* mark buffer ptr as unused */
820                                         
821                                          chan->in_mbuf = NULL;
822                                          chan->in_cbptr = NULL;
823                                          chan->in_len = 0;
824                                   }
825                                   else
826                                   {
827                                                 chan->stat_CRC++;
828                                                 DBGL1(L1_H_XFRERR, "avma1pp_hscx_intr", ("CRC/RAB\n"));
829                                           if (chan->in_mbuf != NULL)
830                                           {
831                                                   i4b_Bfreembuf(chan->in_mbuf);
832                                                   chan->in_mbuf = NULL;
833                                                   chan->in_cbptr = NULL;
834                                                   chan->in_len = 0;
835                                           }
836                                   }
837                                 }
838                         } /* END enough space in mbuf */
839                         else
840                         {
841                                  if(chan->bprot == BPROT_NONE)
842                                  {
843                                           /* setup mbuf data length */
844                                 
845                                           chan->in_mbuf->m_len = chan->in_len;
846                                           chan->in_mbuf->m_pkthdr.len = chan->in_len;
847
848                                           if(sc->sc_trace & TRACE_B_RX)
849                                           {
850                                                         i4b_trace_hdr_t hdr;
851                                                         hdr.unit = sc->sc_unit;
852                                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
853                                                         hdr.dir = FROM_NT;
854                                                         hdr.count = ++sc->sc_trace_bcount;
855                                                         MICROTIME(hdr.time);
856                                                         MPH_Trace_Ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
857                                                 }
858
859                                           if(!(isic_hscx_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
860                                                  activity = ACT_RX;
861                                 
862                                           /* move rx'd data to rx queue */
863
864                                           if (!(IF_QFULL(&chan->rx_queue)))
865                                           {
866                                                 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
867                                           }
868                                           else
869                                           {
870                                                 i4b_Bfreembuf(chan->in_mbuf);
871                                           }
872
873                                           /* signal upper layer that data are available */
874                                           (*chan->drvr_linktab->bch_rx_data_ready)(chan->drvr_linktab->unit);
875
876                                           /* alloc new buffer */
877                                 
878                                           if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
879                                                  panic("L1 avma1pp_hscx_intr: RPF, cannot allocate new mbuf!\n");
880         
881                                           /* setup new data ptr */
882                                 
883                                           chan->in_cbptr = chan->in_mbuf->m_data;
884         
885                                           /* OK to copy the data */
886                                           bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
887
888                                           chan->in_cbptr += fifo_data_len;
889                                           chan->in_len = fifo_data_len;
890
891                                           chan->rxcount += fifo_data_len;
892                                         }
893                                  else
894                                         {
895                                           DBGL1(L1_H_XFRERR, "avma1pp_hscx_intr", ("RAWHDLC rx buffer overflow in RPF, in_len=%d\n", chan->in_len));
896                                           chan->in_cbptr = chan->in_mbuf->m_data;
897                                           chan->in_len = 0;
898                                         }
899                           }
900                 } /* if(error == 0) */
901                 else
902                 {
903                         /* land here for RDO */
904                         if (chan->in_mbuf != NULL)
905                         {
906                                 i4b_Bfreembuf(chan->in_mbuf);
907                                 chan->in_mbuf = NULL;
908                                 chan->in_cbptr = NULL;
909                                 chan->in_len = 0;
910                         }
911                         sc->avma1pp_txl = 0;
912                         sc->avma1pp_cmd |= HSCX_CMD_RRS;
913                         AVMA1PPSETCMDLONG(param);
914                         hscx_write_reg(h_chan, HSCX_STAT, param, sc);
915                         sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
916                         AVMA1PPSETCMDLONG(param);
917                         hscx_write_reg(h_chan, HSCX_STAT, param, sc);
918                 }
919         }
920
921
922         /* transmit fifo empty, new data can be written to fifo */
923         
924         if(stat & HSCX_INT_XPR)
925         {
926                 /*
927                  * for a description what is going on here, please have
928                  * a look at isic_bchannel_start() in i4b_bchan.c !
929                  */
930
931                 DBGL1(L1_H_IRQ, "avma1pp_hscx_intr", ("unit %d, chan %d - XPR, Tx Fifo Empty!\n", sc->sc_unit, h_chan));
932
933                 if(chan->out_mbuf_cur == NULL)  /* last frame is transmitted */
934                 {
935                         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
936
937                         if(chan->out_mbuf_head == NULL)
938                         {
939                                 chan->state &= ~HSCX_TX_ACTIVE;
940                                 (*chan->drvr_linktab->bch_tx_queue_empty)(chan->drvr_linktab->unit);
941                         }
942                         else
943                         {
944                                 chan->state |= HSCX_TX_ACTIVE;
945                                 chan->out_mbuf_cur = chan->out_mbuf_head;
946                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
947                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
948
949                                 if(sc->sc_trace & TRACE_B_TX)
950                                 {
951                                         i4b_trace_hdr_t hdr;
952                                         hdr.unit = sc->sc_unit;
953                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
954                                         hdr.dir = FROM_TE;
955                                         hdr.count = ++sc->sc_trace_bcount;
956                                         MICROTIME(hdr.time);
957                                         MPH_Trace_Ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
958                                 }
959                                 
960                                 if(chan->bprot == BPROT_NONE)
961                                 {
962                                         if(!(isic_hscx_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
963                                                 activity = ACT_TX;
964                                 }
965                                 else
966                                 {
967                                         activity = ACT_TX;
968                                 }
969                         }
970                 }
971                         
972                 isic_hscx_fifo(chan, sc);
973         }
974
975         /* call timeout handling routine */
976         
977         if(activity == ACT_RX || activity == ACT_TX)
978                 (*chan->drvr_linktab->bch_activity)(chan->drvr_linktab->unit, activity);
979 }
980
981 /*
982  * this is the main routine which checks each channel and then calls
983  * the real interrupt routine as appropriate
984  */
985 static void
986 avma1pp_hscx_int_handler(struct l1_softc *sc)
987 {
988         u_int stat;
989
990         /* has to be a u_int because the byte count is in the 2nd byte */
991         stat = hscx_read_reg_int(0, HSCX_STAT, sc);
992         if (stat & HSCX_INT_MASK)
993           avma1pp_hscx_intr(0, stat, sc);
994         stat = hscx_read_reg_int(1, HSCX_STAT, sc);
995         if (stat & HSCX_INT_MASK)
996           avma1pp_hscx_intr(1, stat, sc);
997 }
998
999 static void
1000 avma1pp_disable(device_t dev)
1001 {
1002         struct avma1pp_softc *asc = device_get_softc(dev);
1003
1004         bus_space_write_1(asc->avma1pp_btag, asc->avma1pp_bhandle, STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
1005 }
1006
1007 static void
1008 avma1pp_intr(void *xsc)
1009 {
1010 #define ISICINTR(sc)    isicintr(sc)
1011         u_char stat;
1012         struct avma1pp_softc *asc;
1013         struct l1_softc *sc;
1014
1015         asc = xsc;
1016         sc = asc->avma1pp_isc;
1017
1018         stat = bus_space_read_1(asc->avma1pp_btag, asc->avma1pp_bhandle, STAT0_OFFSET);
1019         DBGL1(L1_H_IRQ, "avma1pp_intr", ("stat %x\n", stat));
1020         /* was there an interrupt from this card ? */
1021         if ((stat & ASL_IRQ_Pending) == ASL_IRQ_Pending)
1022                 return; /* no */
1023         /* interrupts are low active */
1024         if (!(stat & ASL_IRQ_TIMER))
1025           DBGL1(L1_H_IRQ, "avma1pp_intr", ("timer interrupt ???\n"));
1026         if (!(stat & ASL_IRQ_HSCX))
1027         {
1028           DBGL1(L1_H_IRQ, "avma1pp_intr", ("HSCX\n"));
1029                 avma1pp_hscx_int_handler(sc);
1030         }
1031         if (!(stat & ASL_IRQ_ISAC))
1032         {
1033           DBGL1(L1_H_IRQ, "avma1pp_intr", ("ISAC\n"));
1034                 ISICINTR(sc);
1035         }
1036 }
1037
1038 static void
1039 avma1pp_hscx_init(struct l1_softc *sc, int h_chan, int activate)
1040 {
1041         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1042         u_int param = 0;
1043
1044         DBGL1(L1_BCHAN, "avma1pp_hscx_init", ("unit=%d, channel=%d, %s\n",
1045                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate"));
1046
1047         if (activate == 0)
1048         {
1049                 /* only deactivate if both channels are idle */
1050                 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
1051                         sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
1052                 {
1053                         return;
1054                 }
1055                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1056                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1057                 AVMA1PPSETCMDLONG(param);
1058                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1059                 return;
1060         }
1061         if(chan->bprot == BPROT_RHDLC)
1062         {
1063                   DBGL1(L1_BCHAN, "avma1pp_hscx_init", ("BPROT_RHDLC\n"));
1064
1065                 /* HDLC Frames, transparent mode 0 */
1066                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1067                 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
1068                 AVMA1PPSETCMDLONG(param);
1069                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1070                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1071                 AVMA1PPSETCMDLONG(param);
1072                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1073                 sc->avma1pp_cmd = 0;
1074         }
1075         else
1076         {
1077                   DBGL1(L1_BCHAN, "avma1pp_hscx_init", ("BPROT_NONE??\n"));
1078
1079                 /* Raw Telephony, extended transparent mode 1 */
1080                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1081                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1082                 AVMA1PPSETCMDLONG(param);
1083                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1084                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1085                 AVMA1PPSETCMDLONG(param);
1086                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1087                 sc->avma1pp_cmd = 0;
1088         }
1089 }
1090
1091 static void
1092 avma1pp_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1093 {
1094 #ifdef __FreeBSD__
1095         struct l1_softc *sc = &l1_sc[unit];
1096 #else
1097         struct l1_softc *sc = isic_find_sc(unit);
1098 #endif
1099         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1100
1101         int s = SPLI4B();
1102         
1103         if(activate == 0)
1104         {
1105                 /* deactivation */
1106                 chan->state = HSCX_IDLE;
1107                 avma1pp_hscx_init(sc, h_chan, activate);
1108         }
1109                 
1110         DBGL1(L1_BCHAN, "avma1pp_bchannel_setup", ("unit=%d, channel=%d, %s\n",
1111                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate"));
1112
1113         /* general part */
1114
1115         chan->unit = sc->sc_unit;       /* unit number */
1116         chan->channel = h_chan;         /* B channel */
1117         chan->bprot = bprot;            /* B channel protocol */
1118         chan->state = HSCX_IDLE;        /* B channel state */
1119
1120         /* receiver part */
1121
1122         i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1123
1124         chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1125
1126         chan->rxcount = 0;              /* reset rx counter */
1127         
1128         i4b_Bfreembuf(chan->in_mbuf);   /* clean rx mbuf */
1129
1130         chan->in_mbuf = NULL;           /* reset mbuf ptr */
1131         chan->in_cbptr = NULL;          /* reset mbuf curr ptr */
1132         chan->in_len = 0;               /* reset mbuf data len */
1133         
1134         /* transmitter part */
1135
1136         i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1137
1138         chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1139         
1140         chan->txcount = 0;              /* reset tx counter */
1141         
1142         i4b_Bfreembuf(chan->out_mbuf_head);     /* clean tx mbuf */
1143
1144         chan->out_mbuf_head = NULL;     /* reset head mbuf ptr */
1145         chan->out_mbuf_cur = NULL;      /* reset current mbuf ptr */    
1146         chan->out_mbuf_cur_ptr = NULL;  /* reset current mbuf data ptr */
1147         chan->out_mbuf_cur_len = 0;     /* reset current mbuf data cnt */
1148         
1149         if(activate != 0)
1150         {
1151                 /* activation */
1152                 avma1pp_hscx_init(sc, h_chan, activate);
1153                 chan->state |= HSCX_AVMA1PP_ACTIVE;
1154         }
1155
1156         splx(s);
1157 }
1158
1159 static void
1160 avma1pp_bchannel_start(int unit, int h_chan)
1161 {
1162 #ifdef __FreeBSD__
1163         struct l1_softc *sc = &l1_sc[unit];
1164 #else
1165         struct l1_softc *sc = isic_find_sc(unit);
1166 #endif
1167         register l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1168         int s;
1169         int activity = -1;
1170
1171         s = SPLI4B();                           /* enter critical section */
1172         if(chan->state & HSCX_TX_ACTIVE)        /* already running ? */
1173         {
1174                 splx(s);
1175                 return;                         /* yes, leave */
1176         }
1177
1178         /* get next mbuf from queue */
1179         
1180         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1181         
1182         if(chan->out_mbuf_head == NULL)         /* queue empty ? */
1183         {
1184                 splx(s);                        /* leave critical section */
1185                 return;                         /* yes, exit */
1186         }
1187
1188         /* init current mbuf values */
1189         
1190         chan->out_mbuf_cur = chan->out_mbuf_head;
1191         chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1192         chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;    
1193         
1194         /* activity indicator for timeout handling */
1195
1196         if(chan->bprot == BPROT_NONE)
1197         {
1198                 if(!(isic_hscx_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1199                         activity = ACT_TX;
1200         }
1201         else
1202         {
1203                 activity = ACT_TX;
1204         }
1205
1206         chan->state |= HSCX_TX_ACTIVE;          /* we start transmitting */
1207         
1208         if(sc->sc_trace & TRACE_B_TX)   /* if trace, send mbuf to trace dev */
1209         {
1210                 i4b_trace_hdr_t hdr;
1211                 hdr.unit = unit;
1212                 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1213                 hdr.dir = FROM_TE;
1214                 hdr.count = ++sc->sc_trace_bcount;
1215                 MICROTIME(hdr.time);
1216                 MPH_Trace_Ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1217         }                       
1218
1219         isic_hscx_fifo(chan, sc);
1220
1221         /* call timeout handling routine */
1222         
1223         if(activity == ACT_RX || activity == ACT_TX)
1224                 (*chan->drvr_linktab->bch_activity)(chan->drvr_linktab->unit, activity);
1225
1226         splx(s);        
1227 }
1228
1229 /*---------------------------------------------------------------------------*
1230  *      return the address of isic drivers linktab      
1231  *---------------------------------------------------------------------------*/
1232 static isdn_link_t *
1233 avma1pp_ret_linktab(int unit, int channel)
1234 {
1235 #ifdef __FreeBSD__
1236         struct l1_softc *sc = &l1_sc[unit];
1237 #else
1238         struct l1_softc *sc = isic_find_sc(unit);
1239 #endif
1240         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1241
1242         return(&chan->isdn_linktab);
1243 }
1244  
1245 /*---------------------------------------------------------------------------*
1246  *      set the driver linktab in the b channel softc
1247  *---------------------------------------------------------------------------*/
1248 static void
1249 avma1pp_set_linktab(int unit, int channel, drvr_link_t *dlt)
1250 {
1251 #ifdef __FreeBSD__
1252         struct l1_softc *sc = &l1_sc[unit];
1253 #else
1254         struct l1_softc *sc = isic_find_sc(unit);
1255 #endif
1256         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1257
1258         chan->drvr_linktab = dlt;
1259 }
1260
1261
1262 /*---------------------------------------------------------------------------*
1263  *      initialize our local linktab
1264  *---------------------------------------------------------------------------*/
1265 static void
1266 avma1pp_init_linktab(struct l1_softc *sc)
1267 {
1268         l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1269         isdn_link_t *lt = &chan->isdn_linktab;
1270
1271         /* make sure the hardware driver is known to layer 4 */
1272         /* avoid overwriting if already set */
1273         if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
1274         {
1275                 ctrl_types[CTRL_PASSIVE].set_linktab = avma1pp_set_linktab;
1276                 ctrl_types[CTRL_PASSIVE].get_linktab = avma1pp_ret_linktab;
1277         }
1278
1279         /* local setup */
1280         lt->unit = sc->sc_unit;
1281         lt->channel = HSCX_CH_A;
1282         lt->bch_config = avma1pp_bchannel_setup;
1283         lt->bch_tx_start = avma1pp_bchannel_start;
1284         lt->bch_stat = avma1pp_bchannel_stat;
1285         lt->tx_queue = &chan->tx_queue;
1286
1287         /* used by non-HDLC data transfers, i.e. telephony drivers */
1288         lt->rx_queue = &chan->rx_queue;
1289
1290         /* used by HDLC data transfers, i.e. ipr and isp drivers */     
1291         lt->rx_mbuf = &chan->in_mbuf;   
1292                                                 
1293         chan = &sc->sc_chan[HSCX_CH_B];
1294         lt = &chan->isdn_linktab;
1295
1296         lt->unit = sc->sc_unit;
1297         lt->channel = HSCX_CH_B;
1298         lt->bch_config = avma1pp_bchannel_setup;
1299         lt->bch_tx_start = avma1pp_bchannel_start;
1300         lt->bch_stat = avma1pp_bchannel_stat;
1301         lt->tx_queue = &chan->tx_queue;
1302
1303         /* used by non-HDLC data transfers, i.e. telephony drivers */
1304         lt->rx_queue = &chan->rx_queue;
1305
1306         /* used by HDLC data transfers, i.e. ipr and isp drivers */     
1307         lt->rx_mbuf = &chan->in_mbuf;   
1308 }
1309
1310 /*
1311  * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1312  */
1313 static void
1314 avma1pp_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
1315 {
1316 #ifdef __FreeBSD__
1317         struct l1_softc *sc = &l1_sc[unit];
1318 #else
1319         struct l1_softc *sc = isic_find_sc(unit);
1320 #endif
1321         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1322         int s;
1323
1324         s = SPLI4B();
1325         
1326         bsp->outbytes = chan->txcount;
1327         bsp->inbytes = chan->rxcount;
1328
1329         chan->txcount = 0;
1330         chan->rxcount = 0;
1331
1332         splx(s);
1333 }
1334
1335 /*---------------------------------------------------------------------------*
1336  *      fill HSCX fifo with data from the current mbuf
1337  *      Put this here until it can go into i4b_hscx.c
1338  *---------------------------------------------------------------------------*/
1339 int
1340 isic_hscx_fifo(l1_bchan_state_t *chan, struct l1_softc *sc)
1341 {
1342         int len;
1343         int nextlen;
1344         int i;
1345         int cmd = 0;
1346         /* using a scratch buffer simplifies writing to the FIFO */
1347         u_char scrbuf[HSCX_FIFO_LEN];
1348
1349         len = 0;
1350
1351         /*
1352          * fill the HSCX tx fifo with data from the current mbuf. if
1353          * current mbuf holds less data than HSCX fifo length, try to
1354          * get the next mbuf from (a possible) mbuf chain. if there is
1355          * not enough data in a single mbuf or in a chain, then this
1356          * is the last mbuf and we tell the HSCX that it has to send
1357          * CRC and closing flag
1358          */
1359          
1360         while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1361         {
1362                 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1363
1364 #ifdef NOTDEF
1365                 printf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1366                         chan->out_mbuf_head,
1367                         chan->out_mbuf_cur,                     
1368                         chan->out_mbuf_cur_ptr,
1369                         chan->out_mbuf_cur_len,
1370                         len,
1371                         nextlen);
1372 #endif
1373
1374                 cmd |= HSCX_CMDR_XTF;
1375                 /* collect the data in the scratch buffer */
1376                 for (i = 0; i < nextlen; i++)
1377                         scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1378
1379                 len += nextlen;
1380                 chan->txcount += nextlen;
1381         
1382                 chan->out_mbuf_cur_ptr += nextlen;
1383                 chan->out_mbuf_cur_len -= nextlen;
1384                         
1385                 if(chan->out_mbuf_cur_len == 0) 
1386                 {
1387                         if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1388                         {
1389                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1390                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1391         
1392                                 if(sc->sc_trace & TRACE_B_TX)
1393                                 {
1394                                         i4b_trace_hdr_t hdr;
1395                                         hdr.unit = sc->sc_unit;
1396                                         hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1397                                         hdr.dir = FROM_TE;
1398                                         hdr.count = ++sc->sc_trace_bcount;
1399                                         MICROTIME(hdr.time);
1400                                         MPH_Trace_Ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1401                                 }
1402                         }
1403                         else
1404                         {
1405                                 if (chan->bprot != BPROT_NONE)
1406                                         cmd |= HSCX_CMDR_XME;
1407                                 i4b_Bfreembuf(chan->out_mbuf_head);
1408                                 chan->out_mbuf_head = NULL;
1409                         }
1410                 }
1411         }
1412         /* write what we have from the scratch buf to the HSCX fifo */
1413         if (len != 0)
1414                 HSCX_WRFIFO(chan->channel, scrbuf, len);
1415         return(cmd);
1416 }
1417
1418 #endif /* NISIC > 0 && defined(AVM_A1_PCI) */