sys/i4b/layer1/i4b_avm_fritz_pnp.c

   1 /*
   2  *   Copyright (c) 1999 Udo Schweigert. All rights reserved.
   3  *
   4  *   Redistribution and use in source and binary forms, with or without
   5  *   modification, are permitted provided that the following conditions
   6  *   are met:
   7  *
   8  *   1. Redistributions of source code must retain the above copyright
   9  *      notice, this list of conditions and the following disclaimer.
  10  *   2. Redistributions in binary form must reproduce the above copyright
  11  *      notice, this list of conditions and the following disclaimer in the
  12  *      documentation and/or other materials provided with the distribution.
  13  *   3. Neither the name of the author nor the names of any co-contributors
  14  *      may be used to endorse or promote products derived from this software
  15  *      without specific prior written permission.
  16  *   4. Altered versions must be plainly marked as such, and must not be
  17  *      misrepresented as being the original software and/or documentation.
  18  *
  19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  *   SUCH DAMAGE.
  30  *
  31  *---------------------------------------------------------------------------
  32  *   A lot of code was borrowed from i4b_bchan.c and i4b_hscx.c
  33  *   Based on AVM Fritz!PCI driver by Gary Jennejohn
  34  *---------------------------------------------------------------------------
  35  *   In case of trouble please contact Udo Schweigert <ust@cert.siemens.de>
  36  *---------------------------------------------------------------------------
  37  *
  38  *      Fritz!Card PnP specific routines for isic driver
  39  *      ------------------------------------------------
  40  *
  41  * $FreeBSD$
  42  *
  43  *      last edit-date: [Thu 10 Jun 08:50:28 CEST 1999]
  44  *
  45  *---------------------------------------------------------------------------*/
  46
  47 #if defined(__FreeBSD__)
  48 #include "isic.h"
  49 #include "opt_i4b.h"
  50
  51 #if NISIC > 0 && defined(AVM_PNP)
  52
  53 #include <sys/param.h>
  54 #if defined(__FreeBSD__) && __FreeBSD__ >= 3
  55 #include <sys/ioccom.h>
  56 #else
  57 #include <sys/ioctl.h>
  58 #endif
  59 #include <sys/kernel.h>
  60 #include <sys/systm.h>
  61 #include <sys/mbuf.h>
  62
  63 #include <machine/clock.h>
  64 #include <i386/isa/isa_device.h>
  65
  66 #include <sys/socket.h>
  67 #include <net/if.h>
  68
  69 #include <machine/i4b_debug.h>
  70 #include <machine/i4b_ioctl.h>
  71
  72 #include <i4b/include/i4b_global.h>
  73 #include <i4b/include/i4b_l1l2.h>
  74 #include <i4b/include/i4b_mbuf.h>
  75
  76 #include <i4b/layer1/i4b_l1.h>
  77 #include <i4b/layer1/i4b_isac.h>
  78 #include <i4b/layer1/i4b_hscx.h>
  79
  80 static void hscx_write_reg(int, u_int, struct isic_softc *, int);
  81 static void hscx_write_reg_val(int, u_int, u_char, struct isic_softc *);
  82 static u_char hscx_read_reg(int, u_int, struct isic_softc *);
  83 static void hscx_read_fifo(int, void *, size_t, struct isic_softc *);
  84 static void hscx_write_fifo(int, const void *, size_t, struct isic_softc *);
  85 static void avm_pnp_hscx_int_handler(struct isic_softc *);
  86 static void avm_pnp_hscx_intr(int, int, int, struct isic_softc *);
  87 static void avm_pnp_init_linktab(struct isic_softc *);
  88 static void avm_pnp_bchannel_setup(int, int, int, int);
  89 static void avm_pnp_bchannel_start(int, int);
  90 static void avm_pnp_hscx_init(struct isic_softc *, int, int);
  91 static void avm_pnp_bchannel_stat(int, int, bchan_statistics_t *);
  92 static void avm_pnp_set_linktab(int, int, drvr_link_t *);
  93 static void avm_pnp_intr(int);
  94 static isdn_link_t * avm_pnp_ret_linktab(int, int);
  95 extern void isicintr_sc(struct isic_softc *);
  96
  97 /*---------------------------------------------------------------------------*
  98  *      AVM PnP Fritz!Card special registers
  99  *---------------------------------------------------------------------------*/
 100
 101 /*
 102  *      register offsets from i/o base
 103  */
 104 #define STAT0_OFFSET            0x02
 105 #define STAT1_OFFSET            0x03
 106 #define ADDR_REG_OFFSET         0x04
 107
 108 /* these 2 are used to select an ISAC register set */
 109 #define ISAC_LO_REG_OFFSET      0x04
 110 #define ISAC_HI_REG_OFFSET      0x06
 111
 112 /* offset higher than this goes to the HI register set */
 113 #define MAX_LO_REG_OFFSET       0x2f
 114
 115 /* mask for the offset */
 116 #define ISAC_REGSET_MASK        0x0f
 117
 118 /* the offset from the base to the ISAC registers */
 119 #define ISAC_REG_OFFSET         0x10
 120
 121 /* the offset from the base to the ISAC FIFO */
 122 #define ISAC_FIFO               0x02
 123
 124 /* not really the HSCX, but sort of */
 125 #define HSCX_FIFO               0x00
 126 #define HSCX_STAT               0x04
 127
 128 /*
 129  *      AVM PnP Status Latch 0 read only bits
 130  */
 131 #define ASL_IRQ_ISAC            0x01    /* ISAC  interrupt, active low */
 132 #define ASL_IRQ_HSCX            0x02    /* HSX   interrupt, active low */
 133 #define ASL_IRQ_TIMER           0x04    /* Timer interrupt, active low */
 134 #define ASL_IRQ_BCHAN           ASL_IRQ_HSCX
 135 /* actually active LOW */
 136 #define ASL_IRQ_Pending         0x07
 137
 138 /*
 139  *      AVM Status Latch 0 write only bits
 140  */
 141 #define ASL_RESET_ALL           0x01  /* reset siemens IC's, active 1 */
 142 #define ASL_TIMERDISABLE        0x02  /* active high */
 143 #define ASL_TIMERRESET          0x04  /* active high */
 144 #define ASL_ENABLE_INT          0x08  /* active high */
 145 #define ASL_TESTBIT             0x10  /* active high */
 146
 147 /*
 148  *      AVM Status Latch 1 write only bits
 149  */
 150 #define ASL1_INTSEL              0x0f  /* active high */
 151 #define ASL1_ENABLE_IOM          0x80  /* active high */
 152
 153 /*
 154  * "HSCX" mode bits
 155  */
 156 #define  HSCX_MODE_ITF_FLG      0x01
 157 #define  HSCX_MODE_TRANS        0x02
 158 #define  HSCX_MODE_CCR_7        0x04
 159 #define  HSCX_MODE_CCR_16       0x08
 160 #define  HSCX_MODE_TESTLOOP     0x80
 161
 162 /*
 163  * "HSCX" status bits
 164  */
 165 #define  HSCX_STAT_RME          0x01
 166 #define  HSCX_STAT_RDO          0x10
 167 #define  HSCX_STAT_CRCVFRRAB    0x0E
 168 #define  HSCX_STAT_CRCVFR       0x06
 169 #define  HSCX_STAT_RML_MASK     0x3f00
 170
 171 /*
 172  * "HSCX" interrupt bits
 173  */
 174 #define  HSCX_INT_XPR           0x80
 175 #define  HSCX_INT_XDU           0x40
 176 #define  HSCX_INT_RPR           0x20
 177 #define  HSCX_INT_MASK          0xE0
 178
 179 /*
 180  * "HSCX" command bits
 181  */
 182 #define  HSCX_CMD_XRS           0x80
 183 #define  HSCX_CMD_XME           0x01
 184 #define  HSCX_CMD_RRS           0x20
 185 #define  HSCX_CMD_XML_MASK      0x3f00
 186
 187 /* "fake" addresses for the non-existent HSCX */
 188 /* note: the unit number is in the lower byte for both the ISAC and "HSCX" */
 189 #define HSCX0FAKE       0xfa000 /* read: fake0 */
 190 #define HSCX1FAKE       0xfa100 /* read: fake1 */
 191 #define IS_HSCX_MASK    0xfff00
 192
 193 /*
 194  * to prevent deactivating the "HSCX" when both channels are active we
 195  * define an HSCX_ACTIVE flag which is or'd into the channel's state
 196  * flag in avm_pnp_bchannel_setup upon active and cleared upon deactivation.
 197  * It is set high to allow room for new flags.
 198  */
 199 #define HSCX_AVMPNP_ACTIVE      0x1000
 200
 201 /*---------------------------------------------------------------------------*
 202  *      AVM read fifo routines
 203  *---------------------------------------------------------------------------*/
 204
 205 static void
 206 avm_pnp_read_fifo(void *buf, const void *base, size_t len)
 207 {
 208         int unit;
 209         struct isic_softc *sc;
 210
 211         unit = (int)base & 0xff;
 212         sc = &isic_sc[unit];
 213
 214         /* check whether the target is an HSCX */
 215         if (((int)base & IS_HSCX_MASK) == HSCX0FAKE)
 216         {
 217                 hscx_read_fifo(0, buf, len, sc);
 218                 return;
 219         }
 220         if (((int)base & IS_HSCX_MASK)  == HSCX1FAKE)
 221         {
 222                 hscx_read_fifo(1, buf, len, sc);
 223                 return;
 224         }
 225         /* tell the board to access the ISAC fifo */
 226         outb(sc->sc_port + ADDR_REG_OFFSET, ISAC_FIFO);
 227         insb(sc->sc_port + ISAC_REG_OFFSET, (u_char *)buf, len);
 228 }
 229
 230 static void
 231 hscx_read_fifo(int chan, void *buf, size_t len, struct isic_softc *sc)
 232 {
 233         u_char *ip;
 234         size_t cnt;
 235
 236         outb(sc->sc_port + ADDR_REG_OFFSET, chan);
 237         ip = (u_char *)buf;
 238         cnt = 0;
 239
 240         while (cnt < len)
 241         {
 242                 *ip++ = inb(sc->sc_port + ISAC_REG_OFFSET);
 243                 cnt++;
 244         }
 245 }
 246
 247 /*---------------------------------------------------------------------------*
 248  *      AVM write fifo routines
 249  *---------------------------------------------------------------------------*/
 250 static void
 251 avm_pnp_write_fifo(void *base, const void *buf, size_t len)
 252 {
 253         int unit;
 254         struct isic_softc *sc;
 255
 256         unit = (int)base & 0xff;
 257         sc = &isic_sc[unit];
 258
 259         /* check whether the target is an HSCX */
 260         if (((int)base & IS_HSCX_MASK) == HSCX0FAKE)
 261         {
 262                 hscx_write_fifo(0, buf, len, sc);
 263                 return;
 264         }
 265         if (((int)base & IS_HSCX_MASK)  == HSCX1FAKE)
 266         {
 267                 hscx_write_fifo(1, buf, len, sc);
 268                 return;
 269         }
 270         /* tell the board to use the ISAC fifo */
 271         outb(sc->sc_port + ADDR_REG_OFFSET, ISAC_FIFO);
 272         outsb(sc->sc_port + ISAC_REG_OFFSET, (const u_char *)buf, len);
 273 }
 274
 275 static void
 276 hscx_write_fifo(int chan, const void *buf, size_t len, struct isic_softc *sc)
 277 {
 278         register const u_char *ip;
 279         register size_t cnt;
 280         isic_Bchan_t *Bchan = &sc->sc_chan[chan];
 281
 282         sc->avma1pp_cmd &= ~HSCX_CMD_XME;
 283         sc->avma1pp_txl = 0;
 284
 285         if (Bchan->out_mbuf_cur == NULL && Bchan->bprot != BPROT_NONE)
 286                 sc->avma1pp_cmd |= HSCX_CMD_XME;
 287
 288         if (len != sc->sc_bfifolen)
 289                 sc->avma1pp_txl = len;
 290
 291         hscx_write_reg(chan, HSCX_STAT, sc, 3);
 292
 293         ip = (const u_char *)buf;
 294         cnt = 0;
 295         while (cnt < len)
 296         {
 297                 outb(sc->sc_port + ISAC_REG_OFFSET, *ip++);
 298                 cnt++;
 299         }
 300 }
 301
 302 /*---------------------------------------------------------------------------*
 303  *      AVM write register routines
 304  *---------------------------------------------------------------------------*/
 305 static void
 306 avm_pnp_write_reg(u_char *base, u_int offset, u_int v)
 307 {
 308         int unit;
 309         struct isic_softc *sc;
 310         u_char reg_bank;
 311
 312         unit = (int)base & 0xff;
 313         sc = &isic_sc[unit];
 314
 315         /* check whether the target is an HSCX */
 316         if (((int)base & IS_HSCX_MASK) == HSCX0FAKE)
 317         {
 318                 hscx_write_reg_val(0, offset, v, sc);
 319                 return;
 320         }
 321         if (((int)base & IS_HSCX_MASK) == HSCX1FAKE)
 322         {
 323                 hscx_write_reg_val(1, offset, v, sc);
 324                 return;
 325         }
 326         /* must be the ISAC */
 327         reg_bank = (offset > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
 328         /* set the register bank */
 329         outb(sc->sc_port + ADDR_REG_OFFSET, reg_bank);
 330         outb(sc->sc_port + ISAC_REG_OFFSET + (offset & ISAC_REGSET_MASK), v);
 331 }
 332
 333 static void
 334 hscx_write_reg(int chan, u_int off, struct isic_softc *sc, int which)
 335 {
 336         /* HACK */
 337         if (off == H_MASK)
 338                 return;
 339         /* point at the correct channel */
 340         outb(sc->sc_port + ADDR_REG_OFFSET, chan);
 341         if (which & 4)
 342                 outb(sc->sc_port + ISAC_REG_OFFSET + off + 2, sc->avma1pp_prot);
 343         if (which & 2)
 344                 outb(sc->sc_port + ISAC_REG_OFFSET + off + 1, sc->avma1pp_txl);
 345         if (which & 1)
 346                 outb(sc->sc_port + ISAC_REG_OFFSET + off, sc->avma1pp_cmd);
 347 }
 348
 349 static void
 350 hscx_write_reg_val(int chan, u_int off, u_char val, struct isic_softc *sc)
 351 {
 352         /* HACK */
 353         if (off == H_MASK)
 354                 return;
 355         /* point at the correct channel */
 356         outb(sc->sc_port + ADDR_REG_OFFSET, chan);
 357         outb(sc->sc_port + ISAC_REG_OFFSET + off, val);
 358 }
 359
 360 /*---------------------------------------------------------------------------*
 361  *      AVM read register routines
 362  *---------------------------------------------------------------------------*/
 363
 364 static u_char
 365 avm_pnp_read_reg(u_char *base, u_int offset)
 366 {
 367         int unit;
 368         struct isic_softc *sc;
 369         u_char reg_bank;
 370
 371         unit = (int)base & 0xff;
 372         sc = &isic_sc[unit];
 373
 374         /* check whether the target is an HSCX */
 375         if (((int)base & IS_HSCX_MASK) == HSCX0FAKE)
 376                 return(hscx_read_reg(0, offset, sc));
 377         if (((int)base & IS_HSCX_MASK)  == HSCX1FAKE)
 378                 return(hscx_read_reg(1, offset, sc));
 379         /* must be the ISAC */
 380         reg_bank = (offset > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
 381         /* set the register bank */
 382         outb(sc->sc_port + ADDR_REG_OFFSET, reg_bank);
 383         return(inb(sc->sc_port + ISAC_REG_OFFSET +
 384                 (offset & ISAC_REGSET_MASK)));
 385 }
 386
 387 static u_char
 388 hscx_read_reg(int chan, u_int off, struct isic_softc *sc)
 389 {
 390         /* HACK */
 391         if (off == H_ISTA)
 392                 return(0);
 393         /* point at the correct channel */
 394         outb(sc->sc_port + ADDR_REG_OFFSET, chan);
 395         return(inb(sc->sc_port + ISAC_REG_OFFSET + off));
 396 }
 397
 398 /*---------------------------------------------------------------------------*
 399  *      isic_probe_avm_pnp - probe Fritz!Card PnP
 400  *---------------------------------------------------------------------------*/
 401
 402 int
 403 isic_probe_avm_pnp(struct isa_device *dev, unsigned int iobase2)
 404 {
 405         struct isic_softc *sc = &isic_sc[dev->id_unit];
 406
 407         /* check max unit range */
 408
 409         if(dev->id_unit >= ISIC_MAXUNIT)
 410         {
 411                 printf("isic%d: Error, unit %d >= ISIC_MAXUNIT for AVM Fritz! PnP\n",
 412                                 dev->id_unit, dev->id_unit);
 413                 return(0);
 414         }
 415         sc->sc_unit = dev->id_unit;
 416
 417         /* check IRQ validity */
 418
 419         switch(ffs(dev->id_irq) - 1)
 420         {
 421                 case 3:
 422                 case 4:
 423                 case 5:
 424                 case 7:
 425                 case 10:
 426                 case 11:
 427                 case 12:
 428                 case 15:
 429                         break;
 430
 431                 default:
 432                         printf("isic%d: Error, invalid IRQ [%d] specified for AVM Fritz! PnP!\n",
 433                                 dev->id_unit, ffs(dev->id_irq)-1);
 434                         return(0);
 435                         break;
 436         }
 437         sc->sc_irq = dev->id_irq;
 438
 439         dev->id_intr = (inthand2_t *) avm_pnp_intr;
 440
 441         /* check if memory addr specified */
 442
 443         if(dev->id_maddr)
 444         {
 445                 printf("isic%d: Error, mem addr 0x%lx specified for AVM Fritz! PnP!\n",
 446                         dev->id_unit, (u_long)dev->id_maddr);
 447                 return(0);
 448         }
 449         dev->id_msize = 0;
 450
 451         /* check if we got an iobase */
 452
 453         if(!((dev->id_iobase >= 0x160) && (dev->id_iobase <= 0x360)))
 454         {
 455                 printf("isic%d: Error, invalid iobase 0x%x specified for AVM Fritz! PnP!\n",
 456                         dev->id_unit, dev->id_iobase);
 457                 return(0);
 458         }
 459         sc->sc_port = dev->id_iobase;
 460
 461
 462         /* setup access routines */
 463
 464         sc->clearirq = NULL;
 465         sc->readreg = avm_pnp_read_reg;
 466         sc->writereg = avm_pnp_write_reg;
 467
 468         sc->readfifo = avm_pnp_read_fifo;
 469         sc->writefifo = avm_pnp_write_fifo;
 470
 471         /* setup card type */
 472
 473         sc->sc_cardtyp = CARD_TYPEP_AVM_PNP;
 474
 475         /* setup IOM bus type */
 476
 477         sc->sc_bustyp = BUS_TYPE_IOM2;
 478
 479         sc->sc_ipac = 0;
 480         sc->sc_bfifolen = HSCX_FIFO_LEN;
 481
 482         /* the ISAC lives at offset 0x10, but we can't use that. */
 483         /* instead, put the unit number into the lower byte - HACK */
 484         ISAC_BASE = (caddr_t)((int)(dev->id_iobase & ~0xff) + dev->id_unit);
 485
 486         outb(sc->sc_port + STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
 487         ISAC_WRITE(I_MASK, 0x0);
 488         outb(sc->sc_port + STAT0_OFFSET, ASL_TIMERRESET|ASL_ENABLE_INT|ASL_TIMERDISABLE);
 489         ISAC_WRITE(I_MASK, 0x41);
 490         return (1);
 491 }
 492
 493 /*---------------------------------------------------------------------------*
 494  *      isic_attach_avm_pnp - attach Fritz!Card PnP
 495  *---------------------------------------------------------------------------*/
 496 int
 497 isic_attach_avm_pnp(struct isa_device *dev, unsigned int iobase2)
 498 {
 499         struct isic_softc *sc;
 500         u_int v;
 501         int unit;
 502
 503         unit = dev->id_unit;
 504         sc = &isic_sc[unit];
 505
 506         /* this thing doesn't have an HSCX, so fake the base addresses */
 507         /* put the unit number into the lower byte - HACK */
 508         HSCX_A_BASE = (caddr_t)(HSCX0FAKE + unit);
 509         HSCX_B_BASE = (caddr_t)(HSCX1FAKE + unit);
 510
 511
 512         /* reset the card */
 513
 514         /* the Linux driver does this to clear any pending ISAC interrupts */
 515         v = 0;
 516         v = ISAC_READ(I_STAR);
 517         v = ISAC_READ(I_MODE);
 518         v = ISAC_READ(I_ADF2);
 519         v = ISAC_READ(I_ISTA);
 520         if (v & ISAC_ISTA_EXI)
 521         {
 522                  v = ISAC_READ(I_EXIR);
 523         }
 524         v = ISAC_READ(I_CIRR);
 525         ISAC_WRITE(I_MASK, 0xff);
 526
 527         /* the Linux driver does this to clear any pending HSCX interrupts */
 528         v = hscx_read_reg(0, HSCX_STAT, sc);
 529         v = hscx_read_reg(0, HSCX_STAT+1, sc);
 530         v = hscx_read_reg(0, HSCX_STAT+2, sc);
 531         v = hscx_read_reg(0, HSCX_STAT+3, sc);
 532         v = hscx_read_reg(1, HSCX_STAT, sc);
 533         v = hscx_read_reg(1, HSCX_STAT+1, sc);
 534         v = hscx_read_reg(1, HSCX_STAT+2, sc);
 535         v = hscx_read_reg(1, HSCX_STAT+3, sc);
 536
 537         outb(sc->sc_port + STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
 538         DELAY(SEC_DELAY/100); /* 10 ms */
 539         outb(sc->sc_port + STAT0_OFFSET, ASL_TIMERRESET|ASL_ENABLE_INT|ASL_TIMERDISABLE);
 540         DELAY(SEC_DELAY/100); /* 10 ms */
 541         outb(sc->sc_port + STAT1_OFFSET, ASL1_ENABLE_IOM+(ffs(sc->sc_irq)-1));
 542         DELAY(SEC_DELAY/100); /* 10 ms */
 543
 544         printf("isic%d: ISAC %s (IOM-%c)\n", unit,
 545                 "2085 Version A1/A2 or 2086/2186 Version 1.1",
 546                 sc->sc_bustyp == BUS_TYPE_IOM1 ? '1' : '2');
 547
 548         /* init the ISAC */
 549         isic_isac_init(sc);
 550
 551         /* init the "HSCX" */
 552         avm_pnp_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
 553
 554         avm_pnp_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
 555
 556         /* can't use the normal B-Channel stuff */
 557         avm_pnp_init_linktab(sc);
 558
 559         /* set trace level */
 560
 561         sc->sc_trace = TRACE_OFF;
 562
 563         sc->sc_state = ISAC_IDLE;
 564
 565         sc->sc_ibuf = NULL;
 566         sc->sc_ib = NULL;
 567         sc->sc_ilen = 0;
 568
 569         sc->sc_obuf = NULL;
 570         sc->sc_op = NULL;
 571         sc->sc_ol = 0;
 572         sc->sc_freeflag = 0;
 573
 574         sc->sc_obuf2 = NULL;
 575         sc->sc_freeflag2 = 0;
 576
 577 #if defined(__FreeBSD__) && __FreeBSD__ >=3
 578         callout_handle_init(&sc->sc_T3_callout);
 579         callout_handle_init(&sc->sc_T4_callout);
 580 #endif
 581
 582         /* init higher protocol layers */
 583
 584         MPH_Status_Ind(sc->sc_unit, STI_ATTACH, sc->sc_cardtyp);
 585
 586         return(0);
 587 }
 588
 589 /*
 590  * this is the real interrupt routine
 591  */
 592 static void
 593 avm_pnp_hscx_intr(int h_chan, int stat, int cnt, struct isic_softc *sc)
 594 {
 595         register isic_Bchan_t *chan = &sc->sc_chan[h_chan];
 596         int activity = -1;
 597
 598         DBGL1(L1_H_IRQ, "avm_pnp_hscx_intr", ("%#x\n", stat));
 599
 600         if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
 601         {
 602                 chan->stat_XDU++;
 603                 DBGL1(L1_H_XFRERR, "avm_pnp_hscx_intr", ("xmit data underrun\n"));
 604                 /* abort the transmission */
 605                 sc->avma1pp_txl = 0;
 606                 sc->avma1pp_cmd |= HSCX_CMD_XRS;
 607                 hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 608                 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
 609                 hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 610
 611                 if (chan->out_mbuf_head != NULL)  /* don't continue to transmit this buffer */
 612                 {
 613                         i4b_Bfreembuf(chan->out_mbuf_head);
 614                         chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
 615                 }
 616         }
 617
 618         /*
 619          * The following is based on examination of the Linux driver.
 620          *
 621          * The logic here is different than with a "real" HSCX; all kinds
 622          * of information (interrupt/status bits) are in stat.
 623          *              HSCX_INT_RPR indicates a receive interrupt
 624          *                      HSCX_STAT_RDO indicates an overrun condition, abort -
 625          *                      otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
 626          *                      HSCX_STAT_RME indicates end-of-frame and apparently any
 627          *                      CRC/framing errors are only reported in this state.
 628          *                              if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
 629          *                                      CRC/framing error
 630          */
 631
 632         if(stat & HSCX_INT_RPR)
 633         {
 634                 register int fifo_data_len;
 635                 int error = 0;
 636                 /* always have to read the FIFO, so use a scratch buffer */
 637                 u_char scrbuf[HSCX_FIFO_LEN];
 638
 639                 if(stat & HSCX_STAT_RDO)
 640                 {
 641                         chan->stat_RDO++;
 642                         DBGL1(L1_H_XFRERR, "avm_pnp_hscx_intr", ("receive data overflow\n"));
 643                         error++;
 644                 }
 645
 646                 fifo_data_len = cnt;
 647
 648                 if(fifo_data_len == 0)
 649                         fifo_data_len = sc->sc_bfifolen;
 650
 651                 /* ALWAYS read data from HSCX fifo */
 652
 653                 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
 654                 chan->rxcount += fifo_data_len;
 655
 656                 /* all error conditions checked, now decide and take action */
 657
 658                 if(error == 0)
 659                 {
 660                         if(chan->in_mbuf == NULL)
 661                         {
 662                                 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 663                                         panic("L1 avm_pnp_hscx_intr: RME, cannot allocate mbuf!\n");
 664                                 chan->in_cbptr = chan->in_mbuf->m_data;
 665                                 chan->in_len = 0;
 666                         }
 667
 668                         if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
 669                         {
 670                                 /* OK to copy the data */
 671                                 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 672                                 chan->in_cbptr += fifo_data_len;
 673                                 chan->in_len += fifo_data_len;
 674
 675                                 /* setup mbuf data length */
 676
 677                                 chan->in_mbuf->m_len = chan->in_len;
 678                                 chan->in_mbuf->m_pkthdr.len = chan->in_len;
 679
 680
 681                                 if(sc->sc_trace & TRACE_B_RX)
 682                                 {
 683                                         i4b_trace_hdr_t hdr;
 684                                         hdr.unit = sc->sc_unit;
 685                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 686                                         hdr.dir = FROM_NT;
 687                                         hdr.count = ++sc->sc_trace_bcount;
 688                                         MICROTIME(hdr.time);
 689                                         MPH_Trace_Ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 690                                 }
 691
 692                                 if (stat & HSCX_STAT_RME)
 693                                 {
 694                                   if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
 695                                   {
 696                                          (*chan->drvr_linktab->bch_rx_data_ready)(chan->drvr_linktab->unit);
 697                                          activity = ACT_RX;
 698
 699                                          /* mark buffer ptr as unused */
 700
 701                                          chan->in_mbuf = NULL;
 702                                          chan->in_cbptr = NULL;
 703                                          chan->in_len = 0;
 704                                   }
 705                                   else
 706                                   {
 707                                                 chan->stat_CRC++;
 708                                                 DBGL1(L1_H_XFRERR, "avm_pnp_hscx_intr", ("CRC/RAB\n"));
 709                                           if (chan->in_mbuf != NULL)
 710                                           {
 711                                                   i4b_Bfreembuf(chan->in_mbuf);
 712                                                   chan->in_mbuf = NULL;
 713                                                   chan->in_cbptr = NULL;
 714                                                   chan->in_len = 0;
 715                                           }
 716                                   }
 717                                 }
 718                         } /* END enough space in mbuf */
 719                         else
 720                         {
 721                                  if(chan->bprot == BPROT_NONE)
 722                                  {
 723                                           /* setup mbuf data length */
 724
 725                                           chan->in_mbuf->m_len = chan->in_len;
 726                                           chan->in_mbuf->m_pkthdr.len = chan->in_len;
 727
 728                                           if(sc->sc_trace & TRACE_B_RX)
 729                                           {
 730                                                         i4b_trace_hdr_t hdr;
 731                                                         hdr.unit = sc->sc_unit;
 732                                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 733                                                         hdr.dir = FROM_NT;
 734                                                         hdr.count = ++sc->sc_trace_bcount;
 735                                                         MICROTIME(hdr.time);
 736                                                         MPH_Trace_Ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 737                                                 }
 738
 739                                           /* move rx'd data to rx queue */
 740
 741                                           IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
 742
 743                                           (*chan->drvr_linktab->bch_rx_data_ready)(chan->drvr_linktab->unit);
 744
 745                                           if(!(isic_hscx_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
 746                                                  activity = ACT_RX;
 747
 748                                           /* alloc new buffer */
 749
 750                                           if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 751                                                  panic("L1 avm_pnp_hscx_intr: RPF, cannot allocate new mbuf!\n");
 752
 753                                           /* setup new data ptr */
 754
 755                                           chan->in_cbptr = chan->in_mbuf->m_data;
 756
 757                                           /* OK to copy the data */
 758                                           bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 759
 760                                           chan->in_cbptr += fifo_data_len;
 761                                           chan->in_len = fifo_data_len;
 762
 763                                           chan->rxcount += fifo_data_len;
 764                                         }
 765                                  else
 766                                         {
 767                                           DBGL1(L1_H_XFRERR, "avm_pnp_hscx_intr", ("RAWHDLC rx buffer overflow in RPF, in_len=%d\n", chan->in_len));
 768                                           chan->in_cbptr = chan->in_mbuf->m_data;
 769                                           chan->in_len = 0;
 770                                         }
 771                           }
 772                 } /* if(error == 0) */
 773                 else
 774                 {
 775                         /* land here for RDO */
 776                         if (chan->in_mbuf != NULL)
 777                         {
 778                                 i4b_Bfreembuf(chan->in_mbuf);
 779                                 chan->in_mbuf = NULL;
 780                                 chan->in_cbptr = NULL;
 781                                 chan->in_len = 0;
 782                         }
 783                         sc->avma1pp_txl = 0;
 784                         sc->avma1pp_cmd |= HSCX_CMD_RRS;
 785                         hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 786                         sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
 787                         hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 788                 }
 789         }
 790
 791
 792         /* transmit fifo empty, new data can be written to fifo */
 793
 794         if(stat & HSCX_INT_XPR)
 795         {
 796                 /*
 797                  * for a description what is going on here, please have
 798                  * a look at isic_bchannel_start() in i4b_bchan.c !
 799                  */
 800
 801                 DBGL1(L1_H_IRQ, "avm_pnp_hscx_intr", ("unit %d, chan %d - XPR, Tx Fifo Empty!\n", sc->sc_unit, h_chan));
 802
 803                 if(chan->out_mbuf_cur == NULL || chan->out_mbuf_head == NULL)   /* last frame is transmitted */
 804                 {
 805                         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
 806
 807                         if(chan->out_mbuf_head == NULL)
 808                         {
 809                                 chan->state &= ~HSCX_TX_ACTIVE;
 810                                 (*chan->drvr_linktab->bch_tx_queue_empty)(chan->drvr_linktab->unit);
 811                         }
 812                         else
 813                         {
 814                                 chan->state |= HSCX_TX_ACTIVE;
 815                                 chan->out_mbuf_cur = chan->out_mbuf_head;
 816                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
 817                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
 818
 819                                 if(sc->sc_trace & TRACE_B_TX)
 820                                 {
 821                                         i4b_trace_hdr_t hdr;
 822                                         hdr.unit = sc->sc_unit;
 823                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 824                                         hdr.dir = FROM_TE;
 825                                         hdr.count = ++sc->sc_trace_bcount;
 826                                         MICROTIME(hdr.time);
 827                                         MPH_Trace_Ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
 828                                 }
 829                                 if(chan->bprot == BPROT_NONE)
 830                                 {
 831                                         if(!(isic_hscx_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
 832                                                 activity = ACT_TX;
 833                                 }
 834                                 else
 835                                 {
 836                                         activity = ACT_TX;
 837                                 }
 838                         }
 839                 }
 840
 841                 isic_hscx_fifo(chan, sc);
 842         }
 843
 844         /* call timeout handling routine */
 845
 846         if(activity == ACT_RX || activity == ACT_TX)
 847                 (*chan->drvr_linktab->bch_activity)(chan->drvr_linktab->unit, activity);
 848 }
 849
 850 /*
 851  * this is the main routine which checks each channel and then calls
 852  * the real interrupt routine as appropriate
 853  */
 854 static void
 855 avm_pnp_hscx_int_handler(struct isic_softc *sc)
 856 {
 857         u_char stat = 0;
 858         u_char cnt = 0;
 859
 860         stat = hscx_read_reg(0, HSCX_STAT, sc);
 861         if (stat & HSCX_INT_RPR)
 862           cnt = hscx_read_reg(0, HSCX_STAT+1, sc);
 863         if (stat & HSCX_INT_MASK)
 864           avm_pnp_hscx_intr(0, stat, cnt, sc);
 865
 866         cnt = 0;
 867         stat = hscx_read_reg(1, HSCX_STAT, sc);
 868         if (stat & HSCX_INT_RPR)
 869           cnt = hscx_read_reg(1, HSCX_STAT+1, sc);
 870         if (stat & HSCX_INT_MASK)
 871           avm_pnp_hscx_intr(1, stat, cnt, sc);
 872 }
 873
 874 static void
 875 avm_pnp_hscx_init(struct isic_softc *sc, int h_chan, int activate)
 876 {
 877         isic_Bchan_t *chan = &sc->sc_chan[h_chan];
 878
 879         DBGL1(L1_BCHAN, "avm_pnp_hscx_init", ("unit=%d, channel=%d, %s\n",
 880                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate"));
 881
 882         if (activate == 0)
 883         {
 884                 /* only deactivate if both channels are idle */
 885                 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
 886                         sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
 887                 {
 888                         return;
 889                 }
 890                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
 891                 sc->avma1pp_prot = HSCX_MODE_TRANS;
 892                 hscx_write_reg(h_chan, HSCX_STAT, sc, 5);
 893                 return;
 894         }
 895         if(chan->bprot == BPROT_RHDLC)
 896         {
 897                   DBGL1(L1_BCHAN, "avm_pnp_hscx_init", ("BPROT_RHDLC\n"));
 898
 899                 /* HDLC Frames, transparent mode 0 */
 900                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
 901                 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
 902                 hscx_write_reg(h_chan, HSCX_STAT, sc, 5);
 903                 sc->avma1pp_cmd = HSCX_CMD_XRS;
 904                 hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 905                 sc->avma1pp_cmd = 0;
 906         }
 907         else
 908         {
 909                   DBGL1(L1_BCHAN, "avm_pnp_hscx_init", ("BPROT_NONE??\n"));
 910
 911                 /* Raw Telephony, extended transparent mode 1 */
 912                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
 913                 sc->avma1pp_prot = HSCX_MODE_TRANS;
 914                 hscx_write_reg(h_chan, HSCX_STAT, sc, 5);
 915                 sc->avma1pp_cmd = HSCX_CMD_XRS;
 916                 hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 917                 sc->avma1pp_cmd = 0;
 918         }
 919 }
 920
 921 static void
 922 avm_pnp_bchannel_setup(int unit, int h_chan, int bprot, int activate)
 923 {
 924         struct isic_softc *sc = &isic_sc[unit];
 925         isic_Bchan_t *chan = &sc->sc_chan[h_chan];
 926
 927         int s = SPLI4B();
 928
 929         if(activate == 0)
 930         {
 931                 /* deactivation */
 932                 chan->state &= ~HSCX_AVMPNP_ACTIVE;
 933                 avm_pnp_hscx_init(sc, h_chan, activate);
 934         }
 935
 936         DBGL1(L1_BCHAN, "avm_pnp_bchannel_setup", ("unit=%d, channel=%d, %s\n",
 937                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate"));
 938
 939         /* general part */
 940
 941         chan->unit = sc->sc_unit;       /* unit number */
 942         chan->channel = h_chan;         /* B channel */
 943         chan->bprot = bprot;            /* B channel protocol */
 944         chan->state = HSCX_IDLE;        /* B channel state */
 945
 946         /* receiver part */
 947
 948         i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
 949
 950         chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
 951
 952         chan->rxcount = 0;              /* reset rx counter */
 953
 954         i4b_Bfreembuf(chan->in_mbuf);   /* clean rx mbuf */
 955
 956         chan->in_mbuf = NULL;           /* reset mbuf ptr */
 957         chan->in_cbptr = NULL;          /* reset mbuf curr ptr */
 958         chan->in_len = 0;               /* reset mbuf data len */
 959
 960         /* transmitter part */
 961
 962         i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
 963
 964         chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
 965
 966         chan->txcount = 0;              /* reset tx counter */
 967
 968         i4b_Bfreembuf(chan->out_mbuf_head);     /* clean tx mbuf */
 969
 970         chan->out_mbuf_head = NULL;     /* reset head mbuf ptr */
 971         chan->out_mbuf_cur = NULL;      /* reset current mbuf ptr */
 972         chan->out_mbuf_cur_ptr = NULL;  /* reset current mbuf data ptr */
 973         chan->out_mbuf_cur_len = 0;     /* reset current mbuf data cnt */
 974
 975         if(activate != 0)
 976         {
 977                 /* activation */
 978                 avm_pnp_hscx_init(sc, h_chan, activate);
 979                 chan->state |= HSCX_AVMPNP_ACTIVE;
 980         }
 981
 982         splx(s);
 983 }
 984
 985 static void
 986 avm_pnp_bchannel_start(int unit, int h_chan)
 987 {
 988         struct isic_softc *sc = &isic_sc[unit];
 989         register isic_Bchan_t *chan = &sc->sc_chan[h_chan];
 990         int s;
 991         int activity = -1;
 992
 993         s = SPLI4B();                           /* enter critical section */
 994         if(chan->state & HSCX_TX_ACTIVE)        /* already running ? */
 995         {
 996                 splx(s);
 997                 return;                         /* yes, leave */
 998         }
 999
1000         /* get next mbuf from queue */
1001
1002         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1003
1004         if(chan->out_mbuf_head == NULL)         /* queue empty ? */
1005         {
1006                 splx(s);                        /* leave critical section */
1007                 return;                         /* yes, exit */
1008         }
1009
1010         /* init current mbuf values */
1011
1012         chan->out_mbuf_cur = chan->out_mbuf_head;
1013         chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1014         chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1015
1016         /* activity indicator for timeout handling */
1017
1018         if(chan->bprot == BPROT_NONE)
1019         {
1020                 if(!(isic_hscx_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1021                         activity = ACT_TX;
1022         }
1023         else
1024         {
1025                 activity = ACT_TX;
1026         }
1027
1028         chan->state |= HSCX_TX_ACTIVE;          /* we start transmitting */
1029
1030         if(sc->sc_trace & TRACE_B_TX)   /* if trace, send mbuf to trace dev */
1031         {
1032                 i4b_trace_hdr_t hdr;
1033                 hdr.unit = unit;
1034                 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1035                 hdr.dir = FROM_TE;
1036                 hdr.count = ++sc->sc_trace_bcount;
1037                 MICROTIME(hdr.time);
1038                 MPH_Trace_Ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1039         }
1040
1041         isic_hscx_fifo(chan, sc);
1042
1043         /* call timeout handling routine */
1044
1045         if(activity == ACT_RX || activity == ACT_TX)
1046                 (*chan->drvr_linktab->bch_activity)(chan->drvr_linktab->unit, activity);
1047
1048         splx(s);
1049 }
1050
1051 /*---------------------------------------------------------------------------*
1052  *      return the address of isic drivers linktab
1053  *---------------------------------------------------------------------------*/
1054 static isdn_link_t *
1055 avm_pnp_ret_linktab(int unit, int channel)
1056 {
1057         struct isic_softc *sc = &isic_sc[unit];
1058         isic_Bchan_t *chan = &sc->sc_chan[channel];
1059
1060         return(&chan->isdn_linktab);
1061 }
1062
1063 /*---------------------------------------------------------------------------*
1064  *      set the driver linktab in the b channel softc
1065  *---------------------------------------------------------------------------*/
1066 static void
1067 avm_pnp_set_linktab(int unit, int channel, drvr_link_t *dlt)
1068 {
1069         struct isic_softc *sc = &isic_sc[unit];
1070         isic_Bchan_t *chan = &sc->sc_chan[channel];
1071
1072         chan->drvr_linktab = dlt;
1073 }
1074
1075
1076 /*---------------------------------------------------------------------------*
1077  *      initialize our local linktab
1078  *---------------------------------------------------------------------------*/
1079 static void
1080 avm_pnp_init_linktab(struct isic_softc *sc)
1081 {
1082         isic_Bchan_t *chan = &sc->sc_chan[HSCX_CH_A];
1083         isdn_link_t *lt = &chan->isdn_linktab;
1084
1085         /* make sure the hardware driver is known to layer 4 */
1086         /* avoid overwriting if already set */
1087         if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
1088         {
1089                 ctrl_types[CTRL_PASSIVE].set_linktab = avm_pnp_set_linktab;
1090                 ctrl_types[CTRL_PASSIVE].get_linktab = avm_pnp_ret_linktab;
1091         }
1092
1093         /* local setup */
1094         lt->unit = sc->sc_unit;
1095         lt->channel = HSCX_CH_A;
1096         lt->bch_config = avm_pnp_bchannel_setup;
1097         lt->bch_tx_start = avm_pnp_bchannel_start;
1098         lt->bch_stat = avm_pnp_bchannel_stat;
1099         lt->tx_queue = &chan->tx_queue;
1100
1101         /* used by non-HDLC data transfers, i.e. telephony drivers */
1102         lt->rx_queue = &chan->rx_queue;
1103
1104         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1105         lt->rx_mbuf = &chan->in_mbuf;
1106
1107         chan = &sc->sc_chan[HSCX_CH_B];
1108         lt = &chan->isdn_linktab;
1109
1110         lt->unit = sc->sc_unit;
1111         lt->channel = HSCX_CH_B;
1112         lt->bch_config = avm_pnp_bchannel_setup;
1113         lt->bch_tx_start = avm_pnp_bchannel_start;
1114         lt->bch_stat = avm_pnp_bchannel_stat;
1115         lt->tx_queue = &chan->tx_queue;
1116
1117         /* used by non-HDLC data transfers, i.e. telephony drivers */
1118         lt->rx_queue = &chan->rx_queue;
1119
1120         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1121         lt->rx_mbuf = &chan->in_mbuf;
1122 }
1123
1124 /*
1125  * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1126  */
1127 static void
1128 avm_pnp_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
1129 {
1130         struct isic_softc *sc = &isic_sc[unit];
1131         isic_Bchan_t *chan = &sc->sc_chan[h_chan];
1132         int s;
1133
1134         s = SPLI4B();
1135
1136         bsp->outbytes = chan->txcount;
1137         bsp->inbytes = chan->rxcount;
1138
1139         chan->txcount = 0;
1140         chan->rxcount = 0;
1141
1142         splx(s);
1143 }
1144
1145 /*---------------------------------------------------------------------------*
1146  *      fill HSCX fifo with data from the current mbuf
1147  *      Put this here until it can go into i4b_hscx.c
1148  *---------------------------------------------------------------------------*/
1149 static int
1150 isic_hscx_fifo(isic_Bchan_t *chan, struct isic_softc *sc)
1151 {
1152         int len;
1153         int nextlen;
1154         int i;
1155         /* using a scratch buffer simplifies writing to the FIFO */
1156         u_char scrbuf[HSCX_FIFO_LEN];
1157
1158         len = 0;
1159
1160         /*
1161          * fill the HSCX tx fifo with data from the current mbuf. if
1162          * current mbuf holds less data than HSCX fifo length, try to
1163          * get the next mbuf from (a possible) mbuf chain. if there is
1164          * not enough data in a single mbuf or in a chain, then this
1165          * is the last mbuf and we tell the HSCX that it has to send
1166          * CRC and closing flag
1167          */
1168
1169         while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1170         {
1171                 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1172
1173 #ifdef NOTDEF
1174                 printf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1175                         chan->out_mbuf_head,
1176                         chan->out_mbuf_cur,
1177                         chan->out_mbuf_cur_ptr,
1178                         chan->out_mbuf_cur_len,
1179                         len,
1180                         nextlen);
1181 #endif
1182
1183                 /* collect the data in the scratch buffer */
1184                 for (i = 0; i < nextlen; i++)
1185                         scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1186
1187                 len += nextlen;
1188                 chan->txcount += nextlen;
1189
1190                 chan->out_mbuf_cur_ptr += nextlen;
1191                 chan->out_mbuf_cur_len -= nextlen;
1192
1193                 if(chan->out_mbuf_cur_len == 0)
1194                 {
1195                         if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1196                         {
1197                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1198                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1199
1200                                 if(sc->sc_trace & TRACE_B_TX)
1201                                 {
1202                                         i4b_trace_hdr_t hdr;
1203                                         hdr.unit = sc->sc_unit;
1204                                         hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1205                                         hdr.dir = FROM_TE;
1206                                         hdr.count = ++sc->sc_trace_bcount;
1207                                         MICROTIME(hdr.time);
1208                                         MPH_Trace_Ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1209                                 }
1210                         }
1211                         else
1212                         {
1213                                 i4b_Bfreembuf(chan->out_mbuf_head);
1214                                 chan->out_mbuf_head = NULL;
1215                         }
1216                 }
1217         }
1218         /* write what we have from the scratch buf to the HSCX fifo */
1219         if (len != 0)
1220                 HSCX_WRFIFO(chan->channel, scrbuf, len);
1221
1222         return(0);
1223 }
1224
1225 void
1226 avm_pnp_intr(int unit)
1227 {
1228         struct isic_softc *sc;
1229         u_char stat;
1230         register u_char isac_irq_stat;
1231         int was_isac = 0;
1232
1233         sc = &isic_sc[unit];
1234
1235         for(;;) {
1236                 stat = inb(sc->sc_port + STAT0_OFFSET);
1237
1238                 DBGL1(L1_H_IRQ, "avm_pnp_intr", ("stat %x\n", stat));
1239
1240                 /* was there an interrupt from this card ? */
1241                 if ((stat & ASL_IRQ_Pending) == ASL_IRQ_Pending)
1242                         break; /* no */
1243
1244                 /* interrupts are low active */
1245                 if (!(stat & ASL_IRQ_TIMER))
1246                         DBGL1(L1_H_IRQ, "avm_pnp_intr", ("timer interrupt ???\n"));
1247
1248                 if (!(stat & ASL_IRQ_ISAC))
1249                 {
1250                         DBGL1(L1_H_IRQ, "avm_pnp_intr", ("ISAC\n"));
1251                         isac_irq_stat = ISAC_READ(I_ISTA);
1252                         isic_isac_irq(sc, isac_irq_stat);
1253                         was_isac = 1;
1254                 }
1255
1256                 if (!(stat & ASL_IRQ_HSCX))
1257                 {
1258                         DBGL1(L1_H_IRQ, "avm_pnp_intr", ("HSCX\n"));
1259                         avm_pnp_hscx_int_handler(sc);
1260                 }
1261         }
1262         if (was_isac) {
1263                 ISAC_WRITE(0x20, 0xFF);
1264                 ISAC_WRITE(0x20, 0x0);
1265         }
1266 }
1267 #endif /* NISIC > 0 && defined(AVM_PNP) */
1268 #endif /* FreeBSD */