2 * Copyright (c) 1996, 1998 Gary Jennejohn. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 * 4. Altered versions must be plainly marked as such, and must not be
17 * misrepresented as being the original software and/or documentation.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 *---------------------------------------------------------------------------
33 * $Id: i4b_isac.h,v 1.2 1999/12/13 21:25:26 hm Exp $
37 * last edit-date: [Mon Dec 13 22:01:25 1999]
39 *---------------------------------------------------------------------------*/
45 * The ISAC databook specifies a delay of 2.5 DCL clock cycles between
46 * writes to the ISAC command register CMDR. This is the delay used to
47 * satisfy this requirement.
50 #define I4B_ISAC_CMDRWRDELAY 30
52 #if (I4B_ISAC_CMDRWRDELAY > 0)
53 #define ISACCMDRWRDELAY() DELAY(I4B_ISAC_CMDRWRDELAY)
55 #warning "I4B_ISAC_CMDRWRDELAY set to 0!"
56 #define ISACCMDRWRDELAY()
60 ISAC_VA, /* 2085 A1 or A2, 2086/2186 V1.1 */
61 ISAC_VB1, /* 2085 B1 */
62 ISAC_VB2, /* 2085 B2 */
63 ISAC_VB3, /* 2085 B3/V2.3 */
64 ISAC_UNKN /* unknown version */
67 #define ISAC_FIFO_LEN 32 /* 32 bytes FIFO on chip */
70 * definitions of registers and bits for the ISAC ISDN chip.
73 typedef struct isac_reg {
75 /* 32 byte deep FIFO always first */
77 unsigned char isac_fifo [ISAC_FIFO_LEN];
79 /* most registers can be read/written, but have different names */
80 /* so define a union with read/write names to make that clear */
84 unsigned char isac_ista;
85 unsigned char isac_star;
86 unsigned char isac_mode;
87 unsigned char isac_timr;
88 unsigned char isac_exir;
89 unsigned char isac_rbcl;
90 unsigned char isac_sapr;
91 unsigned char isac_rsta;
92 unsigned char dummy_28;
93 unsigned char isac_rhcr;
94 unsigned char isac_rbch;
95 unsigned char isac_star2;
96 unsigned char dummy_2c;
97 unsigned char dummy_2d;
98 unsigned char dummy_2e;
99 unsigned char dummt_2f;
100 unsigned char isac_spcr;
101 unsigned char isac_cirr;
102 unsigned char isac_mor;
103 unsigned char isac_sscr;
104 unsigned char isac_sfcr;
105 unsigned char isac_c1r;
106 unsigned char isac_c2r;
107 unsigned char isac_b1cr;
108 unsigned char isac_b2cr;
109 unsigned char isac_adf2;
110 unsigned char isac_mosr;
111 unsigned char isac_sqrr;
114 unsigned char isac_mask;
115 unsigned char isac_cmdr;
116 unsigned char isac_mode;
117 unsigned char isac_timr;
118 unsigned char isac_xad1;
119 unsigned char isac_xad2;
120 unsigned char isac_sap1;
121 unsigned char isac_sap2;
122 unsigned char isac_tei1;
123 unsigned char isac_tei2;
124 unsigned char dummy_2a;
125 unsigned char isac_star2;
126 unsigned char dummy_2c;
127 unsigned char dummy_2d;
128 unsigned char dummy_2e;
129 unsigned char dummt_2f;
130 unsigned char isac_spcr;
131 unsigned char isac_cixr;
132 unsigned char isac_mox;
133 unsigned char isac_sscx;
134 unsigned char isac_sfcw;
135 unsigned char isac_c1r;
136 unsigned char isac_c2r;
137 unsigned char isac_stcr;
138 unsigned char isac_adf1;
139 unsigned char isac_adf2;
140 unsigned char isac_mocr;
141 unsigned char isac_sqxr;
146 #define REG_OFFSET(type, field) (int)(&(((type *)0)->field))
148 /* ISAC read registers */
150 #define i_ista isac_rw.isac_r.isac_ista
151 #define I_ISTA REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_ista)
152 #define i_star isac_rw.isac_r.isac_star
153 #define I_STAR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_star)
154 #define i_mode isac_rw.isac_r.isac_mode
155 #define I_MODE REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_mode)
156 #define i_timr isac_rw.isac_r.isac_timr
157 #define I_TIMR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_timr)
158 #define i_exir isac_rw.isac_r.isac_exir
159 #define I_EXIR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_exir)
160 #define i_rbcl isac_rw.isac_r.isac_rbcl
161 #define I_RBCL REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_rbcl)
162 #define i_sapr isac_rw.isac_r.isac_sapr
163 #define I_SAPR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_sapr)
164 #define i_rsta isac_rw.isac_r.isac_rsta
165 #define I_RSTA REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_rsta)
166 #define i_rhcr isac_rw.isac_r.isac_rhcr
167 #define I_RHCR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_rhcr)
168 #define i_rbch isac_rw.isac_r.isac_rbch
169 #define I_RBCH REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_rbch)
170 #define i_star2 isac_rw.isac_r.isac_star2
171 #define I_STAR2 REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_star2)
172 #define i_spcr isac_rw.isac_r.isac_spcr
173 #define I_SPCR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_spcr)
174 #define i_cirr isac_rw.isac_r.isac_cirr
175 #define I_CIRR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_cirr)
176 #define i_mor isac_rw.isac_r.isac_mor
177 #define I_MOR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_mor)
178 #define i_sscr isac_rw.isac_r.isac_sscr
179 #define I_SSCR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_sscr)
180 #define i_sfcr isac_rw.isac_r.isac_sfcr
181 #define I_SFCR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_sfcr)
182 #define i_c1r isac_rw.isac_r.isac_c1r
183 #define I_C1R REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_c1r)
184 #define i_c2r isac_rw.isac_r.isac_c2r
185 #define I_C2R REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_c2r)
186 #define i_b1cr isac_rw.isac_r.isac_b1cr
187 #define I_B1CR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_b1cr)
188 #define i_b2cr isac_rw.isac_r.isac_b2cr
189 #define I_B2CR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_b2cr)
190 #define i_adf2 isac_rw.isac_r.isac_adf2
191 #define I_ADF2 REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_adf2)
192 #define i_mosr isac_rw.isac_r.isac_mosr
193 #define I_MOSR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_mosr)
194 #define i_sqrr isac_rw.isac_r.isac_sqrr
195 #define I_SQRR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_sqrr)
197 /* ISAC write registers - isac_mode, isac_timr, isac_star2, isac_spcr, */
198 /* isac_c1r, isac_c2r, isac_adf2 see read registers */
200 #define i_mask isac_rw.isac_w.isac_mask
201 #define I_MASK REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_mask)
202 #define i_cmdr isac_rw.isac_w.isac_cmdr
203 #define I_CMDR REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_cmdr)
204 #define i_xad1 isac_rw.isac_w.isac_xad1
205 #define I_XAD1 REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_xad1)
206 #define i_xad2 isac_rw.isac_w.isac_xad2
207 #define I_XAD2 REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_xad2)
208 #define i_sap1 isac_rw.isac_w.isac_sap1
209 #define I_SAP1 REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_sap1)
210 #define i_sap2 isac_rw.isac_w.isac_sap2
211 #define I_SAP2 REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_sap2)
212 #define i_tei1 isac_rw.isac_w.isac_tei1
213 #define i_tei2 isac_rw.isac_w.isac_tei2
214 #define i_cixr isac_rw.isac_w.isac_cixr
215 #define I_CIXR REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_cixr)
216 #define I_CIX0 I_CIXR
217 #define i_mox isac_rw.isac_w.isac_mox
218 #define I_MOX REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_mox)
219 #define i_sscx isac_rw.isac_w.isac_sscx
220 #define I_SSCX REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_sscx)
221 #define i_sfcw isac_rw.isac_w.isac_sfcw
222 #define I_SFCW REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_sfcw)
223 #define i_stcr isac_rw.isac_w.isac_stcr
224 #define I_STCR REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_stcr)
225 #define i_adf1 isac_rw.isac_w.isac_adf1
226 #define I_ADF1 REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_adf1)
227 #define i_mocr isac_rw.isac_w.isac_mocr
228 #define I_MOCR REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_mocr)
229 #define i_sqxr isac_rw.isac_w.isac_sqxr
230 #define I_SQXR REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_sqxr)
232 #define ISAC_ISTA_RME 0x80
233 #define ISAC_ISTA_RPF 0x40
234 #define ISAC_ISTA_RSC 0x20
235 #define ISAC_ISTA_XPR 0x10
236 #define ISAC_ISTA_TIN 0x08
237 #define ISAC_ISTA_CISQ 0x04
238 #define ISAC_ISTA_SIN 0x02
239 #define ISAC_ISTA_EXI 0x01
241 #define ISAC_MASK_RME 0x80
242 #define ISAC_MASL_RPF 0x40
243 #define ISAC_MASK_RSC 0x20
244 #define ISAC_MASK_XPR 0x10
245 #define ISAC_MASK_TIN 0x08
246 #define ISAC_MASK_CISQ 0x04
247 #define ISAC_MASK_SIN 0x02
248 #define ISAC_MASK_EXI 0x01
249 #define ISAC_MASK_ALL 0xff
251 #define ISAC_STAR_XDOV 0x80
252 #define ISAC_STAR_XFW 0x40
253 #define ISAC_STAR_XRNR 0x20
254 #define ISAC_STAR_RRNR 0x10
255 #define ISAC_STAR_MBR 0x08
256 #define ISAC_STAR_MAC1 0x04
257 #define ISAC_STAR_BVS 0x02
258 #define ISAC_STAR_MAC0 0x01
260 #define ISAC_CMDR_RMC 0x80
261 #define ISAC_CMDR_RRES 0x40
262 #define ISAC_CMDR_RNR 0x20
263 #define ISAC_CMDR_STI 0x10
264 #define ISAC_CMDR_XTF 0x08
265 #define ISAC_CMDR_XIF 0x04
266 #define ISAC_CMDR_XME 0x02
267 #define ISAC_CMDR_XRES 0x01
269 #define ISAC_MODE_MDS2 0x80
270 #define ISAC_MODE_MDS1 0x40
271 #define ISAC_MODE_MDS0 0x20
272 #define ISAC_MODE_TMD 0x10
273 #define ISAC_MODE_RAC 0x08
274 #define ISAC_MODE_DIM2 0x04
275 #define ISAC_MODE_DIM1 0x02
276 #define ISAC_MODE_DIM0 0x01
278 #define ISAC_EXIR_XMR 0x80
279 #define ISAC_EXIR_XDU 0x40
280 #define ISAC_EXIR_PCE 0x20
281 #define ISAC_EXIR_RFO 0x10
282 #define ISAC_EXIR_SOV 0x08
283 #define ISAC_EXIR_MOS 0x04
284 #define ISAC_EXIR_SAW 0x02
285 #define ISAC_EXIR_WOV 0x01
287 #define ISAC_RSTA_RDA 0x80
288 #define ISAC_RSTA_RDO 0x40
289 #define ISAC_RSTA_CRC 0x20
290 #define ISAC_RSTA_RAB 0x10
291 #define ISAC_RSTA_SA1 0x08
292 #define ISAC_RSTA_SA0 0x04
293 #define ISAC_RSTA_CR 0x02
294 #define ISAC_RSTA_TA 0x01
296 #define ISAC_RSTA_MASK 0x70 /* the interesting bits */
298 #define ISAC_RBCH_XAC 0x80
299 #define ISAC_RBCH_VN1 0x40
300 #define ISAC_RBCH_VN0 0x20
301 #define ISAC_RBCH_OV 0x10
302 /* the other 4 bits are the high bits of the receive byte count */
304 #define ISAC_SPCR_SPU 0x80
305 #define ISAC_SPCR_SAC 0x40
306 #define ISAC_SPCR_SPM 0x20
307 #define ISAC_SPCR_TLP 0x10
308 #define ISAC_SPCR_C1C1 0x08
309 #define ISAC_SPCR_C1C0 0x04
310 #define ISAC_SPCR_C2C1 0x02
311 #define ISAC_SPCR_C2C0 0x01
313 #define ISAC_CIRR_SQC 0x80
314 #define ISAC_CIRR_BAS 0x40
316 #define ISAC_CIRR_CIC0 0x02
317 /* bit 0 is always 0 */
318 /* C/I codes from bits 5-2 (>> 2 & 0xf) */
319 /* the indications */
320 #define ISAC_CIRR_IPU 0x07
321 #define ISAC_CIRR_IDR 0x00
322 #define ISAC_CIRR_ISD 0x02
323 #define ISAC_CIRR_IDIS 0x03
324 #define ISAC_CIRR_IEI 0x06
325 #define ISAC_CIRR_IRSY 0x04
326 #define ISAC_CIRR_IARD 0x08
327 #define ISAC_CIRR_ITI 0x0a
328 #define ISAC_CIRR_IATI 0x0b
329 #define ISAC_CIRR_IAI8 0x0c
330 #define ISAC_CIRR_IAI10 0x0d
331 #define ISAC_CIRR_IDID 0x0f
333 #define ISAC_CI_MASK 0x0f
335 #define ISAC_CIXR_RSS 0x80
336 #define ISAC_CIXR_BAC 0x40
338 #define ISAC_CIXR_TCX 0x02
339 #define ISAC_CIXR_ECX 0x01
340 /* in IOM-2 mode the low bits are always 1 */
341 #define ISAC_CIX0_LOW 0x03
342 /* C/I codes from bits 5-2 (>> 2 & 0xf) */
344 #define ISAC_CIXR_CTIM 0
345 #define ISAC_CIXR_CRS 0x01
346 #define ISAC_CIXR_CSCZ 0x04
347 #define ISAC_CIXR_CSSZ 0x02
348 #define ISAC_CIXR_CAR8 0x08
349 #define ISAC_CIXR_CAR10 0x09
350 #define ISAC_CIXR_CARL 0x0a
351 #define ISAC_CIXR_CDIU 0x0f
353 #define ISAC_STCR_TSF 0x80
354 #define ISAC_STCR_TBA2 0x40
355 #define ISAC_STCR_TBA1 0x20
356 #define ISAC_STCR_TBA0 0x10
357 #define ISAC_STCR_ST1 0x08
358 #define ISAC_STCR_ST0 0x04
359 #define ISAC_STCR_SC1 0x02
360 #define ISAC_STCR_SC0 0x01
362 #define ISAC_ADF1_WTC1 0x80
363 #define ISAC_ADF1_WTC2 0x40
364 #define ISAC_ADF1_TEM 0x20
365 #define ISAC_ADF1_PFS 0x10
366 #define ISAC_ADF1_CFS 0x08
367 #define ISAC_ADF1_FC2 0x04
368 #define ISAC_ADF1_FC1 0x02
369 #define ISAC_ADF1_ITF 0x01
371 #define ISAC_ADF2_IMS 0x80
372 /* all other bits are 0 */
374 /* bits 7-5 are always 0 */
375 #define ISAC_SQRR_SYN 0x10
376 #define ISAC_SQRR_SQR1 0x08
377 #define ISAC_SQRR_SQR2 0x04
378 #define ISAC_SQRR_SQR3 0x02
379 #define ISAC_SQRR_SQR4 0x01
381 #define ISAC_SQXR_IDC 0x80
382 #define ISAC_SQXR_CFS 0x40
383 #define ISAC_SQXR_CI1E 0x20
384 #define ISAC_SQXR_SQIE 0x10
385 #define ISAC_SQXR_SQX1 0x08
386 #define ISAC_SQXR_SQX2 0x04
387 #define ISAC_SQXR_SQX3 0x02
388 #define ISAC_SQXR_SQX4 0x01
390 #endif /* I4B_ISAC_H_ */