sys/i4b/layer1/i4b_sws.c

   1 /*
   2  *   Copyright (c) 1998 German Tischler. All rights reserved.
   3  *
   4  *   Redistribution and use in source and binary forms, with or without
   5  *   modification, are permitted provided that the following conditions
   6  *   are met:
   7  *
   8  *   1. Redistributions of source code must retain the above copyright
   9  *      notice, this list of conditions and the following disclaimer.
  10  *   2. Redistributions in binary form must reproduce the above copyright
  11  *      notice, this list of conditions and the following disclaimer in the
  12  *      documentation and/or other materials provided with the distribution.
  13  *   3. Neither the name of the author nor the names of any co-contributors
  14  *      may be used to endorse or promote products derived from this software
  15  *      without specific prior written permission.
  16  *   4. Altered versions must be plainly marked as such, and must not be
  17  *      misrepresented as being the original software and/or documentation.
  18  *
  19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  *   SUCH DAMAGE.
  30  *
  31  *---------------------------------------------------------------------------
  32  *
  33  * Card format:
  34  *
  35  * iobase + 0 : reset on  (0x03)
  36  * iobase + 1 : reset off (0x0)
  37  * iobase + 2 : isac read/write
  38  * iobase + 3 : hscx read/write ( offset 0-0x3f    hscx0 ,
  39  *                                offset 0x40-0x7f hscx1 )
  40  * iobase + 4 : offset for indirect adressing
  41  *
  42  *---------------------------------------------------------------------------
  43  *
  44  *      isic - I4B Siemens ISDN Chipset Driver for SWS cards
  45  *      ====================================================
  46  *
  47  *      $Id: i4b_sws.c,v 1.2 1999/12/13 21:25:26 hm Exp $
  48  *
  49  * $FreeBSD$
  50  *
  51  *      last edit-date: [Mon Dec 13 22:02:39 1999]
  52  *
  53  *---------------------------------------------------------------------------*/
  54
  55 #include "isic.h"
  56 #include "opt_i4b.h"
  57
  58 #if defined (SEDLBAUER) && NISIC > 0
  59
  60 #define SWS_RESON  0 /* reset on                 */
  61 #define SWS_RESOFF 1 /* reset off                */
  62 #define SWS_ISAC   2 /* ISAC                     */
  63 #define SWS_HSCX0  3 /* HSCX0                    */
  64 #define SWS_RW     4 /* indirect access register */
  65 #define SWS_HSCX1  5 /* this is for fakeing that we mean hscx1, though */
  66                      /* access is done through hscx0                   */
  67
  68 #define SWS_REGS   8 /* we use an area of 8 bytes for io */
  69
  70 #include <sys/param.h>
  71 #include <sys/systm.h>
  72 #include <sys/mbuf.h>
  73 #include <sys/socket.h>
  74
  75 #include <machine/clock.h>
  76
  77 #include <net/if.h>
  78
  79 #include <machine/i4b_debug.h>
  80 #include <machine/i4b_ioctl.h>
  81
  82 #include <i4b/layer1/i4b_l1.h>
  83 #include <i4b/layer1/i4b_isac.h>
  84 #include <i4b/layer1/i4b_hscx.h>
  85
  86 #include <i4b/include/i4b_global.h>
  87 #include <i4b/include/i4b_l1l2.h>
  88 #include <i4b/include/i4b_mbuf.h>
  89
  90 /*---------------------------------------------------------------------------*
  91  *      SWS P&P ISAC get fifo routine
  92  *---------------------------------------------------------------------------*/
  93 static void
  94 sws_read_fifo(struct l1_softc *sc,int what,void *buf,size_t size) {
  95         bus_space_tag_t    t = rman_get_bustag(sc->sc_resources.io_base[0]);
  96         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
  97
  98         switch ( what ) {
  99                 case ISIC_WHAT_ISAC:
 100                         bus_space_write_1(t,h,SWS_RW,0x0);
 101                         bus_space_read_multi_1(t,h,SWS_ISAC,buf,size);
 102                         break;
 103                 case ISIC_WHAT_HSCXA:
 104                         bus_space_write_1(t,h,SWS_RW,0x0);
 105                         bus_space_read_multi_1(t,h,SWS_HSCX0,buf,size);
 106                         break;
 107                 case ISIC_WHAT_HSCXB:
 108                         bus_space_write_1(t,h,SWS_RW,0x0+0x40);
 109                         bus_space_read_multi_1(t,h,SWS_HSCX0,buf,size);
 110                         break;
 111         }
 112 }
 113
 114 static void
 115 sws_write_fifo(struct l1_softc *sc,int what,void *buf,size_t size) {
 116         bus_space_tag_t    t = rman_get_bustag(sc->sc_resources.io_base[0]);
 117         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
 118
 119         switch ( what ) {
 120                 case ISIC_WHAT_ISAC:
 121                         bus_space_write_1(t,h,SWS_RW,0x0);
 122                         bus_space_write_multi_1(t,h,SWS_ISAC,buf,size);
 123                         break;
 124                 case ISIC_WHAT_HSCXA:
 125                         bus_space_write_1(t,h,SWS_RW,0x0);
 126                         bus_space_write_multi_1(t,h,SWS_HSCX0,buf,size);
 127                         break;
 128                 case ISIC_WHAT_HSCXB:
 129                         bus_space_write_1(t,h,SWS_RW,0x0+0x40);
 130                         bus_space_write_multi_1(t,h,SWS_HSCX0,buf,size);
 131                         break;
 132         }
 133 }
 134
 135 static void
 136 sws_write_reg(struct l1_softc *sc,int what,bus_size_t reg,u_int8_t data) {
 137         bus_space_tag_t    t = rman_get_bustag(sc->sc_resources.io_base[0]);
 138         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
 139
 140         switch ( what ) {
 141                 case ISIC_WHAT_ISAC:
 142                         bus_space_write_1(t,h,SWS_RW,reg);
 143                         bus_space_write_1(t,h,SWS_ISAC,data);
 144                         break;
 145                 case ISIC_WHAT_HSCXA:
 146                         bus_space_write_1(t,h,SWS_RW,reg);
 147                         bus_space_write_1(t,h,SWS_HSCX0,data);
 148                         break;
 149                 case ISIC_WHAT_HSCXB:
 150                         bus_space_write_1(t,h,SWS_RW,reg+0x40);
 151                         bus_space_write_1(t,h,SWS_HSCX0,data);
 152                         break;
 153         }
 154 }
 155
 156 static u_char
 157 sws_read_reg (struct l1_softc *sc,int what,bus_size_t reg) {
 158         bus_space_tag_t    t = rman_get_bustag(sc->sc_resources.io_base[0]);
 159         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
 160
 161         switch ( what ) {
 162                 case ISIC_WHAT_ISAC:
 163                         bus_space_write_1(t,h,SWS_RW,reg);
 164                         return bus_space_read_1(t,h,SWS_ISAC);
 165                 case ISIC_WHAT_HSCXA:
 166                         bus_space_write_1(t,h,SWS_RW,reg);
 167                         return bus_space_read_1(t,h,SWS_HSCX0);
 168                 case ISIC_WHAT_HSCXB:
 169                         bus_space_write_1(t,h,SWS_RW,reg+0x40);
 170                         return bus_space_read_1(t,h,SWS_HSCX0);
 171                 default:
 172                         return 0;
 173         }
 174 }
 175
 176 /* attach callback routine */
 177 int
 178 isic_attach_sws(device_t dev)
 179 {
 180         int unit = device_get_unit(dev);
 181         struct l1_softc *sc = &l1_sc[unit];
 182
 183         struct i4b_info * info = &(sc->sc_resources);
 184         bus_space_tag_t    t = rman_get_bustag(info->io_base[0]);
 185         bus_space_handle_t h = rman_get_bushandle(info->io_base[0]);
 186
 187         /* fill in l1_softc structure */
 188         sc->readreg     = sws_read_reg;
 189         sc->writereg    = sws_write_reg;
 190         sc->readfifo    = sws_read_fifo;
 191         sc->writefifo   = sws_write_fifo;
 192         sc->clearirq    = NULL;
 193         sc->sc_cardtyp  = CARD_TYPEP_SWS;
 194         sc->sc_bustyp   = BUS_TYPE_IOM2;
 195         sc->sc_ipac     = 0;
 196         sc->sc_bfifolen = HSCX_FIFO_LEN;
 197
 198         /*
 199          * Read HSCX A/B VSTR.  Expected value for the SWS PnP card is
 200          * 0x05 ( = version 2.1 ) in the least significant bits.
 201          */
 202
 203         if( ((HSCX_READ(0, H_VSTR) & 0xf) != 0x5) ||
 204             ((HSCX_READ(1, H_VSTR) & 0xf) != 0x5) )
 205         {
 206                 printf("isic%d: HSCX VSTR test failed for SWS PnP\n",
 207                         sc->sc_unit);
 208                 printf("isic%d: HSC0: VSTR: %#x\n",
 209                         sc->sc_unit, HSCX_READ(0, H_VSTR));
 210                 printf("isic%d: HSC1: VSTR: %#x\n",
 211                         sc->sc_unit, HSCX_READ(1, H_VSTR));
 212                 return (ENXIO);
 213         }
 214
 215         /* reset card */
 216         bus_space_write_1(t,h,SWS_RESON,0x3);
 217         DELAY(SEC_DELAY / 5);
 218         bus_space_write_1(t,h,SWS_RESOFF,0x0);
 219         DELAY(SEC_DELAY / 5);
 220
 221         return(0);
 222 }
 223 #endif /* defined(SEDLBAUER) && NISIC > 0 */