2 * Copyright (c) 1997, 2002 Hellmuth Michaelis. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 /*---------------------------------------------------------------------------
28 * i4b - Siemens HSCX chip (B-channel) handling
29 * --------------------------------------------
30 * last edit-date: [Sat Mar 9 16:01:49 2002]
32 *---------------------------------------------------------------------------*/
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include <sys/param.h>
38 #include <sys/systm.h>
40 #include <sys/socket.h>
44 #include <i4b/include/i4b_debug.h>
45 #include <i4b/include/i4b_ioctl.h>
46 #include <i4b/include/i4b_trace.h>
48 #include <i4b/layer1/isic/i4b_isic.h>
49 #include <i4b/layer1/isic/i4b_hscx.h>
51 #include <i4b/layer1/i4b_l1.h>
53 #include <i4b/include/i4b_global.h>
54 #include <i4b/include/i4b_mbuf.h>
56 /*---------------------------------------------------------------------------*
58 *---------------------------------------------------------------------------*/
60 isic_hscx_irq(register struct l1_softc *sc, u_char ista, int h_chan, u_char ex_irq)
62 register l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
67 NDBGL1(L1_H_IRQ, "%#x", ista);
71 /* get channel extended irq reg */
73 exir = HSCX_READ(h_chan, H_EXIR);
75 if(exir & HSCX_EXIR_RFO)
78 NDBGL1(L1_H_XFRERR, "ex_irq: receive data overflow");
81 if((exir & HSCX_EXIR_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
84 NDBGL1(L1_H_XFRERR, "ex_irq: xmit data underrun");
85 isic_hscx_cmd(sc, h_chan, HSCX_CMDR_XRES);
87 if (chan->out_mbuf_head != NULL) /* don't continue to transmit this buffer */
89 i4b_Bfreembuf(chan->out_mbuf_head);
90 chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
96 /* rx message end, end of frame */
98 if(ista & HSCX_ISTA_RME)
100 register int fifo_data_len;
104 rsta = HSCX_READ(h_chan, H_RSTA);
106 if((rsta & 0xf0) != 0xa0)
108 if((rsta & HSCX_RSTA_VFR) == 0)
111 cmd |= (HSCX_CMDR_RHR);
112 NDBGL1(L1_H_XFRERR, "received invalid Frame");
116 if(rsta & HSCX_RSTA_RDO)
119 NDBGL1(L1_H_XFRERR, "receive data overflow");
123 if((rsta & HSCX_RSTA_CRC) == 0)
126 cmd |= (HSCX_CMDR_RHR);
127 NDBGL1(L1_H_XFRERR, "CRC check failed");
131 if(rsta & HSCX_RSTA_RAB)
134 NDBGL1(L1_H_XFRERR, "Receive message aborted");
139 fifo_data_len = ((HSCX_READ(h_chan, H_RBCL)) &
140 ((sc->sc_bfifolen)-1));
142 if(fifo_data_len == 0)
143 fifo_data_len = sc->sc_bfifolen;
145 /* all error conditions checked, now decide and take action */
149 if(chan->in_mbuf == NULL)
151 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
152 panic("L1 isic_hscx_irq: RME, cannot allocate mbuf!\n");
153 chan->in_cbptr = chan->in_mbuf->m_data;
157 fifo_data_len -= 1; /* last byte in fifo is RSTA ! */
159 if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
161 /* read data from HSCX fifo */
163 HSCX_RDFIFO(h_chan, chan->in_cbptr, fifo_data_len);
165 cmd |= (HSCX_CMDR_RMC);
166 isic_hscx_cmd(sc, h_chan, cmd);
169 chan->in_len += fifo_data_len;
170 chan->rxcount += fifo_data_len;
172 /* setup mbuf data length */
174 chan->in_mbuf->m_len = chan->in_len;
175 chan->in_mbuf->m_pkthdr.len = chan->in_len;
177 if(sc->sc_trace & TRACE_B_RX)
180 hdr.unit = L0ISICUNIT(sc->sc_unit);
181 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
183 hdr.count = ++sc->sc_trace_bcount;
185 i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
188 (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
192 /* mark buffer ptr as unused */
194 chan->in_mbuf = NULL;
195 chan->in_cbptr = NULL;
200 NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RME, in_len=%d, fifolen=%d", chan->in_len, fifo_data_len);
201 chan->in_cbptr = chan->in_mbuf->m_data;
203 cmd |= (HSCX_CMDR_RHR | HSCX_CMDR_RMC);
208 if (chan->in_mbuf != NULL)
210 i4b_Bfreembuf(chan->in_mbuf);
211 chan->in_mbuf = NULL;
212 chan->in_cbptr = NULL;
215 cmd |= (HSCX_CMDR_RMC);
221 if(ista & HSCX_ISTA_RPF)
223 if(chan->in_mbuf == NULL)
225 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
226 panic("L1 isic_hscx_irq: RPF, cannot allocate mbuf!\n");
227 chan->in_cbptr = chan->in_mbuf->m_data;
231 chan->rxcount += sc->sc_bfifolen;
233 if((chan->in_len + sc->sc_bfifolen) <= BCH_MAX_DATALEN)
235 /* read data from HSCX fifo */
237 HSCX_RDFIFO(h_chan, chan->in_cbptr, sc->sc_bfifolen);
239 chan->in_cbptr += sc->sc_bfifolen;
240 chan->in_len += sc->sc_bfifolen;
244 if(chan->bprot == BPROT_NONE)
246 /* setup mbuf data length */
248 chan->in_mbuf->m_len = chan->in_len;
249 chan->in_mbuf->m_pkthdr.len = chan->in_len;
251 if(sc->sc_trace & TRACE_B_RX)
254 hdr.unit = L0ISICUNIT(sc->sc_unit);
255 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
257 hdr.count = ++sc->sc_trace_bcount;
259 i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
262 /* silence detection */
264 if(!(i4b_l1_bchan_tel_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
267 (void) IF_HANDOFF(&chan->rx_queue, chan->in_mbuf, NULL);
269 /* signal upper driver that data is available */
271 (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
273 /* alloc new buffer */
275 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
276 panic("L1 isic_hscx_irq: RPF, cannot allocate new mbuf!\n");
278 /* setup new data ptr */
280 chan->in_cbptr = chan->in_mbuf->m_data;
282 /* read data from HSCX fifo */
284 HSCX_RDFIFO(h_chan, chan->in_cbptr, sc->sc_bfifolen);
286 chan->in_cbptr += sc->sc_bfifolen;
287 chan->in_len = sc->sc_bfifolen;
289 chan->rxcount += sc->sc_bfifolen;
293 NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
294 chan->in_cbptr = chan->in_mbuf->m_data;
296 cmd |= (HSCX_CMDR_RHR);
300 /* command to release fifo space */
302 cmd |= HSCX_CMDR_RMC;
305 /* transmit fifo empty, new data can be written to fifo */
307 if(ista & HSCX_ISTA_XPR)
310 * for a description what is going on here, please have
311 * a look at isic_bchannel_start() in i4b_bchan.c !
318 NDBGL1(L1_H_IRQ, "unit %d, chan %d - XPR, Tx Fifo Empty!", sc->sc_unit, h_chan);
320 if(chan->out_mbuf_cur == NULL) /* last frame is transmitted */
322 IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
324 if(chan->out_mbuf_head == NULL)
326 chan->state &= ~HSCX_TX_ACTIVE;
327 (*chan->isic_drvr_linktab->bch_tx_queue_empty)(chan->isic_drvr_linktab->unit);
331 chan->state |= HSCX_TX_ACTIVE;
332 chan->out_mbuf_cur = chan->out_mbuf_head;
333 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
334 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
336 if(sc->sc_trace & TRACE_B_TX)
339 hdr.unit = L0ISICUNIT(sc->sc_unit);
340 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
342 hdr.count = ++sc->sc_trace_bcount;
344 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
347 if(chan->bprot == BPROT_NONE)
349 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
361 while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
363 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
366 printf("i:mh=%x, mc=%x, mcp=%x, mcl=%d l=%d nl=%d # ",
369 chan->out_mbuf_cur_ptr,
370 chan->out_mbuf_cur_len,
375 isic_hscx_waitxfw(sc, h_chan); /* necessary !!! */
377 HSCX_WRFIFO(h_chan, chan->out_mbuf_cur_ptr, nextlen);
378 cmd |= HSCX_CMDR_XTF;
381 chan->txcount += nextlen;
383 chan->out_mbuf_cur_ptr += nextlen;
384 chan->out_mbuf_cur_len -= nextlen;
386 if(chan->out_mbuf_cur_len == 0)
388 if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
390 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
391 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
393 if(sc->sc_trace & TRACE_B_TX)
396 hdr.unit = L0ISICUNIT(sc->sc_unit);
397 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
399 hdr.count = ++sc->sc_trace_bcount;
401 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
406 if (chan->bprot != BPROT_NONE)
407 cmd |= HSCX_CMDR_XME;
408 i4b_Bfreembuf(chan->out_mbuf_head);
409 chan->out_mbuf_head = NULL;
416 if(cmd) /* is there a command for the HSCX ? */
418 isic_hscx_cmd(sc, h_chan, cmd); /* yes, to HSCX */
421 /* call timeout handling routine */
423 if(activity == ACT_RX || activity == ACT_TX)
424 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
427 /*---------------------------------------------------------------------------*
428 * HSCX initialization
430 * for telephony: extended transparent mode 1
431 * for raw hdlc: transparent mode 0
432 *---------------------------------------------------------------------------*/
434 isic_hscx_init(struct l1_softc *sc, int h_chan, int activate)
436 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
438 HSCX_WRITE(h_chan, H_MASK, 0xff); /* mask irq's */
442 /* CCR1: Power Up, Clock Mode 5 */
443 HSCX_WRITE(h_chan, H_CCR1, HSCX_CCR1_PU | /* power up */
444 HSCX_CCR1_CM1); /* IPAC clock mode 5 */
448 /* CCR1: Power Up, Clock Mode 5 */
449 HSCX_WRITE(h_chan, H_CCR1, HSCX_CCR1_PU | /* power up */
450 HSCX_CCR1_CM2 | /* HSCX clock mode 5 */
454 /* XAD1: Transmit Address Byte 1 */
455 HSCX_WRITE(h_chan, H_XAD1, 0xff);
457 /* XAD2: Transmit Address Byte 2 */
458 HSCX_WRITE(h_chan, H_XAD2, 0xff);
460 /* RAH2: Receive Address Byte High Reg. 2 */
461 HSCX_WRITE(h_chan, H_RAH2, 0xff);
463 /* XBCH: reset Transmit Byte Count High */
464 HSCX_WRITE(h_chan, H_XBCH, 0x00);
466 /* RLCR: reset Receive Length Check Register */
467 HSCX_WRITE(h_chan, H_RLCR, 0x00);
469 /* CCR2: set tx/rx clock shift bit 0 */
470 /* disable CTS irq, disable RIE irq*/
471 HSCX_WRITE(h_chan, H_CCR2, HSCX_CCR2_XCS0|HSCX_CCR2_RCS0);
473 /* XCCR: tx bit count per time slot */
474 HSCX_WRITE(h_chan, H_XCCR, 0x07);
476 /* RCCR: rx bit count per time slot */
477 HSCX_WRITE(h_chan, H_RCCR, 0x07);
479 if(sc->sc_bustyp == BUS_TYPE_IOM2)
483 case HSCX_CH_A: /* Prepare HSCX channel A */
484 /* TSAX: tx clock shift bits 1 & 2 */
485 /* tx time slot number */
486 HSCX_WRITE(h_chan, H_TSAX, 0x2f);
488 /* TSAR: rx clock shift bits 1 & 2 */
489 /* rx time slot number */
490 HSCX_WRITE(h_chan, H_TSAR, 0x2f);
493 case HSCX_CH_B: /* Prepare HSCX channel B */
494 /* TSAX: tx clock shift bits 1 & 2 */
495 /* tx time slot number */
496 HSCX_WRITE(h_chan, H_TSAX, 0x03);
498 /* TSAR: rx clock shift bits 1 & 2 */
499 /* rx time slot number */
500 HSCX_WRITE(h_chan, H_TSAR, 0x03);
504 else /* IOM 1 setup */
506 /* TSAX: tx clock shift bits 1 & 2 */
507 /* tx time slot number */
508 HSCX_WRITE(h_chan, H_TSAX, 0x07);
510 /* TSAR: rx clock shift bits 1 & 2 */
511 /* rx time slot number */
512 HSCX_WRITE(h_chan, H_TSAR, 0x07);
517 if(chan->bprot == BPROT_RHDLC)
519 /* HDLC Frames, transparent mode 0 */
520 HSCX_WRITE(h_chan, H_MODE,
521 HSCX_MODE_MDS1|HSCX_MODE_RAC|HSCX_MODE_RTS);
525 /* Raw Telephony, extended transparent mode 1 */
526 HSCX_WRITE(h_chan, H_MODE,
527 HSCX_MODE_MDS1|HSCX_MODE_MDS0|HSCX_MODE_ADM|HSCX_MODE_RTS);
530 isic_hscx_cmd(sc, h_chan, HSCX_CMDR_RHR|HSCX_CMDR_XRES);
532 isic_hscx_cmd(sc, h_chan, HSCX_CMDR_RHR);
537 /* TSAX: tx time slot */
538 HSCX_WRITE(h_chan, H_TSAX, 0xff);
540 /* TSAR: rx time slot */
541 HSCX_WRITE(h_chan, H_TSAR, 0xff);
543 /* Raw Telephony, extended transparent mode 1 */
544 HSCX_WRITE(h_chan, H_MODE,
545 HSCX_MODE_MDS1|HSCX_MODE_MDS0|HSCX_MODE_ADM|HSCX_MODE_RTS);
548 /* don't touch ICA, EXA and EXB bits, this could be HSCX_CH_B */
549 /* always disable RSC and TIN */
551 chan->hscx_mask |= HSCX_MASK_RSC | HSCX_MASK_TIN;
556 chan->hscx_mask &= ~(HSCX_MASK_RME | HSCX_MASK_RPF | HSCX_MASK_XPR);
561 chan->hscx_mask |= HSCX_MASK_RME | HSCX_MASK_RPF | HSCX_MASK_XPR;
564 /* handle ICA, EXA, and EXB via interrupt mask of channel b */
566 if (h_chan == HSCX_CH_A)
569 HSCX_B_IMASK &= ~(HSCX_MASK_EXA | HSCX_MASK_ICA);
571 HSCX_B_IMASK |= HSCX_MASK_EXA | HSCX_MASK_ICA;
572 HSCX_WRITE(HSCX_CH_A, H_MASK, HSCX_A_IMASK);
573 HSCX_WRITE(HSCX_CH_B, H_MASK, HSCX_B_IMASK);
578 HSCX_B_IMASK &= ~HSCX_MASK_EXB;
580 HSCX_B_IMASK |= HSCX_MASK_EXB;
581 HSCX_WRITE(HSCX_CH_B, H_MASK, HSCX_B_IMASK);
584 /* clear spurious interrupts left over */
586 if(h_chan == HSCX_CH_A)
588 HSCX_READ(h_chan, H_EXIR);
589 HSCX_READ(h_chan, H_ISTA);
591 else /* mask ICA, because it must not be cleared by reading ISTA */
593 HSCX_WRITE(HSCX_CH_B, H_MASK, HSCX_B_IMASK | HSCX_MASK_ICA);
594 HSCX_READ(h_chan, H_EXIR);
595 HSCX_READ(h_chan, H_ISTA);
596 HSCX_WRITE(HSCX_CH_B, H_MASK, HSCX_B_IMASK);
600 /*---------------------------------------------------------------------------*
601 * write command to HSCX command register
602 *---------------------------------------------------------------------------*/
604 isic_hscx_cmd(struct l1_softc *sc, int h_chan, unsigned char cmd)
608 while(((HSCX_READ(h_chan, H_STAR)) & HSCX_STAR_CEC) && timeout)
616 NDBGL1(L1_H_ERR, "HSCX wait for CEC timeout!");
619 HSCX_WRITE(h_chan, H_CMDR, cmd);
622 /*---------------------------------------------------------------------------*
623 * wait for HSCX transmit FIFO write enable
624 *---------------------------------------------------------------------------*/
626 isic_hscx_waitxfw(struct l1_softc *sc, int h_chan)
631 int timeout = WAITTO;
633 while((!(((HSCX_READ(h_chan, H_STAR)) &
634 (HSCX_STAR_CEC | HSCX_STAR_XFW)) == HSCX_STAR_XFW)) && timeout)
642 NDBGL1(L1_H_ERR, "HSCX wait for XFW timeout!");
644 else if (timeout != WAITTO)
646 NDBGL1(L1_H_XFRERR, "HSCX wait for XFW time: %d uS", (WAITTO-timeout)*50);