2 * Copyright (c) 1996, 2000 Gary Jennejohn. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 * 4. Altered versions must be plainly marked as such, and must not be
17 * misrepresented as being the original software and/or documentation.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 /*---------------------------------------------------------------------------
36 * last edit-date: [Wed Jan 24 09:10:42 2001]
38 *---------------------------------------------------------------------------*/
44 * The ISAC databook specifies a delay of 2.5 DCL clock cycles between
45 * writes to the ISAC command register CMDR. This is the delay used to
46 * satisfy this requirement.
49 #define I4B_ISAC_CMDRWRDELAY 30
51 #if (I4B_ISAC_CMDRWRDELAY > 0)
52 #define ISACCMDRWRDELAY() DELAY(I4B_ISAC_CMDRWRDELAY)
54 #warning "I4B_ISAC_CMDRWRDELAY set to 0!"
55 #define ISACCMDRWRDELAY()
59 ISAC_VA, /* 2085 A1 or A2, 2086/2186 V1.1 */
60 ISAC_VB1, /* 2085 B1 */
61 ISAC_VB2, /* 2085 B2 */
62 ISAC_VB3, /* 2085 B3/V2.3 */
63 ISAC_UNKN /* unknown version */
66 #define ISAC_FIFO_LEN 32 /* 32 bytes FIFO on chip */
69 * definitions of registers and bits for the ISAC ISDN chip.
72 typedef struct isac_reg {
74 /* 32 byte deep FIFO always first */
76 unsigned char isac_fifo [ISAC_FIFO_LEN];
78 /* most registers can be read/written, but have different names */
79 /* so define a union with read/write names to make that clear */
83 unsigned char isac_ista;
84 unsigned char isac_star;
85 unsigned char isac_mode;
86 unsigned char isac_timr;
87 unsigned char isac_exir;
88 unsigned char isac_rbcl;
89 unsigned char isac_sapr;
90 unsigned char isac_rsta;
91 unsigned char dummy_28;
92 unsigned char isac_rhcr;
93 unsigned char isac_rbch;
94 unsigned char isac_star2;
95 unsigned char dummy_2c;
96 unsigned char dummy_2d;
97 unsigned char dummy_2e;
98 unsigned char dummt_2f;
99 unsigned char isac_spcr;
100 unsigned char isac_cirr;
101 unsigned char isac_mor;
102 unsigned char isac_sscr;
103 unsigned char isac_sfcr;
104 unsigned char isac_c1r;
105 unsigned char isac_c2r;
106 unsigned char isac_b1cr;
107 unsigned char isac_b2cr;
108 unsigned char isac_adf2;
109 unsigned char isac_mosr;
110 unsigned char isac_sqrr;
113 unsigned char isac_mask;
114 unsigned char isac_cmdr;
115 unsigned char isac_mode;
116 unsigned char isac_timr;
117 unsigned char isac_xad1;
118 unsigned char isac_xad2;
119 unsigned char isac_sap1;
120 unsigned char isac_sap2;
121 unsigned char isac_tei1;
122 unsigned char isac_tei2;
123 unsigned char dummy_2a;
124 unsigned char isac_star2;
125 unsigned char dummy_2c;
126 unsigned char dummy_2d;
127 unsigned char dummy_2e;
128 unsigned char dummt_2f;
129 unsigned char isac_spcr;
130 unsigned char isac_cixr;
131 unsigned char isac_mox;
132 unsigned char isac_sscx;
133 unsigned char isac_sfcw;
134 unsigned char isac_c1r;
135 unsigned char isac_c2r;
136 unsigned char isac_stcr;
137 unsigned char isac_adf1;
138 unsigned char isac_adf2;
139 unsigned char isac_mocr;
140 unsigned char isac_sqxr;
145 #define REG_OFFSET(type, field) (int)(&(((type *)0)->field))
147 /* ISAC read registers */
149 #define i_ista isac_rw.isac_r.isac_ista
150 #define I_ISTA REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_ista)
151 #define i_star isac_rw.isac_r.isac_star
152 #define I_STAR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_star)
153 #define i_mode isac_rw.isac_r.isac_mode
154 #define I_MODE REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_mode)
155 #define i_timr isac_rw.isac_r.isac_timr
156 #define I_TIMR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_timr)
157 #define i_exir isac_rw.isac_r.isac_exir
158 #define I_EXIR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_exir)
159 #define i_rbcl isac_rw.isac_r.isac_rbcl
160 #define I_RBCL REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_rbcl)
161 #define i_sapr isac_rw.isac_r.isac_sapr
162 #define I_SAPR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_sapr)
163 #define i_rsta isac_rw.isac_r.isac_rsta
164 #define I_RSTA REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_rsta)
165 #define i_rhcr isac_rw.isac_r.isac_rhcr
166 #define I_RHCR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_rhcr)
167 #define i_rbch isac_rw.isac_r.isac_rbch
168 #define I_RBCH REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_rbch)
169 #define i_star2 isac_rw.isac_r.isac_star2
170 #define I_STAR2 REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_star2)
171 #define i_spcr isac_rw.isac_r.isac_spcr
172 #define I_SPCR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_spcr)
173 #define i_cirr isac_rw.isac_r.isac_cirr
174 #define I_CIRR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_cirr)
175 #define i_mor isac_rw.isac_r.isac_mor
176 #define I_MOR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_mor)
177 #define i_sscr isac_rw.isac_r.isac_sscr
178 #define I_SSCR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_sscr)
179 #define i_sfcr isac_rw.isac_r.isac_sfcr
180 #define I_SFCR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_sfcr)
181 #define i_c1r isac_rw.isac_r.isac_c1r
182 #define I_C1R REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_c1r)
183 #define i_c2r isac_rw.isac_r.isac_c2r
184 #define I_C2R REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_c2r)
185 #define i_b1cr isac_rw.isac_r.isac_b1cr
186 #define I_B1CR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_b1cr)
187 #define i_b2cr isac_rw.isac_r.isac_b2cr
188 #define I_B2CR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_b2cr)
189 #define i_adf2 isac_rw.isac_r.isac_adf2
190 #define I_ADF2 REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_adf2)
191 #define i_mosr isac_rw.isac_r.isac_mosr
192 #define I_MOSR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_mosr)
193 #define i_sqrr isac_rw.isac_r.isac_sqrr
194 #define I_SQRR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_sqrr)
196 /* ISAC write registers - isac_mode, isac_timr, isac_star2, isac_spcr, */
197 /* isac_c1r, isac_c2r, isac_adf2 see read registers */
199 #define i_mask isac_rw.isac_w.isac_mask
200 #define I_MASK REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_mask)
201 #define i_cmdr isac_rw.isac_w.isac_cmdr
202 #define I_CMDR REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_cmdr)
203 #define i_xad1 isac_rw.isac_w.isac_xad1
204 #define I_XAD1 REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_xad1)
205 #define i_xad2 isac_rw.isac_w.isac_xad2
206 #define I_XAD2 REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_xad2)
207 #define i_sap1 isac_rw.isac_w.isac_sap1
208 #define I_SAP1 REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_sap1)
209 #define i_sap2 isac_rw.isac_w.isac_sap2
210 #define I_SAP2 REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_sap2)
211 #define i_tei1 isac_rw.isac_w.isac_tei1
212 #define i_tei2 isac_rw.isac_w.isac_tei2
213 #define i_cixr isac_rw.isac_w.isac_cixr
214 #define I_CIXR REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_cixr)
215 #define I_CIX0 I_CIXR
216 #define i_mox isac_rw.isac_w.isac_mox
217 #define I_MOX REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_mox)
218 #define i_sscx isac_rw.isac_w.isac_sscx
219 #define I_SSCX REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_sscx)
220 #define i_sfcw isac_rw.isac_w.isac_sfcw
221 #define I_SFCW REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_sfcw)
222 #define i_stcr isac_rw.isac_w.isac_stcr
223 #define I_STCR REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_stcr)
224 #define i_adf1 isac_rw.isac_w.isac_adf1
225 #define I_ADF1 REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_adf1)
226 #define i_mocr isac_rw.isac_w.isac_mocr
227 #define I_MOCR REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_mocr)
228 #define i_sqxr isac_rw.isac_w.isac_sqxr
229 #define I_SQXR REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_sqxr)
231 #define ISAC_ISTA_RME 0x80
232 #define ISAC_ISTA_RPF 0x40
233 #define ISAC_ISTA_RSC 0x20
234 #define ISAC_ISTA_XPR 0x10
235 #define ISAC_ISTA_TIN 0x08
236 #define ISAC_ISTA_CISQ 0x04
237 #define ISAC_ISTA_SIN 0x02
238 #define ISAC_ISTA_EXI 0x01
240 #define ISAC_MASK_RME 0x80
241 #define ISAC_MASL_RPF 0x40
242 #define ISAC_MASK_RSC 0x20
243 #define ISAC_MASK_XPR 0x10
244 #define ISAC_MASK_TIN 0x08
245 #define ISAC_MASK_CISQ 0x04
246 #define ISAC_MASK_SIN 0x02
247 #define ISAC_MASK_EXI 0x01
248 #define ISAC_MASK_ALL 0xff
250 #define ISAC_STAR_XDOV 0x80
251 #define ISAC_STAR_XFW 0x40
252 #define ISAC_STAR_XRNR 0x20
253 #define ISAC_STAR_RRNR 0x10
254 #define ISAC_STAR_MBR 0x08
255 #define ISAC_STAR_MAC1 0x04
256 #define ISAC_STAR_BVS 0x02
257 #define ISAC_STAR_MAC0 0x01
259 #define ISAC_CMDR_RMC 0x80
260 #define ISAC_CMDR_RRES 0x40
261 #define ISAC_CMDR_RNR 0x20
262 #define ISAC_CMDR_STI 0x10
263 #define ISAC_CMDR_XTF 0x08
264 #define ISAC_CMDR_XIF 0x04
265 #define ISAC_CMDR_XME 0x02
266 #define ISAC_CMDR_XRES 0x01
268 #define ISAC_MODE_MDS2 0x80
269 #define ISAC_MODE_MDS1 0x40
270 #define ISAC_MODE_MDS0 0x20
271 #define ISAC_MODE_TMD 0x10
272 #define ISAC_MODE_RAC 0x08
273 #define ISAC_MODE_DIM2 0x04
274 #define ISAC_MODE_DIM1 0x02
275 #define ISAC_MODE_DIM0 0x01
277 #define ISAC_EXIR_XMR 0x80
278 #define ISAC_EXIR_XDU 0x40
279 #define ISAC_EXIR_PCE 0x20
280 #define ISAC_EXIR_RFO 0x10
281 #define ISAC_EXIR_SOV 0x08
282 #define ISAC_EXIR_MOS 0x04
283 #define ISAC_EXIR_SAW 0x02
284 #define ISAC_EXIR_WOV 0x01
286 #define ISAC_RSTA_RDA 0x80
287 #define ISAC_RSTA_RDO 0x40
288 #define ISAC_RSTA_CRC 0x20
289 #define ISAC_RSTA_RAB 0x10
290 #define ISAC_RSTA_SA1 0x08
291 #define ISAC_RSTA_SA0 0x04
292 #define ISAC_RSTA_CR 0x02
293 #define ISAC_RSTA_TA 0x01
295 #define ISAC_RSTA_MASK 0x70 /* the interesting bits */
297 #define ISAC_RBCH_XAC 0x80
298 #define ISAC_RBCH_VN1 0x40
299 #define ISAC_RBCH_VN0 0x20
300 #define ISAC_RBCH_OV 0x10
301 /* the other 4 bits are the high bits of the receive byte count */
303 #define ISAC_SPCR_SPU 0x80
304 #define ISAC_SPCR_SAC 0x40
305 #define ISAC_SPCR_SPM 0x20
306 #define ISAC_SPCR_TLP 0x10
307 #define ISAC_SPCR_C1C1 0x08
308 #define ISAC_SPCR_C1C0 0x04
309 #define ISAC_SPCR_C2C1 0x02
310 #define ISAC_SPCR_C2C0 0x01
312 #define ISAC_CIRR_SQC 0x80
313 #define ISAC_CIRR_BAS 0x40
315 #define ISAC_CIRR_CIC0 0x02
316 /* bit 0 is always 0 */
317 /* C/I codes from bits 5-2 (>> 2 & 0xf) */
318 /* the indications */
319 #define ISAC_CIRR_IPU 0x07
320 #define ISAC_CIRR_IDR 0x00
321 #define ISAC_CIRR_ISD 0x02
322 #define ISAC_CIRR_IDIS 0x03
323 #define ISAC_CIRR_IEI 0x06
324 #define ISAC_CIRR_IRSY 0x04
325 #define ISAC_CIRR_IARD 0x08
326 #define ISAC_CIRR_ITI 0x0a
327 #define ISAC_CIRR_IATI 0x0b
328 #define ISAC_CIRR_IAI8 0x0c
329 #define ISAC_CIRR_IAI10 0x0d
330 #define ISAC_CIRR_IDID 0x0f
332 #define ISAC_CI_MASK 0x0f
334 #define ISAC_CIXR_RSS 0x80
335 #define ISAC_CIXR_BAC 0x40
337 #define ISAC_CIXR_TCX 0x02
338 #define ISAC_CIXR_ECX 0x01
339 /* in IOM-2 mode the low bits are always 1 */
340 #define ISAC_CIX0_LOW 0x03
341 /* C/I codes from bits 5-2 (>> 2 & 0xf) */
343 #define ISAC_CIXR_CTIM 0
344 #define ISAC_CIXR_CRS 0x01
345 #define ISAC_CIXR_CSCZ 0x04
346 #define ISAC_CIXR_CSSZ 0x02
347 #define ISAC_CIXR_CAR8 0x08
348 #define ISAC_CIXR_CAR10 0x09
349 #define ISAC_CIXR_CARL 0x0a
350 #define ISAC_CIXR_CDIU 0x0f
352 #define ISAC_STCR_TSF 0x80
353 #define ISAC_STCR_TBA2 0x40
354 #define ISAC_STCR_TBA1 0x20
355 #define ISAC_STCR_TBA0 0x10
356 #define ISAC_STCR_ST1 0x08
357 #define ISAC_STCR_ST0 0x04
358 #define ISAC_STCR_SC1 0x02
359 #define ISAC_STCR_SC0 0x01
361 #define ISAC_ADF1_WTC1 0x80
362 #define ISAC_ADF1_WTC2 0x40
363 #define ISAC_ADF1_TEM 0x20
364 #define ISAC_ADF1_PFS 0x10
365 #define ISAC_ADF1_CFS 0x08
366 #define ISAC_ADF1_FC2 0x04
367 #define ISAC_ADF1_FC1 0x02
368 #define ISAC_ADF1_ITF 0x01
370 #define ISAC_ADF2_IMS 0x80
371 /* all other bits are 0 */
373 /* bits 7-5 are always 0 */
374 #define ISAC_SQRR_SYN 0x10
375 #define ISAC_SQRR_SQR1 0x08
376 #define ISAC_SQRR_SQR2 0x04
377 #define ISAC_SQRR_SQR3 0x02
378 #define ISAC_SQRR_SQR4 0x01
380 #define ISAC_SQXR_IDC 0x80
381 #define ISAC_SQXR_CFS 0x40
382 #define ISAC_SQXR_CI1E 0x20
383 #define ISAC_SQXR_SQIE 0x10
384 #define ISAC_SQXR_SQX1 0x08
385 #define ISAC_SQXR_SQX2 0x04
386 #define ISAC_SQXR_SQX3 0x02
387 #define ISAC_SQXR_SQX4 0x01
389 #endif /* I4B_ISAC_H_ */