2 * Copyright (c) 1998 Doug Rabson
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef _MACHINE_CPUFUNC_H_
30 #define _MACHINE_CPUFUNC_H_
34 #include <sys/types.h>
35 #include <machine/ia64_cpu.h>
42 __asm __volatile("break 0x80100"); /* XXX use linux value */
47 extern u_int64_t ia64_port_base;
49 static __inline volatile void *
50 ia64_port_address(u_int port)
52 return (volatile void *)(ia64_port_base
54 | (port & ((1 << 12) - 1)));
57 static __inline volatile void *
58 ia64_memory_address(u_int addr)
60 return (volatile void *) IA64_PHYS_TO_RR6(addr);;
63 static __inline u_int8_t
66 volatile u_int8_t *p = ia64_port_address(port);
73 static __inline u_int16_t
76 volatile u_int16_t *p = ia64_port_address(port);
83 static __inline u_int32_t
86 volatile u_int32_t *p = ia64_port_address(port);
94 insb(u_int port, void *addr, size_t count)
102 insw(u_int port, void *addr, size_t count)
110 insl(u_int port, void *addr, size_t count)
118 outb(u_int port, u_int8_t data)
120 volatile u_int8_t *p = ia64_port_address(port);
127 outw(u_int port, u_int16_t data)
129 volatile u_int16_t *p = ia64_port_address(port);
136 outl(u_int port, u_int32_t data)
138 volatile u_int32_t *p = ia64_port_address(port);
145 outsb(u_int port, const void *addr, size_t count)
147 const u_int8_t *p = addr;
153 outsw(u_int port, const void *addr, size_t count)
155 const u_int16_t *p = addr;
161 outsl(u_int port, const void *addr, size_t count)
163 const u_int32_t *p = addr;
168 static __inline u_int8_t
171 volatile u_int8_t *p = ia64_memory_address(addr);
178 static __inline u_int16_t
181 volatile u_int16_t *p = ia64_memory_address(addr);
188 static __inline u_int32_t
191 volatile u_int32_t *p = ia64_memory_address(addr);
199 writeb(u_int addr, u_int8_t data)
201 volatile u_int8_t *p = ia64_memory_address(addr);
208 writew(u_int addr, u_int16_t data)
210 volatile u_int16_t *p = ia64_memory_address(addr);
217 writel(u_int addr, u_int32_t data)
219 volatile u_int32_t *p = ia64_memory_address(addr);
228 __asm __volatile ("rsm psr.i;;");
234 __asm __volatile (";; ssm psr.i;; srlz.d");
237 static __inline critical_t
242 __asm __volatile ("mov %0=psr;;" : "=r" (psr));
248 critical_exit(critical_t psr)
250 __asm __volatile ("mov psr.l=%0;; srlz.d" :: "r" (psr));
255 #endif /* !_MACHINE_CPUFUNC_H_ */