2 * Copyright (c) 1990 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 4. Neither the name of the University nor the names of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
39 * Routines to handle clock hardware.
43 * inittodr, settodr and support routines written
44 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
46 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
49 #include "opt_clock.h"
53 #include <sys/param.h>
54 #include <sys/systm.h>
58 #include <sys/mutex.h>
61 #include <sys/timetc.h>
62 #include <sys/kernel.h>
63 #include <sys/limits.h>
64 #include <sys/module.h>
65 #include <sys/sysctl.h>
67 #include <sys/power.h>
69 #include <machine/clock.h>
70 #include <machine/cputypes.h>
71 #include <machine/frame.h>
72 #include <machine/intr_machdep.h>
73 #include <machine/md_var.h>
74 #include <machine/psl.h>
76 #include <machine/smp.h>
78 #include <machine/specialreg.h>
80 #include <i386/isa/isa.h>
83 #include <isa/isavar.h>
85 #include <i386/isa/timerreg.h>
88 #include <i386/bios/mca_machdep.h>
92 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
93 * can use a simple formula for leap years.
95 #define LEAPYEAR(y) (((u_int)(y) % 4 == 0) ? 1 : 0)
96 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
98 #define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x))
102 * Time in timer cycles that it takes for microtime() to disable interrupts
103 * and latch the count. microtime() currently uses "cli; outb ..." so it
104 * normally takes less than 2 timer cycles. Add a few for cache misses.
105 * Add a few more to allow for latency in bogus calls to microtime() with
106 * interrupts already disabled.
108 #define TIMER0_LATCH_COUNT 20
111 * Maximum frequency that we are willing to allow for timer0. Must be
112 * low enough to guarantee that the timer interrupt handler returns
113 * before the next timer interrupt.
115 #define TIMER0_MAX_FREQ 20000
118 int adjkerntz; /* local offset from GMT in seconds */
120 int disable_rtc_set; /* disable resettodr() if != 0 */
123 int statclock_disable;
125 #define TIMER_FREQ 1193182
127 u_int timer_freq = TIMER_FREQ;
128 int timer0_max_count;
129 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
130 struct mtx clock_lock;
132 static int beeping = 0;
133 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
134 static u_int hardclock_max_count;
135 static struct intsrc *i8254_intsrc;
136 static u_int32_t i8254_lastcount;
137 static u_int32_t i8254_offset;
138 static int (*i8254_pending)(struct intsrc *);
139 static int i8254_ticked;
142 * XXX new_function and timer_func should not handle clockframes, but
143 * timer_func currently needs to hold hardclock to handle the
144 * timer0_state == 0 case. We should use inthand_add()/inthand_remove()
145 * to switch between clkintr() and a slightly different timerintr().
147 static void (*new_function)(struct clockframe *frame);
148 static u_int new_rate;
149 static u_int timer0_prescaler_count;
150 static u_char timer0_state;
152 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
153 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
155 /* Values for timerX_state: */
157 #define RELEASE_PENDING 1
159 #define ACQUIRE_PENDING 3
161 static u_char timer2_state;
162 static void (*timer_func)(struct clockframe *frame) = hardclock;
164 static unsigned i8254_get_timecount(struct timecounter *tc);
165 static void set_timer_freq(u_int freq, int intr_freq);
167 static struct timecounter i8254_timecounter = {
168 i8254_get_timecount, /* get_timecount */
170 ~0u, /* counter_mask */
177 clkintr(struct clockframe *frame)
180 if (timecounter->tc_get_timecount == i8254_get_timecount) {
181 mtx_lock_spin(&clock_lock);
185 i8254_offset += timer0_max_count;
189 mtx_unlock_spin(&clock_lock);
193 if (timer_func == hardclock)
197 switch (timer0_state) {
203 if ((timer0_prescaler_count += timer0_max_count)
204 >= hardclock_max_count) {
205 timer0_prescaler_count -= hardclock_max_count;
213 case ACQUIRE_PENDING:
214 mtx_lock_spin(&clock_lock);
215 i8254_offset = i8254_get_timecount(NULL);
217 timer0_max_count = TIMER_DIV(new_rate);
218 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
219 outb(TIMER_CNTR0, timer0_max_count & 0xff);
220 outb(TIMER_CNTR0, timer0_max_count >> 8);
221 mtx_unlock_spin(&clock_lock);
222 timer_func = new_function;
223 timer0_state = ACQUIRED;
226 case RELEASE_PENDING:
227 if ((timer0_prescaler_count += timer0_max_count)
228 >= hardclock_max_count) {
229 mtx_lock_spin(&clock_lock);
230 i8254_offset = i8254_get_timecount(NULL);
232 timer0_max_count = hardclock_max_count;
234 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
235 outb(TIMER_CNTR0, timer0_max_count & 0xff);
236 outb(TIMER_CNTR0, timer0_max_count >> 8);
237 mtx_unlock_spin(&clock_lock);
238 timer0_prescaler_count = 0;
239 timer_func = hardclock;
240 timer0_state = RELEASED;
250 /* Reset clock interrupt by asserting bit 7 of port 0x61 */
252 outb(0x61, inb(0x61) | 0x80);
258 * The acquire and release functions must be called at ipl >= splclock().
261 acquire_timer0(int rate, void (*function)(struct clockframe *frame))
265 if (rate <= 0 || rate > TIMER0_MAX_FREQ)
267 switch (timer0_state) {
270 timer0_state = ACQUIRE_PENDING;
273 case RELEASE_PENDING:
274 if (rate != old_rate)
277 * The timer has been released recently, but is being
278 * re-acquired before the release completed. In this
279 * case, we simply reclaim it as if it had not been
282 timer0_state = ACQUIRED;
286 return (-1); /* busy */
288 new_function = function;
289 old_rate = new_rate = rate;
295 acquire_timer2(int mode)
298 if (timer2_state != RELEASED)
300 timer2_state = ACQUIRED;
303 * This access to the timer registers is as atomic as possible
304 * because it is a single instruction. We could do better if we
305 * knew the rate. Use of splclock() limits glitches to 10-100us,
306 * and this is probably good enough for timer2, so we aren't as
307 * careful with it as with timer0.
309 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
318 switch (timer0_state) {
321 timer0_state = RELEASE_PENDING;
324 case ACQUIRE_PENDING:
325 /* Nothing happened yet, release quickly. */
326 timer0_state = RELEASED;
340 if (timer2_state != ACQUIRED)
342 timer2_state = RELEASED;
343 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
348 * This routine receives statistical clock interrupts from the RTC.
349 * As explained above, these occur at 128 interrupts per second.
350 * When profiling, we receive interrupts at a rate of 1024 Hz.
352 * This does not actually add as much overhead as it sounds, because
353 * when the statistical clock is active, the hardclock driver no longer
354 * needs to keep (inaccurate) statistics on its own. This decouples
355 * statistics gathering from scheduling interrupts.
357 * The RTC chip requires that we read status register C (RTC_INTR)
358 * to acknowledge an interrupt, before it will generate the next one.
359 * Under high interrupt load, rtcintr() can be indefinitely delayed and
360 * the clock can tick immediately after the read from RTC_INTR. In this
361 * case, the mc146818A interrupt signal will not drop for long enough
362 * to register with the 8259 PIC. If an interrupt is missed, the stat
363 * clock will halt, considerably degrading system performance. This is
364 * why we use 'while' rather than a more straightforward 'if' below.
365 * Stat clock ticks can still be lost, causing minor loss of accuracy
366 * in the statistics, but the stat clock will no longer stop.
369 rtcintr(struct clockframe *frame)
372 while (rtcin(RTC_INTR) & RTCIR_PERIOD) {
373 if (profprocs != 0) {
390 DB_SHOW_COMMAND(rtc, rtc)
392 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
393 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
394 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
395 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
404 mtx_lock_spin(&clock_lock);
406 /* Select timer0 and latch counter value. */
407 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
409 low = inb(TIMER_CNTR0);
410 high = inb(TIMER_CNTR0);
412 mtx_unlock_spin(&clock_lock);
413 return ((high << 8) | low);
417 * Wait "n" microseconds.
418 * Relies on timer 1 counting down from (timer_freq / hz)
419 * Note: timer had better have been programmed before this is first used!
424 int delta, prev_tick, tick, ticks_left;
429 static int state = 0;
433 for (n1 = 1; n1 <= 10000000; n1 *= 10)
438 printf("DELAY(%d)...", n);
441 * Guard against the timer being uninitialized if we are called
442 * early for console i/o.
444 if (timer0_max_count == 0)
445 set_timer_freq(timer_freq, hz);
448 * Read the counter first, so that the rest of the setup overhead is
449 * counted. Guess the initial overhead is 20 usec (on most systems it
450 * takes about 1.5 usec for each of the i/o's in getit(). The loop
451 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The
452 * multiplications and divisions to scale the count take a while).
454 * However, if ddb is active then use a fake counter since reading
455 * the i8254 counter involves acquiring a lock. ddb must not do
456 * locking for many reasons, but it calls here for at least atkbd
465 n -= 0; /* XXX actually guess no initial overhead */
467 * Calculate (n * (timer_freq / 1e6)) without using floating point
468 * and without any avoidable overflows.
474 * Use fixed point to avoid a slow division by 1000000.
475 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest.
476 * 2^15 is the first power of 2 that gives exact results
477 * for n between 0 and 256.
479 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15;
482 * Don't bother using fixed point, although gcc-2.7.2
483 * generates particularly poor code for the long long
484 * division, since even the slow way will complete long
485 * before the delay is up (unless we're interrupted).
487 ticks_left = ((u_int)n * (long long)timer_freq + 999999)
490 while (ticks_left > 0) {
494 tick = prev_tick - 1;
496 tick = timer0_max_count;
503 delta = prev_tick - tick;
506 delta += timer0_max_count;
508 * Guard against timer0_max_count being wrong.
509 * This shouldn't happen in normal operation,
510 * but it may happen if set_timer_freq() is
520 printf(" %d calls to getit() at %d usec each\n",
521 getit_calls, (n + 5) / getit_calls);
526 sysbeepstop(void *chan)
528 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
534 sysbeep(int pitch, int period)
538 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
540 /* Something else owns it. */
542 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */
544 mtx_lock_spin(&clock_lock);
545 outb(TIMER_CNTR2, pitch);
546 outb(TIMER_CNTR2, (pitch>>8));
547 mtx_unlock_spin(&clock_lock);
549 /* enable counter2 output to speaker */
550 outb(IO_PPI, inb(IO_PPI) | 3);
552 timeout(sysbeepstop, (void *)NULL, period);
559 * RTC support routines
572 val = inb(IO_RTC + 1);
579 writertc(u_char reg, u_char val)
587 outb(IO_RTC + 1, val);
588 inb(0x84); /* XXX work around wrong order in rtcin() */
595 return(bcd2bin(rtcin(port)));
599 calibrate_clocks(void)
601 u_int count, prev_count, tot_count;
602 int sec, start_sec, timeout;
605 printf("Calibrating clock(s) ... ");
606 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
610 /* Read the mc146818A seconds counter. */
612 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
613 sec = rtcin(RTC_SEC);
620 /* Wait for the mC146818A seconds counter to change. */
623 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
624 sec = rtcin(RTC_SEC);
625 if (sec != start_sec)
632 /* Start keeping track of the i8254 counter. */
633 prev_count = getit();
634 if (prev_count == 0 || prev_count > timer0_max_count)
639 * Wait for the mc146818A seconds counter to change. Read the i8254
640 * counter for each iteration since this is convenient and only
641 * costs a few usec of inaccuracy. The timing of the final reads
642 * of the counters almost matches the timing of the initial reads,
643 * so the main cause of inaccuracy is the varying latency from
644 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
645 * rtcin(RTC_SEC) that returns a changed seconds count. The
646 * maximum inaccuracy from this cause is < 10 usec on 486's.
650 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
651 sec = rtcin(RTC_SEC);
653 if (count == 0 || count > timer0_max_count)
655 if (count > prev_count)
656 tot_count += prev_count - (count - timer0_max_count);
658 tot_count += prev_count - count;
660 if (sec != start_sec)
667 printf("i8254 clock: %u Hz\n", tot_count);
673 printf("failed, using default i8254 clock of %u Hz\n",
679 set_timer_freq(u_int freq, int intr_freq)
681 int new_timer0_max_count;
683 mtx_lock_spin(&clock_lock);
685 new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq);
686 if (new_timer0_max_count != timer0_max_count) {
687 timer0_max_count = new_timer0_max_count;
688 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
689 outb(TIMER_CNTR0, timer0_max_count & 0xff);
690 outb(TIMER_CNTR0, timer0_max_count >> 8);
692 mtx_unlock_spin(&clock_lock);
699 mtx_lock_spin(&clock_lock);
700 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
701 outb(TIMER_CNTR0, timer0_max_count & 0xff);
702 outb(TIMER_CNTR0, timer0_max_count >> 8);
703 mtx_unlock_spin(&clock_lock);
710 /* Restore all of the RTC's "status" (actually, control) registers. */
711 /* XXX locking is needed for RTC access. */
712 writertc(RTC_STATUSB, RTCSB_24HR);
713 writertc(RTC_STATUSA, rtc_statusa);
714 writertc(RTC_STATUSB, rtc_statusb);
718 * Restore all the timers non-atomically (XXX: should be atomically).
720 * This function is called from pmtimer_resume() to restore all the timers.
721 * This should not be necessary, but there are broken laptops that do not
722 * restore all the timers on resume.
728 i8254_restore(); /* restore timer_freq and hz */
729 rtc_restore(); /* reenable RTC interrupts */
733 * Initialize 8254 timer 0 early so that it can be used in DELAY().
734 * XXX initialization of other timers is unintentionally left blank.
741 writertc(RTC_STATUSA, rtc_statusa);
742 writertc(RTC_STATUSB, RTCSB_24HR);
744 set_timer_freq(timer_freq, hz);
745 freq = calibrate_clocks();
746 #ifdef CLK_CALIBRATION_LOOP
749 "Press a key on the console to abort clock calibration\n");
750 while (cncheckc() == -1)
756 * Use the calibrated i8254 frequency if it seems reasonable.
757 * Otherwise use the default, and don't use the calibrated i586
760 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq;
761 if (delta < timer_freq / 100) {
762 #ifndef CLK_USE_I8254_CALIBRATION
765 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
772 "%d Hz differs from default of %d Hz by more than 1%%\n",
776 set_timer_freq(timer_freq, hz);
777 i8254_timecounter.tc_frequency = timer_freq;
778 tc_init(&i8254_timecounter);
784 * Initialize the time of day register, based on the time base which is, e.g.
788 inittodr(time_t base)
790 unsigned long sec, days;
803 /* Look if we have a RTC present and the time is valid */
804 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
807 /* wait for time update to complete */
808 /* If RTCSA_TUP is zero, we have at least 244us before next update */
810 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
816 #ifdef USE_RTC_CENTURY
817 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
819 year = readrtc(RTC_YEAR) + 1900;
827 month = readrtc(RTC_MONTH);
828 for (m = 1; m < month; m++)
829 days += daysinmonth[m-1];
830 if ((month > 2) && LEAPYEAR(year))
832 days += readrtc(RTC_DAY) - 1;
833 for (y = 1970; y < year; y++)
834 days += DAYSPERYEAR + LEAPYEAR(y);
835 sec = ((( days * 24 +
836 readrtc(RTC_HRS)) * 60 +
837 readrtc(RTC_MIN)) * 60 +
839 /* sec now contains the number of seconds, since Jan 1 1970,
840 in the local time zone */
842 sec += tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
844 y = time_second - sec;
845 if (y <= -2 || y >= 2) {
846 /* badly off, adjust it */
855 printf("Invalid time in real time clock.\n");
856 printf("Check and reset the date immediately!\n");
860 * Write system time back to RTC
875 /* Disable RTC updates and interrupts. */
876 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
878 /* Calculate local time to put in RTC */
880 tm -= tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
882 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
883 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
884 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
886 /* We have now the days since 01-01-1970 in tm */
887 writertc(RTC_WDAY, (tm + 4) % 7 + 1); /* Write back Weekday */
888 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
890 y++, m = DAYSPERYEAR + LEAPYEAR(y))
893 /* Now we have the years in y and the day-of-the-year in tm */
894 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
895 #ifdef USE_RTC_CENTURY
896 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
902 if (m == 1 && LEAPYEAR(y))
909 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
910 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
912 /* Reenable RTC updates and interrupts. */
913 writertc(RTC_STATUSB, rtc_statusb);
918 * Start both clocks running.
925 if (statclock_disable) {
927 * The stat interrupt mask is different without the
928 * statistics clock. Also, don't set the interrupt
929 * flag which would normally cause the RTC to generate
932 rtc_statusb = RTCSB_24HR;
934 /* Setting stathz to nonzero early helps avoid races. */
935 stathz = RTC_NOPROFRATE;
936 profhz = RTC_PROFRATE;
939 /* Finish initializing 8254 timer 0. */
940 intr_add_handler("clk", 0, (driver_intr_t *)clkintr, NULL,
941 INTR_TYPE_CLK | INTR_FAST, NULL);
942 i8254_intsrc = intr_lookup_source(0);
943 if (i8254_intsrc != NULL)
944 i8254_pending = i8254_intsrc->is_pic->pic_source_pending;
946 /* Initialize RTC. */
947 writertc(RTC_STATUSA, rtc_statusa);
948 writertc(RTC_STATUSB, RTCSB_24HR);
950 /* Don't bother enabling the statistics clock. */
951 if (!statclock_disable) {
952 diag = rtcin(RTC_DIAG);
954 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
956 intr_add_handler("rtc", 8, (driver_intr_t *)rtcintr, NULL,
957 INTR_TYPE_CLK | INTR_FAST, NULL);
959 writertc(RTC_STATUSB, rtc_statusb);
966 cpu_startprofclock(void)
969 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
970 writertc(RTC_STATUSA, rtc_statusa);
971 psdiv = pscnt = psratio;
975 cpu_stopprofclock(void)
978 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
979 writertc(RTC_STATUSA, rtc_statusa);
984 sysctl_machdep_i8254_freq(SYSCTL_HANDLER_ARGS)
990 * Use `i8254' instead of `timer' in external names because `timer'
991 * is is too generic. Should use it everywhere.
994 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
995 if (error == 0 && req->newptr != NULL) {
997 if (timer0_state != RELEASED)
998 return (EBUSY); /* too much trouble to handle */
1000 set_timer_freq(freq, hz);
1001 i8254_timecounter.tc_frequency = freq;
1006 SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW,
1007 0, sizeof(u_int), sysctl_machdep_i8254_freq, "IU", "");
1010 i8254_get_timecount(struct timecounter *tc)
1016 eflags = read_eflags();
1017 mtx_lock_spin(&clock_lock);
1019 /* Select timer0 and latch counter value. */
1020 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
1022 low = inb(TIMER_CNTR0);
1023 high = inb(TIMER_CNTR0);
1024 count = timer0_max_count - ((high << 8) | low);
1025 if (count < i8254_lastcount ||
1026 (!i8254_ticked && (clkintr_pending ||
1027 ((count < 20 || (!(eflags & PSL_I) && count < timer0_max_count / 2u)) &&
1028 i8254_pending != NULL && i8254_pending(i8254_intsrc))))) {
1030 i8254_offset += timer0_max_count;
1032 i8254_lastcount = count;
1033 count += i8254_offset;
1034 mtx_unlock_spin(&clock_lock);
1040 * Attach to the ISA PnP descriptors for the timer and realtime clock.
1042 static struct isa_pnp_id attimer_ids[] = {
1043 { 0x0001d041 /* PNP0100 */, "AT timer" },
1044 { 0x000bd041 /* PNP0B00 */, "AT realtime clock" },
1049 attimer_probe(device_t dev)
1053 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, attimer_ids)) <= 0)
1059 attimer_attach(device_t dev)
1064 static device_method_t attimer_methods[] = {
1065 /* Device interface */
1066 DEVMETHOD(device_probe, attimer_probe),
1067 DEVMETHOD(device_attach, attimer_attach),
1068 DEVMETHOD(device_detach, bus_generic_detach),
1069 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1070 DEVMETHOD(device_suspend, bus_generic_suspend), /* XXX stop statclock? */
1071 DEVMETHOD(device_resume, bus_generic_resume), /* XXX restart statclock? */
1075 static driver_t attimer_driver = {
1081 static devclass_t attimer_devclass;
1083 DRIVER_MODULE(attimer, isa, attimer_driver, attimer_devclass, 0, 0);
1084 DRIVER_MODULE(attimer, acpi, attimer_driver, attimer_devclass, 0, 0);
1085 #endif /* DEV_ISA */